ON Semiconductor MC14551B Technical data

MC14551B

Quad 2-Channel Analog
Multiplexer/Demultiplexer

The MC14551B is a digitally–controlled analog switch. This device
implements a 4PDT solid state switch with low ON impedance and
very low OFF Leakage current. Control of analog signals up to the
complete supply voltage range can be achieved.

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• Triple Diode Protection on All Control Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Analog Voltage Range (V

Note: VEE must be  V

– VEE) = 3.0 to 18 V

DD

SS

• Linearized Transfer Characteristics

• Low Noise — 12 nV√Cycle, f ≥ 1.0 kHz typical

• For Low R

CMOS Devices

, Use The HC4051, HC4052, or HC4053 High–Speed

ON

• Switch Function is Break Before Make

MAXIMUM RATINGS

Symbol Parameter Value Unit

V

Vin, V

T

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C

This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
to the range V
V

DD

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V

DC Supply Voltage Range

DD

(Referenced to V
Input or Output Voltage (DC or

out

Transient) (Referenced to V
Control Input & V

I

Input Current (DC or Transient),

in

per Control Pin

I

Switch Through Current ± 25 mA

sw

P

Power Dissipation, per Package

D

T

Ambient Temperature Range – 55 to + 125 C

A

Storage Temperature Range – 65 to + 150 C

stg

T

Lead Temperature

L

(8–Second Soldering)

 (Vin or V

for Switch I/O.

SS

, VEE or VDD). Unused outputs must be left open.

SS

(2.)

, VSS ≥ VEE)

EE

for

SS

for Switch I/O)

EE

)  VDD for control inputs and VEE ≤ (Vin or V

out

– 0.5 to + 18.0 V

– 0.5 to VDD + 0.5 V

± 10 mA

(3.)

and V

in

500 mW

260 C

should be constrained

out

out

) ≤

MARKING

DIAGRAMS

16

PDIP–16

P SUFFIX

CASE 648

SOIC–16

D SUFFIX

CASE 751B

SOEIAJ–16

F SUFFIX

CASE 966

A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week

MC14551BCP

AWLYYWW

1

16

14551B

AWLYWW

1

16

MC14551B

ALYW

1

ORDERING INFORMATION

Device Package Shipping

MC14551BCP PDIP–16 2000/Box
MC14551BD SOIC–16
MC14551BDR2 SOIC–16 2500/Tape & Reel
MC14551BF SOEIAJ–16 See Note 1.

1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.

48/Rail

 Semiconductor Components Industries, LLC, 2000

August, 2000 – Rev. 4

1 Publication Order Number:

MC14551B/D

SWITCHES

IN/OUT

MC14551B

PIN ASSIGNMENT

1

V

V

W1

X0

X1

Y0

15

10
11
12

EE

SS

9

1
2
3
6

X

Y

2

3

4

6

7

8

CONTROL

W0
W1
X0
X1
Y0
Y1
Z0
Z1

16

15

14

13

125

11

10

9

W

X

Y

Z

V

DD

W0

W

Z

Z1

Z0

Y1

CONTROL

14

4

COMMONS

5

13

OUT/IN

VDD = Pin 16
V

= Pin 8

SS

= Pin 7

V

EE

Control ON

0 W0X0Y0Z0
1 W1X1Y1Z1

NOTE: Control Input referenced to V

Outputs reference to V

. VEE must be  VSS.

EE

, Analog Inputs and

SS

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2

MC14551B

ELECTRICAL CHARACTERISTICS

– 55C 25C 125C

Characteristic Symbol V

DD

Test Conditions

Min Max Min Typ

SUPPLY REQUIREMENTS (Voltages Referenced to VEE)

Power Supply Voltage

Range

Quiescent Current Per

Package

Total Supply Current

(Dynamic Plus
Quiescent, Per Package)

V

I

DD

I

D(AV)

DD

— VDD – 3.0 ≥ VSS ≥

V

EE

5.0

Control Inputs: V

10

VSS or VDD,

15

Switch I/O: V

 VDD, and ∆V
 500 mV

5.0

TA = 25C only (The

10

channel component,

15

(V

in

– V

(5.)

)/Ron, is

out

EE

 V

in =

switch

3.0 18 3.0 — 18 3.0 18 V

—

5.0
10
20

—
—
—

I/O

—
—

Typical (0.20 µA/kHz) f + I

not included.)

CONTROL INPUT (Voltages Referenced to VSS)

Low–Level Input Voltage V

High–Level Input Voltage V

Input Leakage Current I
Input Capacitance C

5.0

IL

Ron = per spec,

10

I

off

= per spec

15

5.0

IH

Ron = per spec,

10

I

off

= per spec

15

in

15 Vin = 0 or V
— — — — 5.0 7.5 — — pF

in

DD

—

1.5

3.0

4.0
—

—
—

—
—
—

3.5

7.0
11

—
—

3.5

7.0
11

— ±0.1 — ±0.00001 ±0.1 — ±1.0 µA

SWITCHES IN/OUT AND COMMONS OUT/IN — W, X, Y, Z (Voltages Referenced to VEE)

Recommended Peak–to–

V

I/O

— Channel On or Off 0 V

0 — V

DD

Peak Voltage Into or Out
of the Switch

Recommended Static or

Dynamic Voltage Across
the Switch

(5.)

(Figure 3)
Output Offset Voltage V
ON Resistance R

∆ON Resistance Between

Any Two Channels
in the Same Package

Off–Channel Leakage

Current (Figure 8)

∆V

∆R

I

switch

OO

on

on

off

— Channel On 0 600 0 — 600 0 300 mV

— Vin = 0 V, No Load — — — 10 — — — µV

5.0

∆V

 500 mV
10
15

switch

V

= VIL or V

in

(Control), and Vin =
0 to V

DD

5.0
10
15

15 Vin = VIL or V

(Switch)

(5.)

,

——800

IH

—
—
—

IH

— ±100 — ±0.05 ±100 — ±1000 nA

400
220

70
50
45

—
—
—

—
—
—

(Control) Channel to
Channel or Any One

Channel
Capacitance, Switch I/O C
Capacitance, Common O/I C
Capacitance, Feedthrough

(Channel Off)

I/O
O/I

C

I/O

— Switch Off — — — 10 — — — pF
— — — — 17 — — — pF
——Pins Not Adjacent

Pins Adjacent

—————

—

4. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.

5. For voltage drops across the switch (∆V
current out of the switch may contain both V
Maximum Ratings are exceeded. (See first page of this data sheet.)

) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the

switch

and switch input components. The reliability of the device will be unaffected unless the

DD

(4.)

Max Min Max

0.005

0.010

0.015

5.0
10
20

(0.07 µA/kHz) f + I

(0.36 µA/kHz) f + I

2.25

4.50

6.75

2.75

5.50

8.25

250
120

80

25
10
10

0.15

1.5

3.0

4.0
—

—
—

DD

1050

500
280

70
50
45

———

0.47

—
—
—

DD
DD
DD

—
—
—

3.5

7.0
11

0 V

—
—
—

—
—
—

—

150
300
600

1.5

3.0

4.0
—

—
—

DDVp–p

1200

520
300

135

95
65

—
—

Unit

µA

µA

V

V

Ω

Ω

pF

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3

MC14551B

ELECTRICAL CHARACTERISTICS (C

Characteristic

Propagation Delay Times

Switch Input to Switch Output (R

, t

t
t
t

PLH
PLH
PLH

= (0.17 ns/pF) CL + 26.5 ns

PHL

, t

= (0.08 ns/pF) CL + 11 ns

PHL

, t

= (0.06 ns/pF) CL + 9.0 ns

PHL

Control Input to Output (RL = 10 kΩ)

V

= VSS (Figure 4)

EE

Second Harmonic Distortion

R

= 10 kΩ, f = 1 kHz, Vin = 5 V

L

Bandwidth (Figure 5)

R

= 1 kΩ, Vin = 1/2 (VDD – VEE)

L

20 Log (V

) = – 3 dB, CL = 50 pF

out/Vin

Off Channel Feedthrough Attenuation, Figure 5

R

= 1 kΩ, Vin = 1/2 (VDD – VEE)

L

= 55 MHz

f

in

Channel Separation (Figure 6)

R

= 1 kΩ, Vin = 1/2 (VDD – VEE)

L

= 3 MHz

f

in

Crosstalk, Control Input to Common O/I, Figure 7

R1 = 1 kΩ, R
Control t

= 10 kΩ,

L

= tf = 20 ns

r

L

p–p

= 50 pF, TA = 25C, VEE  VSS)

L

Symbol

t

PLH

= 10 kΩ)

t

PLH

,

p–p

,

p–p

,

p–p

VDD – V

EE

Vdc

, t

PHL

5.0
10
15

, t

PHL

5.0
10
15

Min Typ

—
—
—

—
—
—

35
15
12

350
140
100

(6.)

Max Unit

90
40
30

875
350
250

— 10 — 0.07 — %

BW 10 — 17 — MHz

— 10 — – 50 — dB

— 10 — – 50 — dB

— 10 — 75 — mV

6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

ns

ns

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4

MC14551B

V

V

DD

IN/OUT OUT/IN

V

DD

LEVEL
CONVERTED
CONTROL

V

EE

Figure 1. Switch Circuit Schematic

DD

V

DD

V

EE

IN/OUT OUT/IN

CONTROL

CONTROL9

W015

W11

X02

X13

Y06

Y110

Z011

Z112

16 V

DD

LEVEL

CONVERTER

87

V

SS

V

EE

CONTROL

Figure 2. MC14551B Functional Diagram

14W

4X

5Y

13Z

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5

MC14551B

TEST CIRCUITS

CONTROL

SECTION

OF IC

SOURCE

Figure 3. ∆V Across Switch Figure 4. Propagation Delay Times,

Control input used to turn ON or OFF
the switch under test.

CONTROL V

V

VDD - V

EE

2

Figure 5. Bandwidth and Off–Channel

Feedthrough Attenuation

ON SWITCH

PULSE

GENERATOR

LOAD

V

R

L

VDDVEEVEEV

CONTROL V

out

C

L

DD

Control to Output

R

L

ON

out

R

in

CL = 50 pF

L

VDD - V

EE

CONTROL

OFF

V

out

R

V

in

CL = 50 pF

L

2

Figure 6. Channel Separation

(Adjacent Channels Used for Setup)

CONTROL V

R

CL = 50 pF

L

R1

Figure 7. Crosstalk, Control Input

to Common O/I

V

DD

10 k

V

DD

VEE = V

SS

OFF CHANNEL UNDER TEST

V

DD

V

CONTROL

out

SECTION

OF IC

OTHER
CHANNEL(S)

EE

V

EE

V

DD

V

EE

V

DD

Figure 8. Off Channel Leakage

KEITHLEY 160

DIGITAL

MULTIMETER

1 kΩ

RANGE

X/Y

PLOTTER

Figure 9. Channel Resistance (RON) Test Circuit

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6

MC14551B

TYPICAL RESISTANCE CHARACTERISTICS

350

300

250

200

150

100

, ON" RESISTANCE (OHMS)

ON

R

50

0

700

600

500

350

300

250

200

T

= 125°C

A

25°C

-55°C

-8.0-10 -6.0 -4.0 -2.0 0 2.0 4.0 6.0 8.0 10

V

, INPUT VOLTAGE (VOLTS)

in

150

100

, ON" RESISTANCE (OHMS)

ON

R

50

0

-8.0-10 -6.0 -4.0 -2.0 0 2.0 4.0 6.0 8.0 10

V

, INPUT VOLTAGE (VOLTS)

in

Figure 10. VDD @ 7.5 V, VEE @ – 7.5 V Figure 11. VDD @ 5.0 V, VEE @ – 5.0 V

350

T

= 25°C

300

250

A

VDD = 2.5 V

T

= 125°C

A

25°C

-55°C

400

300

200

, ON" RESISTANCE (OHMS)

ON

R

100

0

200

150

T

= 125°C

A

25°C

-55°C

-8.0-10 -6.0 -4.0 -2.0 0 2.0 4.0 6.0 8.0 10

, INPUT VOLTAGE (VOLTS)

V

in

100

, ON" RESISTANCE (OHMS)

ON

R

50

0

-8.0-10 -6.0 -4.0 -2.0 0 2.0 4.0 6.0 8.0 10

, INPUT VOLTAGE (VOLTS)

V

in

5.0 V

Figure 12. VDD @ 2.5 V, VEE @ – 2.5 V Figure 13. Comparison at 25C, VDD @ – V

7.5 V

EE

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7

MC14551B

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

APPLICATIONS INFORMATION

Figure A illustrates use of the on–chip level converter
detailed in Figure 2. The 0–to–5 volt Digital Control signal
is used to directly control a 9 V

The digital control logic levels are determined by V
and VSS. The VDD voltage is the logic high voltage; the V

analog signal.

p–p

DD

SS

voltage is logic low. For the example, VDD = + 5 V = logic
high at the control inputs; VSS = GND = 0 V = logic low.

The maximum analog signal level is determined by V

DD

and VEE. The VDD voltage determines the maximum
recommended peak above VSS. The VEE voltage
determines the maximum swing below VSS. For the
example, VDD – VSS = 5 volt maximum swing above VSS;
VSS – VEE = 5 volt maximum swing below VSS. The
example shows a ± 4.5 volt signal which allows a 1/2 volt

V

DDVSS

9 V

+5 V

EXTERNAL

CMOS

DIGITAL

CIRCUITRY

0-TO-5 V DIGITAL

CONTROL SIGNAL

p-p

ANALOG SIGNAL

SWITCH

I/O

CONTROL

COMMON

MC14551B

margin at each peak. If voltage transients above V

DD

and/or
below VEE are anticipated on the analog channels, external
diodes (Dx) are recommended as shown in Figure B. These
diodes should be small signal types able to absorb the
maximum anticipated current surges during clipping.

The absolute maximum potential difference between

V

and VEE is 18.0 volts. Most parameters are specified

DD

up to 15 volts which is the recommended maximum
difference between V

and VEE.

DD

Balanced supplies are not required. However, VSS must
be greater than or equal to VEE. For example, VDD =
+ 10 volts, VSS = + 5 volts, and VEE = – 3 volts is acceptable.
See the table below.

-5 V+5 V

V

O/I

EE

9 V

p-p

ANALOG SIGNAL

+4.5 V

GND

-4.5 V

Figure A. Application Example

V

DD

D

x

SWITCH

I/O

D

x

V

EE

Figure B. External Schottky or Germanium Clipping Diodes

POSSIBLE SUPPLY CONNECTIONS

ÎÎ

V

DD

In Volts

ÎÎ

+ 8
+ 5
+ 5
+ 5

+ 10

ÎÎ

V

SS

In Volts

ÎÎ

0
0
0
0

ÎÎ

V

EE

In Volts

ÎÎ

– 8

– 12

0
– 5
– 5

COMMON

O/I

Control Inputs

ООООО

Logic High/Logic Low

In Volts

ООООО

+ 8/0
+ 5/0
+ 5/0
+ 5/0

+ 10/ + 5

V

DD

D

x

D

x

V

EE

ОООООООО

Maximum Analog Signal Range

ОООООООО

In Volts

+ 8 to – 8 = 16 V

+ 5 to – 12 = 17 V

+ 5 to 0 = 5 V

+ 5 to – 5 = 10 V

+ 10 to – 5 = 15 V

p–p

p–p

p–p

p–p

p–p

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8

PACKAGE DIMENSIONS

–A–

916

B

18

F

H

G

D

16 PL

0.25 (0.010) T

C

S

SEATING

–T–

PLANE

K

M

A

MC14551B

PDIP–16

P SUFFIX

CASE 648–08

ISSUE R

J

M

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

DIM MIN MAX MIN MAX

L

M

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01

MILLIMETERSINCHES



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9

–T–

–A–

16 9

–B–

18

G

K

C

SEATING

PLANE

D

16 PL

0.25 (0.010) A

M

S

B

T

S

MC14551B

PACKAGE DIMENSIONS

SOIC–16

D SUFFIX

CASE 751B–05

ISSUE J

8 PLP

M

0.25 (0.010) B

M

S

X 45

R



NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

F

J

A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7



P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

INCHESMILLIMETERS

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10

16 9

1

Z

D

e

b

0.13 (0.005)

M

8

H

E

E

A

A

1

0.10 (0.004)

MC14551B

PACKAGE DIMENSIONS

SOEIAJ–16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966–01

ISSUE O

L

E

M



L

DETAIL P

VIEW P

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

Q

1

c

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

MILLIMETERS

DIM MIN MAX MIN MAX

--- 2.05 --- 0.081

A
A

0.05 0.20 0.002 0.008

1

0.35 0.50 0.014 0.020

b

0.18 0.27 0.007 0.011

c

9.90 10.50 0.390 0.413

D

5.10 5.45 0.201 0.215

E

1.27 BSC 0.050 BSC

e
H

7.40 8.20 0.291 0.323

E

0.50 0.85 0.020 0.033

L
L

1.10 1.50 0.043 0.059

E

0

M



Q

0.70 0.90 0.028 0.035

1

--- 0.78 --- 0.031

Z

INCHES

10



10

0





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11

MC14551B

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without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
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Phone: [phone] or 800–344–3860 Toll Free USA/Canada
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Email: [e-mail]

Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada

N. American Technical Support: 800–282–9855 Toll Free USA/Canada
EUROPE: LDC for ON Semiconductor – European Support

German Phone: [phone] (Mon–Fri 2:30pm to 7:00pm CET)

Email: ONlit–[e-mail]

French Phone: [phone] (Mon–Fri 2:00pm to 7:00pm CET)

Email: ONlit–[e-mail]

English Phone: [phone] (Mon–Fri 12:00pm to 5:00pm GMT)

Email: [e-mail]

EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781

*Available from Germany, France, Italy, UK

CENTRAL/SOUTH AMERICA:

Spanish Phone: [phone] (Mon–Fri 8:00am to 5:00pm MST)

Email: ONlit–[e-mail]

ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support

Phone: [phone] (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)

Toll Free from Hong Kong & Singapore:
001–800–4422–3781

Email: ONlit–[e-mail]

JAPAN: ON Semiconductor, Japan Customer Focus Center

4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031

Phone: [phone]
Email: [e-mail]

ON Semiconductor Website: http://onsemi.com

For additional information, please contact your local
Sales Representative.

http://onsemi.com

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