查询MC1455BD供应商
MC1455, MC1455B,
NCV1455B
Timers
The MC1455 monolithic timing circuit is a highly stable controller
capable of producing accurate time delays or oscillation. Additional
terminals are provided for triggering or resetting if desired. In the time
delay mode, time is precisely controlled by one external resistor and
capacitor. For astable operation as an oscillator, the free−running
frequency and the duty cycle are both accurately controlled with two
external resistors and one capacitor. The circuit may be triggered and
reset on falling waveforms, and the output structure can source or sink
up to 200 mA or drive MTTL circuits.
• Direct Replacement for NE555 Timers
• Timing from Microseconds through Hours
• Operates in Both Astable and Monostable Modes
• Adjustable Duty Cycle
• High Current Output Can Source or Sink 200 mA
• Output Can Drive MTTL
• Temperature Stability of 0.005% per °C
• Normally ON or Normally OFF Output
38
10 k
0.1 F
t = 1.1; R and C = 22 sec
Time delay (t) is variable by
changing R and C (see Figure 16).
0.01 F
4
2
MC1455
5
1.0 k
6
R
7
1.0 F
1
1N4740
20M
C
MT2
G
−10 V
Figure 1. 22 Second Solid State Time Delay Relay Circuit
V
CC
8
5 k
Threshold
Control Voltage
Trigger
6
5
2
+
Comp
A
−
5 k
+
Comp
B
−
5 k
1
Gnd Reset
R
S
Flip
Flop
Inhibit/
Reset
Q
4
3.5 k
250 V
MT1
Load
1N4003
−
10 F
+
7
3
Discharge
Output
117 Vac/60 Hz
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MARKING
DIAGRAMS
XXXXXXXXX
AWL
8
1
YYWW
P1 SUFFIX
PLASTIC PACKAGE
CASE 626
8
8
1
D SUFFIX
PLASTIC PACKAGE
CASE 751
XXXXXX
ALYW
1
xx = Specific Device Code
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page ___ of this data sheet.
(Create − Named − OrderingInfoText.)
V
I
V
R
Reset 4 8
+
0.01 F
V
O
Test circuit for measuring DC parameters (to set output and
measure parameters):
a) When V
b) When V
c) When V
c) high, apply Reset voltage, and test for current flowing into Pin 7.
c) When Reset is not in use, it should be tied to V
5
Control
Voltage
Output
I
Sink
I
Source
2/3 VCC, VO is low.
S
1/3 VCC, VO is high.
S
is low, Pin 7 sinks current. To test for Reset, set V
O
MC1455
3
Gnd
1
CC
7
V
CC
Discharge
Threshold
6
Trigger
2
CC
700
V
S
2.0 k
I
th
O
.
CC
Figure 2. Representative Block Diagram Figure 3. General Test Circuit
Semiconductor Components Industries, LLC, 2004
March, 2004 − Rev. 8
1 Publication Order Number:
MC1455/D
MC1455, MC1455B, NCV1455B
MAXIMUM RATINGS (T
= +25°C, unless otherwise noted.)
A
Rating
Power Supply Voltage V
Discharge Current (Pin 7) I
Power Dissipation (Package Limitation)
P1 Suffix, Plastic Package
Derate above T
= +25°C
A
D Suffix, Plastic Package
Derate above T
= +25°C
A
Operating Temperature Range (Ambient)
MC1455B
MC1455
NCV1455B
Maximum Operating Die Junction Temperature T
Storage Temperature Range T
ELECTRICAL CHARACTERISTICS (T
Characteristics
Operating Supply Voltage Range V
Supply Current
= 5.0 V, RL =
V
CC
= 15 V, RL = , Low State (Note 1)
V
CC
= +25°C, VCC = +5.0 V to +15 V, unless otherwise noted.)
A
Symbol Min Typ Max Unit
CC
I
CC
4.5 − 16 V
−
−
Timing Error (R = 1.0 k to 100 k) (Note 2)
Initial Accuracy C = 0.1 F
Drift with Temperature
Drift with Supply Voltage
Threshold Voltage/Supply Voltage Vth/V
Trigger Voltage
V
= 15 V
CC
= 5.0 V
V
CC
V
Trigger Current I
Reset Voltage V
Reset Current I
Threshold Current (Note 3) I
Discharge Leakage Current (Pin 7) I
Control Voltage Level
= 15 V
V
CC
= 5.0 V
V
CC
Output Voltage Low
= 10 mA (VCC = 15 V)
I
Sink
I
= 50 mA (VCC = 15 V)
Sink
= 100 mA (VCC = 15 V)
I
Sink
I
= 200 mA (VCC = 15 V)
Sink
= 8.0 mA (VCC = 5.0 V)
I
Sink
= 5.0 mA (VCC = 5.0 V)
I
Sink
Output Voltage High
V
CC
V
CC
V
CC
= 15 V (I
= 15 V (I
= 5.0 V (I
Source
Source
Source
= 200 mA)
= 100 mA)
= 100 mA)
dischg
V
V
V
Rise Time Differential Output t
Fall Time Differential Output t
CC
T
T
R
R
th
CL
OL
OH
r
f
−
−
−
− 2/3 −
−
−
− 0.5 − A
0.4 0.7 1.0 V
− 0.1 − mA
− 0.1 0.25 A
− − 100 nA
9.0
2.6
−
−
−
−
−
−
−
12.75
2.75
− 100 − ns
− 100 − ns
1. ‘Supply current when output is high is typically 1.0 mA less.
2. Tested at V
3. This will determine the maximum value of R
= 0°C for MC1455, T
4. T
low
= +70°C for MC1455, T
T
high
5. NCV prefix is for Automotive and other applications requiring site and change control.
= 5.0 V and VCC = 15 V Monostable mode.
CC
= −40°C for MC1455B, NCV1455B
low
= +85°C for MC1455B, T
high
+ RB for 15 V operation. The maximum total R = 20 M.
A
= +125°C for NCV1455B
high
Symbol Value Unit
CC
7
P
D
P
D
T
A
+18 Vdc
200 mA
625
5.0
625
160
−40 to +85
mW
mW/°C
mW
°C/W
°C
0 to +70
−40 to +125
J
stg
+150 °C
−65 to +150 °C
mA
3.0
10
1.0
50
0.1
6.0
15
−
−
−
%
PPM/°C
%/V
V
5.0
1.67
−
−
V
10
3.33
11
4.0
V
0.1
0.4
2.0
2.5
−
0.25
0.25
0.75
2.5
−
−
0.35
V
12.5
13.3
3.3
−
−
−
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2
MC1455, MC1455B, NCV1455B
150
125
100
75
50
PW, PULSE WIDTH (ns min)
25
0
V
, MINIMUM TRIGGER VOLTAGE (x VCC = Vdc)
T(min)
Figure 4. Trigger Pulse Width
2.0
1.8
1.6
1.4
1.2
(Vdc)
OH
1.0
−V
0.8
CC
V
0.6
0.4
0.2
0
1.0
2.0 5.0 10 20 50 100
Figure 6. High Output Voltage Figure 7. Low Output Voltage
I
Source
25°C
25°C
(mA)
0°C
70°C
0.30.20.10
5.0 V ≤ VCC ≤ 15 V
0.4
10
25°C
8.0
6.0
4.0
, SUPPLY CURRENT (mA)
CC
2.0
I
0
, SUPPLY VOLTAGE (Vdc)
V
CC
Figure 5. Supply Current
10
(mA)
I
Sink
= 5.0 Vdc
CC
25°C
1.0
0.1
, LOW OUTPUT VOLTAGE (Vdc)
OL
V
0.01
1.0 2.0 5.0 10 20 50 100
@ V
155.0 10
10
1.0
0.1
, LOW OUTPUT VOLTAGE (Vdc)
OL
V
0.01
1.0
25°C
2.0 5.0 10 20 50 100
I
(mA)
Sink
Figure 8. Low Output Voltage
@ VCC = 10 Vdc
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, LOW OUTPUT VOLTAGE (Vdc)
V
3
OL
1.0
0.1
0.01
10
25°C
1.0
2.0 5.0 10 20 50 100
I
(mA)
Sink
Figure 9. Low Output Voltage
@ VCC = 15 Vdc
MC1455, MC1455B, NCV1455B
1.015
1.010
1.005
1.000
0.995
, DELAY TIME NORMALIZED
d
t
0.990
0.985
0101510 20
5.0
VCC, SUPPLY VOLTAGE (Vdc)
Figure 10. Delay Time versus Supply Voltage
300
250
200
1.015
1.010
1.005
1.000
0.995
, DELAY TIME NORMALIZED
d
t
0.990
0.985
− 75 − 50 −25 0 25 50 75 100 125
T
, AMBIENT TEMPERATURE (°C)
A
Figure 11. Delay Time versus Temperature
150
100
, PROPAGATION DELAY TIME (ns)t
pd
0°C
70°C
50
0
0
V
T(min)
25°C
0.1 0.2 0.3 0.4
, MINIMUM TRIGGER VOLTAGE (x VCC = Vdc)
Figure 12. Propagation Delay
versus Trigger Voltage
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MC1455, MC1455B, NCV1455B
Control Voltage
Threshold
V
CC
Comparator
Trigger
Comparator
1.0 k4.7 k 830 4.7k
5.0 k
Flip−Flop Output
6.8 k
Threshold
10 k
Trigger
Reset
Reset
Discharge
Gnd
Discharge
100 k
100
Figure 13. Representative Circuit Schematic
GENERAL OPERATION
The MC1455 is a monolithic timing circuit which uses an
external resistor − c apacitor n etwork a s i ts t iming e lement. I t
can be used in both the monostable (one−shot) and astable
modes with frequency and duty cycle controlled by the
capacitor and resistor values. While the timing is dependent
upon the external passive components, t he m onolithic c ircuit
provides the starting circuit, voltage comparison and other
functions needed f or a c omplete t iming c ircuit. I nternal t o t he
integrated circuit are two comparators, one for the input
signal and t he o ther f or c apacitor v oltage; a lso a f lip−flop and
digital output are included. The comparator reference
voltages are always a fixed ratio of the supply voltage thus
providing output timing independent of supply voltage.
7.0 k
3.9 k
Output
5.0 k
5.0 k
c b
4.7 k
e
c
220
4.7 k
b
has been triggered by an input signal, it cannot be retriggered
until the present timing period has been completed. The time
that the output is high is given by the equation t = 1.1 R
Various combinations of R and C and their associated times
are shown in Figure 16. The trigger pulse width must be less
than the timing period.
A reset pin is provided to discharge the capacitor, thus
interrupting the timing cycle. As long as the reset pin is low ,
the capacitor discharge transistor is turned “on” and
prevents the capacitor from charging. While the reset
voltage is applied the digital output will remain the same.
The reset pin should be tied to the supply voltage when not
in use.
C.
A
Monostable Mode
In the monostable mode, a capacitor and a single resistor
are used for the timing network. Both the threshold terminal
and the discharge transistor terminal are connected together
in this mode (refer to circuit in Figure 14). When the input
voltage to the trigger comparator falls below 1/3 V
CC
, the
comparator output triggers the flip−flop so that its output
sets low. This turns the capacitor discharge transistor “off”
and drives the digital output to the high state. This condition
allows the capacitor to charge at an exponential rate which
is set by the RC time constant. When the capacitor voltage
reaches 2/3 V
, the threshold comparator resets the
CC
flip−flop. This action discharges the timing capacitor and
returns the digital output to the low state. Once the flip−flop
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+VCC (5.0 V to 15 V)
R
R
L
Output
L
Trigger
Reset
4
3
2
MC1455
V
CC
8
Discharge
7
6
Threshold
5
Control
1
Voltage
0.01 F
R
A
C
Figure 14. Monostable Circuit
5
MC1455, MC1455B, NCV1455B
100
10
µ
1.0
0.1
C, CAPACITANCE ( F)
0.01
t = 50 s/cm
(RA = 10 k, C = 0.01 F, RL = 1.0 k, VCC = 15 V)
Figure 15. Monostable Waveforms Figure 16. Time Delay
+VCC (5.0 V to 15 V)
Output
3
Trigger
2
Reset
4
MC1455
R
L
R
L
V
CC
8
7Discharge
6Threshold
5
Control
1
Voltage
R
A
R
B
C
Figure 17. Astable Circuit Figure 18. Astable Waveforms
Astable Mode
In the astable mode the timer is connected so that it will
retrigger itself and cause the capacitor voltage to oscillate
between 1/3 V
and 2/3 VCC. See Figure 17.
CC
The external capacitor c hanges t o 2 /3 VCC through RA and
RB and discharges to 1/3 VCC through RB. By varying the
ratio of these resistors the duty cycle can be varied. The
charge and discharge times are independent of the supply
voltage.
The charge time (output high) is given by:
t1 0.695(RA RB)C
The discharge time (output low) is given by:
t2 0.695(RB)C
Thus the total period is given by:
T t1 t2 0.695(RA 2RB)C
0.001
10 s 100 s 1.0 ms 10 ms 100 ms 1.0 10 100
, TIME DELAY (s)
t
d
(R
= 5.1 k, C = 0.01 F, RL = 1.0 k; RB = 3.9 k, VCC = 15 V)
A
t = 20 s/cm
To obtain the maximum duty cycle RA must be as small as
possible; but it must also be large enough to limit the
discharge current (Pin 7 current) within the maximum rating
of the discharge transistor (200 mA).
The minimum value of R
VCC(Vdc)
R
A
100
10
µ
1.0
0.1
I7 (A)
is given by:
A
VCC(Vdc)
0.2
The frequency of oscillation is then:
f
1
1
(RA 2RB)C
and may be easily found as shown in Figure 19.
R
The duty cycle is given by:
DC
B
RA 2R
1.44
B
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6
C, CAPACITANCE ( F)
0.01
(R
+ 2 RB)
A
0.001
0.1 1.0 10 100 1.0 k 10 k 100
f, FREE RUNNING FREQUENCY (Hz)
Figure 19. Free Running Frequency
MC1455, MC1455B, NCV1455B
APPLICATIONS INFORMATION
Linear Voltage Ramp
In the monostable mode, the resistor can be replaced by a
constant current source to provide a l inear r amp v oltage. T he
capacitor still charges from 0 VCC to 2/3 VCC. The linear
ramp time is given by:
t =
V
2
CC
3
, where I =
1
V
CC
− VB − V
R
E
BE
If VB is much larger than VBE, then t can be made
independent of VCC.
V
CC
Digital
Output
Trigger
Reset 4
3
2
MC1455
1
8V
CC
0.01 F
R
E
2N4403
or Equiv
V
E
7
I
6
Sweep
5
Output
C
Control
Voltage
R1
V
R2
B
Missing Pulse Detector
The timer can be used to produce an output when an input
pulse fails to occur within the delay of the timer. To
accomplish this, set the time delay to be slightly longer than
the time between successive input pulses. The timing cycle
is then continuously reset by the input pulse train until a
change in frequency or a missing pulse allows completion of
the timing cycle, causing a change in the output level.
+V
(5.0 V to 15 V)
CC
V
CC
Discharge
7
Threshold
6
5
0.01 F
Control
Voltage
R
A
2N4403
or Equiv
C
Output
Input
R
L
Trigger
Reset
48
3
MC1455
2
1
Figure 20. Linear Voltage Sweep Circuit Figure 21. Missing Pulse Detector
t = 100 s/cm
= 10 k, R2 = 100 k, R1 = 39 k, C = 0.01 F, VCC = 15 V) (RA = 2.0 k, RL = 1.0 k, C = 0.01 F, VCC = 15 V)
(R
E
t = 500 s/cm
Figure 22. Linear Voltage Ramp Waveforms Figure 23. Missing Pulse Detector Waveforms
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7
MC1455, MC1455B, NCV1455B
Pulse Width Modulation
If the timer is triggered with a continuous pulse train in the
monostable mode of operation, the charge time of the
capacitor can be varied by changing the control voltage at
Pin 5. In this manner, the output pulse width can be
modulated by applying a modulating signal that controls the
threshold voltage.
+VCC (5.0 V to 15 V)
Output
Clock
Input
R
L
3
2
48
MC1455
1
Figure 24. Pulse Width Modulator
9.1 k
84
6
7
1.0 F
2
MC1455
1
5
3
0.01 F
0.001 F
27 k
5.0 F
R
A
7
6
C
5
Modulation
Input
Figure 25. Pulse Width Modulation Waveforms
T est Sequences
Several timers can be connected to drive each other for
sequential timing. An example is shown in Figure 26 where
(RA = 10 k, C = 0.02 F, VCC = 15 V)
t = 0.5 ms/cm
the sequence is started by triggering the first timer which
runs for 10 ms. The output then switches low momentarily
and starts the second timer which runs for 50 ms and so forth.
V
(5.0 V to 15 V)
CC
5.0 F
18.2 k
6
7
2
84
5
MC1455
3
1
9.1 k
84
6
7
MC1455
2
1
27 k
0.01 F 0.01 F
5
3
0.001 F
Load
Load
Load
Figure 26. Sequential Timer
DEVICE ORDERING INFORMATION
Device Operating Temperature Range Package Shipping
MC1455P1 TA = 0°C to +70°C Plastic Dip 50 Units/Rail
MC1455D TA = 0°C to +70°C SO−8 98 Units/Rail
MC1455BD TA = −40°C to +85°C SO−8 98 Units/Rail
MC1455BP1 TA = −40°C to +85°C Plastic Dip 50 Units/Rail
NCV1455BDR2* TA = −40°C to +125°C SO−8 2500/Tape & Rail
*NCV prefix is for automotive and other applications requiring site and control changes.
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8
NOTE 2
−T−
SEATING
PLANE
H
58
−B−
14
F
−A−
C
N
D
G
0.13 (0.005) B
MC1455, MC1455B, NCV1455B
PACKAGE DIMENSIONS
P1 SUFFIX
PLASTIC PACKAGE
CASE 626−05
ISSUE L
L
J
K
M
M
A
T
M
M
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
DIM MIN MAX MIN MAX
A 9.40 10.16 0.370 0.400
B 6.10 6.60 0.240 0.260
C 3.94 4.45 0.155 0.175
D 0.38 0.51 0.015 0.020
F 1.02 1.78 0.040 0.070
G 2.54 BSC 0.100 BSC
H 0.76 1.27 0.030 0.050
J 0.20 0.30 0.008 0.012
K 2.92 3.43 0.115 0.135
L 7.62 BSC 0.300 BSC
M −−− 10 −−− 10
N 0.76 1.01 0.030 0.040
INCHESMILLIMETERS
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9
−Y−
−Z−
MC1455, MC1455B, NCV1455B
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC PACKAGE
CASE 751−07
(SO−8)
ISSUE AA
−X−
B
H
A
58
1
4
G
D
0.25 (0.010) Z
M
S
Y
0.25 (0.010)
C
SEATING
PLANE
SXS
M
0.10 (0.004)
M
Y
K
N
X 45
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
MILLIMETERS
DIMAMIN MAX MIN MAX
4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0 8 0 8
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
INCHES
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC1455/D
10
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