MC14543B
BCD-to-Seven Segment
Latch/Decoder/Driver for
Liquid Crystals
The MC14543B BCD–to–seven segment latch/decoder/driver is
designed for use with liquid crystal readouts, and is constructed with
complementary MOS (CMOS) enhancement mode devices. The
circuit provides the functions of a 4–bit storage latch and an 8421
BCD–to–seven segment decoder and driver. The device has the
capability to invert the logic levels of the output combination. The
phase (Ph), blanking (BI), and latch disable (LD) inputs are used to
reverse the truth table phase, blank the display, and store a BCD code,
respectively . For liquid crystal (LC) readouts, a square wave is applied
to the Ph input of the circuit and the electrically common backplane of
the display. The outputs of the circuit are connected directly to the
segments of the LC readout. For other types of readouts, such as
light–emitting diode (LED), incandescent, gas discharge, and
fluorescent readouts, connection diagrams are given on this data sheet.
Applications include instrument (e.g., counter, DVM etc.) display
driver, computer/calculator display driver, cockpit display driver, and
various clock, watch, and timer uses.
• Latch Storage of Code
• Blanking Input
• Readout Blanking on All Illegal Input Combinations
• Direct LED (Common Anode or Cathode) Driving Capability
• Supply Voltage Range = 3.0 V to 18 V
• Capable of Driving 2 Low–power TTL Loads, 1 Low–power Schottky
TTL Load or 2 HTL Loads Over the Rated Temperature Range
• Pin–for–Pin Replacement for CD4056A (with Pin 7 Tied to V
• Chip Complexity: 207 FETs or 52 Equivalent Gates
MAXIMUM RATINGS (Voltages Referenced to V
Symbol
V
DD
V
I
in
P
T
T
stg
I
OHmax
I
OLmax
P
OHmax
P
OLmax
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C
4. P
OHmax
DC Supply Voltage Range –0.5 to +18.0 V
Input Voltage Range, All Inputs –0.5 to VDD + 0.5 V
in
DC Input Current per Pin ±10 mA
Power Dissipation,
D
Operating Temperature Range –55 to +125 °C
A
Storage Temperature Range –65 to +150 °C
Maximum Continuous Output
Drive Current (Source or Sink)
Maximum Continuous Output
= IOH (VOH – VDD) and P
Parameter Value Unit
per Package (Note 3.)
Power (Source or Sink)
(4.)
= IOL (VOL – VSS)
OLmax
) (Note 2.)
SS
500 mW
10
(per Output)
70
(per Output)
SS
mA
mW
).
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MARKING
DIAGRAMS
16
PDIP–16
P SUFFIX
CASE 648
SOIC–16
D SUFFIX
CASE 751B
SOEIAJ–16
F SUFFIX
CASE 966
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
MC14543BCP
AWLYYWW
1
16
14543B
AWLYWW
1
16
MC14543B
ALYW
1
ORDERING INFORMATION
Device Package Shipping
MC14543BCP PDIP–16 2000/Box
MC14543BD SOIC–16 48/Rail
MC14543BDR2 SOIC–16 2500/Tape & Reel
MC14543BF SOEIAJ–16 See Note 1.
MC14543BFEL SOEIAJ–16 See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
This device contains protection circuitry to guard
against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high–impedance circuit. For proper
operation, Vin and V
range V
logic voltage level (e.g., either V
puts must be left open.
(Vin or V
SS
Unused inputs must always be tied to an appropriate
should be constrained to the
out
) VDD.
out
or VDD). Unused out-
SS
Semiconductor Components Industries, LLC, 2000
August, 2000 – Rev. 4
1 Publication Order Number:
MC14543B/D
MC14543B
PIN ASSIGNMENT
1
LD
2
C
3
B
D
4
A
PH
6
7
BI
8
V
SS
V
16
DD
15
f
g
14
e
13
d
125
11
c
10
b
9
a
TRUTH TABLE
Inputs Outputs
LD BI Ph* D C B A a b c d e f g Display
X 1 0 X X X X 0 0 0 0 0 0 0 Blank
1 0 0 00 001111110 0
1 0 0 00 010110000 1
1 0 0 00 101101101 2
1 0 0 00 111111001 3
1 0 0 01 000110011 4
1 0 0 01 011011011 5
1 0 0 01 101011111 6
1 0 0 01 111110000 7
1 0 0 10 001111111 8
1 0 0 10 011111011 9
1 0 0 1 0 1 0 0 0 0 0 0 0 0 Blank
1 0 0 1 0 1 1 0 0 0 0 0 0 0 Blank
1 0 0 1 1 0 0 0 0 0 0 0 0 0 Blank
1 0 0 1 1 0 1 0 0 0 0 0 0 0 Blank
1 0 0 1 1 1 0 0 0 0 0 0 0 0 Blank
1 0 0 1 1 1 1 0 0 0 0 0 0 0 Blank
000XXXX ** **
† † † † Inverse of Output Display
X = Don’t care
† = Above Combinations
* = For liquid crystal readouts, apply a square wave to Ph
For common cathode LED readouts, select Ph = 0
For common anode LED readouts, select Ph = 1
** = Depends upon the BCD code previously applied when LD = 1
Combinations as above
Above
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2
MC14543B
V
DD
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
V
DD
Characteristic Symbol
Output Voltage “0” Level
V
= VDD or 0
in
V
OL
Vdc
5.0
10
15
V
= 0 or V
in
“1” Level
DD
V
OH
5.0
10
15
Input Voltage “0” Level
(V
= 4.5 or 0.5 Vdc)
O
= 9.0 or 1.0 Vdc)
(V
O
(V
= 13.5 or 1.5 Vdc)
O
“1” Level
(V
= 0.5 or 4.5 Vdc)
O
(V
= 1.0 or 9.0 Vdc)
O
(V
= 1.5 or 13.5 Vdc)
O
Output Drive Current
(V
= 2.5 Vdc) Source
OH
= 4.6 Vdc)
(V
OH
(V
= 0.5 Vdc)
OH
(V
= 9.5 Vdc)
OH
(V
= 13.5 Vdc)
OH
(VOL = 0.4 Vdc) Sink
(V
= 0.5 Vdc)
OL
= 9.5 Vdc)
(V
OL
(V
= 1.5 Vdc)
OL
Input Current I
Input Capacitance C
Quiescent Current
(Per Package) V
= 0 µA
I
out
Total Supply Current
= 0 or VDD,
in
(6.) (7.)
(Dynamic plus Quiescent,
Per Package)
= 50 pF on all outputs, all
(C
L
V
IL
5.0
10
15
V
IH
5.0
10
15
I
OH
5.0
5.0
10
10
15
I
OL
5.0
10
10
15
in
in
I
DD
15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdc
— — — — 5.0 7.5 — — pF
5.0
10
15
I
T
5.0
10
15
buffers switching)
5. Noise immunity specified for worst–case input combination.
Noise Margin for both “1” and “0” level = 1.0 V min @ V
= 2.0 V min @ V
= 2.5 V min @ V
6. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDf
where: I
is in µA (per package), CL in pF, VDD in V, and f in kHz is input frequency.
T
7. The formulas given are for the typical characteristics only at 25C.
– 55C 25C 125C
Min Max Min Typ
—
—
—
4.95
9.95
14.95
—
—
—
3.5
7.0
11
– 3.0
– 0.64
—
– 1.6
– 4.2
0.64
1.6
—
4.2
—
—
—
= 5.0 V
DD
= 10 V
DD
= 15 V
DD
SS
)
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
—
—
—
—
—
—
—
—
—
—
—
—
5.0
10
20
(5.)
—
—
—
4.95
9.95
14.95
—
—
—
3.5
7.0
11
– 2.4
– 0.51
—
– 1.3
– 3.4
0.51
1.3
—
3.4
—
—
—
0
0
0
5.0
10
15
2.25
4.50
6.75
2.75
5.50
8.25
– 4.2
– 0.88
– 10.1
– 2.25
– 8.8
0.88
2.25
10.1
8.8
0.005
0.010
0.015
IT = (1.6 µA/kHz) f + I
IT = (3.1 µA/kHz) f + I
IT = (4.7 µA/kHz) f + I
Max Min Max
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
—
—
—
—
—
—
—
—
—
—
—
—
5.0
10
20
DD
DD
DD
—
—
—
4.95
9.95
14.95
—
—
—
3.5
7.0
11
– 1.7
– 0.36
—
– 0.9
– 2.4
0.36
0.9
—
2.4
—
—
—
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
—
—
—
—
—
—
—
—
—
—
150
300
600
Unit
Vdc
Vdc
Vdc
Vdc
mAdc
mAdc
µAdc
µAdc
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3
MC14543B
SWITCHING CHARACTERISTICS
(8.)
(C
= 50 pF, T
L
= 25C)
A
Characteristic Symbol V
Output Rise Time
t
= (3.0 ns/pF) CL + 30 ns
TLH
= (1.5 ns/pF) CL + 15 ns
t
TLH
= (1.1 ns/pF) CL + 10 ns
t
TLH
Output Fall Time
t
= (1.5 ns/pF) CL + 25 ns
THL
= (0.75 ns/pF) CL + 12.5 ns
t
THL
t
= (0.55 ns/pF) CL + 12.5 ns
THL
Turn–Off Delay Time
t
= (1.7 ns/pF) CL + 520 ns
PLH
= (0.66 ns/pF) CL + 217 ns
t
PLH
t
= (0.5 ns/pF) CL + 160 ns
PLH
Turn–On Delay Time
t
= (1.7 ns/pF) CL + 420 ns
PHL
= (0.66 ns/pF) CL + 172 ns
t
PHL
t
= (0.5 ns/pF) CL + 130 ns
PHL
Setup Time t
Hold Time t
Latch Disable Pulse Width (Strobing Data) t
8. The formulas given are for the typical characteristics only.
t
TLH
t
THL
t
PLH
t
PHL
WH
DD
Min Typ Max Unit
ns
5.0
10
15
—
—
—
100
50
40
200
100
80
ns
5.0
10
15
—
—
—
100
50
40
200
100
80
ns
5.0
10
15
—
—
—
605
250
185
1210
500
370
ns
5.0
10
15
su
5.0
10
15
h
5.0
10
15
5.0
10
15
—
—
—
350
450
500
40
30
20
250
100
80
505
205
155
125
50
40
1650
660
495
—
—
—
—
—
—
—
—
—
ns
ns
ns
A5
B3
C2
D4
LD1
VDD = PIN 16
V
= PIN 8
SS
LOGIC DIAGRAM
BI7
9a
10b
11c
12d
13e
15f
14g
PHASE6
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4
MC14543B
0
P
OHmax
= 70 mWdc
VDD = 5.0 Vdc
-6.0
-12
-18
, SOURCE CURRENT (mAdc)
OH
I
VDD = 15 Vdc
-24
-16 -12 -8.0 -4.0 0
VDD = 10 Vdc
VSS = 0 Vdc
(VOH - VDD), SOURCE DEVICE VOLTAGE (Vdc)
Figure 1. Typical Output Source
Characteristics
24
VDD = 15 Vdc
18
12
VDD = 10 Vdc
, SINK CURRENT (mAdc)
OL
6.0
I
VDD = 5.0 Vdc
0
0 4.0 8.0 12 16
P
OLmax
= 70 mWdc
VSS = 0 Vdc
(VOL - VSS), SINK DEVICE VOLTAGE (Vdc)
Figure 2. Typical Output Sink
Characteristics
(a) Inputs D, Ph, and BI low, and Inputs A, B, and LD high.
20 ns 20 ns
C
t
PHL
g
90%
10%
90%
50%
t
THL
t
PLH
50%
t
TLH
10%
V
DD
V
SS
V
OH
V
OL
Inputs BI and Ph low, and Inputs D and LD high.
f in respect to a system clock.
50%
L
20 ns
loads.
All outputs connected to respective C
20 ns
A, B, AND C
10%
90%
1
2f
50% DUTY CYCLE
ANY OUTPUT
Figure 3. Dynamic Power Dissipation
Signal Waveforms
(b) Inputs D, Ph, and BI low, and Inputs A and B high.
LD
C
V
DD
V
SS
V
OH
V
OL
g
(c) Data DCBA strobed into latches
LD
90%
t
su
10%
50%
50% 50%
50%
t
WH
t
h
20 ns
V
DD
V
SS
V
DD
V
SS
V
OH
V
OL
V
DD
V
SS
Figure 4. Dynamic Signal Waveforms
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5
MC14543B
CONNECTIONS TO VARIOUS DISPLAY READOUTS
LIQUID CRYSTAL (LC) READOUT
MC14543B
OUTPUT
Ph
ONE OF SEVEN SEGMENTS
SQUARE WAVE
COMMON
BACKPLANE
(V
TO VDD)
SS
LIGHT EMITTING DIODE (LED) READOUT
COMMON
V
SS
CATHODE LED
MC14543B
OUTPUT
Ph
NOTE: Bipolar transistors may be added for gain (for VDD 10 V or I
COMMON
ANODE LED
MC14543B
OUTPUT
Ph
V
DD
≥ 10 mA).
out
INCANDESCENT READOUT
APPROPRIATE
VOLTAGE
MC14543B
OUTPUT
Ph
V
SS
GAS DISCHARGE READOUT
APPROPRIATE
V
DD
MC14543B
OUTPUT
Ph
V
SS
VOLTAGE
CONNECTIONS TO SEGMENTS
a
b
fg
= PIN 8
SS
c
d
e
VDD = PIN 16
V
DISPLAY
0123456789
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6
–T–
–A–
916
B
18
F
C
S
–T–
H
G
D
16 PL
0.25 (0.010) T
K
M
–A–
16 9
–B–
18
G
K
C
SEATING
PLANE
D
16 PL
0.25 (0.010) A
M
S
B
T
S
MC14543B
PACKAGE DIMENSIONS
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
L
SEATING
PLANE
J
M
A
SOIC–16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
8 PLP
M
0.25 (0.010) B
M
S
X 45
R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM MIN MAX MIN MAX
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
M
F
J
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
DIM MIN MAX MIN MAX
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
MILLIMETERSINCHES
INCHESMILLIMETERS
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7
16 9
1
Z
D
e
b
0.13 (0.005)
M
8
H
E
E
A
A
1
0.10 (0.004)
MC14543B
PACKAGE DIMENSIONS
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
ISSUE O
L
E
M
L
DETAIL P
VIEW P
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
Q
1
c
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
MILLIMETERS
DIM MIN MAX MIN MAX
--- 2.05 --- 0.081
A
A
0.05 0.20 0.002 0.008
1
0.35 0.50 0.014 0.020
b
0.18 0.27 0.007 0.011
c
9.90 10.50 0.390 0.413
D
5.10 5.45 0.201 0.215
E
1.27 BSC 0.050 BSC
e
H
7.40 8.20 0.291 0.323
E
0.50 0.85 0.020 0.033
L
L
1.10 1.50 0.043 0.059
E
0
M
Q
0.70 0.90 0.028 0.035
1
--- 0.78 --- 0.031
Z
INCHES
10
10
0
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MC14543B/D
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