MC14536B
Programmable Timer
The MC14536B programmable timer is a 24–stage binary ripple
counter with 16 stages selectable by a binary code. Provisions for an
on–chip RC oscillator or an external clock are provided. An on–chip
monostable circuit incorporating a pulse–type output has been
included. By selecting the appropriate counter stage in conjunction
with the appropriate input clock frequency, a variety of timing can be
achieved.
0
• 24 Flip–Flop Stages — Will Count From 2
• Last 16 Stages Selectable By Four–Bit Select Code
• 8–Bypass Input Allows Bypassing of First Eight Stages
• Set and Reset Inputs
• Clock Inhibit and Oscillator Inhibit Inputs
• On–Chip RC Oscillator Provisions
• On–Chip Monostable Output Provisions
• Clock Conditioning Circuit Permits Operation With Very Long Rise
and Fall Times
• Test Mode Allows Fast Test Sequence
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS (Voltages Referenced to V
Symbol
V
DD
Vin, V
Iin, I
P
T
T
stg
T
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
to the range V
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
DC Supply Voltage Range –0.5 to +18.0 V
Input or Output Voltage Range
out
Input or Output Current
out
Power Dissipation,
D
Operating Temperature Range –55 to +125 °C
A
Storage Temperature Range –65 to +150 °C
Lead Temperature
L
SS
or VDD). Unused outputs must be left open.
SS
Parameter Value Unit
(DC or Transient)
(DC or Transient) per Pin
per Package (Note 3.)
(8–Second Soldering)
and V
(Vin or V
) VDD.
out
in
24
to 2
) (Note 2.)
SS
–0.5 to VDD + 0.5 V
±10 mA
500 mW
260 °C
should be constrained
out
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MARKING
DIAGRAMS
16
PDIP–16
P SUFFIX
CASE 648
SOIC–16
DW SUFFIX
CASE 751G
SOEIAJ–16
F SUFFIX
CASE 966
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
MC14536BCP
AWLYYWW
1
16
14536B
AWLYYWW
1
16
MC14536B
ALYW
1
ORDERING INFORMATION
Device Package Shipping
MC14536BCP PDIP–16 2000/Box
MC14536BDW SOIC–16 47/Rail
MC14536BDWR2 SOIC–16 1000/Tape & Reel
MC14536BF SOEIAJ–16 See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
Semiconductor Components Industries, LLC, 2001
February, 2001 – Rev. 7
1 Publication Order Number:
MC14536B/D
MC14536B
OSC. INHIBIT14
IN
1
3
OUT
SET
RESET
IN 1
OUT 1
OUT 2
8-BYPASS
CLOCK INH
V
1
2
3
4
6
7
8
SS
16
15
14
13
125
11
10
9
V
DD
MONO-IN
OSC INH
DECODE
D
C
B
A
Figure 1. Pin Assignment
A9
B10
C11
D12
8 BYPASSSETRESETCLOCK INH.
STAGES 9 THRU 24
Q24Q23Q22Q21Q20Q19Q18Q17Q16Q15Q14Q13Q12Q11Q10Q
9
DECODER
MONOSTABLE
MULTIVIBRATOR
13MONO-IN15
DECODE
OUT
7216
STAGES
1 THRU 8
4
5
OUT
1
2
V
= PIN 16
DD
V
= PIN 8
SS
Figure 2. Block Diagram
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2
MC14536B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
– 55C 25C 125C
Typ
(Note 4.)
0
0
0
5.0
10
15
2.25
4.50
6.75
2.75
5.50
8.25
– 1.7
– 0.36
– 0.9
– 3.5
– 4.2
– 0.88
– 2.25
– 8.8
0.88
2.25
8.8
0.010
0.020
0.030
Max Min Max
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5.0
10
20
DD
DD
DD
—
—
—
4.95
9.95
14.95
—
—
—
3.5
7.0
11
– 0.7
– 0.14
– 0.35
– 1.1
– 1.7
– 0.36
– 0.9
– 2.4
0.36
0.9
2.4
—
—
—
0.05
0.05
0.05
Characteristic Symbol
Output Voltage “0” Level
V
= VDD or 0
in
“1” Level
V
= 0 or V
in
DD
Input Voltage “0” Level
(V
= 4.5 or 0.5 Vdc)
O
= 9.0 or 1.0 Vdc)
(V
O
(V
= 13.5 or 1.5 Vdc)
O
“1” Level
(V
= 0.5 or 4.5 Vdc)
O
= 1.0 or 9.0 Vdc)
(V
O
(V
= 1.5 or 13.5 Vdc)
O
Output Drive Current
(V
= 2.5 Vdc) Source
OH
= 4.6 Vdc) Pins 4 & 5
(V
OH
(V
= 9.5 Vdc)
OH
(V
= 13.5 Vdc)
OH
(VOH = 2.5 Vdc) Source
(V
= 4.6 Vdc) Pin 13
OH
= 9.5 Vdc)
(V
OH
(V
= 13.5 Vdc)
OH
(VOL = 0.4 Vdc) Sink
(V
= 0.5 Vdc)
OL
(V
= 1.5 Vdc)
OL
Input Current I
Input Capacitance
(V
= 0)
in
Quiescent Current
(Per Package)
Total Supply Current (Note 5., 6.)
(Dynamic plus Quiescent,
Per Package)
(C
= 50 pF on all outputs, all
L
V
DD
Vdc
V
OL
5.0
10
15
V
OH
5.0
10
15
V
IL
5.0
10
15
V
IH
5.0
10
15
I
OH
5.0
5.0
10
15
5.0
5.0
10
15
I
OL
5.0
10
15
in
C
in
I
DD
15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdc
— — — — 5.0 7.5 — — pF
5.0
10
15
I
T
5.0
10
15
Min Max Min
—
—
—
4.95
9.95
14.95
—
—
—
3.5
7.0
11
– 1.2
– 0.25
– 0.62
– 1.8
– 3.0
– 0.64
– 1.6
– 4.2
0.64
1.6
4.2
—
—
—
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5.0
10
20
14.95
– 0.25
– 2.4
– 0.51
—
—
—
4.95
9.95
—
—
—
3.5
7.0
11
– 1.0
– 0.5
– 1.5
– 1.3
– 3.4
0.51
1.3
3.4
—
—
—
IT = (1.50 µA/kHz) f + I
IT = (2.30 µA/kHz) f + I
IT = (3.55 µA/kHz) f + I
buffers switching)
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25C.
6. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: I
is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.003.
T
—
—
—
1.5
3.0
4.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
150
300
600
Unit
Vdc
Vdc
Vdc
Vdc
mAdc
mAdc
mAdc
µAdc
µAdc
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3
MC14536B
SWITCHING CHARACTERISTICS (Note 7.) (C
Characteristic Symbol V
= 50 pF, T
L
= 25C)
A
DD
Min Typ
Max Unit
(Note 8.)
Output Rise and Fall Time (Pin 13)
t
, t
TLH
t
TLH
t
TLH
= (1.5 ns/pF) CL + 25 ns
THL
, t
= (0.75 ns/pF) CL + 12.5 ns
THL
, t
= (0.55 ns/pF) CL + 9.5 ns
THL
Propagation Delay Time
Clock to Q1, 8–Bypass (Pin 6) High
, t
t
PLH
t
PLH
t
PLH
= (1.7 ns/pF) CL + 1715 ns
PHL
, t
= (0.66 ns/pF) CL + 617 ns
PHL
, t
= (0.5 ns/pF) CL + 425 ns
PHL
Clock to Q1, 8–Bypass (Pin 6) Low
t
, t
PLH
t
PLH
t
PLH
= (1.7 ns/pF) CL + 3715 ns
PHL
, t
= (0.66 ns/pF) CL + 1467 ns
PHL
, t
= (0.5 ns/pF) CL + 1075 ns
PHL
Clock to Q16
t
, t
PHL
t
PHL
t
PHL
Reset to Q
t
PHL
t
PHL
t
PHL
= (1.7 ns/pF) CL + 6915 ns
PLH
, t
= (0.66 ns/pF) CL + 2967 ns
PLH
, t
= (0.5 ns/pF) CL + 2175 ns
PLH
n
= (1.7 ns/pF) CL + 1415 ns
= (0.66 ns/pF) CL + 567 ns
= (0.5 ns/pF) CL + 425 ns
Clock Pulse Width t
Clock Pulse Frequency
(50% Duty Cycle)
Clock Rise and Fall Time t
t
TLH
t
t
PLH
t
t
PLH
t
t
PLH
t
t
TLH
t
THL
PHL
PHL
PHL
PHL
WH
f
cl
THL
,
5.0
10
15
—
—
—
100
50
40
200
100
80
,
5.0
10
15
—
—
—
1800
650
450
3600
1300
1000
,
5.0
10
15
—
—
—
3.8
1.5
1.1
7.6
3.0
2.3
,
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
,
5.0
10
—
—
—
—
—
—
600
200
170
—
—
—
7.0
3.0
2.2
1500
600
450
300
100
85
1.2
3.0
5.0
No Limit
14
6.0
4.5
3000
1200
900
—
—
—
0.4
1.5
2.0
15
Reset Pulse Width t
WH
5.0
10
15
1000
400
300
500
200
150
—
—
—
7. The formulas given are for the typical characteristics only at 25C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
ns
ns
µs
µs
ns
ns
MHz
—
ns
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4
MC14536B
PIN DESCRIPTIONS
INPUTS
SET (Pin 1) — A high on Set asynchronously forces
Decode Out to a high level. This is accomplished by setting
an output conditioning latch to a high level while at the same
time resetting the 24 flip–flop stages. After Set goes low
(inactive), the occurrence of the first negative clock
transition on IN
causes Decode Out to go low. The
1
counter’s flip–flop stages begin counting on the second
negative clock transition of IN
. When Set is high, the
1
on–chip RC oscillator is disabled. This allows for very
low–power standby operation.
RESET (Pin 2) — A high on Reset asynchronously
forces Decode Out to a low level; all 24 flip–flop stages are
also reset to a low level. Like the Set input, Reset disables
the on–chip RC oscillator for standby operation.
IN
(Pin 3) — The device’s internal counters advance on
1
the negative–going edge of this input. IN
may be used as an
1
external clock input or used in conjunction with OUT1 and
OUT2 to form an RC oscillator. When an external clock is
used, both OU T1 and OU T2 may be left unconnected or
used to drive 1 LSTTL or several CMOS loads.
8–BYPASS (Pin 6) — A high on this input causes the first
8 flip–flop stages to be bypassed. This device essentially
becomes a 16–stage counter with all 16 stages selectable.
Selection is accomplished by the A, B, C, and D inputs. (See
the truth tables.)
CLOCK INHIBIT (Pin 7) — A high on this input
disconnects the first counter stage from the clocking source.
This holds the present count and inhibits further counting.
However, the clocking source may continue to run.
Therefore, when Clock Inhibit is brought low, no oscillator
start–up time is required. When Clock Inhibit is low, the
counter will start counting on the occurrence of the first
negative edge of the clocking source at IN
.
1
OSC INHIBIT (Pin 14) — A high level on this pin stops
the RC oscillator which allows for very low–power standby
operation. May also be used, in conjunction with an external
clock, with essentially the same results as the Clock Inhibit
input.
MONO–IN (Pin 15) — Used as the timing pin for the
on–chip monostable multivibrator. If the Mono–In input is
connected to V
, the monostable circuit is disabled, and
SS
Decode Out is directly connected to the selected Q output.
The monostable circuit is enabled if a resistor is connected
between Mono–In and V
. This resistor and the device’s
DD
internal capacitance will determine the minimum output
pulse widths. With the addition of an external capacitor to
V
, the pulse width range may be extended. For reliable
SS
operation the resistor value should be limited to the range of
5 kΩ to 100 kΩ and the capacitor value should be limited to
a maximum of 1000 pf. (See figures 3, 4, 5, and 10).
A, B, C, D (Pins 9, 10, 11, 12) — These inputs select the
flip–flop stage to be connected to Decode Out. (See the truth
tables.)
OUTPUTS
OUT1, OUT2 (Pin 4, 5) — Outputs used in conjunction
with IN1 to form an RC oscillator. These outputs are
buffered and may be used for 2
0
frequency division of an
external clock.
DECODE OUT (Pin 13) — Output function depends on
configuration. When the monostable circuit is disabled, this
output is a 50% duty cycle square wave during free run.
TEST MODE
The test mode configuration divides the 24 flip–flop
stages into three 8–stage sections to facilitate a fast test
sequence. The test mode is enabled when 8–Bypass, Set a nd
Reset are at a high level. (See Figure 8.)
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