ON Semiconductor MC14518B Technical data

MC14518B

Dual Up Counters

The MC14518B dual BCD counter and the MC14520B dual binary
counter are constructed with MOS P–channel and N–channel
enhancement mode devices in a single monolithic structure. Each
consists of two identical, independent, internally synchronous 4–stage
counters. The counter stages are type D flip–flops, with
interchangeable Clock and Enable lines for incrementing on either the
positive–going or negative–going transition as required when
cascading multiple stages. Each counter can be cleared by applying a
high level on the Reset line. In addition, the MC14518B will count out
of all undefined states within two clock periods. These complementary
MOS up counters find primary use in multi–stage synchronous or
ripple counting applications requiring low power dissipation and/or
high noise immunity.

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Internally Synchronous for High Internal and External Speeds

• Logic Edge–Clocked Design — Incremented on Positive Transition

of Clock or Negative Transition on Enable

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

MAXIMUM RATINGS (Voltages Referenced to V

Symbol Parameter Value Unit

V

DD

Vin, V

Iin, I

P

T

T

stg

T

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C

This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
to the range V

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V

DC Supply Voltage Range –0.5 to +18.0 V
Input or Output Voltage Range

out

out

D

A

L

(DC or Transient)

Input or Output Current

(DC or Transient) per Pin

Power Dissipation,

per Package (Note 3.)
Operating Temperature Range –55 to +125 °C
Storage Temperature Range –65 to +150 °C
Lead Temperature

(8–Second Soldering)

 (Vin or V

SS

or VDD). Unused outputs must be left open.

SS

)  VDD.

out

) (Note 2.)

SS

–0.5 to VDD + 0.5 V

±10 mA

500 mW

260 °C

and V

in

should be constrained

out

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MARKING

DIAGRAMS

16

PDIP–16

P SUFFIX

CASE 648

SOIC–16
DW SUFFIX
CASE 751G

SOEIAJ–16

F SUFFIX

CASE 966

A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week

MC14518BCP

AWLYYWW

1

16

14518B

AWLYYWW

1

16

MC14518B

ALYW

1

ORDERING INFORMATION

Device Package Shipping

MC14518BCP PDIP–16 2000/Box
MC14518BDW SOIC–16 47/Rail

MC14518BDWR2 SOIC–16 1000/Tape & Reel
MC14518BF SOEIAJ–16 See Note 1.

MC14518BFEL SOEIAJ–16 See Note 1.

1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.

 Semiconductor Components Industries, LLC, 2000

August, 2000 – Rev. 4

1 Publication Order Number:

MC14518B/D

MC14518B

PIN ASSIGNMENT

CLOCK

ENABLE

CLOCK

10

ENABLE

15

1

C

A

2

E

A

3

Q0

A

Q1

4

A

Q2

A

Q3

6

A

7

R

A

8

V

SS

BLOCK DIAGRAM

1

2

7

9

16

15

14

13

125

11

10

9

VDD = PIN 16

VSS = PIN 8

V

R

Q3

Q2

Q1

Q0

E

C

DD

B

B

B

B

B

B

B

Q0

3
4

Q1

C

Q2

5
6

Q3

R

11

Q0

12

Q1

C

R

Q2
Q3

13
14

TRUTH TABLE

Clock Enable Reset Action

1 0 Increment Counter

0 0 Increment Counter

X 0 No Change

X 0 No Change

0 0 No Change

1 0 No Change

X X 1 Q0 thru Q3 = 0

X = Don’t Care

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2

MC14518B

V

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

DD

Characteristic Symbol

Output Voltage “0” Level

V

= VDD or 0

in

“1” Level

V

= 0 or V

in

DD

Input Voltage “0” Level

= 4.5 or 0.5 Vdc)

(V

O

(V

= 9.0 or 1.0 Vdc)

O

(V

= 13.5 or 1.5 Vdc)

O

“1” Level

= 0.5 or 4.5 Vdc)

(V

O

(V

= 1.0 or 9.0 Vdc)

O

(V

= 1.5 or 13.5 Vdc)

O

Output Drive Current

(V

= 2.5 Vdc) Source

OH

= 4.6 Vdc)

(V

OH

(V

= 9.5 Vdc)

OH

(V

= 13.5 Vdc)

OH

(VOL = 0.4 Vdc) Sink
(V

= 0.5 Vdc)

OL

(V

= 1.5 Vdc)

OL

Input Current I
Input Capacitance

(V

= 0)

in

Quiescent Current

(Per Package)

Total Supply Current

(5.) (6.)

(Dynamic plus Quiescent,
Per Package)
(C

= 50 pF on all outputs, all

L

Vdc

V

OL

5.0
10
15

V

OH

5.0
10
15

V

IL

5.0
10
15

V

IH

5.0
10
15

I

OH

5.0

5.0
10
15

I

OL

5.0
10
15

in

C

in

I

DD

15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdc

— — — — 5.0 7.5 — — pF

5.0
10
15

I

T

5.0
10
15

Min Max Min Typ

—
—
—

4.95

9.95

14.95

—
—
—

3.5

7.0
11

– 3.0

– 0.64

– 1.6
– 4.2

0.64

1.6

4.2

—
—
—

)

SS

– 55C 25C 125C

(4.)

Max Min Max

0.05

0.05

0.05
—

—
—

1.5

3.0

4.0

—
—
—

—
—
—
—

—
—
—

5.0
10
20

—
—
—

4.95

9.95

14.95

—
—
—

3.5

7.0
11

– 2.4

– 0.51

– 1.3
– 3.4

0.51

1.3

3.4

—
—
—

0
0
0

5.0
10
15

2.25

4.50

6.75

2.75

5.50

8.25

– 4.2
– 0.88
– 2.25

– 8.8

0.88

2.25

8.8

0.005

0.010

0.015

IT = (0.6 µA/kHz) f + I
IT = (1.2 µA/kHz) f + I
IT = (1.7 µA/kHz) f + I

0.05

0.05

0.05
—

—
—

1.5

3.0

4.0

—
—
—

—
—
—
—

—
—
—

5.0
10
20

DD
DD
DD

—
—
—

4.95

9.95

14.95

—
—
—

3.5

7.0
11

– 1.7

– 0.36

– 0.9
– 2.4

0.36

0.9

2.4

—
—
—

0.05

0.05

0.05

buffers switching)

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25C.

6. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: I

is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

T

—
—
—

1.5

3.0

4.0

—
—
—

—
—
—
—

—
—
—

150
300
600

Unit

Vdc

Vdc

Vdc

Vdc

mAdc

mAdc

µAdc

µAdc

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3

MC14518B

SWITCHING CHARACTERISTICS

(7.)

(C

= 50 pF, T

L

= 25C)

A

All Types

100

50
40

280
115

80

330
130

90

100

50
35

2.5

6.0

8.0
—

—
—

220
100

70

125

55
40

– 45
– 15

– 5

(8.)

Max

200
100

80

560
230
160

650
230
170

—
—
—

1.5

3.0

4.0
15

5
4

—
—
—

—
—
—

—
—
—

Characteristic Symbol V

Output Rise and Fall Time

t

, t

TLH

t

TLH

t

TLH

= (1.5 ns/pF) CL + 25 ns

THL

, t

= (0.75 ns/pF) CL + 12.5 ns

THL

, t

= (0.55 ns/pF) CL + 9.5 ns

THL

Propagation Delay Time

Clock to Q/Enable to Q

, t

t

PLH

t

PLH

t

PLH

= (1.7 ns/pF) CL + 215 ns

PHL

, t

= (0.66 ns/pF) CL + 97 ns

PHL

, t

= (0.5 ns/pF) CL + 75 ns

PHL

Reset to Q

t

= (1.7 ns/pF) CL + 265 ns

PHL

= (0.66 ns/pF) CL + 117 ns

t

PHL

t

= (0.66 ns/pF) CL + 95 ns

PHL

Clock Pulse Width t

Clock Pulse Frequency f

Clock or Enable Rise and Fall Time t

THL

Enable Pulse Width t

Reset Pulse Width t

Reset Removal Time t

t

TLH

t

THL

t

PLH

t

PHL

t

PHL

w(H)

t

w(L)

cl

, t

WH(E)

WH(R)

rem

,

,

TLH

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

DD

Min Typ

—
—
—

—
—
—

—
—
—

200
100

70
—

—
—

—
—
—

440
200
140

280
120

90

– 5

15
20

7. The formulas given are for the typical characteristics only at 25C.

8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Unit

ns

ns

ns

ns

MHz

µs

ns

ns

ns

V

DD

C

L

20 ns

0.01 µF
CERAMIC

C

L

V

SS

C

L

C

L

500 µF

PULSE

GENERATOR

20 ns

50%

VARIABLE

C

E
R

I

D

90%

Q0
Q1

Q2
Q3

V

SS

10%

WIDTH

Figure 1. Power Dissipation Test Circuit and Waveform

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4

MC14518B

PULSE

GENERATOR

CLOCK

ENABLE

RESET

V

DD

20 ns

CLOCK

Q0

C

INPUT

Q1

Q2

E

Q3

R

V

SS

C

C

L

L

C

C

L

L

Figure 2. Switching Time Test Circuit and Waveforms

0987654321

Q0

20 ns

V

90%

DD

50%

10%

t

WH

t

PLHtPHL

t

WL

90%

Q

t

r

18

1716151413121110987654321

V

SS

50%

10%

t

f

0987654321

MC14518B

MC14520B

Q1

Q2

Q3

Q0

Q1

Q2

Q3

1312111098765432143

Figure 3. Timing Diagram

2

101514

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5

MC14518B

Q0 Q1 Q2 Q3

D

Q

D

Q

D

Q

D

Q

RESET

ENABLE

CLOCK

Q

C

R

Q

C

R

Q

C

R

Figure 4. Decade Counter (MC14518B) Logic Diagram

(1/2 of Device Shown)

Q0 Q1 Q2 Q3

D

Q

D

Q

D

Q

Q

C

R

D

Q

RESET

ENABLE

CLOCK

Q

C

R

Q

C

R

Q

C

R

Figure 5. Binary Counter (MC14520B) Logic Diagram

(1/2 of Device Shown)

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6

Q

C

R

PACKAGE DIMENSIONS

PLASTIC DIP PACKAGE

–A–

916

B

18

F

H

G

D

16 PL

0.25 (0.010) T

C

S

SEATING

–T–

PLANE

K

M

A

PLASTIC SOIC PACKAGE

MC14518B

PDIP–16

P SUFFIX

CASE 648–08

ISSUE R

J

M

SOIC–16

DW SUFFIX

CASE 751G–03

ISSUE B

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

DIM MIN MAX MIN MAX

L

M

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01

MILLIMETERSINCHES



16 9

M

B

H8X

M

0.25

0.25 B

14X

D

B16X

M

S

A

T

e

A



NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.

E



h X 45

81

B

S

A

L

A1

SEATING
PLANE

T

C

3. DIMENSIONS D AND E DO NOT INLCUDE MOLD
PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.

MILLIMETERS

DIM MIN MAX

A 2.35 2.65

A1 0.10 0.25

B 0.35 0.49
C 0.23 0.32
D 10.15 10.45

E 7.40 7.60
e 1.27 BSC

H 10.05 10.55

h 0.25 0.75
L 0.50 0.90

 0 7



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7

16 9

1

Z

D

e

b

0.13 (0.005)

M

8

H

E

E

A

A

1

0.10 (0.004)

MC14518B

PACKAGE DIMENSIONS

SOEIAJ–16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966–01

ISSUE O

L

E

M



L

DETAIL P

VIEW P

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

Q

1

c

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

MILLIMETERS

DIM MIN MAX MIN MAX

--- 2.05 --- 0.081

A
A

0.05 0.20 0.002 0.008

1

0.35 0.50 0.014 0.020

b

0.18 0.27 0.007 0.011

c

9.90 10.50 0.390 0.413

D

5.10 5.45 0.201 0.215

E

1.27 BSC 0.050 BSC

e

H

7.40 8.20 0.291 0.323

E

0.50 0.85 0.020 0.033

L
L

1.10 1.50 0.043 0.059

E

0

M



Q

0.70 0.90 0.028 0.035

1

--- 0.78 --- 0.031

Z

INCHES

10



10

0





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without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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MC14518B/D