ON Semiconductor MC14516B Technical data
MC14516B
Binary Up/Down Counter
The MC14516B synchronous up/down binary counter is
constructed with MOS P–channel and N–channel enhancement mode
devices in a monolithic structure.
This counter can be preset by applying the desired value, in binary,
to the Preset inputs (P0, P1, P2, P3) and then bringing the Preset
Enable (PE) high. The direction of counting is controlled by applying
a high (for up counting) or a low (for down counting) to the
UP/DOWN input. The state of the counter changes on the positive
transition of the clock input.
Cascading can be accomplished by connecting the Carry Out
Carry In of the next stage while clocking each counter in parallel. The
outputs (Q0, Q1, Q2, Q3) can be reset to a low state by applying a high
to the reset (R) pin.
This CMOS counter finds primary use in up/down and difference
counting. Other applications include: (1) Frequency synthesizer
applications where low power dissipation and/or high noise immunity
is desired, (2) Analog–to–digital and digital–to–analog conversions,
and (3) Magnitude and sign generation.
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Internally Synchronous for High Speed
• Logic Edge–Clocked Design — Count Occurs on Positive Going
Edge of Clock
• Single Pin Reset
• Asynchronous Preset Enable Operation
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky Load Over the Rated Temperature Range
to the
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MARKING
DIAGRAMS
16
PDIP–16
P SUFFIX
CASE 648
SOIC–16
D SUFFIX
CASE 751B
SOEIAJ–16
F SUFFIX
CASE 966
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
MC14516BCP
AWLYYWW
1
16
AWLYWW
1
16
MC14516B
1
14516B
ALYW
MAXIMUM RATINGS (Voltages Referenced to V
Symbol Parameter Value Unit
V
DD
Vin, V
Iin, I
P
T
T
stg
T
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C
Semiconductor Components Industries, LLC, 2000
August, 2000 – Rev. 4
DC Supply Voltage Range –0.5 to +18.0 V
Input or Output Voltage Range
out
out
D
A
L
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation,
per Package (Note 3.)
Ambient Temperature Range –55 to +125 °C
Storage Temperature Range –65 to +150 °C
Lead Temperature
(8–Second Soldering)
) (Note 2.)
SS
–0.5 to VDD + 0.5 V
±10 mA
500 mW
260 °C
1 Publication Order Number:
ORDERING INFORMATION
Device Package Shipping
MC14516BCP PDIP–16 2000/Box
MC14516BD SOIC–16 48/Rail
MC14516BDR2 SOIC–16 2500/Tape & Reel
MC14516BF SOEIAJ–16 See Note 1.
MC14516BFEL SOEIAJ–16 See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
This device contains protection circuitry to guard
against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high–impedance circuit. For proper
operation, V
range V
Unused inputs must always be tied to an appropriate
logic voltage level (e.g., either V
puts must be left open.
and V
in
(Vin or V
SS
should be constrained to the
out
) VDD.
out
or VDD). Unused out-
SS
MC14516B/D
PE
Q3
CARRY IN
Q0
CARRY OUT
V
MC14516B
PIN ASSIGNMENT
1
2
P3
3
P0
4
6
7
8
SS
BLOCK DIAGRAM
16
15
14
13
125
11
10
9
V
C
Q2
P2
P1
Q1
U/D
R
DD
1
5
9
10
15
4
12
13
3
PE
CARRY IN
RESET
UP/DOWN
CLOCK
P0
P1
P2
P3
VDD = PIN 16
VSS = PIN 8
Q0
Q1
Q2
Q3
CARRY
OUT
6
11
14
2
7
TRUTH TABLE
Preset
Carry In Up/Down
1 X 0 0 X No Count
0 1 0 0 Count Up
0 0 0 0 Count Down
X X 1 0 X Preset
X X X 1 X Reset
X = Don’t Care
NOTE: When counting up, the Carry Out
when Q0 through Q3 are high and Carry In
Carry Out
is low only when Q0 through Q3 and Carry In are low.
Enable
Reset Clock Action
signal is normally high and is low only
is lo w. When counting down,
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MC14516B
V
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
DD
Characteristic Symbol
Output Voltage “0” Level
V
= VDD or 0
in
“1” Level
V
= 0 or V
in
DD
Input Voltage “0” Level
= 4.5 or 0.5 Vdc)
(V
O
(V
= 9.0 or 1.0 Vdc)
O
(V
= 13.5 or 1.5 Vdc)
O
“1” Level
= 0.5 or 4.5 Vdc)
(V
O
(V
= 1.0 or 9.0 Vdc)
O
(V
= 1.5 or 13.5 Vdc)
O
Output Drive Current
(V
= 2.5 Vdc) Source
OH
= 4.6 Vdc)
(V
OH
(V
= 9.5 Vdc)
OH
(V
= 13.5 Vdc)
OH
(VOL = 0.4 Vdc) Sink
(V
= 0.5 Vdc)
OL
(V
= 1.5 Vdc)
OL
Input Current I
Input Capacitance
(V
= 0)
in
Quiescent Current
(Per Package)
Total Supply Current
(5.) (6.)
(Dynamic plus Quiescent,
Per Package)
(C
= 50 pF on all outputs, all
L
Vdc
V
OL
5.0
10
15
V
OH
5.0
10
15
V
IL
5.0
10
15
V
IH
5.0
10
15
I
OH
5.0
5.0
10
15
I
OL
5.0
10
15
in
C
in
I
DD
15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdc
— — — — 5.0 7.5 — — pF
5.0
10
15
I
T
5.0
10
15
Min Max Min Typ
—
—
—
4.95
9.95
14.95
—
—
—
3.5
7.0
11
– 3.0
– 0.64
– 1.6
– 4.2
0.64
1.6
4.2
—
—
—
)
SS
– 55C 25C 125C
(4.)
Max Min Max
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
—
—
—
—
—
—
—
—
—
—
5.0
10
20
—
—
—
4.95
9.95
14.95
—
—
—
3.5
7.0
11
– 2.4
– 0.51
– 1.3
– 3.4
0.51
1.3
3.4
—
—
—
0
0
0
5.0
10
15
2.25
4.50
6.75
2.75
5.50
8.25
– 4.2
– 0.88
– 2.25
– 8.8
0.88
2.25
8.8
0.005
0.010
0.015
IT = (0.58 µA/kHz) f + I
IT = (1.20 µA/kHz) f + I
IT = (1.70 µA/kHz) f + I
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
—
—
—
—
—
—
—
—
—
—
5.0
10
20
DD
DD
DD
—
—
—
4.95
9.95
14.95
—
—
—
3.5
7.0
11
– 1.7
– 0.36
– 0.9
– 2.4
0.36
0.9
2.4
—
—
—
0.05
0.05
0.05
buffers switching)
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25C.
6. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: I
is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
T
—
—
—
1.5
3.0
4.0
—
—
—
—
—
—
—
—
—
—
150
300
600
Unit
Vdc
Vdc
Vdc
Vdc
mAdc
mAdc
µAdc
µAdc
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MC14516B
PLH PHL
()
L
PLH,PHL
()
L
SWITCHING CHARACTERISTICS
(7.)
(C
= 50 pF, T
L
= 25C)
A
All Types
100
50
40
315
130
100
315
130
100
180
80
60
315
130
100
550
225
150
190
100
80
200
100
75
3.0
6.0
8.0
(8.)
Max
200
100
80
630
260
200
630
260
200
360
160
120
630
360
200
1100
450
300
—
—
—
—
—
—
1.5
3.0
4.0
Characteristic Symbol V
Output Rise and Fall Time
t
, t
TLH
t
TLH
t
TLH
= (1.5 ns/pF) CL + 25 ns
THL
, t
= (0.75 ns/pF) CL + 12.5 ns
THL
, t
= (0.55 ns/pF) CL + 9.5 ns
THL
Propagation Delay Time
Clock to Q
, t
t
PLH
t
PLH
t
PLH
= (1.7 ns/pF) CL + 230 ns
PHL
, t
= (0.66 ns/pF) CL + 97 ns
PHL
, t
= (0.5 ns/pF) CL + 75 ns
PHL
Clock to Carry Out
t
, t
PLH
t
PLH
t
PLH
= (1.7 ns/pF) CL + 230 ns
PHL
, t
= (0.66 ns/pF) CL + 97 ns
PHL
, t
= (0.5 ns/pF) CL + 75 ns
PHL
Carry In to Carry Out
t
, t
PLH
t
PLH
t
PLH
= (1.7 ns/pF) CL + 230 ns
PHL
, t
= (0.66 ns/pF) CL + 97 ns
PHL
, t
= (0.5 ns/pF) CL + 75 ns
PHL
Preset or Reset to Q
, t
t
PLH
t
PLH
t
PLH
= (1.7 ns/pF) CL + 230 ns
PHL
, t
= (0.66 ns/pF) CL + 97 ns
PHL
, t
= (0.5 ns/pF) CL + 75 ns
PHL
Preset or Reset to Carry Out
t
, t
PLH
t
PLH
t
PLH
= (1.7 ns/pF) CL + 465 ns
PHL
, t
= (0.66 ns/pF) CL + 192 ns
PHL
, t
= (0.5 ns/pF) CL + 125 ns
PHL
Reset Pulse Width t
Clock Pulse Width t
Clock Pulse Frequency f
t
t
t
PLH
t
t
PLH
t
t
PLH
t
t
PLH
t
t
PLH
t
TLH
THL
PHL
PHL
PHL
PHL
PHL
WH
DD
Min Typ
,
5.0
10
15
—
—
—
,
5.0
10
15
—
—
—
,
5.0
10
15
—
—
—
,
5.0
10
15
—
—
—
,
5.0
10
15
—
—
—
,
5.0
10
15
w
5.0
10
15
5.0
10
15
cl
5.0
10
15
—
—
—
380
200
160
350
170
140
—
—
—
7. The formulas given are for the typical characteristics only at 25C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an Indication of the IC’s potential performance.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
MHz
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