ON Semiconductor MC14011B, MC14023B, MC14025B, MC14071B, MC14073B Datasheet

MC14001B Series
B-Suffix Series CMOS Gates

MC14001B, MC14011B, MC14023B,
MC14025B, MC14071B, MC14073B,
MC14081B, MC14082B

The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired.

Features

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• All Outputs Buffered

• Capable of Driving Two Low−power TTL Loads or One Low−power

Schottky TTL Load Over the Rated Temperature Range.

• Double Diode Protection on All Inputs Except: Triple Diode

Protection on MC14011B and MC14081B

• Pin−for−Pin Replacements for Corresponding CD4000 Series

B Suffix Devices

• These Devices are Pb−Free and are RoHS Compliant

• NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable

MAXIMUM RATINGS (Voltages Referenced to V

Symbol

V

Vin, V

Iin, I

T

V

Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.

1. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
to the range V

Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V

DC Supply Voltage Range −0.5 to +18.0 V

DD

Input or Output Voltage Range

out

(DC or Transient)

Input or Output Current

out

(DC or Transient) per Pin

P

Power Dissipation, per Package

D

(Note 1)

T

Ambient Temperature Range −55 to +125 °C

A

Storage Temperature Range −65 to +150 °C

stg

T

Lead Temperature

L

(8−Second Soldering)

ESD Withstand Voltage

ESD

SS

SS

Parameter Value Unit

Human Body Model
Machine Model
Charged Device Model

v (Vin or V

or VDD). Unused outputs must be left open.

) v VDD.

out

)

SS

−0.5 to VDD + 0.5 V

± 10 mA

500 mW

260 °C

> 3000

> 300

N/A

and V

in

should be constrained

out

V

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MARKING

DIAGRAMS

14

PDIP−14

P SUFFIX

CASE 646

SOIC−14

D SUFFIX

CASE 751A

TSSOP−14
DT SUFFIX

CASE 948G

xx = Specific Device Code
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package

(Note: Microdot may be in either location)

MC140xxBCP

AWLYYWWG

1

14

140xxBG

AWLYWW

1

14

14

0xxB

ALYWG

G

1

DEVICE INFORMATION

Device Description

MC14001B Quad 2−Input NOR Gate

MC14011B Quad 2−Input NAND Gate

MC14023B Triple 3−Input NAND Gate

MC14025B Triple 3−Input NOR Gate

MC14071B Quad 2−Input OR Gate

MC14073B Triple 3−Input AND Gate

MC14081B Quad 2−Input AND Gate

MC14082B Dual 4−Input AND Gate

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.

© Semiconductor Components Industries, LLC, 2013

April, 2013 − Rev. 10

1 Publication Order Number:

MC14001B/D

MC14001B Series

LOGIC DIAGRAMS

NOR

MC14001B

Quad 2−Input NOR Gate

1
2

5
6

2 INPUT

8
9

12
13

MC14025B

Triple 3−Input NOR Gate

1
2
8

3
4

5

3 INPUT

11
12
13

NAND

MC14011B

Quad 2−Input NAND Gate

3

4

10

11

1
2

5
6

8
9

12
13

3

4

10

11

Quad 2−Input OR Gate

1
2

5
6

8
9

12
13

MC14023B

Triple 3−Input NAND Gate

1

9

6

10

2

9

8
3

4

6

5

11
12

10

13

Triple 3−Input AND Gate

1
2
8

3
4

5

11
12
13

OR

MC14071B

MC14073B

AND

MC14081B

Quad 2−Input AND Gate

3

4

10

11

1
2

5
6

8
9

12
13

3

4

10

11

MC14082B

Dual 4−Input AND Gate

9

6

10

2
3

4

1

5
9

10
11

12

NC = 6, 8

13

VDD = PIN 14

V

= PIN 7

SS

FOR ALL DEVICES

MC14001B

Quad 2−Input NOR Gate

IN 1

IN 2

OUT

OUT

IN 1

IN 2

V

1

A

2

A

3

A

4

B

B

6

B

7

SS

14

V

DD

IN 2

13

IN 1

12

11

OUT

OUT

105

9

IN 2

8

IN 1

MC14071B

Quad 2−Input OR Gate

IN 1

IN 2

OUT

OUT

IN 1

IN 2

V

1

A

2

A

3

A

4

B

B

6

B

7

SS

14

V

DD

13

IN 2

12

IN 1

11

OUT

OUT

105

9

IN 2

8

IN 1

MC14011B

Quad 2−Input NAND Gate

1

IN 1

A

2

D

D

C

C

IN 2

A

3

OUT

A

4

OUT

D

C

IN 1

IN 2

B

B

6

B

7

V

SS

MC14073B

Triple 3−Input AND Gate

1

IN 1

A

2

D

D

C

C

IN 2

A

3

IN 1

B

4

IN 2

D

C

IN 3

OUT

B

B

6

B

7

V

SS

PIN ASSIGNMENTS

Triple 3−Input NAND Gate

14

V

DD

13

IN 2

D

12

IN 1

D

11

OUT

D

OUT

105

14

13

12

11

105

C

9

IN 2

C

8

IN 1

C

V

DD

IN 3

C

IN 2

C

IN 1

C

OUT

C

9

OUT

A

8

IN 3

A

IN 1

A

IN 2

A

IN 1

B

IN 2

B

IN 3

B

OUT

B

V

SS

Quad 2−Input AND Gate

IN 1

A

IN 2

A

OUT

A

OUT

B

IN 1

B

IN 2

B

V

SS

MC14023B

1

2

3

4

6

7

MC14081B

1

2

3

4

6

7

MC14025B

Triple 3−Input NOR Gate

1

14

V

DD

13

IN 3

C

12

IN 2

C

11

IN 1

C

OUT

105

C

9

OUT

A

8

IN 3

A

IN 1

IN 2

IN 1

IN 2

IN 3

OUT

A

2

A

3

B

4

B

B

6

B

7

V

SS

14

V

DD

IN 3

13

C

IN 2

12

C

11

IN 1

C

OUT

105

C

9

OUT

A

8

IN 3

A

MC14082B

Dual 4−Input AND Gate

1

14

V

DD

13

IN 2

D

12

IN 1

D

11

OUT

D

OUT

105

C

9

IN 2

C

8

IN 1

C

OUT

IN 1

IN 2

IN 3

IN 4

A

2

A

3

A

4

A

A

6

NC

7

V

SS

14

V

DD

13

OUT

B

12

IN 4

B

11

IN 3

B

IN 2

105

B

9

IN 1

B

8

NC

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2

NC = NO CONNECTION

MC14001B Series

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

V

DD

Characteristic

Output Voltage “0” Level

V

= VDD or 0

in

“1” Level

V

= 0 or V

in

DD

Input Voltage “0” Level

(V

= 4.5 or 0.5 Vdc)

O

= 9.0 or 1.0 Vdc)

(V

O

(V

= 13.5 or 1.5 Vdc)

O

“1” Level

(V

= 0.5 or 4.5 Vdc)

O

= 1.0 or 9.0 Vdc)

(V

O

(V

= 1.5 or 13.5 Vdc)

O

Output Drive Current

(V

= 2.5 Vdc) Source

OH

= 4.6 Vdc)

(V

OH

(V

= 9.5 Vdc)

OH

(V

= 13.5 Vdc)

OH

(VOL = 0.4 Vdc) Sink
(V

= 0.5 Vdc)

OL

= 1.5 Vdc)

(V

OL

Input Current

Input Capacitance

(V

= 0)

in

Quiescent Current

(Per Package)

Total Supply Current

(3) (4)

(Dynamic plus Quiescent,
Per Gate, C

= 50 pF)

L

Symbol

V

OL

V

OH

V

IL

V

IH

I

OH

I

OL

I

in

C

in

I

DD

I

T

Vdc

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0

5.0
10
15

5.0
10
15

15

5.0
10
15

5.0
10
15

Min

−

−

−

4.95

9.95

14.95

−

−

−

3.5

7.0
11

– 3.0

– 0.64

– 1.6
– 4.2

0.64

1.6

4.2

−

−

−

−

−

−

SS

− 55_C

)

Max

0.05

0.05

0.05

−

−

−

1.5

3.0

4.0

−

−

−

−

−

−

−

−

−

−

± 0.1

−

0.25

0.5

1.0

25_C

Min

−

−

−

4.95

9.95

14.95

−

−

−

3.5

7.0
11

– 2.4

– 0.51

– 1.3
– 3.4

0.51

1.3

3.4

−

−

−

−

−

(2)

Typ

0
0
0

5.0
10
15

2.25

4.50

6.75

2.75

5.50

8.25

– 4.2

– 0.88

– 2.25

– 8.8

0.88

2.25

8.8

± 0.00001

5.0

0.0005

0.0010

0.0015

± 0.1

IT = (0.3 mA/kHz) f + IDD/N
I

= (0.6 mA/kHz) f + IDD/N

T

I

= (0.9 mA/kHz) f + IDD/N

T

Max

0.05

0.05

0.05

−

−

−

1.5

3.0

4.0

−

−

−

−

−

−

−

−

−

−

7.5

0.25

0.5

1.0

Min

−

−

−

4.95

9.95

14.95

−

−

−

3.5

7.0
11

– 1.7

– 0.36

– 0.9
– 2.4

0.36

0.9

2.4

−

−

−

−

−

125_C

Max

0.05

0.05

0.05

−

−

−

1.5

3.0

4.0

−

−

−

−

−

−

−

−

−

−

± 1.0

−

7.5
15
30

Unit

Vdc

Vdc

Vdc

Vdc

mAdc

mAdc

mAdc

pF

mAdc

mAdc

2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

3. The formulas given are for the typical characteristics only at 25_C.

4. To calculate total supply current at loads other than 50 pF:

) = IT(50 pF) + (CL − 50) Vfk

I

T(CL

where: IT is in mA (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates

per package.

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MC14001B Series

B−SERIES GATE SWITCHING TIMES

SWITCHING CHARACTERISTICS

Characteristic

Output Rise Time, All B−Series Gates

t

= (1.35 ns/pF) CL + 33 ns

TLH

= (0.60 ns/pF) CL + 20 ns

t

TLH

t

= (0.40 ns/PF) CL + 20 ns

TLH

Output Fall Time, All B−Series Gates

t

= (1.35 ns/pF) CL + 33 ns

THL

= (0.60 ns/pF) CL + 20 ns

t

THL

t

= (0.40 ns/pF) CL + 20 ns

THL

Propagation Delay Time

(5)

(CL = 50 pF, T

= 25_C)

A

t

Symbol

t

TLH

t

THL

, t

PLH

PHL

V

DD

Vdc

5.0
10
15

5.0
10
15

Min

−

−

−

−

−

−

Typ

100

50
40

100

50
40

(6)

Max

200
100

80

200
100

80

MC14001B, MC14011B only

t

, t

PLH

t

PLH

t

PLH

= (0.90 ns/pF) CL + 80 ns

PHL

, t

= (0.36 ns/pF) CL + 32 ns

PHL

, t

= (0.26 ns/pF) CL + 27 ns

PHL

5.0
10
15

−

−

−

125

50
40

250
100

80

All Other 2, 3, and 4 Input Gates

t

PLH

t

PLH

t

PLH

, t

= (0.90 ns/pF) CL + 115 ns

PHL

, t

= (0.36 ns/pF) CL + 47 ns

PHL

, t

= (0.26 ns/pF) CL + 37 ns

PHL

5.0
10
15

−

−

−

160

65
50

300
130
100

8−Input Gates (MC14068B, MC14078B)

t

PLH

t

PLH

t

PLH

, t

= (0.90 ns/pF) CL + 155 ns

PHL

, t

= (0.36 ns/pF) CL + 62 ns

PHL

, t

= (0.26 ns/pF) CL + 47 ns

PHL

5.0
10
15

−

−

−

200

80
60

350
150
110

5. The formulas given are for the typical characteristics only at 25_C.

6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Unit

ns

ns

ns

V

14

DD

PULSE

GENERATOR

INPUT

*

C

OUTPUT

L

VSS7

*All unused inputs of AND, NAND gates must be connected to VDD.

All unused inputs of OR, NOR gates must be connected to V

SS

.

Figure 1. Switching Time Test Circuit and Waveforms

20 ns 20 ns

INPUT

OUTPUT

INVERTING

OUTPUT

NON-INVERTING

t

PHL

t

t

THL

PLH

V

0 V

V

V

V

V

DD

OH

OL

OH

OL

90%

50%

10%

90%

t

TLH

50%

10%

90%

50%

10%

t

PLH

t

TLH

t

PHL

t

THL

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