ON Semiconductor MC14069UB Technical data
MC14069UB
Hex Inverter
The MC14069UB hex inverter is constructed with MOS P−channel
and N−channel enhancement mode devices in a single monolithic
structure. These inverters find primary use where low power
dissipation and/or high noise immunity is desired. Each of the six
inverters is a single stage to minimize propagation delays.
Features
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
• Triple Diode Protection on All Inputs
• Pin−for−Pin Replacement for CD4069UB
• Meets JEDEC UB Specifications
• Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to V
Symbol
V
Vin, V
Iin, I
T
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C
DC Supply Voltage Range −0.5 to +18.0 V
DD
Input or Output Voltage Range
out
(DC or Transient)
Input or Output Current
out
(DC or Transient) per Pin
P
Power Dissipation, per Package
D
(Note 1)
T
Ambient Temperature Range −55 to +125 °C
A
Storage Temperature Range −65 to +150 °C
stg
T
Lead Temperature
L
(8−Second Soldering)
Parameter Value Unit
)
SS
−0.5 to VDD + 0.5 V
±10 mA
500 mW
260 °C
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MARKING
DIAGRAMS
14
PDIP−14
P SUFFIX
CASE 646
SOIC−14
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
SOEIAJ−14
F SUFFIX
CASE 965
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
MC14069UBCP
AWLYYWW
1
14
AWLYWW
1
14
1
14
MC14069UB
AWLYWW
1
14069U
14
069U
ALYW
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
to the range V
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2005
February, 2005 − Rev. 6
(Vin or V
SS
or VDD). Unused outputs must be left open.
SS
) VDD.
out
and V
in
should be constrained
out
1 Publication Order Number:
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
MC14069UB/D
MC14069UB
11
13
IN 1
OUT 1
IN 2
OUT 2
IN 3
OUT 3
V
SS
1
2
3
4
6
7
14
13
12
11
105
9
8
V
DD
IN 6
OUT 6
IN 5
OUT 5
IN 4
OUT 4
Figure 1. Pin Assignment
10
12
2
V
= PIN 14
DD
4
V
= PIN 7
SS
6
INPUT*
V
DD
OUTPUT
8
V
SS
*Double diode protection on all inputs not shown
(1/6 of circuit shown)
1
3
5
9
Figure 2. Circuit SchematicFigure 3. Logic Diagram
20 ns 20 ns
90%
t
50%
10%
THL
90%
50%
10%
t
TLH
INPUT
t
PHL
OUTPUT
t
PLH
V
DD
V
SS
V
OH
V
OL
PULSE
GENERATOR
INPUT
V
14
VSS7
DD
OUTPUT
C
L
Figure 4. Switching Time Test Circuit and Waveforms
ORDERING INFORMATION
Device Package Shipping
MC14069UBCP PDIP−14 500 Units / Tape & Ammo Box
MC14069UBCPG PDIP−14
500 Units / Tape & Ammo Box
(Pb−Free)
MC14069UBD SOIC−14 55 Units / Rail
MC14069UBDG SOIC−14
55 Units / Rail
(Pb−Free)
MC14069UBDR2 SOIC−14 2500 Units / Tape & Reel
MC14069UBDR2G SOIC−14
2500 Units / Tape & Reel
(Pb−Free)
MC14069UBDTR2 TSSOP−14* 2500 Units / Tape & Reel
MC14069UBFEL SOEIAJ−14 2000 Units / Tape & Reel
MC14069UBFELG SOEIAJ−14
2000 Units / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
†
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