ON Semiconductor MC14069UB Technical data

MC14069UB

Hex Inverter

The MC14069UB hex inverter is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. These inverters find primary use where low power dissipation and/or high noise immunity is desired. Each of the six inverters is a single stage to minimize propagation delays.

Features

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low−Power TTL Loads or One Low−Power

Schottky TTL Load Over the Rated Temperature Range

• Triple Diode Protection on All Inputs

• Pin−for−Pin Replacement for CD4069UB

• Meets JEDEC UB Specifications

• Pb−Free Packages are Available*

MAXIMUM RATINGS (Voltages Referenced to V

Symbol

Vin, V

Iin, I

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.

1. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C

DC Supply Voltage Range −0.5 to +18.0 V

Input or Output Voltage Range

out

(DC or Transient) Input or Output Current

out

(DC or Transient) per Pin

Power Dissipation, per Package

(Note 1)

Ambient Temperature Range −55 to +125 °C

Storage Temperature Range −65 to +150 °C

stg

Lead Temperature

(8−Second Soldering)

Parameter Value Unit

)

−0.5 to VDD + 0.5 V

±10 mA

500 mW

260 °C

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MARKING

DIAGRAMS

PDIP−14

P SUFFIX

CASE 646

SOIC−14

D SUFFIX

CASE 751A

TSSOP−14 DT SUFFIX

CASE 948G

SOEIAJ−14

F SUFFIX

CASE 965

A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week

MC14069UBCP

AWLYYWW

AWLYWW

MC14069UB

AWLYWW

14069U

069U

ALYW

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, V to the range V

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

 Semiconductor Components Industries, LLC, 2005

February, 2005 − Rev. 6

 (Vin or V

or VDD). Unused outputs must be left open.

)  VDD.

out

and V

should be constrained

out

1 Publication Order Number:

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.

MC14069UB/D

MC14069UB

IN 1

OUT 1

IN 2

OUT 2

IN 3

OUT 3

1 2 3 4

6 7

14 13 12 11 105

9 8

IN 6

OUT 6

IN 5

OUT 5

IN 4

OUT 4

Figure 1. Pin Assignment

= PIN 14

= PIN 7

INPUT*

OUTPUT

*Double diode protection on all inputs not shown

(1/6 of circuit shown)

Figure 2. Circuit SchematicFigure 3. Logic Diagram

20 ns 20 ns

90%

50%

10%

THL

90% 50%

10%

TLH

INPUT

PHL

OUTPUT

PLH

PULSE

GENERATOR

INPUT

VSS7

OUTPUT

Figure 4. Switching Time Test Circuit and Waveforms

ORDERING INFORMATION

Device Package Shipping

MC14069UBCP PDIP−14 500 Units / Tape & Ammo Box MC14069UBCPG PDIP−14

500 Units / Tape & Ammo Box

(Pb−Free) MC14069UBD SOIC−14 55 Units / Rail MC14069UBDG SOIC−14

55 Units / Rail

(Pb−Free) MC14069UBDR2 SOIC−14 2500 Units / Tape & Reel MC14069UBDR2G SOIC−14

2500 Units / Tape & Reel

(Pb−Free) MC14069UBDTR2 TSSOP−14* 2500 Units / Tape & Reel MC14069UBFEL SOEIAJ−14 2000 Units / Tape & Reel MC14069UBFELG SOEIAJ−14

2000 Units / Tape & Reel

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

†

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MC14069UB

Symbo

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

Characteristic

Output Voltage “0” Level

= V

ООООООООО

Vin = 0 “1” Level

ООООООООО

Input Voltage “0” Level

ООООООООО

= 4.5 Vdc)

= 9.0 Vdc)

ООООООООО

= 13.5 Vdc)

ООООООООО

= 0.5 Vdc)

= 1.0 Vdc)

ООООООООО

= 1.5 Vdc)

Output Drive Current

ООООООООО

= 2.5 Vdc) Source

= 4.6 Vdc)

ООООООООО

= 9.5 Vdc)

ООООООООО

= 13.5 Vdc)

“1” Level

(VOL = 0.4 Vdc) Sink (V

= 0.5 Vdc)

ООООООООО

= 1.5 Vdc)

Input Current Input Capacitance

ООООООООО

= 0)

Quiescent Current

(Per Package)

ООООООООО

Total Supply Current

ООООООООО

(Dynamic plus Quiescent, Per Gate) (C

ООООООООО

Output Rise and Fall Times

(3) (4)

= 50 pF)

(3)

(CL = 50 pF)

ООООООООО

, t

TLH

ООООООООО

TLH

= (1.35 ns/pF) C

THL

, t

= (0.60 ns/pF) C

THL

, t

= (0.40 ns/pF) C

THL

Propagation Delay Times

ООООООООО

(CL = 50 pF)

, t

PLH

ООООООООО

PLH

ООООООООО

PLH

= (0.90 ns/pF) CL + 20 ns

PHL

, t

= (0.36 ns/pF) CL + 22 ns

PHL

, t

= (0.26 ns/pF) CL + 17 ns

PHL

+ 33 ns

+ 20 ns

(3)

TLH

THL

PLH

PHL

Vdc

5.0

Min

4.95

9.95

14.95

10 15

4.0

8.0

12.5

– 3.0

– 0.64

– 1.6

– 4.2

0.64 10 15

1.6

4.2

−

ООООООООООООООО

10 15

ООООООООООООООО

10 15

− 55C

−

)

Max

0.05

1.0

2.0

2.5

± 0.1

0.25

0.5

1.0

−

25C

Min

−

ÎÎ

−

4.95

9.95

ÎÎ

14.95

ÎÎ

−

ÎÎ

−

ÎÎ

4.0

8.0

ÎÎ

12.5

ÎÎ

– 2.4

– 0.51

ÎÎ

– 1.3

ÎÎ

– 3.4

0.51

1.3

ÎÎ

3.4

−

ÎÎ

−

ÎÎ

−

(2)

Typ

0 0

5.0 10

2.25

4.50

6.75

2.75

5.50

8.25

– 4.2

– 0.88

– 2.25

– 8.8

0.88

2.25

8.8

±0.00001

5.0

0.0005

0.0010

0.0015

IT = (0.3 A/kHz) f + IDD/6 I

= (0.6 A/kHz) f + IDD/6

= (0.9 A/kHz) f + IDD/6

−

ÎÎ

−

ÎÎ

−

ÎÎ

−

ÎÎ

100

50 40

40 30

Max

0.05

ÎÎ

0.05

−

ÎÎ

−

ÎÎ

1.0

2.0

ÎÎ

2.5

ÎÎ

−

ÎÎ

−

ÎÎ

−

ÎÎ

−

ÎÎ

−

ÎÎ

−

± 0.1

7.5

ÎÎ

0.25

0.5

ÎÎ

1.0

200

ÎÎ

100

ÎÎ

125

ÎÎ

75 55

ÎÎ

Min

−

4.95

9.95

14.95

−

4.0

8.0

12.5

– 1.7

– 0.36

– 0.9

– 2.4

0.36

0.9

2.4

−

125C

Max

0.05

± 1.0

2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

3. The formulas given are for the typical characteristics only at 25C.

4. To calculate total supply current at loads other than 50 pF: I

) = IT(50 pF) + (CL – 50) Vfk

T(CL

where: I

is in A (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

1.0

2.0

2.5

7.5 15 30

Unit

Vdc

−

Vdc

−

− Vdc

Vdc

−

mAdc

−

mAdc

−

Adc

−

Adc

−

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−T−

SEATING PLANE

14 8

MC14069UB

PACKAGE DIMENSIONS

PDIP−14

P SUFFIX

CASE 646−06

ISSUE N

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

14 PL

0.13 (0.005)

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

DIM MIN MAX MIN MAX

A 0.715 0.770 18.16 18.80 B 0.240 0.260 6.10 6.60 C 0.145 0.185 3.69 4.69 D 0.015 0.021 0.38 0.53 F 0.040 0.070 1.02 1.78 G 0.100 BSC 2.54 BSC H 0.052 0.095 1.32 2.41 J 0.008 0.015 0.20 0.38 K 0.115 0.135 2.92 3.43 L

0.290 0.310 7.37 7.87

M −−− 10 −−− 10 N 0.015 0.039 0.38 1.01

MILLIMETERSINCHES



−T−

SEATING PLANE

SOIC−14

D SUFFIX

CASE 751A−03

ISSUE G

−A−

D 14 PL

0.25 (0.010) A

−B−

7 PL

0.25 (0.010) B

R X 45



NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL

CONDITION.

DIM MIN MAX MIN MAX

A 8.55 8.75 0.337 0.344 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7

 

P 5.80 6.20 0.228 0.244 R 0.25 0.50 0.010 0.019

INCHESMILLIMETERS

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MC14069UB

PACKAGE DIMENSIONS

TSSOP−14 DT SUFFIX

CASE 948G−01

ISSUE O

0.10 (0.004)

−T−

SEATING PLANE

14X REFK

0.25 (0.010)

U0.15 (0.006) T

2X L/2

0.10 (0.004) V

PIN 1 IDENT.

U0.15 (0.006) T

−V−

−U− F

DETAIL E

SECTION N−N

DETAIL E

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−.

DIM MIN MAX MIN MAX

A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C −−− 1.20 −−− 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024

−W−

J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC M 0 8 0 8



INCHESMILLIMETERS

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14 8

0.13 (0.005)

0.10 (0.004)

VIEW P

MC14069UB

PACKAGE DIMENSIONS

SOEIAJ−14

F SUFFIX

CASE 965−01

ISSUE O



DETAIL P

NOTES:

1 DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DIMENSIONS D AND E DO NOT INCLUDE MOLD

FLASH OR PROTRUSIONS AND ARE MEASURED

AT THE PARTING LINE. MOLD FLASH OR

PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)

PER SIDE. 4 TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY. 5 THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

MILLIMETERS

DIM MIN MAX MIN MAX

−−− 2.05 −−− 0.081

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.18 0.27 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

0.50 L

1.10 1.50 0.043 0.059



0.70 0.90 0.028 0.035

−−− 1.42 −−− 0.056

INCHES



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MC14069UB/D

ON Semiconductor MC14069UB Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual