ON Semiconductor MC14066B Technical data

MC14066B

Quad Analog Switch/Quad Multiplexer

The MC14066B consists of four independent switches capable of controlling either digital or analog signals. This quad bilateral switch is useful in signal gating, chopper, modulator, demodulator and CMOS logic implementation.

The MC14066B is designed to be pin−for−pin compatible with the MC14016B, but has much lower ON resistance. Input voltage swings as large as the full supply voltage can be controlled via each independent control input.

Features

• Triple Diode Protection on All Control Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Linearized Transfer Characteristics

• Low Noise − 12 nV/√Cycle, f ≥ 1.0 kHz typical

• Pin−for−Pin Replacement for CD4016, CD4016, MC14016B

• For Lower R

• Pb−Free Packages are Available*

MAXIMUM RATINGS (Voltages Referenced to V

Symbol

V

Vin, V

I

T

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.

1. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, V to the range V

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V

DC Supply Voltage Range −0.5 to +18.0 V

DD

Input or Output Voltage Range

out

(DC or Transient)

I

Input Current (DC or Transient)

in

per Control Pin Switch Through Current ±25 mA

SW

P

Power Dissipation, per Package

D

(Note 1)

T

Ambient Temperature Range −55 to +125 °C

A

Storage Temperature Range −65 to +150 °C

stg

T

Lead Temperature

L

(8−Second Soldering)

, Use The HC4066 High−Speed CMOS Device

ON

)

SS

Parameter Value Unit

−0.5 to VDD + 0.5 V

±10 mA

500 mW

260 °C

and V

 (Vin or V

SS

or VDD). Unused outputs must be left open.

SS

)  VDD.

out

in

should be constrained

out

http://onsemi.com

MARKING

DIAGRAMS

14

PDIP−14

P SUFFIX

CASE 646

SOIC−14

D SUFFIX

CASE 751A

TSSOP−14 DT SUFFIX

CASE 948G

SOEIAJ−14

F SUFFIX

CASE 965

A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week

MC14066BCP

AWLYYWW

1

14

14066B

AWLYWW

1

14

066B

ALYW

1

14

MC14066B

AWLYWW

1

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet.

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

 Semiconductor Components Industries, LLC, 2005

February, 2005 − Rev. 5

1 Publication Order Number:

MC14066B/D

MC14066B

PIN ASSIGNMENT

BLOCK DIAGRAM

IN 1

IN 2

IN 3

IN 4

13

1

5

4

6

8

12

11

CONTROL 1

CONTROL 2

CONTROL 3

CONTROL 4

2

3

9

10

CONTROL 2

CONTROL 3

OUT 1

OUT 2

OUT 3

OUT 4

V

DD

V

SS

OUT 1

OUT 2

= PIN 14

= PIN 7

IN 1

IN 2

V

1

2

3

4

6

7

SS

14

13

12

11

105

9

8

V

DD

CONTROL 1

CONTROL 4

IN 4

OUT 4

OUT 3

IN 3

LOGIC DIAGRAM AND TRUTH TABLE

(1/4 OF DEVICE SHOWN)

IN/OUT

CONTROL

Control Switch

0=V 1=V

SS DD

OFF

ON

Logic Diagram Restrictions

VSS ≤ Vin ≤ V

VSS ≤ V

OUT/IN

DD

≤ V

out

DD

CMOS INPUT

V

300

CIRCUIT SCHEMATIC

(1/4 OF CIRCUIT SHOWN)

V

DD



V

DD

V

SS

V

DD

V

SS

V

DD

V

DD

V

SS

http://onsemi.com

2

MC14066B

Î

ELECTRICAL CHARACTERISTICS

−55C

Min

Max

Characteristic

Symbol

V

DD

Test Conditions

Min

SUPPLY REQUIREMENTS (Voltages Referenced to VEE)

Power Supply Voltage

V

DD

—

3.0

18

3.0

Range

Quiescent Current Per

ОООООО

Package

ОООООО

Total Supply Current

(Dynamic Plus Quiescent,

ОООООО

Per Package

ОООООО

I

DD

ÎÎ

I

D(AV)

ÎÎ

5.0

Control Inputs:

ООООО

10 15

5.0 10 15

= VSS or VDD,

V

in

Switch I/O: V

ООООО

 VDD, and

ООООО

V

switch

TA = 25C only The

channel component,

ООООО

– V

(V

in

ООООО

not included.)

 V

SS

 500 mV

)/Ron, is

out

−

0.25

Î

I/O

Î

(3)

ООООООООООООО

Î

−

0.5

−

1.0

Î

Typical (0.20 A/kHz) f + I

CONTROL INPUTS (Voltages Referenced to VSS)

Low−Level Input Voltage

ОООООО

High−Level Input Voltage

ОООООО

Input Leakage Current Input Capacitance

V

IL

ÎÎ

V

IH

ÎÎ

I

in

C

in

5.0

Ron = per spec,

10

I

= per spec

off

ООООО

15

5.0

Ron = per spec,

ООООО

10

I

= per spec

off

15

ООООО

15

Vin = 0 or V

−

DD

Î

3.5

Î

7.0 11

Î

−

1.5

−

3.0

Î

−

4.0

−

3.5

Î

−

7.0

−

Î

−

± 0.1

−

SWITCHES IN AND OUT (Voltages Referenced to VSS)

Recommended Peak−to−

ОООООО

Peak Voltage Into or Out of the Switch

ОООООО

Recommended Static or

Dynamic Voltage Across

ОООООО

the Switch (3) (Figure 1) Output Offset Voltage ON Resistance

ОООООО

ON Resistance Between

Any Two Channels

ОООООО

in the Same Package Off−Channel Leakage

ОООООО

Current (Figure 6)

ОООООО

Capacitance, Switch I/O Capacitance, Feedthrough

ОООООО

(Switch Off)

V

I/O

ÎÎ

V

switch

ÎÎ

V

OO

R

on

ÎÎ

R

on

ÎÎ

I

off

ÎÎ

C

I/O

C

I/O

ÎÎ

−

Channel On or Off

ООООО

−

Channel On

ООООО

−

Vin = 0 V, No Load

5.0

V

 500 mV 10 15

switch

V

= VIL or V

ООООО

in

(Control), and Vin =

ООООО

0 to V

(Switch)

DD

IH

5.0 10

ОООООÎÎ

15 15

Vin = VIL or V

ООООО

(Control) Channel to Channel or Any One

ООООО

Channel

−

Switch Off

IH

−

ОООООÎÎ

−

0

V

Î

(3)

,

Î

DD

Î

0

600

Î

−

800

−

400

Î

−

220

Î

−

70

−

50

Î

−

45

−

±100

Î

−

Î

2. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.

3. For voltage drops across the switch (V current out of the switch may contain both V Maximum Ratings are exceeded. (See first page of this data sheet.)

) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the

switch

and switch input components. The reliability of the device will be unaffected unless the

DD

25C

(2)

Typ

−

0.005

ÎÎ

−

0.010

−

0.015

ÎÎ

(0.07 A/kHz) f + I

(0.36 A/kHz) f + I

−

2.25

−

4.50

ÎÎ

−

6.75

2.75

ÎÎ

5.50

11

8.25

ÎÎ

−

±0.00001

−

0

−

5.0

−

ÎÎ

−

ÎÎ

10

250 120

ÎÎ

80

ÎÎ

25 10

ÎÎ

10

± 0.05

ÎÎ

10

0.47

ÎÎ

Max

18

0.25

Î

0.5

1.0

Î

DD DD DD

1.5

3.0

Î

4.0

−

Î

−

Î

± 0.1

7.5

V

DD

Î

600

Î

−

1050

500

Î

280

Î

70 50

Î

45

±100

Î

15

−

Î

Min

3.0

−

Î

−

Î

−

Î

−

3.5

Î

7.0 11

Î

−

0

Î

0

Î

−

Î

−

Î

−

Î

−

Î

−

Î

125C

Max

18

7.5

Î

15 30

Î

1.5

3.0

Î

4.0

−

Î

−

Î

± 1.0

−

V

DDVp–p

Î

300

Î

−

1200

520

Î

300

Î

135

95

Î

65

±1000

Î

−

Î

Unit

V

A

V

A pF

mV

V



nA

pF pF

http://onsemi.com

3

MC14066B

Î

ELECTRICAL CHARACTERISTICS (Note 4) (C

Characteristic

Propagation Delay Times V

ОООООООООООООО

Input to Output (R

, t

t

ОООООООООООООО

PLH

PHL

t

, t

PLH

t

PLH

PHL

, t

PHL

ОООООООООООООО

Control to Output (RL = 1 k) (Figure 2)

Output “1” to High Impedance

ОООООООООООООО

Output “0” to High Impedance

ОООООООООООООО

High Impedance to Output “1”

ОООООООООООООО

High Impedance to Output “0”

ОООООООООООООО

Second Harmonic Distortion VSS = – 5 Vdc

= 1.77 Vdc, RMS Centered @ 0.0 Vdc,

(V

in

ОООООООООООООО

R

= 10 k, f = 1.0 kHz)

L

Bandwidth (Switch ON) (Figure 3) VSS = – 5 Vdc

ОООООООООООООО

(R

= 1 k, 20 Log (V

L

= 5 V

V

in

ОООООООООООООО

p−p

Feedthrough Attenuation (Switch OFF) VSS = – 5 Vdc

(V

= 5 V

in

p−p

Channel Separation (Figure 4) VSS = – 5 Vdc

ОООООООООООООО

(V

= 5 V

in

(Switch A ON, Switch B OFF)

ОООООООООООООО

p−p

= 10 k)

L

= (0.17 ns/pF) CL + 15.5 ns = (0.08 ns/pF) CL + 6.0 ns = (0.06 ns/pF) CL + 4.0 ns

) = − 3 dB, CL = 50 pF,

out/Vin

)

, RL = 1 k, fin = 1.0 MHz) (Figure 3)

, RL = 1 k, f

= 8.0 MHz)

in

= 50 pF, TA = 25C unless otherwise noted.)

L

V

DD

Vdc

ÎÎ

5.0

ÎÎ

10

ÎÎ

15

5.0

ÎÎ

10

ÎÎ

15

5.0 10

ÎÎ

15

5.0

ÎÎ

10 15

ÎÎ

5.0

ÎÎ

SS

= 0 Vdc

Symbol

t

, t

PLH

ÎÎ

t

PHZ

ÎÎ

t

PLZ

ÎÎ

t

PZH

ÎÎ

t

PZL

PHL

10

ÎÎ

15

−

5.0

ÎÎ

5.0

ÎÎ

5.0

ÎÎ

Min

−

(5)

Typ

ÎÎ

20

ÎÎ

10

ÎÎ

7.0

40

ÎÎ

35

ÎÎ

30 40

35

ÎÎ

30 60

ÎÎ

20 15

ÎÎ

60 20

ÎÎ

15

0.1

ÎÎ

65

ÎÎ

– 50

ÎÎ

Max

ÎÎ

40

ÎÎ

20

ÎÎ

15

80

ÎÎ

70

ÎÎ

60 80

70

ÎÎ

60

120

ÎÎ

40 30

ÎÎ

120

40

ÎÎ

30

−

ÎÎ

−

ÎÎ

−

ÎÎ

Crosstalk, Control Input to Signal Output (Figure 5)

V

= – 5 Vdc

ОООООООООООООО

= 1 k, RL = 10 k, Control t

(R

1

TLH

= t

THL

SS

= 20 ns)

−

ÎÎ

5.0

ÎÎ

−

ÎÎ

300

ÎÎ

−

ÎÎ

4. The formulas given are for the typical characteristics only at 25C.

5. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Unit

Î

MHz

Î

mV

Î

ns

%

dB

p−p

ORDERING INFORMATION

Device Package Shipping

MC14066BCP PDIP−14 500 Units / Rail MC14066BCPG PDIP−14

500 Units / Rail

(Pb−Free) MC14066BD SOIC−14 55 Units / Rail MC14066BDG SOIC−14

55 Units / Rail

(Pb−Free) MC14066BDR2 SOIC−14 2500 Units / Tape & Reel MC14066BDR2G SOIC−14

2500 Units / Tape & Reel

(Pb−Free) MC14066BDTR2 TSSOP−14* 2500 Units / Tape & Reel MC14066BF SOEIAJ−14 50 Units / Rail MC14066BFEL SOEIAJ−14 2000 Units / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

http://onsemi.com

4

†

MC14066B

TEST CIRCUITS

V

out

V

C

ON SWITCH

V

CONTROL

20 ns

SECTION

OF IC

LOAD

V

SOURCE

V

C

t

PZH

V

out

V

out

10%

90%

t

PZL

Figure 1. V Across Switch Figure 2. Turn−On Delay Time Test Circuit

and Waveforms

in

90%

50%

10%

90%

10%

t

R

V

PHZ

PLZ

C

L

x

V

DD

V

SS

V

= V

in

DD

Vx = V

SS

Vin = V

SS

Vx = V

DD

VC = VDD FOR BANDWIDTH TEST V

= VSS FOR FEEDTHROUGH TEST

C

VDD − V

SS

2

V

in

V

C

VDDV

SS

Figure 3. Bandwidth and

Feedthrough Attenuation

V

in

1 k

= −5.0 V TO +5.0 V SWING

V

C

V

− V

DD

SS

2

V

in

R

V

out

R

L

C

L

DD

V

SS

L

R

L

C

L

C

L

Figure 4. Channel Separation

OFF CHANNEL UNDER TEST

V

DD

V

SS

V

SS

V

DD

10 k

V

out

A

CONTROL

R

L

CL = 50 pF

SECTION

OF IC

Figure 5. Crosstalk,

Control to Output

Figure 6. Off Channel Leakage

http://onsemi.com

5

10 k

MC14066B

V

DD

KEITHLEY 160

DIGITAL

MULTIMETER

V

DD

V

SS

RANGE

Figure 7. Channel Resistance (RON) Test Circuit

TYPICAL RESISTANCE CHARACTERISTICS

1 k

X−Y

PLOTTER

350

300

250

200

150

100

, ON" RESISTANCE (OHMS)

ON

R

50

0

−8.0−10 −6.0 −4.0 −2.0 0 0.2 4.0 6.0 8.0 10

700

600

500

400

V

, INPUT VOLTAGE (VOLTS)

in

Figure 8. V

350

300

250

200

T

= 125°C

A

25°C

−55 °C

= 7.5 V, VSS = − 7.5 V Figure 9. VDD = 5.0 V, VSS = − 5.0 V

DD

150

100

, ON" RESISTANCE (OHMS)

ON

R

50

0

−8.0−10 −6.0 −4.0 −2.0 0 0.2 4.0 6.0 8.0 10

V

, INPUT VOLTAGE (VOLTS)

in

350

T

= 25°C

300

250

A

VDD = 2.5 V

200

T

= 125°C

A

25°C

−55 °C

300

200

, ON" RESISTANCE (OHMS)

ON

R

100

0

−8.0−10 −6.0 −4.0 −2.0 0 0.2 4.0 6.0 8.0 10

T

= 125°C

A

25°C

−55 °C

V

, INPUT VOLTAGE (VOLTS)

in

Figure 10. VDD = 2.5 V, VSS = − 2.5 V

150

100

, ON" RESISTANCE (OHMS)

ON

R

50

0

http://onsemi.com

6

5.0 V

7.5 V

−8.0−10 −6.0 −4.0 −2.0 0 0.2 4.0 6.0 8.0 10

V

, INPUT VOLTAGE (VOLTS)

in

Figure 11. Comparison at 25°C, VDD = − V

SS

MC14066B

APPLICATIONS INFORMATION

Figure A illustrates use of the Analog Switch. The 0−to−5 V digital control signal is used to directly control a 5 V peak−to−peak analog signal.

The digital control logic levels are determined by V and VSS. The VDD voltage is the logic high voltage, the V

DD

SS

voltage is logic low. For the example, VDD = + 5 V = logic high at the control inputs; VSS = GND = 0 V = logic low.

The maximum analog signal level is determined by V

DD

and VSS. The analog voltage must not swing higher than VDD or lower than VSS.

The example shows a 5 V peak−to−peak signal which allows no margin at either peak. If voltage transients above

+5 V

V

DD

+5 V

EXTERNAL

CMOS

DIGITAL

CIRCUITRY

5 V

p−p

ANALOG SIGNAL

0−TO−5 V DIGITAL

CONTROL SIGNALS

SWITCH

IN

MC14066B

VDD and/or below VSS are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure B. These diodes should be small signal types able to absorb the maximum anticipated current surges during clipping.

The absolute maximum potential difference between

V

and VSS is 18 V. Most parameters are specified up to

DD

15 V which is the recommended maximum difference between V

V

SS

SWITCH

OUT

and VSS.

DD

5 V

p−p

ANALOG SIGNAL

+5.0 V

+2.5 V

GND

Figure A. Application Example

V

DD

D

X

SWITCH

IN

D

X

V

SS

SWITCH

OUT

V

DD

D

X

D

X

V

SS

Figure B. External Germanium or Schottky Clipping Diodes

http://onsemi.com

7

−T−

SEATING PLANE

14 8

17

N

HG

MC14066B

PACKAGE DIMENSIONS

PDIP−14

P SUFFIX

CASE 646−06

ISSUE N

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

B

A

F

L

C

D

14 PL

0.13 (0.005)

K

J

M

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

DIM MIN MAX MIN MAX

A 0.715 0.770 18.16 18.80 B 0.240 0.260 6.10 6.60 C 0.145 0.185 3.69 4.69 D 0.015 0.021 0.38 0.53 F 0.040 0.070 1.02 1.78 G 0.100 BSC 2.54 BSC H 0.052 0.095 1.32 2.41 J 0.008 0.015 0.20 0.38 K 0.115 0.135 2.92 3.43 L

0.290 0.310 7.37 7.87

M −−− 10 −−− 10 N 0.015 0.039 0.38 1.01

MILLIMETERSINCHES



−T−

SEATING PLANE

SOIC−14

D SUFFIX

CASE 751A−03

ISSUE G

−A−

14

1

G

D 14 PL

0.25 (0.010) A

8

−B−

P

7 PL

M

0.25 (0.010) B

7

C

R X 45

K

M

S

B

T

S

M



M

J

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL

F

CONDITION.

DIM MIN MAX MIN MAX

A 8.55 8.75 0.337 0.344 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7

 

P 5.80 6.20 0.228 0.244 R 0.25 0.50 0.010 0.019

INCHESMILLIMETERS

http://onsemi.com

8

MC14066B

PACKAGE DIMENSIONS

TSSOP−14

DT SUFFIX

CASE 948G−01

ISSUE O

0.10 (0.004)

−T−

SEATING PLANE

14X REFK

S

U

T

S

N

0.25 (0.010)

U0.15 (0.006) T

S

2X L/2

0.10 (0.004) V

14

M

8

M

L

PIN 1 IDENT.

1

S

U0.15 (0.006) T

A

−V−

B

N

−U− F

7

DETAIL E

K

K1

J

J1

SECTION N−N

C

D

G

H

DETAIL E

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−.

DIM MIN MAX MIN MAX

A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C −−− 1.20 −−− 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030

G 0.65 BSC 0.026 BSC

H 0.50 0.60 0.020 0.024

−W−

J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC

M 0 8 0 8



INCHESMILLIMETERS

http://onsemi.com

9

14 8

1

Z

D

e

b

0.13 (0.005)

M

E

7

A

0.10 (0.004)

H

E

VIEW P

1

MC14066B

PACKAGE DIMENSIONS

SOEIAJ−14

F SUFFIX

CASE 965−01

ISSUE O

L

E

Q

1



M

L DETAIL P

c

NOTES:

1 DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DIMENSIONS D AND E DO NOT INCLUDE MOLD

FLASH OR PROTRUSIONS AND ARE MEASURED

AT THE PARTING LINE. MOLD FLASH OR

PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)

PER SIDE. 4 TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY. 5 THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

MILLIMETERS

DIM MIN MAX MIN MAX

−−− 2.05 −−− 0.081

A

0.05 0.20 0.002 0.008

1

0.35 0.50 0.014 0.020

b

0.18 0.27 0.007 0.011

c

9.90 10.50 0.390 0.413

D

5.10 5.45 0.201 0.215

E

1.27 BSC 0.050 BSC

e

H

7.40 8.20 0.291 0.323

E

0.50 0.85 0.020 0.033

0.50 L

1.10 1.50 0.043 0.059

E

0

M



Q

0.70 0.90 0.028 0.035

1

−−− 1.42 −−− 0.056

Z

INCHES

10



10

0



ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082−1312 USA

Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center

2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051

Phone: 81−3−5773−3850

http://onsemi.com

ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder

For additional information, please contact your local Sales Representative.

MC14066B/D

10

ON Semiconductor MC14066B Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual