ON Semiconductor MC14043B, MC14044B Technical data

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MC14043B, MC14044B

CMOS MSI

Quad R–S Latches

The MC14043B and MC14044B quad R–S latches are constructed
with MOS P–channel and N–channel enhancement mode devices in a
single monolithic structure. Each latch has an independent Q output
and set and reset inputs. The Q outputs are gated through three–state
buffers having a common enable input. The outputs are enabled with a
logical “1” or high on the enable input; a logical “0” or low
disconnects the latch from the Q outputs, resulting in an open circuit at
the Q outputs.

• Double Diode Input Protection

• Three–State Outputs with Common Enable

• Outputs Capable of Driving T wo Low–power TTL Loads or One

Low–Power Schottky TTL Load Over the Rated T emperature Range

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

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16

PDIP–16

P SUFFIX

CASE 648

16

SOIC–16

D SUFFIX

CASE 751B

MARKING

DIAGRAMS

MC140XXBCP

AWLYYWW

1

140XXB

AWLYWW

1

MAXIMUM RATINGS (Voltages Referenced to V

Symbol

V

DD

Vin, V

Iin, I

P

T

T

stg

T

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
to the range V

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V

DC Supply Voltage Range –0.5 to +18.0 V
Input or Output Voltage Range

out

Input or Output Current

out

Power Dissipation,

D

Ambient Temperature Range –55 to +125 °C

A

Storage Temperature Range –65 to +150 °C
Lead Temperature

L

SS

or VDD). Unused outputs must be left open.

SS

Parameter Value Unit

(DC or Transient)

(DC or Transient) per Pin

per Package (Note 3.)

(8–Second Soldering)

v (Vin or V

) v VDD.

out

) (Note 2.)

SS

–0.5 to VDD + 0.5 V

±10 mA

500 mW

260 °C

and V

in

should be constrained

out

16

SOEIAJ–16

F SUFFIX

CASE 966

XX = Specific Device Code
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

MC140XXB

AWLYWW

1

ORDERING INFORMATION

Device Package Shipping

MC14043BCP PDIP–16 2000/Box
MC14043BD SOIC–16 2400/Box
MC14043BDR2 SOIC–16 2500/Tape & Reel
MC14043BF SOEIAJ–16 See Note 1.
MC14043BFEL SOEIAJ–16 See Note 1.
MC14044BCP PDIP–16 2000/Box
MC14044BD SOIC–16 2400/Box
MC14044BDR2 SOIC–16 2500/Tape & Reel

1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev . 3

1 Publication Order Number:

MC14043B/D

MC14043B, MC14044B

PIN ASSIGNMENT

MC14043B MC14044B

1

Q3

2

Q0

3

R0

4

S0

E

S1

6

R1

7
8

V

SS

16

V

DD

15

R3

14

S3

13

NC

125

S2

11

R2

10

Q2

9

Q1

Q3

NC

S0
R0

E
R1
S1

V

SS

NC = NO CONNECTION

1
2
3
4

6
7
8

16

V

DD

S3

15
14

R3

13

Q0

125

R2

11

S2

10

Q2

9

Q1

4

S0

3

R0

6

S1

7

R1

12

S2

11

R2

14

S3

15

R3

5

ENABLE

MC14043B

2

Q0

9

Q1

10

Q2

1

Q3

V

= PIN 16

DD

= PIN 8

V

SS

NC = PIN 13

TRUTH TABLE

SRE Q

XX0

0

0

0

1

1

0

1

1

X = Don’t Care

Impedance
No Change

1
1
1
1

High

MC14044B

4

R0

3

S0

6

R1

7

S1

12

R2

11

S2

14

R3

15

S3

0
1
1

5

ENABLE

13

Q0

9

Q1

10

Q2

1

Q3

V

= PIN 16

DD

= PIN 8

V

SS

NC = PIN 2

TRUTH TABLE

S R EQ

XX0

0

0

0

1

1

0

1

1

X = Don’t Care

Impedance

1
1
1

No Change

1

High

0
1
0

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2

MC14043B, MC14044B

V

DD

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

V

Characteristic

Output Voltage “0” Level

= VDD or 0

V

in

ОООООООО

“1” Level

V

= 0 or V

ОООООООО

in

Input Voltage “0” Level

ОООООООО

(V

O

(V

ОООООООО

O

(V

O

ОООООООО

(V

O

(V

O

ОООООООО

(V

O

Output Drive Current

ОООООООО

(V

OH

(V

ОООООООО

OH

(V

OH

ОООООООО

(V

OH

DD

= 4.5 or 0.5 Vdc)
= 9.0 or 1.0 Vdc)
= 13.5 or 1.5 Vdc)

“1” Level
= 0.5 or 4.5 Vdc)
= 1.0 or 9.0 Vdc)
= 1.5 or 13.5 Vdc)

= 2.5 Vdc) Source
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)

(VOL = 0.4 Vdc) Sink
(V

= 0.5 Vdc)

OL

ОООООООО

(V

= 1.5 Vdc)

OL

Input Current
Input Capacitance

ОООООООО

(V

= 0)

in

Quiescent Current

(Per Package)

ОООООООО

Total Supply Current

ОООООООО

(Dynamic plus Quiescent,
Per Package)

ОООООООО

= 50 pF on all outputs all

(C

L

ОООООООО

buffers switching)

(5.) (6.)

Three–State Output Leakage

Current

ОООООООО

Symbol

V

OL

ÎÎ

V

OH

ÎÎ

V

ÎÎ

ÎÎ

V

ÎÎ

ÎÎ

I

OH

ÎÎ

ÎÎ

ÎÎ

I

OL

ÎÎ

I

in

C

ÎÎ

I

DD

ÎÎ

I

ÎÎ

ÎÎ

ÎÎ

I

TL

ÎÎ

Vdc

5.0
10

Î

15

5.0
10

Î

15

IL

Î

5.0
10

Î

15

IH

Î

5.0
10

Î

15

Î

5.0

5.0

Î

10

Î

15

5.0
10

Î

15
15

in

—

Î

5.0
10

Î

15

T

5.0

Î

10
15

Î

Î

15

Î

Min

—
—

Î

—

4.95

9.95

Î

14.95

Î

—
—

Î

—

Î

3.5

7.0

Î

11

Î

– 3.0

– 0.64

Î

– 1.6

Î

– 4.2

0.64

1.6

Î

4.2
—
—

Î

—
—

Î

—

ООООООООООООООО

ООООООООООООООО

ООООООООООООООО

—

Î

SS

– 55_C

)

Max

0.05

0.05

Î

0.05
—

—

Î

—

Î

1.5

3.0

Î

4.0

Î

—
—

Î

—

Î

—
—

Î

—

Î

—
—

—

Î

—

± 0.1

—

Î

1.0

2.0

Î

4.0

± 0.1

Î

25_C

Min

—
—

ÎÎ

—

4.95

9.95

ÎÎ

14.95

ÎÎ

—
—

ÎÎ

—

ÎÎ

3.5

7.0

ÎÎ

11

ÎÎ

– 2.4

– 0.51

ÎÎ

– 1.3

ÎÎ

– 3.4

0.51

1.3

ÎÎ

3.4
—
—

ÎÎ

—
—

ÎÎ

—

(4.)

Typ

0
0

Î

0

5.0
10

Î

15

Î

2.25

4.50

Î

6.75

Î

2.75

5.50

Î

8.25

Î

– 4.2

– 0.88

Î

– 2.25

Î

– 8.8

0.88

2.25

Î

8.8

±0.00001

5.0

Î

0.002

0.004

Î

0.006

IT = (0.58 µA/kHz) f + I
IT = (1.15 µA/kHz) f + I
IT = (1.73 µA/kHz) f + I

—

± 0.0001

ÎÎ

Î

Max

0.05

0.05

ÎÎ

0.05
—

—

ÎÎ

—

ÎÎ

1.5

3.0

ÎÎ

4.0

ÎÎ

—
—

ÎÎ

—

ÎÎ

—
—

ÎÎ

—

ÎÎ

—
—

—

ÎÎ

—

± 0.1

7.5

ÎÎ

1.0

2.0

ÎÎ

4.0

DD
DD
DD

± 0.1

ÎÎ

Min

—
—

Î

—

4.95

9.95

Î

14.95

Î

—
—

Î

—

Î

3.5

7.0

Î

11

Î

– 1.7

– 0.36

Î

– 0.9

Î

– 2.4

0.36

0.9

Î

2.4
—
—

Î

—
—

Î

—

—

Î

125_C

Max

0.05

0.05

Î

0.05

Î

Î

Î

Î

Î

Î

Î

Î

Î

± 1.0

Î

Î

± 3.0

Î

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25_C.

6. To calculate total supply current at loads other than 50 pF:
) = IT(50 pF) + (CL – 50) Vfk

I

T(CL

where: I

is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.

T

—
—
—

1.5

3.0

4.0

—
—
—

—
—
—
—

—
—
—

—

30
60

120

Unit

Vdc

Î

Vdc

Î

Vdc

Î

Î

Vdc

Î

Î

mAdc

Î

Î

Î

mAdc

Î

µAdc

pF

Î

µAdc

Î

µAdc

Î

Î

Î

µAdc

Î

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3

MC14043B, MC14044B

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

SWITCHING CHARACTERISTICS

(7.)

(C

L

= 50 pF, T

Characteristic

Output Rise Time

ООООООООООООО

t

= (1.35 ns/pF) CL + 32.5 ns

TLH

= (0.60 ns/pF) CL + 20 ns

t

TLH

ООООООООООООО

t

= (0.40 ns/pF) CL + 20 ns

TLH

Output Fall Time

t

= (1.35 ns/pF) CL + 32.5 ns

THL

ООООООООООООО

t

= (0.60 ns/pF) CL + 20 ns

THL

ООООООООООООО

t

= (0.40 ns/pF) CL + 20 ns

THL

Propagation Delay Time

t

= (0.90 ns/pF) CL + 130 ns

PLH

ООООООООООООО

= (0.36 ns/pF) CL + 57 ns

t

PLH

t

= (0.26 ns/pF) CL + 47 ns

ООООООООООООО

PLH

t

= (0.90 ns/pF) CL + 130 ns

PHL

t

= (0.90 ns/pF) CL + 57 ns

PHL

ООООООООООООО

= (0.26 ns/pF) CL + 47 ns

t

PHL

Set, Set Pulse Width

ООООООООООООО

Reset, Reset Pulse Width

ООООООООООООО

Three–State Enable/Disable Delay

ООООООООООООО

ООООООООООООО

= 25_C)

A

Symbol

t

TLH

ÎÎÎ

ÎÎÎ

t

THL

ÎÎÎ

ÎÎÎ

t

PLH

ÎÎÎ

ÎÎÎ

t

PHL

ÎÎÎ

t

W

ÎÎÎ

t

W

ÎÎÎ

t

PLZ

t

ÎÎÎ

PHZ

t

PZL

ÎÎÎ

t

PZH

V

DD

Vdc

ÎÎ

5.0
10

ÎÎ

15

5.0

ÎÎ

10

ÎÎ

15

5.0

ÎÎ

10
15

ÎÎ

5.0
10

ÎÎ

15

5.0
10

ÎÎ

15

5.0
10

ÎÎ

15

,
,
,

5.0
10

ÎÎ

15

ÎÎ

Min

ÎÎ

—
—

ÎÎ

—

—

ÎÎ

—

ÎÎ

—

—

ÎÎ

—
—

ÎÎ

—
—

ÎÎ

—

200
100

ÎÎ

70

200
100

ÎÎ

70
—

—

ÎÎ

—

ÎÎ

(8.)

Typ

ÎÎ

100

50

ÎÎ

40

100

ÎÎ

50

ÎÎ

40

175

ÎÎ

75
60

ÎÎ

175

75

ÎÎ

60
80

40

ÎÎ

30
80

40

ÎÎ

30

150

80

ÎÎ

55

ÎÎ

Max

ÎÎ

200
100

ÎÎ

80

200

ÎÎ

100

ÎÎ

80

350

ÎÎ

175
120

ÎÎ

350
175

ÎÎ

120

—
—

ÎÎ

—
—

—

ÎÎ

—

300
160

ÎÎ

110

ÎÎ

7. The formulas given are for the typical characteristics only at 25_C.

8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Unit

ns

Î

Î

ns

Î

Î

ns

Î

Î

ns

Î

ns

Î

ns

Î

ns

Î

Î

SET

RESET

Q

90%

MC14043B MC14044B

20 ns 20 ns

10%

20 ns 20 ns

90%

50%

10%

t

10%

t

PHL

THL

50%

AC WAVEFORMS

V

V

V

V

t

TLH

90%

50%

t

PLH

V

V

20 ns 20 ns

V

DD

50%

SS

SET

90%

10%

DD

V

SS

20 ns 20 ns

t

90%

THL

V

DD

V

SS

V

OH

V

OL

DD

50%

t

PLH

t

TLH

50%

90%

t

PHL

10%

10%

SS

RESET

OH

Q

OL

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4

MC14043B, MC14044B

THREE–STATE ENABLE/DISABLE DELAYS

Set, Reset, Enable, and Switch Conditions for 3–State T ests

MC14043B MC14044B

Test Enable S1 S2 Q

t

PZH

t

PZL

t

PHZ

t

PLZ

Open Closed A V

Closed Open B V

Open Closed A V

Closed Open B V

ENABLE

Q

A

Q

B

S R S R

V

DD
SS
DD
SS

V

SS

V

V

DD

V

V

SS

V

V

DD

50%

t

PZH

10%

t

PZL

t
t

PHZ

PLZ

SS
DD
SS
DD

V
V
V
V

90%

10%

DD

SS

DD

SS

OUTPUT

UNDER

V

DD

V

SS

V

DD

V

OL

V

OH

V

SS

TO

TEST

C

50 pF

V

DD

S1

1 k

L

S2

V

SS

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5

–T–

MC14043B, MC14044B

–A–

916

B

18

F

H

G

D

16 PL

0.25 (0.010) T

–A–

16 9

18

G

SEATING

PLANE

D

16 PL

0.25 (0.010) A

M

C

S

–T–

K

M

–B–

K

C

S

B

T

S

P ACKAGE DIMENSIONS

PDIP–16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

L

SEATING
PLANE

J

M

A

SOIC–16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

8 PLP

M

0.25 (0.010) B

M

S

X 45

R

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

DIM MIN MAX MIN MAX

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC

M

F

J

H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009

M 0 7 0 7

P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

MILLIMETERSINCHES

____

INCHESMILLIMETERS

____

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6

16 9

1

Z

D

e

b

0.13 (0.005)

M

8

H

E

E

A

A

1

0.10 (0.004)

MC14043B, MC14044B

P ACKAGE DIMENSIONS

SOEIAJ–16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966–01

ISSUE O

L

E

M

_

L

DETAIL P

VIEW P

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE

Q

1

c

MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).

MILLIMETERS

DIM MIN MAX MIN MAX

––– 2.05 ––– 0.081

A

A

0.05 0.20 0.002 0.008

1

0.35 0.50 0.014 0.020

b

0.18 0.27 0.007 0.011

c

9.90 10.50 0.390 0.413

D

5.10 5.45 0.201 0.215

E

1.27 BSC 0.050 BSC

e

H

7.40 8.20 0.291 0.323

E

0.50 0.85 0.020 0.033

L
L

1.10 1.50 0.043 0.059

E

0

M

_

Q

0.70 0.90 0.028 0.035

1

––– 0.78 ––– 0.031

Z

INCHES

10

_

10

0

_

_

http://onsemi.com

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MC14043B, MC14044B

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
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8

MC14043B/D