MC14017B
Decade Counter
The MC14017B is a five−stage Johnson decade counter with
built−in code converter. High speed operation and spike−free outputs
are obtained by use of a Johnson decade counter design. The ten
decoded outputs are normally low, and go high only at their
appropriate decimal time period. The output changes occur on the
positive−going edge of the clock pulse. This part can be used in
frequency division applications as well as decade counter or decimal
decode display applications.
Features
• Fully Static Operation
• DC Clock Input Circuit Allows Slow Rise Times
• Carry Out Output for Cascading
• Divide−by−N Counting
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
• Pin−for−Pin Replacement for CD4017B
• Triple Diode Protection on All Inputs
• Pb−Free Packages are Available*
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PDIP−16
P SUFFIX
CASE 648
SOIC−16
D SUFFIX
CASE 751B
16
1
16
MARKING
DIAGRAMS
MC14017BCP
AWLYYWWG
14017BG
AWLYWW
1
MAXIMUM RATINGS (Voltages Referenced to V
Symbol Parameter Value Unit
V
Vin, V
Iin, I
P
T
T
T
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and V
to the range VSS v (Vin or V
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
DC Supply Voltage Range − 0.5 to +18.0 V
DD
Input or Output Voltage Range
out
(DC or Transient)
Input or Output Current
out
D
A
stg
L
(DC or Transient) per Pin
Power Dissipation, per Package
(Note 1)
Ambient Temperature Range − 55 to +125 °C
Storage Temperature Range − 65 to +150 °C
Lead Temperature
(8−Second Soldering)
) v VDD.
out
)
SS
− 0.5 to VDD + 0.5 V
± 10 mA
500 mW
260 °C
should be constrained
out
16
SOEIAJ−16
F SUFFIX
CASE 966
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Indicator
MC14017B
ALYWG
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
August, 2005 − Rev. 6
1 Publication Order Number:
MC14017B/D
MC14017B
PIN ASSIGNMENT
(Positive Logic)
Clock Decode
Clock Enable Reset Output=n
0X0 n
X10 n
XX1Q0
0 0 n+1
X0 n
X0n
1 0 n+1
X = Don’t Care. If n < 5 Carry = “1”,
Otherwise = “0”.
1
Q5
2
Q1
3
Q0
4
Q2
Q6
6
Q7
7
Q3
8
V
SS
16
V
DD
15
RESET
14
CLOCK
13
CE
125
C
out
11
Q9
10
Q4
9
Q8
BLOCK DIAGRAMFUNCTIONAL TRUTH TABLE
CLOCK
CLOCK
ENABLE
RESET
14
13
15 C
Q0 3
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
out
VDD = PIN 16
VSS = PIN 8
2
4
7
10
1
5
6
9
11
12
CLOCK
CLOCK
ENABLE
RESET
LOGIC DIAGRAM
Q5 Q1 Q7 Q3 Q9
117621
14
C
13
15
Q
C
D
Q
RR
354910
Q0 Q6 Q2 Q3 Q4
C
C
D
RR
Q
Q
C
C
D
RR
Q
Q
C
C
D
RR
Q
Q
C
C
D
RR
Q
Q
12
CARRY
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2
MC14017B
Î
Î
Î
Î
l
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
l
l
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
l
l
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
V
ОООООООО
ОООООООО
Characteristic
Output Voltage “0” Leve
Vin = VDD or 0
ОООООООО
ОООООООО
Vin = 0 or V
ОООООООО
DD
“1” Leve
Input Voltage “0” Leve
(VO = 4.5 or 0.5 Vdc)
ОООООООО
(VO = 9.0 or 1.0 Vdc)
ОООООООО
(VO = 13.5 or 1.5 Vdc)
ОООООООО
(VO = 0.5 or 4.5 Vdc)
ОООООООО
(VO = 1.0 or 9.0 Vdc)
ОООООООО
(VO = 1.5 or 13.5 Vdc)
“1” Leve
Output Drive Current
(VOH = 2.5 Vdc) Source
ОООООООО
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
ОООООООО
(VOH = 13.5 Vdc)
ОООООООО
(VOL = 0.4 Vdc) Sink
ОООООООО
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
ОООООООО
Input Current
Input Capacitance
Symbo
ÎÎ
ÎÎ
V
OL
ÎÎ
V
OH
ÎÎ
V
IL
ÎÎ
ÎÎ
V
IH
ÎÎ
ÎÎ
I
OH
ÎÎ
ÎÎ
I
OL
ÎÎ
ÎÎ
I
in
C
in
DD
Î
Vdc
Î
5.0
10
15
Î
5.0
10
Î
15
5.0
Î
10
Î
15
5.0
Î
10
Î
15
5.0
Î
5.0
10
Î
15
5.0
Î
10
15
Î
15
—
Min
Î
—
—
—
Î
4.95
9.95
Î
14.95
—
Î
—
Î
—
3.5
Î
7.0
Î
11
– 3.0
Î
– 0.64
– 1.6
Î
– 4.2
0.64
Î
1.6
4.2
Î
—
—
SS
− 55_C
)
Max
Î
0.05
0.05
0.05
Î
—
—
Î
—
1.5
Î
3.0
Î
4.0
—
Î
—
Î
—
—
Î
—
—
Î
—
—
Î
—
—
Î
± 0.1
—
Min
ÎÎ
—
—
—
ÎÎ
4.95
9.95
ÎÎ
14.95
—
ÎÎ
—
ÎÎ
—
3.5
ÎÎ
7.0
ÎÎ
11
– 2.4
ÎÎ
– 0.51
– 1.3
ÎÎ
– 3.4
0.51
ÎÎ
1.3
3.4
ÎÎ
—
—
25_C
Typ
(Note 2)
Î
0
0
0
Î
5.0
10
Î
15
2.25
Î
4.50
Î
6.75
2.75
Î
5.50
Î
8.25
– 4.2
Î
– 0.88
– 2.25
Î
– 8.8
0.88
Î
2.25
8.8
Î
± 0.00001
5.0
Max
ÎÎ
0.05
0.05
0.05
ÎÎ
—
—
ÎÎ
—
1.5
ÎÎ
3.0
ÎÎ
4.0
—
ÎÎ
—
ÎÎ
—
—
ÎÎ
—
—
ÎÎ
—
—
ÎÎ
—
—
ÎÎ
± 0.1
7.5
Min
Î
—
—
—
Î
4.95
9.95
Î
14.95
—
Î
—
Î
—
3.5
Î
7.0
Î
11
– 1.7
Î
– 0.36
– 0.9
Î
– 2.4
0.36
Î
0.9
2.4
Î
—
—
125_C
Max
Î
0.05
0.05
0.05
Î
—
—
Î
—
1.5
Î
3.0
Î
4.0
—
Î
—
Î
—
—
Î
—
—
Î
—
—
Î
—
—
Î
± 1.0
—
(Vin = 0)
Quiescent Current
(Per Package)
ОООООООО
Total Supply Current (Notes 3 & 4)
ОООООООО
(Dynamic plus Quiescent,
Per Package)
ОООООООО
(CL = 50 pF on all outputs, all
ОООООООО
buffers switching)
I
DD
ÎÎ
I
T
ÎÎ
ÎÎ
ÎÎ
5.0
10
Î
15
5.0
Î
10
15
Î
Î
—
—
Î
—
ООООООООООООООО
ООООООООООООООО
ООООООООООООООО
5.0
10
Î
20
—
—
ÎÎ
—
0.005
0.010
Î
0.015
IT = (0.27 mA/kHz) f + I
IT = (0.55 mA/kHz) f + I
IT = (0.83 mA/kHz) f + I
5.0
10
ÎÎ
20
DD
DD
DD
—
—
Î
—
150
300
Î
600
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in mA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.0011.
Unit
Î
Î
Vdc
Î
Vdc
Î
Vdc
Î
Î
Vdc
Î
Î
mAdc
Î
Î
mAdc
Î
Î
mAdc
pF
mAdc
Î
mAdc
Î
Î
Î
ORDERING INFORMATION
Device Package Shipping
MC14017BCP PDIP−16 500 Units / Rail
MC14017BCPG PDIP−16
500 Units / Rail
(Pb−Free)
MC14017BD SOIC−16 48 Units / Rail
MC14017BDR2 SOIC−16 2500 Units / Tape & Reel
MC14017BDR2G SOIC−16
2500 Units / Tape & Reel
(Pb−Free)
MC14017BFEL SOEIAJ−16 2000 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
3
†
MC14017B
Î
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Î
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Î
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Î
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Î
Î
Î
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Î
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Î
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Î
Î
Î
Î
Î
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Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
SWITCHING CHARACTERISTICS (Note 5) (C
= 50 pF, T
L
Characteristic
ООООООООООООО
Output Rise and Fall Time
t
, t
TLH
t
ООООООООООООО
TLH
t
TLH
Propagation Delay Time
ООООООООООООО
Reset to Decode Output
t
ООООООООООООО
PLH
t
PLH
ООООООООООООО
t
PLH
= (1.5 ns/pF) CL + 25 ns
THL
, t
= (0.75 ns/pF) CL + 12.5 ns
THL
, t
= (0.55 ns/pF) CL + 9.5 ns
THL
, t
= (1.7 ns/pF) CL + 415 ns
PHL
, t
= (0.66 ns/PF) CL + 197 ns
PHL
, t
= (0.5 ns/pF) CL + 150 ns
PHL
Propagation Delay Time
Clock to C
ООООООООООООО
t
PLH
ООООООООООООО
t
PLH
t
PLH
ООООООООООООО
out
, t
= (1.7 ns/pF) CL + 315 ns
PHL
, t
= (0.66 ns/pF) CL + 142 ns
PHL
, t
= (0.5 ns/pF) CL + 100 ns
PHL
Propagation Delay Time
Clock to Decode Output
ООООООООООООО
t
, t
PLH
t
PLH
ООООООООООООО
t
PLH
= (1.7 ns/pF) CL + 415 ns
PHL
, t
= (0.66 ns/pF) CL + 197 ns
PHL
, t
= (0.5 ns/pF) CL + 150 ns
PHL
Turn−Off Delay Time
ООООООООООООО
Reset to C
t
PLH
ООООООООООООО
t
PLH
ООООООООООООО
t
PLH
out
= (1.7 ns/pF) CL + 315 ns
= (0.66 ns/pF) CL + 142 ns
= (0.5 ns/pF) CL + 100 ns
Clock Pulse Width
ООООООООООООО
Clock Frequency
ООООООООООООО
ООООООООООООО
Reset Pulse Width
ООООООООООООО
Reset Removal Time
ООООООООООООО
Clock Input Rise and Fall Time
ООООООООООООО
ООООООООООООО
Clock Enable Setup Time
ООООООООООООО
ООООООООООООО
Clock Enable Removal Time
ООООООООООООО
= 25_C)
A
Symbol
ÎÎÎ
t
,
TLH
t
THL
ÎÎÎ
t
,
PLH
ÎÎÎ
t
PHL
ÎÎÎ
ÎÎÎ
t
,
PLH
t
PHL
ÎÎÎ
ÎÎÎ
ÎÎÎ
t
,
PLH
t
PHL
ÎÎÎ
ÎÎÎ
t
PLH
ÎÎÎ
ÎÎÎ
ÎÎÎ
t
w(H)
ÎÎÎ
f
cl
ÎÎÎ
ÎÎÎ
t
w(H)
ÎÎÎ
t
rem
ÎÎÎ
t
,
TLH
t
ÎÎÎ
THL
ÎÎÎ
t
su
ÎÎÎ
ÎÎÎ
t
rem
ÎÎÎ
V
DD
Vdc
ÎÎ
5.0
10
ÎÎ
15
ÎÎ
5.0
ÎÎ
10
ÎÎ
15
ÎÎ
5.0
ÎÎ
10
15
ÎÎ
ÎÎ
5.0
10
ÎÎ
15
ÎÎ
5.0
ÎÎ
10
ÎÎ
15
5.0
10
ÎÎ
15
5.0
ÎÎ
10
15
ÎÎ
5.0
10
ÎÎ
15
5.0
10
ÎÎ
15
5.0
10
ÎÎ
15
ÎÎ
5.0
ÎÎ
10
15
ÎÎ
5.0
10
ÎÎ
15
Min
ÎÎ
—
—
ÎÎ
—
ÎÎ
—
ÎÎ
—
ÎÎ
—
ÎÎ
—
ÎÎ
—
—
ÎÎ
ÎÎ
—
—
ÎÎ
—
ÎÎ
—
ÎÎ
—
ÎÎ
—
250
100
ÎÎ
75
—
ÎÎ
—
—
ÎÎ
500
250
ÎÎ
190
750
275
ÎÎ
210
ОООООООО
ОООООООО
350
ÎÎ
150
115
ÎÎ
420
200
ÎÎ
140
Typ
(Note 6)
ÎÎ
100
50
ÎÎ
40
ÎÎ
500
ÎÎ
230
ÎÎ
175
ÎÎ
400
ÎÎ
175
125
ÎÎ
ÎÎ
500
230
ÎÎ
175
ÎÎ
400
ÎÎ
175
ÎÎ
125
125
50
ÎÎ
35
5.0
ÎÎ
12
16
ÎÎ
250
125
ÎÎ
95
375
135
ÎÎ
105
No Limit
175
ÎÎ
75
52
ÎÎ
260
100
ÎÎ
70
Max
ÎÎ
200
100
ÎÎ
80
ÎÎ
1000
ÎÎ
460
ÎÎ
350
ÎÎ
800
ÎÎ
350
250
ÎÎ
ÎÎ
1000
460
ÎÎ
350
ÎÎ
800
ÎÎ
350
ÎÎ
250
—
—
ÎÎ
—
2.0
ÎÎ
5.0
6.7
ÎÎ
—
—
ÎÎ
—
—
—
ÎÎ
—
—
ÎÎ
—
—
ÎÎ
—
—
ÎÎ
—
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Unit
Î
ns
Î
ns
Î
Î
Î
ns
Î
Î
Î
ns
Î
Î
ns
Î
Î
Î
ns
Î
MHz
Î
Î
ns
Î
ns
Î
—
Î
Î
ns
Î
Î
ns
Î
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4
MC14017B
V
DD
V
I
D
EXTERNAL
POWER
out
Decode
Outputs
Carry
VGS =− V
VDS =V
V
SS
CLOCK
ENABLE
Q0
Q1
Q2
Q3
A
V
DD
V
SS
S1
B
S1
RESET
Q4
Q5
Q6
Q7
Q8
Q9
C
CLOCK
out
SUPPLY
V
SS
Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit
V
DD
Output
Sink Drive
(S1 to A)
Clock to 5
thru 9
(S1 to B)
V
DD
V
out
Output
Source Drive
Clock to
desired
outputs
(S1 to B)
S1 to A
DD
− V
out
DD
PULSE
GENERATOR
500 mF
I
D
0.01 mF
CERAMIC
Q0
Q1
CLOCK
ENABLE
Q2
Q3
Q4
RESET
Q5
Q6
f
c
CLOCK
Q7
Q8
Q9
C
out
V
SS
CLCLCLCLCLCLCLCLCLCLC
L
Figure 2. Typical Power Dissipation Test Circuit
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5
MC14017B
APPLICATIONS INFORMATION
Figure 3 shows a technique for extending the number of decoded output states for the MC14017B. Decoded outputs are
sequential within each stage and from stage to stage, with no dead time (except propagation delay).
CLOCK
CLOCK
ENABLE
RESET
20 ns
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
C
out
t
rem
t
CLOCK
Pcp
PLH
t
PLH
CLOCK
MC14017B
CE
Q0 Q1 Q8 Q9
9 DECODED
OUTPUTS
FIRST STAGE INTERMEDIATE STAGES LAST STAGE
Ncp
t
PHL
t
PHL
t
PLH
t
PLH
RESET
•••
t
PHL
50%
t
PLH
t
PHL
t
PLH
t
THL
RESET
CLOCK
MC14017B
CE
•••
Q0Q1 Q8 Q9
8 DECODED
OUTPUTS
Figure 3. Counter Expansion
t
rem
t
PHL
t
PHL
t
PHL
THL
t
PLH
t
90%
TLH
t
THL
t
PHL
t
PLH
10%
t
PHL
t
PLH
t
t
t
THL
TLH
t
PLH
RESET
CLOCK
MC14017B
CE
•••
Q1 Q8 Q9
8 DECODED
OUTPUTS
90%
PLH
t
10%
THL
t
TLH
50%
t
THL
20 ns
t
TLH
t
THL
t
t
TLH
TLH
20 ns
t
t
THL
t
20 ns
su
20 ns20 ns
t
PLH
90%
10%
t
TLH
t
TLH
t
PHL
t
THL
t
t
PHL
t
TLH
t
PHL
t
50%
THL
THL
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
Figure 4. AC Measurement Definition and Functional Waveforms
http://onsemi.com
6
MC14017B
PACKAGE DIMENSIONS
PDIP−16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648−08
ISSUE T
−A−
916
B
18
F
C
S
SEATING
−T−
PLANE
H
G
D
16 PL
0.25 (0.010) T
K
M
A
L
J
M
SOIC−16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM MIN MAX MIN MAX
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
M
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01
MILLIMETERSINCHES
____
−T−
−A−
16 9
−B−
18
G
K
C
SEATING
PLANE
D
16 PL
0.25 (0.010) A
M
S
B
T
S
8 PLP
0.25 (0.010) B
M
M
R X 45
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
S
_
F
J
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
DIM MIN MAX MIN MAX
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
____
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
INCHESMILLIMETERS
http://onsemi.com
7
16 9
1
Z
D
e
b
0.13 (0.005)
M
8
H
E
E
A
A
1
0.10 (0.004)
MC14017B
PACKAGE DIMENSIONS
SOEIAJ−16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966−01
ISSUE O
L
E
M
_
L
DETAIL P
VIEW P
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
Q
1
c
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
MILLIMETERS
DIM MIN MAX MIN MAX
−−− 2.05 −−− 0.081
A
A
0.05 0.20 0.002 0.008
1
0.35 0.50 0.014 0.020
b
0.18 0.27 0.007 0.011
c
9.90 10.50 0.390 0.413
D
5.10 5.45 0.201 0.215
E
1.27 BSC 0.050 BSC
e
H
7.40 8.20 0.291 0.323
E
0.50 0.85 0.020 0.033
L
L
1.10 1.50 0.043 0.059
E
0
M
_
Q
0.70 0.90 0.028 0.035
1
−−− 0.78 −−− 0.031
Z
INCHES
10
_
10
0
_
_
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MC14017B/D
8
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