ON Semiconductor MC10EP35, MC100EP35 Technical data

MC10EP35, MC100EP35

3.3V / 5V ECL JK Flip-Flop

Description

The MC10/100EP35 is a higher speed/low voltage version of the
EL35 JK flip−flop. The J/K data enters the master portion of the
flip−flop when the clock is LOW and is transferred to the slave, and
thus the outputs, upon a positive transition of the clock. The reset pin is
asynchronous and is activated with a logic HIGH.

The 100 Series contains temperature compensation.

Features

• 410 ps Propagation Delay

• Maximum Frequency > 3 GHz Typical

• PECL Mode Operating Range: V

with VEE = 0 V

• NECL Mode Operating Range: V

with VEE = −3.0 V to −5.5 V

• Open Input Default State

• Q Output Will Default LOW with Inputs Open or at V

• Pb−Free Packages are Available

= 3.0 V to 5.5 V

CC

= 0 V

CC

EE

8

1

SOIC−8
D SUFFIX
CASE 751

8

1

TSSOP−8

DT SUFFIX

CASE 948R

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MARKING

DIAGRAMS*

8

HEP35

ALYW

G

1

8

HP35

ALYWG

G

1

8

KEP35

ALYW

G

1

8

KP35

ALYWG

G

1

G

5R MG

DFN8

MN SUFFIX

CASE 506AA

H = MC10 A = Assembly Location
K = MC100 L = Wafer Lot
5R = MC10 Y = Year
3M = MC100 W = Work Week

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

14

M = Date Code

G = Pb−Free Package

G

3M MG

14

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.

© Semiconductor Components Industries, LLC, 2008

August, 2008 − Rev. 6

1 Publication Order Number:

MC10EP35/D

MC10EP35, MC100EP35

1

RESET

J

2

K

3

45

J

K

Flip Flop

R

Figure 1. 8−Lead Pinout (Top View) and Logic Diagram

78Q

6

V

CC

QCLK

V

EE

Table 1. PIN DESCRIPTION

PIN

CLK*

J*, K* ECL Signal Inputs

RESET* ECL Asynchronous Reset

Q, Q ECL Data Outputs

V

CC

V

EE

EP (DFN8 only) Thermal exposed pad must be

* Pins will default LOW when left open.

FUNCTION

ECL Clock Inputs

Positive Supply

Negative Supply

connected to a sufficient thermal conduit.
Electrically connect to the most negative
supply (GND) or leave unconnected, float­ing open.

Table 2. TRUTH TABLE

J

K

RESET

CLK

Qn+1

L
L
H
H
X

Z = LOW to HIGH Transition

L­H
L
H
X

L
L
L
L
H

Z
Z
Z
Z
X

Table 3. ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor

Internal Input Pullup Resistor N/A

ESD Protection Human Body Model

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg Pb−Free Pkg

Flammability Rating Oxygen Index: 28 to 34 UL−94 V−0 @ 0.125 in

Transistor Count 77 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

Machine Model

Charged Device Model

SOIC−8

TSSOP−8

DFN8

Level 1

Level 1

Level 1

75 kW

> 4 kV

> 200 V

> 2 kV

Level 1
Level 3
Level 1

Qn

L

H

Qn

L

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2

MC10EP35, MC100EP35

Table 4. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

V

CC

V

EE

V

I

I

out

T

A

T

stg

q

JA

q

JC

q

JA

q

JC

q

JA

T

sol

q

JC

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.

2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)

PECL Mode Power Supply VEE = 0 V 6 V

NECL Mode Power Supply VCC = 0 V −6 V

PECL Mode Input Voltage
NECL Mode Input Voltage

Output Current Continuous

VEE = 0 V
VCC = 0 V

Surge

VI  V
VI  V

CC

EE

6

−6

50

100

V
V

mA
mA

Operating Temperature Range −40 to +85 °C

Storage Temperature Range −65 to +150 °C

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

8 SOIC
8 SOIC

190
130

°C/W
°C/W

Thermal Resistance (Junction−to−Case) Standard Board 8 SOIC 41 to 44 °C/W

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

8 TSSOP
8 TSSOP

185
140

°C/W
°C/W

Thermal Resistance (Junction−to−Case) Standard Board 8 TSSOP 41 to 44 °C/W

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

Wave Solder Pb

Pb−Free

<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C

DFN8
DFN8

129

84

265
265

°C/W
°C/W

°C

Thermal Resistance (Junction−to−Case) (Note 2) DFN8 35 to 40 °C/W

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MC10EP35, MC100EP35

Table 5. 10EP DC CHARACTERISTICS, PECL V

= 3.3 V, VEE = 0 V (Note 3)

CC

−40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

I

EE

V

OH

V

OL

V

IH

V

IL

I

IH

I

IL

Power Supply Current 30 40 50 30 40 50 30 40 50 mA

Output HIGH Voltage (Note 4) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV

Output LOW Voltage (Note 4) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV

Input HIGH Voltage (Single−Ended) 2090 2415 2155 2480 2215 2540 mV

Input LOW Voltage (Single−Ended) 1365 1690 1460 1755 1490 1815 mV

Input HIGH Current 150 150 150

Input LOW Current 0.5 0.5 0.5

mA

mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.

3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.

4. All loading with 50 W to VCC − 2.0 V.

Table 6. 10EP DC CHARACTERISTICS, PECL V

= 5.0 V, VEE = 0 V (Note 5)

CC

−40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

I

EE

V

OH

V

OL

V

IH

V

IL

I

IH

I

IL

Power Supply Current 30 40 50 30 40 50 30 40 50 mA

Output HIGH Voltage (Note 6) 3865 3940 4115 3930 4055 4180 3990 4115 4240 mV

Output LOW Voltage (Note 6) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mV

Input HIGH Voltage (Single−Ended) 3790 4115 3855 4180 3915 4240 mV

Input LOW Voltage (Single−Ended) 3065 3390 3130 3455 3190 3515 mV

Input HIGH Current 150 150 150

Input LOW Current 0.5 0.5 0.5

mA

mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.

5. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V.

6. All loading with 50 W to VCC − 2.0 V.

Table 7. 10EP DC CHARACTERISTICS, NECL V

= 0 V; V

CC

= −5.5 V to −3.0 V (Note 7)

EE

−40°C 25°C 85°C

Symbol Characteristic Min Ty p Max Min Ty p Max Min Typ Max Unit

I

EE

V

OH

V

OL

V

IH

V

IL

I

IH

I

IL

Power Supply Current 30 40 50 30 40 50 30 40 50 mA

Output HIGH Voltage (Note 8) −1135 −1010 −885 −1070 −945 −820 −1010 −885 −760 mV

Output LOW Voltage (Note 8) −1935 −1810 −1685 −1870 −1745 −1620 −1810 −1685 −1560 mV

Input HIGH Voltage (Single−Ended) −1210 −885 −1145 −820 −1085 −760 mV

Input LOW Voltage (Single−Ended) −1935 −1610 −1870 −1545 −1810 −1485 mV

Input HIGH Current 150 150 150

Input LOW Current 0.5 0.5 0.5

mA

mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.

7. Input and output parameters vary 1:1 with VCC.

8. All loading with 50 W to VCC − 2.0 V.

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MC10EP35, MC100EP35

Table 8. 100EP DC CHARACTERISTICS, PECL V

= 3.3 V, VEE = 0 V (Note 9)

CC

−40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

I

EE

V

OH

V

OL

V

IH

V

IL

I

IH

I

IL

Power Supply Current 30 40 50 30 40 50 30 40 50 mA

Output HIGH Voltage (Note 10) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV

Output LOW Voltage (Note 10) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV

Input HIGH Voltage (Single−Ended) 2075 2420 2075 2420 2075 2420 mV

Input LOW Voltage (Single−Ended) 1355 1675 1355 1675 1355 1675 mV

Input HIGH Current 150 150 150

Input LOW Current 0.5 0.5 0.5

mA

mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.

9. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.

10.All loading with 50 W to VCC − 2.0 V.

Table 9. 100EP DC CHARACTERISTICS, PECL V

= 5.0 V, VEE = 0 V (Note 11)

CC

−40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

I

EE

V

OH

V

OL

V

IH

V

IL

I

IH

I

IL

Power Supply Current 30 40 50 30 40 50 30 40 50 mA

Output HIGH Voltage (Note 12) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV

Output LOW Voltage (Note 12) 3055 3180 3305 3055 3180 3305 3055 3180 3305 mV

Input HIGH Voltage (Single−Ended) 3775 4120 3775 4120 3775 4120 mV

Input LOW Voltage (Single−Ended) 3055 3375 3055 3375 3055 3375 mV

Input HIGH Current 150 150 150

Input LOW Current 0.5 0.5 0.5

mA

mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.

11.Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V.

12.All loading with 50 W to VCC − 2.0 V.

Table 10. 100EP DC CHARACTERISTICS, NECL V

= 0 V; V

CC

= −5.5 V to −3.0 V (Note 13)

EE

−40°C 25°C 85°C

Symbol Characteristic Min Ty p Max Min Ty p Max Min Typ Max Unit

I

EE

V

OH

V

OL

V

IH

V

IL

I

IH

I

IL

Power Supply Current 30 40 50 30 40 50 30 40 50 mA

Output HIGH Voltage (Note 14) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV

Output LOW Voltage (Note 14) −1945 −1820 −1695 −1945 −1820 −1695 −1945 −1820 −1695 mV

Input HIGH Voltage (Single−Ended) −1225 −880 −1225 −880 −1225 −880 mV

Input LOW Voltage (Single−Ended) −1945 −1625 −1945 −1625 −1945 −1625 mV

Input HIGH Current 150 150 150

Input LOW Current 0.5 0.5 0.5

mA

mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.

13.Input and output parameters vary 1:1 with VCC.

14.All loading with 50 W to VCC − 2.0 V.

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5

MC10EP35, MC100EP35

Table 11. AC CHARACTERISTICS V

= 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; V

CC

= 0 V (Note 15)

EE

−40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Ty p Max Min Typ Max Unit

f

max

t

PLH

t

PHL

t

RR

t

S

t

H

t

PW

Maximum Frequency
(See Figure 2. F

,

Propagation Delay to

max

/JITTER)

Output Differential R, CLK to Q, Q

200 400 480 200 410 490 200 420 575

> 3 > 3 > 3 GHz

Reset Recovery 150 80 150 90 150 100 ps

Setup Time
Hold Time

150
1505050

150
1505050

150
1508080

Minimum Pulse width

ps

ps

ps

RESET 550 400 550 400 550 400

t

JITTER

t

r

t

f

Cycle−to−Cycle Jitter
(See Figure 2. F

max

/JITTER)

Output Rise/Fall Times Q, Q
(20% − 80%)

0.2 < 1 0.2 < 1 0.2 < 1 ps

70 120 170 80 130 180 100 150 200 ps

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.

15.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V.

900

9

800

700

(mV)

600

OUTpp

500

V

400

300

200

(JITTER)

100

0

0 1000 2000 3000 4000 5000

FREQUENCY (MHz)

Figure 2. F

max

/Jitter

8

7

6

5

4

3

2

1

ps (RMS)

OUT

JITTER

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6

MC10EP35, MC100EP35

Zo = 50 W

Zo = 50 W

50 W 50 W

V

VTT = VCC − 2.0 V

TT

Receiver
Device

Driver
Device

QD

Q D

Figure 3. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020/D − Termination of ECL Logic Devices.)

ORDERING INFORMATION

Device Package Shipping

MC10EP35D SOIC−8 98 Units / Rail

MC10EP35DG SOIC−8

(Pb−Free)

MC10EP35DR2 SOIC−8 2500 / Tape & Reel

MC10EP35DR2G SOIC−8

(Pb−Free)

MC10EP35DT TSSOP−8 100 Units / Rail

MC10EP35DTG TSSOP−8

(Pb−Free)

MC10EP35DTR2 TSSOP−8 2500 / Tape & Reel

MC10EP35DTR2G TSSOP−8

(Pb−Free)

MC10EP35MNR4 DFN8 1000 / Tape & Reel

MC10EP35MNR4G DFN8

(Pb−Free)

MC100EP35D SOIC−8 98 Units / Rail

MC100EP35DG SOIC−8

(Pb−Free)

MC100EP35DR2 SOIC−8 2500 / Tape & Reel

MC100EP35DR2G SOIC−8

(Pb−Free)

MC3100EP35DT TSSOP−8 100 Units / Rail

MC3100EP35DTG TSSOP−8

(Pb−Free)

MC100EP35DTR2 TSSOP−8 2500 / Tape & Reel

MC100EP35DTR2G TSSOP−8

(Pb−Free)

MC100EP35MNR4 DFN8 1000 / Tape & Reel

MC100EP35MNR4G DFN8

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

98 Units / Rail

2500 / Tape & Reel

100 Units / Rail

2500 / Tape & Reel

1000 / Tape & Reel

98 Units / Rail

2500 / Tape & Reel

100 Units / Rail

2500 / Tape & Reel

1000 / Tape & Reel

†

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7

MC10EP35, MC100EP35

Resource Reference of Application Notes

AN1405/D − ECL Clock Distribution Techniques

AN1406/D − Designing with PECL (ECL at +5.0 V)

AN1503/D −

AN1504/D − Metastability and the ECLinPS Family

AN1568/D − Interfacing Between LVDS and ECL

AN1672/D − The ECL Translator Guide

AND8001/D − Odd Number Counters Design

AND8002/D − Marking and Date Codes

AND8020/D − Termination of ECL Logic Devices

AND8066/D − Interfacing with ECLinPS

AND8090/D − AC Characteristics of ECL Devices

ECLinPSt I/O SPiCE Modeling Kit

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8

−Y−

−Z−

MC10EP35, MC100EP35

PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AH

−X−

B

H

A

58

1

4

G

D

0.25 (0.010) Z

M

S

0.25 (0.010)

M

M

Y

K

Y

C

SXS

SEATING
PLANE

0.10 (0.004)

N

X 45

_

M

J

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0 8 0 8

____

N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244

INCHES

SOLDERING FOOTPRINT*

1.52

0.060

7.0

0.275

0.6

0.024

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

4.0

0.155

1.270

0.050

SCALE 6:1

mm

ǒ

inches

Ǔ

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9

0.10 (0.004)

−T−

SEATING
PLANE

MC10EP35, MC100EP35

PACKAGE DIMENSIONS

TSSOP−8

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948R−02

ISSUE A

8x REFK

S

U0.15 (0.006) T

2X L/2

85

L

PIN 1
IDENT

S

U0.15 (0.006) T

0.10 (0.004) V

1

−U−

4

A

M

B

−V−

S

U

T

S

0.25 (0.010)

M

F

DETAIL E

C

D

G

DETAIL E

−W−

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.

5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.

DIM MIN MAX MIN MAX

A 2.90 3.10 0.114 0.122
B 2.90 3.10 0.114 0.122
C 0.80 1.10 0.031 0.043
D 0.05 0.15 0.002 0.006
F 0.40 0.70 0.016 0.028
G 0.65 BSC 0.026 BSC
K 0.25 0.40 0.010 0.016
L 4.90 BSC 0.193 BSC
M 0 6 0 6

____

INCHESMILLIMETERS

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10

MC10EP35, MC100EP35

ÇÇÇ

ÇÇÇ

ÇÇÇ

l

PACKAGE DIMENSIONS

DFN8

CASE 506AA−01

ISSUE D

8 X

REFERENCE

2 X

SEATING
PLANE

PIN ONE

2 X

C0.10

C0.08

C0.10

A1

8 X

D

A

B

E

C0.10

TOP VIEW

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994 .

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.25 AND 0.30 MM FROM TERMINAL.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

MILLIMETERS

DIM MIN MAX

A 0.80 1.00
A1 0.00 0.05
A3 0.20 REF

b 0.20 0.30

D 2.00 BSC
D2 1.10 1.30

E 2.00 BSC
E2 0.70 0.90

e 0.50 BSC

K 0.20 −−−

L 0.25 0.35

A

SIDE VIEW

(A3)

C

D2

e/2

1

e

4

L

E2

K

8

5

8 X

0.10 C

b

0.05 C

A BB

NOTE 3

BOTTOM VIEW

ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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MC10EP35/D

11