ON Semiconductor MC10EP35, MC100EP35 Technical data

MC10EP35, MC100EP35

3.3V / 5V ECL JK Flip-Flop

Description

The MC10/100EP35 is a higher speed/low voltage version of the
EL35 JK flip−flop. The J/K data enters the master portion of the
flip−flop when the clock is LOW and is transferred to the slave, and
thus the outputs, upon a positive transition of the clock. The reset pin is
asynchronous and is activated with a logic HIGH.

The 100 Series contains temperature compensation.

Features

• 410 ps Propagation Delay

• Maximum Frequency > 3 GHz Typical

• PECL Mode Operating Range: V

with VEE = 0 V

• NECL Mode Operating Range: V

with VEE = −3.0 V to −5.5 V

• Open Input Default State

• Q Output Will Default LOW with Inputs Open or at V

• Pb−Free Packages are Available

= 3.0 V to 5.5 V

CC

= 0 V

CC

EE

8

1

SOIC−8
D SUFFIX
CASE 751

8

1

TSSOP−8

DT SUFFIX

CASE 948R

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MARKING

DIAGRAMS*

8

HEP35

ALYW

G

1

8

HP35

ALYWG

G

1

8

KEP35

ALYW

G

1

8

KP35

ALYWG

G

1

G

5R MG

DFN8

MN SUFFIX

CASE 506AA

H = MC10 A = Assembly Location
K = MC100 L = Wafer Lot
5R = MC10 Y = Year
3M = MC100 W = Work Week

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

14

M = Date Code

G = Pb−Free Package

G

3M MG

14

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.

© Semiconductor Components Industries, LLC, 2008

August, 2008 − Rev. 6

1 Publication Order Number:

MC10EP35/D

MC10EP35, MC100EP35

1

RESET

J

2

K

3

45

J

K

Flip Flop

R

Figure 1. 8−Lead Pinout (Top View) and Logic Diagram

78Q

6

V

CC

QCLK

V

EE

Table 1. PIN DESCRIPTION

PIN

CLK*

J*, K* ECL Signal Inputs

RESET* ECL Asynchronous Reset

Q, Q ECL Data Outputs

V

CC

V

EE

EP (DFN8 only) Thermal exposed pad must be

* Pins will default LOW when left open.

FUNCTION

ECL Clock Inputs

Positive Supply

Negative Supply

connected to a sufficient thermal conduit.
Electrically connect to the most negative
supply (GND) or leave unconnected, float­ing open.

Table 2. TRUTH TABLE

J

K

RESET

CLK

Qn+1

L
L
H
H
X

Z = LOW to HIGH Transition

L­H
L
H
X

L
L
L
L
H

Z
Z
Z
Z
X

Table 3. ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor

Internal Input Pullup Resistor N/A

ESD Protection Human Body Model

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg Pb−Free Pkg

Flammability Rating Oxygen Index: 28 to 34 UL−94 V−0 @ 0.125 in

Transistor Count 77 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

Machine Model

Charged Device Model

SOIC−8

TSSOP−8

DFN8

Level 1

Level 1

Level 1

75 kW

> 4 kV

> 200 V

> 2 kV

Level 1
Level 3
Level 1

Qn

L

H

Qn

L

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2

MC10EP35, MC100EP35

Table 4. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

V

CC

V

EE

V

I

I

out

T

A

T

stg

q

JA

q

JC

q

JA

q

JC

q

JA

T

sol

q

JC

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.

2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)

PECL Mode Power Supply VEE = 0 V 6 V

NECL Mode Power Supply VCC = 0 V −6 V

PECL Mode Input Voltage
NECL Mode Input Voltage

Output Current Continuous

VEE = 0 V
VCC = 0 V

Surge

VI  V
VI  V

CC

EE

6

−6

50

100

V
V

mA
mA

Operating Temperature Range −40 to +85 °C

Storage Temperature Range −65 to +150 °C

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

8 SOIC
8 SOIC

190
130

°C/W
°C/W

Thermal Resistance (Junction−to−Case) Standard Board 8 SOIC 41 to 44 °C/W

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

8 TSSOP
8 TSSOP

185
140

°C/W
°C/W

Thermal Resistance (Junction−to−Case) Standard Board 8 TSSOP 41 to 44 °C/W

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

Wave Solder Pb

Pb−Free

<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C

DFN8
DFN8

129

84

265
265

°C/W
°C/W

°C

Thermal Resistance (Junction−to−Case) (Note 2) DFN8 35 to 40 °C/W

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MC10EP35, MC100EP35

Table 5. 10EP DC CHARACTERISTICS, PECL V

= 3.3 V, VEE = 0 V (Note 3)

CC

−40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

I

EE

V

OH

V

OL

V

IH

V

IL

I

IH

I

IL

Power Supply Current 30 40 50 30 40 50 30 40 50 mA

Output HIGH Voltage (Note 4) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV

Output LOW Voltage (Note 4) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV

Input HIGH Voltage (Single−Ended) 2090 2415 2155 2480 2215 2540 mV

Input LOW Voltage (Single−Ended) 1365 1690 1460 1755 1490 1815 mV

Input HIGH Current 150 150 150

Input LOW Current 0.5 0.5 0.5

mA

mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.

3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.

4. All loading with 50 W to VCC − 2.0 V.

Table 6. 10EP DC CHARACTERISTICS, PECL V

= 5.0 V, VEE = 0 V (Note 5)

CC

−40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

I

EE

V

OH

V

OL

V

IH

V

IL

I

IH

I

IL

Power Supply Current 30 40 50 30 40 50 30 40 50 mA

Output HIGH Voltage (Note 6) 3865 3940 4115 3930 4055 4180 3990 4115 4240 mV

Output LOW Voltage (Note 6) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mV

Input HIGH Voltage (Single−Ended) 3790 4115 3855 4180 3915 4240 mV

Input LOW Voltage (Single−Ended) 3065 3390 3130 3455 3190 3515 mV

Input HIGH Current 150 150 150

Input LOW Current 0.5 0.5 0.5

mA

mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.

5. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V.

6. All loading with 50 W to VCC − 2.0 V.

Table 7. 10EP DC CHARACTERISTICS, NECL V

= 0 V; V

CC

= −5.5 V to −3.0 V (Note 7)

EE

−40°C 25°C 85°C

Symbol Characteristic Min Ty p Max Min Ty p Max Min Typ Max Unit

I

EE

V

OH

V

OL

V

IH

V

IL

I

IH

I

IL

Power Supply Current 30 40 50 30 40 50 30 40 50 mA

Output HIGH Voltage (Note 8) −1135 −1010 −885 −1070 −945 −820 −1010 −885 −760 mV

Output LOW Voltage (Note 8) −1935 −1810 −1685 −1870 −1745 −1620 −1810 −1685 −1560 mV

Input HIGH Voltage (Single−Ended) −1210 −885 −1145 −820 −1085 −760 mV

Input LOW Voltage (Single−Ended) −1935 −1610 −1870 −1545 −1810 −1485 mV

Input HIGH Current 150 150 150

Input LOW Current 0.5 0.5 0.5

mA

mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.

7. Input and output parameters vary 1:1 with VCC.

8. All loading with 50 W to VCC − 2.0 V.

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