ON Semiconductor MC10EP195, MC100EP195 Technical data

MC10EP195, MC100EP195

3.3V ECL Programmable
Delay Chip

The MC10/100EP195 is a Programmable Delay Chip (PDC)
designed primarily for clock deskewing and timing adjustment. It
provides variable delay of a differential NECL/PECL input transition.

The delay section consists of a programmable matrix of gates and
multiplexers as shown in the logic diagram, Figure 3. The delay
increment of the EP195 has a digitally selectable resolution of about
10 ps and a net range of up to 10.2 ns. The required delay is selected by
the 10 data select inputs D[9:0] values and controlled by the LEN
(pin 10). A LOW level on LEN allows a transparent LOAD mode of
real time delay values by D[9:0]. A LOW to HIGH transition on LEN
will LOCK and HOLD current values present against any subsequent
changes in D[10:0]. The approximate delay values for varying tap
numbers correlating to D0 (LSB) through D9 (MSB) are shown in
Table 6 and Figure 4.

Because the EP195 is designed using a chain of multiplexers it has a
fixed minimum delay of 2.2 ns. An additional pin D10 is provided for
controlling Pins 14 and 15, CASCADE and CASCADE
by LEN, in cascading multiple PDCs for increased programmable
range. The cascade logic allows full control of multiple PDCs.
Switching devices from all “1” states on D[0:9] with SETMAX LOW
to all “0” states on D[0:9] with SETMAX HIGH will increase the
delay equivalent to “D0”, the minimum increment.

Select input pins D[10:0] may be threshold controlled by
combinations of interconnects between V

(pin 7) and VCF (pin 8)

EF

for LVCMOS, ECL, or LVTTL level signals. For LVCMOS input
levels, leave V
V

(Pins 7 and 8). For LVTTL level operation, connect a 1.5 V

EF

supply reference to V
voltage to V
between V

The V

BB

and VEF open. For ECL operation, short VCF and

CF

and leave open VEF pin. The 1.5 V reference

CF

pin can be accomplished by placing a 2.2 kW resistor

CF

and VEE for a 3.3 V power supply.

CF

pin, an internally generated voltage supply, is available to
this device only. For single−ended input conditions, the unused
differential input is connected to V
V

may also rebias AC coupled inputs. When used, decouple V

BB

as a switching reference voltage.

BB

and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V

should be left open.

BB

The 100 Series contains temperature compensation.

• Maximum Input Clock Frequency >1.2 GHz Typical

• Programmable Range: 0 ns to 10 ns

• Delay Range: 2.2 ns to 12.2 ns

• 10 ps Increments

• PECL Mode Operating Range:

= 3.0 V to 3.6 V with VEE = 0 V

V

CC

• NECL Mode Operating Range:

= 0 V with VEE = −3.0 V to −3.6 V

V

CC

, also latched

BB

• Open Input Default State

• Safety Clamp on Inputs

• A Logic High on the EN Pin Will Force Q to Logic

Low

• D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL

Inputs

• V

• Pb−Free Packages are Available

http://onsemi.com

MARKING

DIAGRAM*

AWLYYWWG

LQFP−32

FA SUFFIX

CASE 873A

32

1

QFN32

MN SUFFIX

CASE 488AM

XXX = 10 or 100
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.

Output Reference Voltage

BB

32

1

1

AWLYYWWG

MCXXX

EP195

MCXXX

EP195

G

© Semiconductor Components Industries, LLC, 2006

December, 2006 − Rev. 16

1 Publication Order Number:

MC10EP195/D

MC10EP195, MC100EP195

D8

D9

D10

IN

IN

V

BB

V

EF

V

CF

D7

D6

D5

D4

EE

V

D3

D2

D1

2526272829303132

1

2

3

4

5

6

7

8

VEELEN

MC10EP195

MC100EP195

SETMAX

SETMIN

CC

V

CASCADE

24

23

22

21

20

19

18

17

16

1514131211109

CASCADE

EN

Figure 1. 32−Lead LQFP Pinout (Top View)

V

D0

V

V

V

NC

EE

CC

Q

Q

CC

CC

D8

D9

D10

IN

IN

V

BB

V

EF

V

CF

V

EE

CC

V

D3

CASCADE

D4

D5

D6

D7

32 31 30 29 28 27 26 25

1

2

3

4

5

6

7

8

9 10 1112 1314 1516

VEELEN

SETMAX

SETMIN

Figure 2. 32−Lead QFN (Top View)

D2

D1

CASCADE

EN

24

V

EE

23

D0

22

V

CC

21

Q

20

Q

V

19

CC

V

18

CC

17

NC

Exposed Pad (EP)

http://onsemi.com

2

MC10EP195, MC100EP195

Table 1. PIN DESCRIPTION

Pin Name I/O Default State Description

23, 25, 26, 27,
29, 30, 31, 32,

1, 2

3 D[10] LVCMOS, LVTTL,

4 IN ECL Input Low

5 IN ECL Input High

6 V

7 V

8 V

9, 24, 28 V

13, 18, 19, 22 V

10 LEN ECL Input Low

11 SETMIN ECL Input Low

12 SETMAX ECL Input Low

14 CASCADE ECL Output − Inverted Differential Cascade Output for D[10]. Typically Terminated

15 CASCADE ECL Output − Noninverted Differential Cascade Output. for D[10] Typically

16 EN ECL Input Low

17 NC − − No Connect. The NC Pin is Electrically Connected to the Die and

21 Q ECL Output −

20 Q ECL Output −

1. SETMIN will override SETMAX if both are high. SETMAX and SETMIN will override all D[0:10] inputs.

2. All V

and VEE pins must be externally connected to Power Supply to guarantee proper operation.

CC

D[0:9] LVCMOS, LVTTL,

ECL Input

ECL Input

BB

EF

CF

EE

CC

− − ECL Reference Voltage Output

− − Reference Voltage for ECL Mode Connection

− − LVCMOS, ECL, OR LVTTL Input Mode Select

− − Negative Supply Voltage. All VEE Pins must be Externally

− − Positive Supply Voltage. All VCC Pins must be externally

Low

Low

Single−Ended Parallel Data Inputs [0:9]. Internal 75 kW to VEE.
(Note 1)

Single−Ended CASCADE/CASCADE Control Input. Internal 75 kW
to V

. (Note 1)

EE

Noninverted Differential Input. Internal 75 kW to VEE.

Inverted Differential Input. Internal 75 kW to VEE and 36.5 kW to
V

.

CC

Connected to Power Supply to Guarantee Proper Operation.
(Note 2)

Connected to Power Supply to Guarantee Proper Operation.
(Note 2)

Single−ended D pins LOAD / HOLD input. Internal 75 kW to VEE.

Single−ended Minimum Delay Set Logic Input. Internal 75 kW to
V

. (Note 1)

EE

Single−ended Maximum Delay Set Logic Input. Internal 75 kW to
V

. (Note 1)

EE

with 50 W to V

Terminated with 50 W to V

= VCC − 2 V.

TT

= VCC − 2 V.

TT

Single−ended Output Enable Pin. Internal 75 kW to VEE.

”MUST BE” Left Open

Noninverted Differential Output. Typically Terminated with 50 W to
V

= VCC − 2 V.

TT

Inverted Differential Output. Typically Terminated with 50 W to
VTT = VCC − 2 V.

http://onsemi.com

3

MC10EP195, MC100EP195

Table 2. CONTROL PIN

Pin State Function

EN

LEN

SETMIN

SETMAX

D10

3. Internal pulldown resistor will provide a logic LOW if pin is left unconnected.

Table 3. CONTROL D[0:10] INTERFACE

V

CF

V

CF

V

CF

4. Short VCF (pin 8) and VEF (pin 7).

5. When Operating in LVTTL Mode, the reference voltage can be provided by connecting an external resistor, R
is 2.2 kW $5%), between V

LOW (Note 3) Input Signal is Propagated to the Output

HIGH Output Holds Logic Low State

LOW (Note 3) Transparent or LOAD mode for real time delay values present on D[0:10].

HIGH LOCK and HOLD mode for delay values on D[0:10]; further changes on D[0:10]

LOW (Note 3) Output Delay set by D[0:10]

HIGH Set Minimum Output Delay

LOW (Note 3) Output Delay set by D[0:10]

HIGH Set Maximum Output Delay

LOW (Note 3) CASCADE Output LOW, CASCADE Output HIGH

HIGH CASCADE Output LOW, CASCADE Output HIGH

VEF Pin (Note 4) ECL Mode

No Connect LVCMOS Mode

1.5 V $ 100 mV LVTTL Mode (Note 5)

and VEE pins.

CF

are not recognized and do not affect delay.

(suggested resistor value

CF

Table 4. DATA INPUT ALLOWED OPERATING VOLTAGE MODE TABLE

CONTROL DATA SELECT INPUTS PINS (D [0:10])

POWER SUPPLY

PECL Mode Operating Range YES YES YES N/A

NECL Mode Operating Range N/A N/A N/A YES

LVCMOS LVTTL LVPECL LVNECL

Table 5. ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor (R1)

ESD Protection Human Body Model

Machine Model

Charged Device Model

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 6) Pb Pkg Pb−Free Pkg

LQFP−32 Level 2 Level 2

QFN−32 − Level 1

Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

Transistor Count 1217 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

6. For additional information, see Application Note AND8003/D.

75 kW

> 2 kV

> 100 V

> 2 kV

http://onsemi.com

4

MC10EP195, MC100EP195

Q

Q

0

1

1

GD*

0

1

0

1

1

1

GD*

GD*

0

1

2

GD*

0

1

4

GD*

0

1

8

GD*

R1R1R1R1R1R1R1R1R1R1

D0D1D2D3D4D5D6D7D8D9

0

1

16

GD*

0

1

10 BIT LATCH

(MINIMUM FIXED DELAY APPROX. 2.2 ns)

32

GD*

*GD = (GATE DELAY) APPROXIMATELY 10 ps DELAY PER GATE

0

1

64

GD*

0

1

CASCADE

128

GD*

0

1

256

GD*

0

1

512

GD*

R1

R1

R1

IN

IN

EN

R1

LEN

R1

SET MIN

SET MAX

R1

BBVCFVEF

V

CASCADE

R1

Latch

EE

V

D10

Figure 3. Logic Diagram

http://onsemi.com

5

Table 6. THEORETICAL DELAY VALUES

D(9:0) Value SETMIN SETMAX Programmable Delay*

XXXXXXXXXX H L 0 ps

0000000000 L L 0 ps

0000000001 L L 10 ps

0000000010 L L 20 ps

0000000011 L L 30 ps

0000000100 L L 40 ps

0000000101 L L 50 ps

0000000110 L L 60 ps

0000000111 L L 70 ps

0000001000 L L 80 ps

0000010000 L L 160 ps

0000100000 L L 320 ps

0001000000 L L 640 ps

0010000000 L L 1280 ps

0100000000 L L 2560 ps

1000000000 L L 5120 ps

1111111111 L L 10230 ps

XXXXXXXXXX L H 10240 ps

*Fixed minimum delay not included.

MC10EP195, MC100EP195

http://onsemi.com

6