ON Semiconductor MC100EP91 User Manual

2.5 V/3.3 V Any Level
Positive Input to

-3.3 V/-5.5 V NECL
Output Translator

MC100EP91

Description

The MC100EP91 is a triple any level positive input to NECL output
translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL,
CML or LVDS signals, and translates them to differential NECL
output signals (−3.0 V/−5.5 V).

To accomplish the level translation the EP91 requires three power
rails. The V
and the V
The GND pins are connected to the system ground plane. Both V
and VCC should be bypassed to ground via 0.01 mF capacitors.

Under open input conditions, the D
and the D input will be pulled to GND. These conditions will force the
Q outputs to a low state, and Q outputs to a high state, which will
ensure stability.

The V
this device only. For single-ended input conditions, the unused
differential input is connected to V
V

may also rebias AC coupled inputs. When used, decouple V

BB

and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V

Features

• Maximum Input Clock Frequency = > 2.0 GHz Typical

• Maximum Input Data Rate = > 2.0 Gb/s Typical

• 500 ps Typical Propagation Delay

• Operating Range:

V

CC

• Q Output will Default LOW with Inputs Open or at GND

• These Devices are Pb-Free, Halogen Free and are RoHS Compliant

pins should be connected to the positive power supply,

CC

pin should be connected to the negative power supply.

EE

input will be biased at VCC/2

pin, an internally generated voltage supply, is available to

BB

as a switching reference voltage.

BB

should be left open.

BB

= 2.375 V to 3.8 V; VEE = −3.0 V to −5.5 V; GND = 0 V

EE

BB

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20

1

SOIC−20 WB

DW SUFFIX
CASE 751D

MARKING DIAGRAMS*

20

MC100EP91

AWLYYWWG

1

SOIC−20 WB QFN−24

A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb-Free Package

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D

ORDERING INFORMATION

Device Package Shipping†

MC100EP91DWG SOIC−20 WB

MC100EP91DWR2G

MC100EP91MNG 92 Units / Tube

(Pb-Free)

SOIC−20 WB

(Pb-Free)

QFN−24

(Pb-Free)

24 1

QFN−24
MN SUFFIX
CASE 485L

24

1

100

EP91

ALYWG

G

.

38 Units / Tube

1000 Tape & Reel

© Semiconductor Components Industries, LLC, 2016

March, 2021 − Rev. 7

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D

1 Publication Order Number:

.

MC100EP91/D

MC100EP91

Positive Level

Input

D0

R1

R2

D0

R1

D1

R1

R2

D1

R1

D2

R1

R2

D2

R1

Figure 1. Logic Diagram

Table 1. PIN DESCRIPTION

Pin

SOIC QFN

1, 20 3, 4, 12 V

10 15, 16 V

Name I/O

CC

EE

− − Positive Supply Voltage. All VCC Pins must be Externally

− − Negative Supply Voltage. All VEE Pins must be Externally

14, 17 19, 20, 23,24GND − − Ground

Default

State

Connected to Power Supply to Guarantee Proper
Operation

Connected to Power Supply to Guarantee Proper
Operation

NECL Output

Q0

Q0

Q1

Q1

Q2

Q2

V

CC

V

BB

GND

V

EE

Description

4, 7 7, 11 V

BB

2, 5, 8 5, 8, 13 D[0:2] LVPECL, LVDS, LVTTL,

− − ECL Reference Voltage Output

Low

Noninverted Differential Inputs [0:2]. Internal 75 kW to GND.

LVCMOS, CML, HSTL Input

3, 6, 9 6, 9, 14 D[0:2] LVPECL, LVDS,

LVTTL,LVCMOS, CML,

HSTL Input

High

Inverted Differential Inputs [0:2]. Internal 75 kW to GND and
75 kW to V
(VCC − GND) / 2

. When Inputs are Left Open They Default to

CC

19,16,13 2, 22, 18 Q[0:2] NECL Output − Noninverted Differential Outputs [0:2]. Typically Terminated

with 50 W to V

= VCC − 2 V

TT

18,15,12 1, 21, 17 Q[0:2] NECL Output − Inverted Differential Outputs [0:2]. Typically Terminated with

50 W to V

= VCC − 2 V

TT

11 10 NC − − No Connect. The NC Pin is NOT Electrically Connected to

the Die and may Safely be Connected to Any Voltage from
V

to V

EE

CC

N/A − EP − Exposed Pad (Note 1)

1. The thermally conductive exposed pad on the package bottom (see case drawing) must be attached to a heat−sinking conduit and may
only be electrically connected to V

(not GND).

EE

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2

MC100EP91

GND GND Q1

Exposed Pad

GND

GNDQ1

(EP)

1924 23 22 2021

VCCQ0

1920

Q0

Q1 Q1 Q2 Q2 NC

GNDGND

1718 16 15 14 13 12

MC100EP91

43

56789

V

BB

D1D1 D2

V

BB

CC

21

D0

D0 D2V

Figure 2. SOIC−20 Lead Pinout (Top View)

Q0

1

Q0

2

11

10

V

EE

3

V

CC

4

V

CC

5

D0

6

D0

789 1110

BB

MC100EP91

D1

D1

12

V

NCV

BB

V

CC

Figure 3. QFN−24 Lead Pinout (Top View)*

Q2

18

Q2

17

V

16

EE

15

V

EE

14

D2

D2

13

*All VCC, VEE and GND pins must be externally connected to a power supply and the underside exposed pad must be attached to an adequate

heat−sinking conduit to guarantee proper operation.

Table 2. ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor (R1)

Internal Input Pullup Resistor (R2)

ESD Protection

Human Body Model
Machine Model
Charged Device Model

Moisture Sensitivity (Note 1) Pb-Free Pkg

SOIC−20 WB
QFN−24

Flammability Rating

Oxygen Index: 28 to 34

Transistor Count 446 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

75 kW

75 kW

> 2 kV

> 150 V

> 2 kV

Level 3
Level 1

UL 94 V−0 @ 0.125 in

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3

MC100EP91

Table 3. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

V

V

V

T

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.

Positive Power Supply GND = 0 V 3.8 to 0 V

CC

Negative Power Supply GND = 0 V −6 V

EE

V

Positive Input Voltage GND = 0 V VI ≤ V

I

Operating Voltage GND = 0 V VCC − V

OP

I

Output Current Continuous

out

I

PECL VBB Sink/Source ±0.5 mA

BB

T

Operating Temperature Range −40 to +85 °C

A

Storage Temperature Range −65 to +150 °C

stg

Thermal Resistance (Junction-to-Ambient)

q

JA

JESD 51−3 (1S-Single Layer Test Board)

Thermal Resistance (Junction-to-Ambient)

q

JA

JESD 51−6 (2S2P Multilayer Test Board) with Filled Thermal Vias

Thermal Resistance (Junction-to-Case) Standard Board SOIC−20 WB

q

JC

T

Wave Solder (Pb-Free) 225 °C

sol

Surge

0 lfpm
500 lfpm

0 lfpm
500 lfpm

CC

EE

SOIC−20 WB
SOIC−20 WB

QFN−24
QFN−24

QFN−24

3.8 to 0 V

9.8 V

50

mA

100

90

°C/W

60

37

°C/W

32

30 to 3511°C/W

Table 4. DC CHARACTERISTICS POSITIVE INPUTS (V

= 2.5 V, VEE = −3.0 V to −5.5 V, GND = 0 V (Note 1))

CC

−40°C 25°C 85°C

Symbol

I

CC

V

IH

V

IL

V

IHCMR

I

IH

I

IL

Characteristic

Positive Power Supply Current 10 14 20 10 14 20 10 14 20 mA

Input HIGH Voltage (Single-Ended) 1335 V

Input LOW Voltage (Single-Ended) GND 875 GND 875 GND 875 mV

Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 2)

Input HIGH Current (@ VIH) 150 150 150

Input LOW Current (@ VIL)

D
D

Min Typ Max Min Typ Max Min Typ Max

1335 V

CC

1335 V

CC

CC

0 2.5 0 2.5 0 2.5 V

0.5

−150

0.5

−150

0.5

−150

Unit

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm.

1. Input parameters vary 1:1 with VCC. VCC can vary +1.3 V / −0.125 V.

2. V

min varies 1:1 with GND. V

IHCMR

max varies 1:1 with VCC.

IHCMR

mV

mA

mA

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