ON Semiconductor MC100EP91 User Manual

2.5 V/3.3 V Any Level Positive Input to

-3.3 V/-5.5 V NECL Output Translator

MC100EP91

Description

The MC100EP91 is a triple any level positive input to NECL output translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential NECL output signals (−3.0 V/−5.5 V).

To accomplish the level translation the EP91 requires three power rails. The V and the V The GND pins are connected to the system ground plane. Both V and VCC should be bypassed to ground via 0.01 mF capacitors.

Under open input conditions, the D and the D input will be pulled to GND. These conditions will force the Q outputs to a low state, and Q outputs to a high state, which will ensure stability.

The V this device only. For single-ended input conditions, the unused differential input is connected to V V

may also rebias AC coupled inputs. When used, decouple V

and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V

Features

• Maximum Input Clock Frequency = > 2.0 GHz Typical

• Maximum Input Data Rate = > 2.0 Gb/s Typical

• 500 ps Typical Propagation Delay

• Operating Range:

• Q Output will Default LOW with Inputs Open or at GND

• These Devices are Pb-Free, Halogen Free and are RoHS Compliant

pins should be connected to the positive power supply,

pin should be connected to the negative power supply.

input will be biased at VCC/2

pin, an internally generated voltage supply, is available to

as a switching reference voltage.

should be left open.

= 2.375 V to 3.8 V; VEE = −3.0 V to −5.5 V; GND = 0 V

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SOIC−20 WB

DW SUFFIX CASE 751D

MARKING DIAGRAMS*

MC100EP91

AWLYYWWG

SOIC−20 WB QFN−24

A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb-Free Package

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D

ORDERING INFORMATION

Device Package Shipping†

MC100EP91DWG SOIC−20 WB

MC100EP91DWR2G

MC100EP91MNG 92 Units / Tube

(Pb-Free)

SOIC−20 WB

(Pb-Free)

QFN−24

(Pb-Free)

24 1

QFN−24 MN SUFFIX CASE 485L

100

EP91

ALYWG

38 Units / Tube

1000 Tape & Reel

March, 2021 − Rev. 7

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D

1 Publication Order Number:

MC100EP91/D

MC100EP91

Positive Level

Input

Figure 1. Logic Diagram

Table 1. PIN DESCRIPTION

SOIC QFN

1, 20 3, 4, 12 V

10 15, 16 V

Name I/O

− − Positive Supply Voltage. All VCC Pins must be Externally

− − Negative Supply Voltage. All VEE Pins must be Externally

14, 17 19, 20, 23,24GND − − Ground

Default

State

Connected to Power Supply to Guarantee Proper Operation

NECL Output

GND

Description

4, 7 7, 11 V

2, 5, 8 5, 8, 13 D[0:2] LVPECL, LVDS, LVTTL,

− − ECL Reference Voltage Output

Low

Noninverted Differential Inputs [0:2]. Internal 75 kW to GND.

LVCMOS, CML, HSTL Input

3, 6, 9 6, 9, 14 D[0:2] LVPECL, LVDS,

LVTTL,LVCMOS, CML,

HSTL Input

High

Inverted Differential Inputs [0:2]. Internal 75 kW to GND and 75 kW to V (VCC − GND) / 2

. When Inputs are Left Open They Default to

19,16,13 2, 22, 18 Q[0:2] NECL Output − Noninverted Differential Outputs [0:2]. Typically Terminated

with 50 W to V

= VCC − 2 V

18,15,12 1, 21, 17 Q[0:2] NECL Output − Inverted Differential Outputs [0:2]. Typically Terminated with

50 W to V

= VCC − 2 V

11 10 NC − − No Connect. The NC Pin is NOT Electrically Connected to

the Die and may Safely be Connected to Any Voltage from V

to V

N/A − EP − Exposed Pad (Note 1)

1. The thermally conductive exposed pad on the package bottom (see case drawing) must be attached to a heat−sinking conduit and may only be electrically connected to V

(not GND).

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MC100EP91

GND GND Q1

Exposed Pad

GND

GNDQ1

(EP)

1924 23 22 2021

VCCQ0

1920

Q1 Q1 Q2 Q2 NC

GNDGND

1718 16 15 14 13 12

MC100EP91

56789

D1D1 D2

D0 D2V

Figure 2. SOIC−20 Lead Pinout (Top View)

789 1110

MC100EP91

NCV

Figure 3. QFN−24 Lead Pinout (Top View)*

*All VCC, VEE and GND pins must be externally connected to a power supply and the underside exposed pad must be attached to an adequate

heat−sinking conduit to guarantee proper operation.

Table 2. ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor (R1)

Internal Input Pullup Resistor (R2)

ESD Protection

Human Body Model Machine Model Charged Device Model

Moisture Sensitivity (Note 1) Pb-Free Pkg

SOIC−20 WB QFN−24

Flammability Rating

Oxygen Index: 28 to 34

Transistor Count 446 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

75 kW

> 2 kV

> 150 V

> 2 kV

Level 3 Level 1

UL 94 V−0 @ 0.125 in

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MC100EP91

Table 3. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

Positive Power Supply GND = 0 V 3.8 to 0 V

Negative Power Supply GND = 0 V −6 V

Positive Input Voltage GND = 0 V VI ≤ V

Operating Voltage GND = 0 V VCC − V

Output Current Continuous

out

PECL VBB Sink/Source ±0.5 mA

Operating Temperature Range −40 to +85 °C

Storage Temperature Range −65 to +150 °C

stg

Thermal Resistance (Junction-to-Ambient)

JESD 51−3 (1S-Single Layer Test Board)

Thermal Resistance (Junction-to-Ambient)

JESD 51−6 (2S2P Multilayer Test Board) with Filled Thermal Vias

Thermal Resistance (Junction-to-Case) Standard Board SOIC−20 WB

Wave Solder (Pb-Free) 225 °C

sol

Surge

0 lfpm 500 lfpm

SOIC−20 WB SOIC−20 WB

QFN−24 QFN−24

QFN−24

3.8 to 0 V

9.8 V

100

°C/W

30 to 3511°C/W

Table 4. DC CHARACTERISTICS POSITIVE INPUTS (V

= 2.5 V, VEE = −3.0 V to −5.5 V, GND = 0 V (Note 1))

−40°C 25°C 85°C

Symbol

IHCMR

Characteristic

Positive Power Supply Current 10 14 20 10 14 20 10 14 20 mA

Input HIGH Voltage (Single-Ended) 1335 V

Input LOW Voltage (Single-Ended) GND 875 GND 875 GND 875 mV

Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 2)

Input HIGH Current (@ VIH) 150 150 150

Input LOW Current (@ VIL)

D D

Min Typ Max Min Typ Max Min Typ Max

1335 V

0 2.5 0 2.5 0 2.5 V

0.5

−150

0.5

−150

0.5

−150

Unit

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm.

1. Input parameters vary 1:1 with VCC. VCC can vary +1.3 V / −0.125 V.

2. V

min varies 1:1 with GND. V

IHCMR

max varies 1:1 with VCC.

IHCMR

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MC100EP91

Table 5. DC CHARACTERISTICS POSITIVE INPUT (V

= 3.3 V; VEE = −3.0 V to −5.5 V; GND = 0 V (Note 1))

−40°C 25°C 85°C

Symbol

IHCMR

Characteristic

Positive Power Supply Current 10 16 24 10 16 24 10 16 24 mA

Input HIGH Voltage (Single-Ended) 2135 V

Input LOW Voltage (Single-Ended) GND 1675 GND 1675 GND 1675 mV

PECL Output Voltage Reference 1775 1875 1975 1775 1875 1975 1775 1875 1975 mV

Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 2)

Input HIGH Current (@ VIH) 150 150 150

Input LOW Current (@ VIL)

D D

Min Ty p Max Min Ty p Max Min Typ Max

2135 V

0 3.3 0 3.3 0 3.3 V

0.5

−150

0.5

−150

0.5

−150

Unit

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm.

1. Input parameters vary 1:1 with V

2. V

min varies 1:1 with GND. V

IHCMR

Table 6. DC CHARACTERISTICS NECL OUTPUT (V

. VCC can vary +0.5 / −0.925 V.

max varies 1:1 with VCC.

IHCMR

= 2.375 V to 3.8 V; VEE = −3.0 V to −5.5 V; GND = 0 V (Note 1))

−40°C 25°C 85°C

Symbol

Characteristic

Negative Power Supply Current 40 50 60 38 50 68 38 50 68 mA

Output HIGH Voltage (Note 2) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV

Output LOW Voltage (Note 2) −1945 −1770 −1600 −1945 −1770 −1600 −1945 −1770 −1600 mV

Min Typ Max Min Typ Max Min Typ Max

Unit

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm.

1. Output parameters vary 1:1 with GND.

2. All loading with 50 W resistor to GND − 2.0 V.

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MC100EP91

Table 7. AC CHARACTERISTICS (V

= 2.375 V to 3.8 V; V

= −3.0 V to −5.5 V; GND = 0 V)

−40°C 25°C 85°C

Symbol

OUTPP

PLH

PHL0

SKEW

JITTER

INPP

tr, t

Characteristic

Output Voltage Amplitude fin ≤ 1.0 GHz (Figure 4) f (Note 1) f

≤ 1.5 GHz

≤ 2.0 GHz

Propagation Delay Differential D to Q Single-Ended

Pulse Skew (Note 2) Output-to-Output (Note 3) Part-to-Part (Diff) (Note 3)

RMS Random Clock Jitter (Note 4) fin = 2.0 GHz Peak-to-Peak Data Dependant Jitter f (Note 5)

= 2.0 Gb/s

Input Voltage Swing (Differential Configuration) (Note 6)

Output Rise/Fall Times @ 50 MHz (20%−80%)

Q, Q

Min Typ Max Min Typ Max Min Ty p Max

575 525 300

375 300

800 750 600

500 450

15 25 50

600 650

75 95

125

600 525 250

375 300

800 750 550

500 450

15 30 50

600 675

75 105 125

550 400 150

400 300

800 750 500

550 500

15 30 70

650 750

80 105 150

Unit

0.5202.0 0.5202.0 0.5202.0 ps

200 800 1200 200 800 1200 200 800 1200 mV

75 150 250 75 150 250 75 150 275

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm.

1. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to GND − 2.0 V. Input edge rates 150 ps (20% − 80%).

2. Pulse Skew = |t

3. Skews are valid across specified voltage range, part-to-part skew is for a given temperature.

4. RMS Jitter with 50% Duty Cycle Input Clock Signal.

5. Peak-to-Peak Jitter with input NRZ PRBS 2

PLH

− t

PHL

31−1

at 2.0 Gb/s.

6. Input voltage swing is a Single-Ended measurement operating in differential mode. The device has a DC gain of ≈ 50.

850

750

650

550

(mV)

450

350

OUTPUT VOLTAGE AMPLITUDE

RMS JITTER

250

0.5 1.0 1.5 2.0 2.5

INPUT FREQUENCY (GHz)

Figure 4. Output Voltage Amplitude (V

Input Frequency (f

PLH

) at Ambient Temperature (Typical)

Figure 5. AC Reference Measurement

AMP

) / RMS Jitter vs.

OUTPP

INPP

OUTPP

PHL

9.0

8.0

7.0

6.0

5.0

4.0

RMS JITTER (ps)

3.0

2.0

1.0 0

= VIH(D) − VIL(D)

= VOH(Q) − VOL(Q)

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MC100EP91

Application Information

All MC100EP91 inputs can accept LVPECL, LVTTL, LVCMOS, HSTL, CML, or LVDS signal levels. The limitations for differential input signal (LVDS, HSTL, LVPECL, or CML) are the minimum input swing of 150 mV

LVPECL

Driver

GND

50 W

= VCC − 2.0 V

50 W

Figure 6. Standard LVPECL Interface

EP91

GND V

and the maximum input swing of 3.0 V. Within these conditions, the input voltage can range from V

to GND.

Examples interfaces are illustrated below in a 50 W environment (Z = 50 W).

LVDS Driver

GND GND V

100 W

Figure 7. Standard LVDS Interface

EP91

50 W

HSTL

Driver

GND GND V

50 W 50 W

GND

Figure 8. Standard HSTL Interface

LVTTL

Driver

(externally generated reference voltage)

1.5 V

EP91

CML

Driver

GND GND

Figure 9. Standard 50 W Load CML Interface

EP91

LVCMOS

Driver

Open

EP91

GND

Figure 10. Standard LVTTL Interface

GND V

GND GND

Figure 11. Standard LVCMOS Interface

will default to VCC/2 when left open.

A reference voltage of V

to D input, if D

is interfaced to CMOS signals)

/2 should be applied

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MC100EP91

Driver Device

Q D

Figure 12. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D

Resource Reference of Application Notes

AN1405/D − ECL Clock Distribution Techniques

AN1406/D − Designing with PECL (ECL at +5.0 V)

AN1503/D −

AN1504/D − Metastability and the ECLinPS Family

AN1568/D − Interfacing Between LVDS and ECL

AN1672/D − The ECL Translator Guide

AND8001/D − Odd Number Counters Design

AND8002/D − Marking and Date Codes

AND8020/D − Termination of ECL Logic Devices

AND8066/D − Interfacing with ECLinPS

AND8090/D − AC Characteristics of ECL Devices

ECLinPSt I/O SPiCE Modeling Kit

Zo = 50 W

Receiver Device

50 W 50 W

VTT = GND − 2.0 V

− Termination of ECL Logic Devices)

ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SCALE 2:1

PIN 1

REFEENCE

0.15 C

TOP VIEW

DETAIL B

0.10 C

0.08 C

NOTE 4

DETAIL A

SIDE VIEW

e/2

BOTTOM VIEW

RECOMMENDED

SOLDERING FOOTPRINT

4.30

2.90

A B

SEATING

24X

PLANE

24X

0.10 B

NOTE 3

0.05

24X

0.55

QFN24, 4x4, 0.5P

CASE 485L

ISSUE B

DETAIL A

ALTERNATE

CONSTRUCTIONS

MOLD CMPDEXPOSED Cu

DETAIL B

ALTERNATE TERMINAL

CONSTRUCTIONS

DATE 05 JUN 2012

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM THE TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.

MILLIMETERS

DIM MIN MAX

A 0.80 1.00 A1 0.00 0.05 A3 0.20 REF

b 0.20 0.30

D 4.00 BSC D2 2.70 2.90

E 4.00 BSC E2 2.70 2.90

e 0.50 BSC

L 0.30 0.50 L1 0.05 0.15

GENERIC

MARKING DIAGRAM*

XXXXX XXXXX

ALYWG

XXXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package

(Note: Microdot may be in either location)

*This information is generic. Please refer to

device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present.

24X

0.32

4.30

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

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2.90

0.50

PITCH

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

DIMENSIONS: MILLIMETERS

98AON11783D

QFN24, 4X4, 0.5P

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SCALE 1:1

0.25

b20X

SAS

0.25

18X

RECOMMENDED

SOLDERING FOOTPRINT*

20X

0.52

20 11

20X

1.30

SOIC−20 WB

CASE 751D−05

SEATING PLANE

ISSUE H

h X 45

DATE 22 APR 2015

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION.

MILLIMETERS

DIM MIN MAX

A 2.35 2.65

A1 0.10 0.25

b 0.35 0.49

c 0.23 0.32 D 12.65 12.95 E 7.40 7.60

e 1.27 BSC

H 10.05 10.55

h 0.25 0.75

L 0.50 0.90

q 0 7

GENERIC

MARKING DIAGRAM*

XXXXXXXXXXX XXXXXXXXXXX

AWLYYWWG

11.00

XXXXX = Specific Device Code

A = Assembly Location WL = Wafer Lot YY = Year

1.27

PITCH

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

98ASB42343B

SOIC−20 WB

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

WW = Work Week G = Pb−Free Package

*This information is generic. Please refer to

device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present.

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ON Semiconductor MC100EP91 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual