ON Semiconductor EMG2DXV5T1, EMG2DXV5T1G, EMG5DXV5T1, EMG5DXV5T1G, EMG5DXV5T5G Service Manual

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EMG2DXV5T1, EMG5DXV5T1
Preferred Devices
Dual Bias Resistor Transistors
NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network
This new series of digital transistors is designed to replace a single device and its external resistor bias network. The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base−emitter resistor. The BRT eliminates these individual components by integrating them into a single device. The use of a BRT can reduce both system cost and board space. The device is housed in the SOT−553 package which is designed for low power surface mount applications.
Features
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
Moisture Sensitivity Level: 1
Available in 8 mm, 7 inch Tape and Reel
Lead−Free Solder Plating
Pb−Free Packages are Available
MAXIMUM RATINGS (T
Rating Symbol Value Unit
Collector-Base Voltage V Collector-Emitter Voltage V Collector Current I
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Total Device Dissipation TA = 25°C
Derate above 25°C
Thermal Resistance −
Junction-to-Ambient
Thermal Resistance −
Junction-to-Lead
Junction and Storage Temperature Range
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.
1. FR−4 @ Minimum Pad
2. FR−4 @ 1.0 x 1.0 inch Pad
= 25°C unless otherwise noted)
A
CBO CEO
100 mAdc
230 (Note 1) 338 (Note 2)
1.8 (Note 1)
2.7 (Note 2)
540 (Note 1) 370 (Note 2)
264 (Note 1) 287 (Note 2)
− 55 to +150 °C
P
R
R
TJ, T
C
D
q
JA
q
JL
stg
50 Vdc 50 Vdc
mW
°C/W
°C/W
°C/W
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NPN SILICON
BIAS RESISTOR
TRANSISTORS
(3) (1)(2)
R1
R2
DT
r2
(4)
5
1
CASE 463B
MARKING DIAGRAM
5
XX M G
G
1
xx = Device Code
xx= UF (EMG5)
M = Date Code G = Pb−Free Package
(Note: Microdot may be in either location)
UP (EMG2)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.
R2
SOT−553
R1
DT
r1
(5)
© Semiconductor Components Industries, LLC, 2005
October, 2005 − Rev. 0
Preferred devices are recommended choices for future use
and best overall value.
1 Publication Order Number:
EMG5DXV5/D
EMG2DXV5T1, EMG5DXV5T1
DEVICE MARKING AND RESISTOR VALUES
Device Package Marking R1 (K) R2 (K)
EMG2DXV5T1 SOT−553 UP 47 47 EMG5DXV5T1 SOT−553 UF 10 47
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
A
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS (Q1 & Q2)
Collector-Base Cutoff Current (VCB = 50 V, IE = 0) I Collector-Emitter Cutoff Current (VCE = 50 V, IB = 0) I Emitter-Base Cutoff Current (VEB = 6.0 V, IC = 0)EMG2DXV5T1
EMG5DXV5T1 Collector-Base Breakdown Voltage (IC = 10 mA, IE = 0) Collector-Emitter Breakdown Voltage (Note 3)
(IC = 2.0 mA, IB = 0)
ON CHARACTERISTICS (Q1 & Q2) (Note 3)
DC Current Gain (VCE = 10 V, IC = 5.0 mA) EMG2DXV5T1
EMG5DXV5T1 Collector-Emitter Saturation Voltage (IC = 10 mA, IB = 0.3 mA) V Output Voltage (on)
(VCC = 5.0 V, VB = 3.5 V, RL = 1.0 kW) EMG2DXV5T1 (VCC = 5.0 V, VB = 2.5 V, RL = 1.0 kW) EMG5DXV5T1
Output Voltage (off) (VCC = 5.0 V, VB = 0.5 V, RL = 1.0 kW) Input Resistor EMG2DXV5T1
EMG5DXV5T1 Resistor Ratio EMG2DXV5T1
EMG5DXV5T1
3. Pulse Test: Pulse Width < 300 ms, Duty Cycle < 2.0%
CBO CEO
I
EBO
V
(BR)CBO
V
(BR)CEO
h
CE(sat)
V
V
R
R1/R
FE
OL
OH
100 nAdc
500 nAdc
0.1
0.2
mAdc
50 Vdc 50 Vdc
80 80
140 140
0.25 Vdc Vdc
0.2
0.2
4.9 Vdc
1
2
32.9
7.0
0.8
0.17
47 10
1.0
0.21
61.1 13
1.2
0.25
kW
350
300
250
200
150
100
, POWER DISSIPATION (mW)
D
50
P
0
−50 0 50 100 150
R
q
JA
= 370°C/W
TA, AMBIENT TEMPERATURE (°C)
Figure 1. Derating Curve
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2
EMG2DXV5T1, EMG5DXV5T1
S
TYPICAL ELECTRICAL CHARACTERISTICS — EMG2DXV5T1
10
IC/IB = 10
1
0.1
, MAXIMUM COLLECTOR VOLTAGE (VOLT
0.01
CE(sat)
0
V
20 40
IC, COLLECTOR CURRENT (mA)
Figure 2. V
1
0.8
0.6
CE(sat)
TA=−25°C
versus I
C
25°C
75°C
50
f = 1 MHz IE = 0 V TA = 25°C
1000
100
, DC CURRENT GAIN (NORMALIZED)
FE
10
1 100
IC, COLLECTOR CURRENT (mA)
10
VCE = 10 V
TA=75°C
Figure 3. DC Current Gain
100
75°C
10
1
25°C
TA=−25°C
25°C
−25°C
0.4
, CAPACITANCE (pF)
ob
C
0.2
0
010203040
VR, REVERSE BIAS VOLTAGE (VOLTS)
Figure 4. Output Capacitance
100
VO = 0.2 V
10
1
, INPUT VOLTAGE (VOLTS)
in
V
0.1 010 203040 50
0.1
0.01
, COLLECTOR CURRENT (mA) h
C
I
50
0.001 0246810
Figure 5. Output Current versus Input Voltage
TA=−25°C
IC, COLLECTOR CURRENT (mA)
VO = 5 V
Vin, INPUT VOLTAGE (VOLTS)
25°C
75°C
Figure 6. Input Voltage versus Output Current
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3
EMG2DXV5T1, EMG5DXV5T1
TYPICAL ELECTRICAL CHARACTERISTICS − EMG5DXV5T1
1
IC/IB = 10
0.1
0.01
, MAXIMUM COLLECTOR VOLTAGE (VOLTS)
CE(sat)
0.001
V
020406080
IC, COLLECTOR CURRENT (mA)
Figure 7. V
4
3.5
3
2.5
2
1.5
, CAPACITANCE (pF)
ob
1
C
0.5
0
0 2 4 6 8 101520253035404550
VR, REVERSE BIAS VOLTAGE (VOLTS)
CE(sat)
TA=−25°C
versus I
25°C
75°C
C
f = 1 MHz lE = 0 V TA = 25°C
300
VCE = 10
250
200
150
100
, DC CURRENT GAIN
FE
h
50
0
1 10 100
2468 1520405060708090
IC, COLLECTOR CURRENT (mA)
TA=75°C
25°C
−25°C
Figure 8. DC Current Gain
100
75°C
10
, COLLECTOR CURRENT (mA)
C
I
1
0246810
Vin, INPUT VOLTAGE (VOLTS)
25°C
TA=−25°C
VO = 5 V
Figure 9. Output Capacitance Figure 10. Output Current versus Input Voltage
10
VO= 0.2 V
1
, INPUT VOLTAGE (VOLTS)
in
V
0.1 01020304050
IC, COLLECTOR CURRENT (mA)
TA=−25°C
25°C
75°C
Figure 11. Input Voltage versus Output Current
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4
EMG2DXV5T1, EMG5DXV5T1
TYPICAL APPLICATIONS FOR NPN BRTs
+12 V
FROM mP OR
OTHER LOGIC
Figure 12. Level Shifter: Connects 12 or 24 Volt Circuits to Logic
ISOLATED
LOAD
V
CC
OUT
IN
Figure 13. Open Collector Inverter:
Inverts the Input Signal
+12 V
LOAD
Figure 14. Inexpensive, Unregulated Current Source
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5
EMG2DXV5T1, EMG5DXV5T1
DEVICE ORDERING INFORMATION
Device Package Shipping
EMG2DXV5T1 SOT−553 4000 / Tape & Reel EMG2DXV5T1G SOT−553
(Pb−Free) EMG2DXV5T5 SOT−553 8000 / Tape & Reel EMG2DXV5T5G SOT−553
(Pb−Free) EMG5DXV5T1 SOT−553 4000 / Tape & Reel EMG5DXV5T1G SOT−553
(Pb−Free) EMG5DXV5T5 SOT−553 8000 / Tape & Reel
EMG5DXV5T5G SOT−553
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
4000 / Tape & Reel
8000 / Tape & Reel
4000 / Tape & Reel
8000 / Tape & Reel
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6
SOT−553
D
−X−
45
12 3
e
EMG2DXV5T1, EMG5DXV5T1
E
−Y−
b 5 PL
0.08 (0.003) X
M
PACKAGE DIMENSIONS
XV5 SUFFIX
5−LEAD PACKAGE
CASE 463B−01
ISSUE B
A
Y
L
H
E
c
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
DIMAMIN NOM MAX MIN
b 0.17 0.22 0.27 0.007 c D 1.50 1.60 1.70 0.059 E 1.10 1.20 1.30 0.043 e 0.50 BSC L 0.10 0.20 0.30 0.004
H
E
MILLIMETERS
0.50 0.55 0.60 0.020
0.08 0.13 0.18
1.50 1.60 1.70 0.059 0.063 0.067
0.003 0.005 0.007
INCHES
NOM MAX
0.022 0.024
0.009 0.011
0.063 0.067
0.047 0.051
0.020 BSC
0.008 0.012
SOLDERING FOOTPRINT*
0.3
0.0118
0.45
0.0177
1.0
1.35
0.0531
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
0.0394
0.5
0.0197
0.5
0.0197
SCALE 20:1
ǒ
inches
mm
Ǔ
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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For additional information, please contact your local Sales Representative.
EMG5DXV5/D
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