ON Semiconductor EMD5DXV6-D, EMD5DXV6T5 Service Manual

EMD5DXV6T1,
EMD5DXV6T5

Preferred Devices

Product Preview

Dual Bias Resistor
Transistors

NPN and PNP Silicon Surface Mount
Transistors with Monolithic Bias
Resistor Network

The BRT (Bias Resistor Transistor) contains a single transistor with
a monolithic bias network consisting of two resistors; a series base
resistor and a base−emitter resistor. These digital transistors are
designed to replace a single device and its external resistor bias
network. The BRT eliminates these individual components by
integrating them into a single device. In the EMD5DXV6T1 series,
two complementary BRT devices are housed in the SOT−563 package
which is ideal for low power surface mount applications where board
space is at a premium.

• Simplifies Circuit Design

• Reduces Board Space

• Reduces Component Count

• Available in 8 mm, 7 inch Tape and Reel

• Lead Free Solder Plating

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(1)(2)(3)

R

1

R

Q

1

R

2

(4) (5) (6)

4

5

6

SOT−563

CASE 463A

PLASTIC

MARKING DIAGRAM

2

Q

R

1

3

2

1

2

This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.

U5 D

U5 = Specific Device Code
D = Date Code

ORDERING INFORMATION

Device Package Shipping

EMD5DXV6T1 SOT−563 4 mm pitch

4000/Tape & Reel

EMD5DXV6T5 SOT−563 2 mm pitch

8000/Tape & Reel

Preferred devices are recommended choices for future use
and best overall value.

 Semiconductor Components Industries, LLC, 2003

July, 2003 − Rev. P1

1 Publication Order Number:

EMD5DXV6/D

EMD5DXV6T1, EMD5DXV6T5

MAXIMUM RATINGS (T

= 25°C unless otherwise noted, common for Q1 and Q2, − minus sign for Q1 (PNP) omitted)

A

Rating

Symbol Value Unit

Collector-Base Voltage V
Collector-Emitter Voltage V
Collector Current I

THERMAL CHARACTERISTICS

Characteristic

(One Junction Heated)

Total Device Dissipation TA = 25°C
Derate above 25°C

Thermal Resistance Junction-to-Ambient R

Characteristic

(Both Junctions Heated)

Total Device Dissipation TA = 25°C
Derate above 25°C

Thermal Resistance Junction-to-Ambient R

Junction and Storage Temperature TJ, T

1. FR−4 @ Minimum Pad

Symbol Max Unit

Symbol Max Unit

CBO
CEO

C

P

D



JA

P

D



JA

stg

50 Vdc
50 Vdc

100 mAdc

357

(Note 1)

2.9

(Note 1)

350

(Note 1)

500

(Note 1)

4.0

(Note 1)

250

(Note 1)

−55 to
+150

mW

mW/°C

°C/W

mW

mW/°C

°C/W

°C

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2

EMD5DXV6T1, EMD5DXV6T5

ELECTRICAL CHARACTERISTICS (T

Characteristic

= 25°C unless otherwise noted)

A

Symbol Min Typ Max Unit

Q1 TRANSISTOR: PNP
OFF CHARACTERISTICS

Collector-Base Cutoff Current (VCB = 50 V, IE = 0) I
Collector-Emitter Cutoff Current (VCB = 50 V, IB = 0) I
Emitter-Base Cutoff Current (VEB = 6.0, IC = 5.0 mA) I

CBO
CEO
EBO

− − 100 nAdc

− − 500 nAdc

− − 1.0 mAdc

ON CHARACTERISTICS

Collector-Base Breakdown Voltage (IC = 10 A, IE = 0) V
Collector-Emitter Breakdown Voltage (IC = 2.0 mA, IB = 0) V
DC Current Gain (VCE = 10 V, IC = 5.0 mA) h
Collector−Emitter Saturation Voltage (IC = 10 mA, IB = 0.3 mA) V
Output Voltage (on) (VCC = 5.0 V, V
Output Voltage (off) (VCC = 5.0 V, V

= 2.5 V, RL = 1.0 k) V

B

= 0.5 V, RL = 1.0 k) V

B

(BR)CBO
(BR)CEO

FE

CE(SAT)

OL
OH

Input Resistor R1 3.3 4.7 6.1 k
Resistor Ratio R1/R2 0.38 0.47 0.56

50 − − Vdc
50 − − Vdc
20 35 −

− − 0.25 Vdc

− − 0.2 Vdc

4.9 − − Vdc

Q2 TRANSISTOR: NPN
OFF CHARACTERISTICS

Collector-Base Cutoff Current (VCB = 50 V, IE = 0) I
Collector-Emitter Cutoff Current (VCB = 50 V, IB = 0) I
Emitter-Base Cutoff Current (VEB = 6.0, IC = 5.0 mA) I

CBO
CEO
EBO

− − 100 nAdc

− − 500 nAdc

− − 0.1 mAdc

ON CHARACTERISTICS

Collector-Base Breakdown Voltage (IC = 10 A, IE = 0) V
Collector-Emitter Breakdown Voltage (IC = 2.0 mA, IB = 0) V
DC Current Gain (VCE = 10 V, IC = 5.0 mA) h
Collector−Emitter Saturation Voltage (IC = 10 mA, IB = 0.3 mA) V
Output Voltage (on) (VCC = 5.0 V, V
Output Voltage (off) (VCC = 5.0 V, V

= 2.5 V, RL = 1.0 k) V

B

= 0.5 V, RL = 1.0 k) V

B

(BR)CBO
(BR)CEO

FE

CE(SAT)

OL
OH

Input Resistor R1 33 47 61 k
Resistor Ratio R1/R2 0.8 1.0 1.2

50 − − Vdc
50 − − Vdc
80 140 −

− − 0.25 Vdc

− − 0.2 Vdc

4.9 − − Vdc

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3

EMD5DXV6T1, EMD5DXV6T5

250

200

150

100

R

= 833°C/W



50

, POWER DISSIPATION (MILLIWATTS)

D

P

0

−50 0 50 100 150

JA

, AMBIENT TEMPERATURE (°C)

T

A

Figure 1. Derating Curve

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4

EMD5DXV6T1, EMD5DXV6T5

TYPICAL ELECTRICAL CHARACTERISTICS — EMD5DXV6T1 PNP TRANSISTOR

, MAXIMUM COLLECTOR VOLTAGE (VOLTS)

0.01

CE(sat)

V

0.1

1

IC/IB = 10

T

=75°C

A

25°C

1000

100

VCE = 10 V

T

=75°C

A

−25°C

25°C

−25°C

, DC CURRENT GAIN

10

FE

h

1

0

20 50

, COLLECTOR CURRENT (mA)

I

C

Figure 2. V

3010 60

versus I

CE(sat)

40

C

12

1 1000

100

10

I

, COLLECTOR CURRENT (mA)

C

Figure 3. DC Current Gain

100

f = 1 MHz

10

= 0 mA

I

E

T

= 25°C

A

75°C

10

8

6

, CAPACITANCE (pF)

4

ob

C

SERIES 1

2

0

01020 3040

15 25 35 455

V

, REVERSE BIAS VOLTAGE (VOLTS)

R

Figure 4. Output Capacitance Figure 5. Output Current versus Input Voltage

0.1

, COLLECTOR CURRENT (mA)

C

I

0.01

1

VO = 5 V

T

=−25°C

A

25°C

0

2468 12

V

, INPUT VOLTAGE (VOLTS)

in

10

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5

EMD5DXV6T1, EMD5DXV6T5

TYPICAL ELECTRICAL CHARACTERISTICS — EMD5DXV6T1 NPN TRANSISTOR

0.1

, MAXIMUM COLLECTOR VOLTAGE (VOLTS)

0.01

CE(sat)

V

0.8

0.6

10

IC/IB = 10

1

1000

VCE = 10 V

T

=75°C

A

25°C

−25°C

T

=−25°C

A

25°C

75°C

0

Figure 6. V

20 40

, COLLECTOR CURRENT (mA)

I

C

versus I

CE(sat)

C

50

1

f = 1 MHz
I

= 0 mA

E

= 25°C

T

A

100

, DC CURRENT GAIN

FE

h

10

1 100

I

, COLLECTOR CURRENT (mA)

C

10

Figure 7. DC Current Gain

100

75°C

10

25°C

T

=−25°C

A

1

0.4

, CAPACITANCE (pF)

ob

C

0.2

0

010203040

, REVERSE BIAS VOLTAGE (VOLTS)

V

R

Figure 8. Output Capacitance

100

VO = 0.2 V

10

1

, INPUT VOLTAGE (VOLTS)

in

V

0.1
010 203040 50

Figure 10. Input Voltage versus Output Current

0.1

0.01

, COLLECTOR CURRENT (mA)

C

I

50

, COLLECTOR CURRENT (mA)

I

C

0.001

T

=−25°C

A

VO = 5 V

0246810

, INPUT VOLTAGE (VOLTS)

V

in

Figure 9. Output Current versus Input Voltage

25°C

75°C

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6

EMD5DXV6T1, EMD5DXV6T5

INFORMATION FOR USING THE SOT−563 SURFACE MOUNT PACKAGE

MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the to­tal design. The footprint for the semiconductor packages
must be the correct size to insure proper solder connection

1.35

0.0531

0.5

0.0197

SOT−563

SOT−563 POWER DISSIPATION

The power dissipation of the SOT−563 is a function of
the pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power dissipa­tion. Power dissipation for a surface mount device is deter­mined by T
of the die, R

, the maximum rated junction temperature

J(max)

, the thermal resistance from the device

JA



junction to ambient, and the operating temperature, TA. Us­ing the values provided on the data sheet for the SOT−563
package, PD can be calculated as follows:

PD =

J(max)

R

A



JA

T

− T

The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature T

of 25°C,

A

one can calculate the power dissipation of the device which
in this case is 150 milliwatts.

150°C − 25°C

PD =

833°C/W

= 150 milliwatts

The 833°C/W for the SOT−563 package assumes the use
of the recommended footprint on a glass epoxy printed cir­cuit board to achieve a power dissipation of 150 milliwatts.
There are other alternatives to achieving higher power dis­sipation from the SOT−563 package. Another alternative
would be to use a ceramic substrate or an aluminum core
board such as Thermal Clad



. Using a board material such
as Thermal Clad, an aluminum core board, the power dis­sipation can be doubled using the same footprint.

0.3

0.0118

0.0394

interface between the board and the package. With the cor­rect pad geometry, the packages will self align when sub­jected to a solder reflow process.

0.45

0.0177

1.0

0.5

0.0197

mm



SCALE 20:1



inches

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the
rated temperature of the device. When the entire device is
heated to a high temperature, failure to complete soldering
within a short time could result in device failure. There­fore, the following items should always be observed in or­der to minimize the thermal stress to which the devices are
subjected.

• Always preheat the device.

• The delta temperature between the preheat and solder-

ing should be 100°C or less.*

• When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum tem­perature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering meth­od, the difference shall be a maximum of 10°C.

• The soldering temperature and time shall not exceed

260°C for more than 10 seconds.

• When shifting from preheating to soldering, the maxi-

mum temperature gradient shall be 5°C or less.

• After soldering has been completed, the device should

be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.

• Mechanical stress or shock should not be applied dur-

ing cooling.

* Soldering a device without preheating can cause exces­sive thermal shock and stress which can result in damage
to the device.

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7

A

−X−

6

12 3

G

45

D

0.08 (0.003) X

EMD5DXV6T1, EMD5DXV6T5

PACKAGE DIMENSIONS

SOT−563, 6 LEAD

CASE 463A−01

ISSUE O

B

−Y−

6 5 PL

C

M

Y

K

S

J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETERS

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.

MILLIMETERS

DIMAMIN MAX MIN MAX

1.50 1.70 0.059 0.067

B 1.10 1.30 0.043 0.051
C 0.50 0.60 0.020 0.024
D 0.17 0.27 0.007 0.011
G 0.50 BSC 0.020 BSC
J 0.08 0.18 0.003 0.007
K

0.10 0.30

S

1.50 1.70

INCHES

0.004 0.012

0.059 0.067

STYLE 1:

PIN 1. EMITTER 1

2. BASE 1

3. COLLECTOR 2

4. EMITTER 2

5. BASE 2

6. COLLECTOR 1

STYLE 2:

PIN 1. EMITTER 1

2. EMITTER2

3. BASE 2

4. COLLECTOR 2

5. BASE 1

6. COLLECTOR 1

STYLE 3:

PIN 1. CATHODE 1

2. CATHODE 1

3. ANODE/ANODE 2

4. CATHODE 2

5. CATHODE 2

6. ANODE/ANODE 1

STYLE 4:

PIN 1. COLLECTOR

2. COLLECTOR

3. BASE

4. EMITTER

5. COLLECTOR

6. COLLECTOR

Thermal Clad is a trademark of the Bergquist Company.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

Literature Fulfillment:

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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [e-mail]

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JAPAN: ON Semiconductor, Japan Customer Focus Center

2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051

Phone: 81−3−5773−3850

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For additional information, please contact your local
Sales Representative.

EMD5DXV6/D

8