EMD4DXV6T1,
s
l
l
EMD4DXV6T5
Preferred Devices
Dual Bias Resistor
Transistors
NPN and PNP Silicon Surface Mount
Transistors with Monolithic Bias
Resistor Network
The BR T (Bias Resistor Transistor) contains a single transistor with
a monolithic bias network consisting of two resistors; a series base
resistor and a base−emitter resistor. These digital transistors are
designed to replace a single device and its external resistor bias
network. The BRT eliminates these individual components by
integrating them into a single device. In the EMD4DXV6T1 series,
two complementary BRT devices are housed in the SOT−563 package
which is ideal for low power surface mount applications where board
space is at a premium.
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(1)(2)(3)
R
1
R
Q
1
R
2
(4) (5) (6)
2
Q
R
1
2
Features
• Simplifies Circuit Design
• Reduces Board Space
• Reduces Component Count
• These are Pb−Free Devices
MAXIMUM RATINGS (T
and Q2, − minus sign for Q1 (PNP) omitted)
Rating Symbol Value Unit
Collector-Base Voltage V
Collector-Emitter Voltage V
Collector Current I
THERMAL CHARACTERISTICS
Characteristic
(One Junction Heated)
Total Device Dissipation
TA = 25°C (Note 1)
Derate above 25°C (Note 1)
Thermal Resistance,
Junction-to-Ambient (Note 1)
Total Device Dissipation
TA = 25°C (Note 1)
Derate above 25°C
Thermal Resistance,
Junction-to-Ambient (Note 1)
Junction and Storage Temperature TJ, T
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. FR−4 board with minimum mounting pad.
= 25°C unless otherwise noted, common for Q
A
CBO
CEO
C
Symbol Max Unit
P
D
R
q
JA
P
D
R
q
JA
stg
50 Vdc
50 Vdc
100 mAdc
357
2.9
350 °C/W
500
4.0
250 °C/W
− 55 to +150 °C
mW/°C
mW/°C
1
mW
mW
6
1
SOT−563
CASE 463A
STYLE 1
MARKING DIAGRAM
U7 M G
G
1
U7 = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device Package Shipping
EMD4DXV6T1G SOT−563
(Pb−Free)
EMD4DXV6T5G SOT−563
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Preferred devices are recommended choices for future use
and best overall value.
4000/Tape & Ree
8000/Tape & Ree
†
© Semiconductor Components Industries, LLC, 2005
October, 2005− Rev. 1
1 Publication Order Number:
EMD4DXV6/D
EMD4DXV6T1, EMD4DXV6T5
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
A
Characteristic Symbol Min Typ Max Unit
Q1 TRANSISTOR: PNP
OFF CHARACTERISTICS
Collector-Base Cutoff Current (VCB = 50 V, IE = 0) I
Collector-Emitter Cutoff Current (VCB = 50 V, IB = 0) I
Emitter-Base Cutoff Current (VEB = 6.0, IC = 5.0 mA) I
CBO
CEO
EBO
− − 100 nAdc
− − 500 nAdc
− − 0.2 mAdc
ON CHARACTERISTICS
Collector-Base Breakdown Voltage (IC = 10 mA, IE = 0)
Collector-Emitter Breakdown Voltage (IC = 2.0 mA, IB = 0) V
V
(BR)CBO
(BR)CEO
DC Current Gain (VCE = 10 V, IC = 5.0 mA) h
Collector−Emitter Saturation Voltage (IC = 10 mA, IB = 0.3 mA) V
Output Voltage (on) (VCC = 5.0 V, V
Output Voltage (off) (VCC = 5.0 V, V
= 2.5 V, RL = 1.0 kW)
B
= 0.5 V, RL = 1.0 kW)
B
CE(SAT)
FE
V
OL
V
OH
50 − − Vdc
50 − − Vdc
80 140 −
− − 0.25 Vdc
− − 0.2 Vdc
4.9 − − Vdc
Input Resistor R1 7.0 10 13
Resistor Ratio R1/R2 0.17 0.21 0.25
Q2 TRANSISTOR: NPN
OFF CHARACTERISTICS
Collector-Base Cutoff Current (VCB = 50 V, IE = 0) I
Collector-Emitter Cutoff Current (VCB = 50 V, IB = 0) I
Emitter-Base Cutoff Current (VEB = 6.0, IC = 0 mA) I
CBO
CEO
EBO
ON CHARACTERISTICS
Collector-Base Breakdown Voltage (IC = 10 mA, IE = 0)
Collector-Emitter Breakdown Voltage (IC = 2.0 mA, IB = 0) V
DC Current Gain (VCE = 10 V, IC = 5.0 mA) h
Collector−Emitter Saturation Voltage (IC = 10 mA, IB = 0.3 mA) V
Output Voltage (on) (VCC = 5.0 V, V
Output Voltage (off) (VCC = 5.0 V, V
= 3.5 V, RL = 1.0 kW)
B
= 0.5 V, RL = 1.0 kW)
B
V
(BR)CBO
(BR)CEO
CE(SAT)
V
V
FE
OL
OH
Input Resistor R1 32.9 47 61.1
Resistor Ratio R1/R2 0.8 1.0 1.2
− − 100 nAdc
− − 500 nAdc
− − 0.1 mAdc
50 − − Vdc
50 − − Vdc
80 140 −
− − 0.25 Vdc
− − 0.2 Vdc
4.9 − − Vdc
kW
kW
250
200
150
100
R
= 833°C/W
q
50
, POWER DISSIPATION (MILLIWATTS)
D
P
0
−50 0 50 100 150
JA
TA, AMBIENT TEMPERATURE (°C)
Figure 1. Derating Curve
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2
EMD4DXV6T1, EMD4DXV6T5
TYPICAL ELECTRICAL CHARACTERISTICS — EMD4DXV6T1 PNP TRANSISTOR
1
IC/IB = 10
0.1
0.01
, MAXIMUM COLLECTOR VOLTAGE (VOLTS)
CE(sat)
0.001
V
020406080
IC, COLLECTOR CURRENT (mA)
Figure 2. V
4.5
4
3.5
3
2.5
2
1.5
, CAPACITANCE (pF)
ob
C
1
0.5
0
0 2 4 6 8101520253035404550
VR, REVERSE BIAS VOLTAGE (VOLTS)
CE(sat)
TA=−25°C
75°C
versus I
f = 1 MHz
lE = 0 V
TA = 25°C
25°C
C
180
VCE = 10 V
160
140
120
100
80
60
40
, DC CURRENT GAIN (NORMALIZED)
20
FE
0
1 10 100
2 4 6 8 15 20 40 50 60 70 80 90
IC, COLLECTOR CURRENT (mA)
−25°C
TA=75°C
25°C
Figure 3. DC Current Gain
100
TA=75°C
−25°C
10
, COLLECTOR CURRENT (mA) h
C
I
1
0 246810
Vin, INPUT VOLTAGE (VOLTS)
VO = 5 V
25°C
Figure 4. Output Capacitance Figure 5. Output Current versus Input Voltage
10
VO = 0.2 V
75°C
1
, INPUT VOLTAGE (VOLTS)
in
V
0.1
01020304050
IC, COLLECTOR CURRENT (mA)
25°C
TA=−25°C
Figure 6. Input Voltage versus Output Current
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3
EMD4DXV6T1, EMD4DXV6T5
0
0
TYPICAL ELECTRICAL CHARACTERISTICS — EMD4DXV6T1 NPN TRANSISTOR
10
IC/IB = 10
TA = −25°C
25°C
75°C
1
(VOLTS)
0.1
MAXIMUM COLLECTOR VOLTAGE
0.01
CE(sat),
0 204060 80
V
IC, COLLECTOR CURRENT (mA)
Figure 7. V
CE(sat)
vs. I
C
1
f = 1 MHz
0.8
lE = 0 A
TA = 25°C
0.6
0.4
CAPACITANCE (pF)
ob,
C
0.2
0
010203040
VR, REVERSE BIAS VOLTAGE (VOLTS)
1000
100
DC CURRENT GAIN (NORMALIZED)
10
FE,
110
h
IC, COLLECTOR CURRENT (mA)
Figure 8. DC Current Gain
100
75°C
75°C
10
1
0.1
0.01
COLLECTOR CURRENT (mA)
C,
I
0.001
50
024681
Vin, INPUT VOLTAGE (VOLTS)
25°C
25°C
10
TA = −25°C
TA = −25°C
VCE = 10 V
TA = 75°C
25°C
−25°C
VO = 5 V
Figure 9. Output Capacitance
100
V
= 0.2 V
O
10
1
INPUT VOLTAGE (VOLTS)
in,
V
0.1
010 20304050
Figure 11. Input Voltage vs. Output Current
Figure 10. Output Current vs. Input Voltage
TA = −25°C
25°C
75°C
IC, COLLECTOR CURRENT (mA)
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4
EMD4DXV6T1, EMD4DXV6T5
PACKAGE DIMENSIONS
SOT−563, 6 LEAD
CASE 463A−01
ISSUE F
D
−X−
45L6
12 3
e
E
−Y−
b 6 5 PL
0.08 (0.003) X
M
A
H
E
C
Y
SOLDERING FOOTPRINT*
0.3
0.0118
1.35
0.0531
0.0394
1.0
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE MATERIAL.
MILLIMETERS
DIM MIN NOM MAX
A 0.50 0.55 0.60
b 0.17 0.22 0.27
C
0.08 0.12 0.18 0.003 0.005 0.007
D 1.50 1.60 1.70
E 1.10 1.20 1.30
e 0.5 BSC
L 0.10 0.20 0.30
H
1.50 1.60 1.70
E
STYLE 1:
PIN 1. EMITTER 1
2. BASE 1
3. COLLECTOR 2
4. EMITTER 2
5. BASE 2
6. COLLECTOR 1
INCHES
MIN NOM MAX
0.020 0.021 0.023
0.007 0.009 0.011
0.059 0.062 0.066
0.043 0.047 0.051
0.02 BSC
0.004 0.008 0.012
0.059 0.062 0.066
0.45
0.0177
0.5
0.5
0.0197
0.0197
mm
ǒ
SCALE 20:1
inches
Ǔ
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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EMD4DXV6/D
5
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