EMD4DXV6T1,
EMD4DXV6T5
Preferred Devices
Dual Bias Resistor
Transistors
NPN and PNP Silicon Surface Mount
Transistors with Monolithic Bias
Resistor Network
The BR T (Bias Resistor Transistor) contains a single transistor with
a monolithic bias network consisting of two resistors; a series base
resistor and a base−emitter resistor. These digital transistors are
designed to replace a single device and its external resistor bias
network. The BRT eliminates these individual components by
integrating them into a single device. In the EMD4DXV6T1 series,
two complementary BRT devices are housed in the SOT−563 package
which is ideal for low power surface mount applications where board
space is at a premium.
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(1)(2)(3)
R
1
R
Q
1
R
2
(4) (5) (6)
2
Q
R
1
2
Features
• Simplifies Circuit Design
• Reduces Board Space
• Reduces Component Count
• These are Pb−Free Devices
MAXIMUM RATINGS (T
and Q2, − minus sign for Q1 (PNP) omitted)
Rating Symbol Value Unit
Collector-Base Voltage V
Collector-Emitter Voltage V
Collector Current I
THERMAL CHARACTERISTICS
Characteristic
(One Junction Heated)
Total Device Dissipation
TA = 25°C (Note 1)
Derate above 25°C (Note 1)
Thermal Resistance,
Junction-to-Ambient (Note 1)
Total Device Dissipation
TA = 25°C (Note 1)
Derate above 25°C
Thermal Resistance,
Junction-to-Ambient (Note 1)
Junction and Storage Temperature TJ, T
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. FR−4 board with minimum mounting pad.
= 25°C unless otherwise noted, common for Q
A
CBO
CEO
C
Symbol Max Unit
P
D
R
q
JA
P
D
R
q
JA
stg
50 Vdc
50 Vdc
100 mAdc
357
2.9
350 °C/W
500
4.0
250 °C/W
− 55 to +150 °C
mW/°C
mW/°C
1
mW
mW
6
1
SOT−563
CASE 463A
STYLE 1
MARKING DIAGRAM
U7 M G
G
1
U7 = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device Package Shipping
EMD4DXV6T1G SOT−563
(Pb−Free)
EMD4DXV6T5G SOT−563
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Preferred devices are recommended choices for future use
and best overall value.
4000/Tape & Ree
8000/Tape & Ree
†
© Semiconductor Components Industries, LLC, 2005
October, 2005− Rev. 1
1 Publication Order Number:
EMD4DXV6/D
EMD4DXV6T1, EMD4DXV6T5
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
A
Characteristic Symbol Min Typ Max Unit
Q1 TRANSISTOR: PNP
OFF CHARACTERISTICS
Collector-Base Cutoff Current (VCB = 50 V, IE = 0) I
Collector-Emitter Cutoff Current (VCB = 50 V, IB = 0) I
Emitter-Base Cutoff Current (VEB = 6.0, IC = 5.0 mA) I
CBO
CEO
EBO
− − 100 nAdc
− − 500 nAdc
− − 0.2 mAdc
ON CHARACTERISTICS
Collector-Base Breakdown Voltage (IC = 10 mA, IE = 0)
Collector-Emitter Breakdown Voltage (IC = 2.0 mA, IB = 0) V
V
(BR)CBO
(BR)CEO
DC Current Gain (VCE = 10 V, IC = 5.0 mA) h
Collector−Emitter Saturation Voltage (IC = 10 mA, IB = 0.3 mA) V
Output Voltage (on) (VCC = 5.0 V, V
Output Voltage (off) (VCC = 5.0 V, V
= 2.5 V, RL = 1.0 kW)
B
= 0.5 V, RL = 1.0 kW)
B
CE(SAT)
FE
V
OL
V
OH
50 − − Vdc
50 − − Vdc
80 140 −
− − 0.25 Vdc
− − 0.2 Vdc
4.9 − − Vdc
Input Resistor R1 7.0 10 13
Resistor Ratio R1/R2 0.17 0.21 0.25
Q2 TRANSISTOR: NPN
OFF CHARACTERISTICS
Collector-Base Cutoff Current (VCB = 50 V, IE = 0) I
Collector-Emitter Cutoff Current (VCB = 50 V, IB = 0) I
Emitter-Base Cutoff Current (VEB = 6.0, IC = 0 mA) I
CBO
CEO
EBO
ON CHARACTERISTICS
Collector-Base Breakdown Voltage (IC = 10 mA, IE = 0)
Collector-Emitter Breakdown Voltage (IC = 2.0 mA, IB = 0) V
DC Current Gain (VCE = 10 V, IC = 5.0 mA) h
Collector−Emitter Saturation Voltage (IC = 10 mA, IB = 0.3 mA) V
Output Voltage (on) (VCC = 5.0 V, V
Output Voltage (off) (VCC = 5.0 V, V
= 3.5 V, RL = 1.0 kW)
B
= 0.5 V, RL = 1.0 kW)
B
V
(BR)CBO
(BR)CEO
CE(SAT)
V
V
FE
OL
OH
Input Resistor R1 32.9 47 61.1
Resistor Ratio R1/R2 0.8 1.0 1.2
− − 100 nAdc
− − 500 nAdc
− − 0.1 mAdc
50 − − Vdc
50 − − Vdc
80 140 −
− − 0.25 Vdc
− − 0.2 Vdc
4.9 − − Vdc
kW
kW
250
200
150
100
R
= 833°C/W
q
50
, POWER DISSIPATION (MILLIWATTS)
D
P
0
−50 0 50 100 150
JA
TA, AMBIENT TEMPERATURE (°C)
Figure 1. Derating Curve
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2