THE MARK FOUND ON SOME COMPONENT
PARTS INDICATES THE CRITICAL FOR RISK OF
FIRE AND ELECTRIC SHOCK.
WHEN REPLACING, BE SURE TO USE PARTS OF
IDENTICAL DESIGNATION.
MAKE LEAKAGE-CURRENT OR RESISTANCE
MEASUREMENTS TO DETERMINE THAT EXPOSED
PARTS ARE ACCEPTABLY INSULATED FROM THE
SUPPLY CIRCUIT BEFORE RETURNING THE
APPLIANCE TO THE CUSTOMER.
Digital OutputOptical: 1
Analog OutputsTAPE, VIDEO1, VIDEO2, ZONE2
Multichannel Pre
Outputs7.1 ch
Speaker OutputsL, R, C, SL, SR, SBL, SBR
Phones1
RS2321
IR Input/Output2/1
12 V Trigger Out
Australian: AC 230-240 V, 50 Hz
Australian: 570 W
Australian: 0.5 W
435 × 173.5 × 428.5 mm
17-1/8" × 6-13/16" × 16-7/8"
26.2 lbs.
VIDEO4
VIDEO4
Coaxial: 2
VIDEO2, VIDEO3, VIDEO4, TAPE, CD,
PHONO
L/R/SUBWOOFER
ZONE2 (L, R)
A, B, C
AM
Tuning Frequency Range
Usable Sensitivity300 µV/m
Signal to Noise Ratio40 dB
THD0.70%
North American: 530 kHz~1710 kHz
Australian: 522/530 kHz~1611/1710 kHz
Specifications and features are subject to change without
notice.
SERVICE PROCEDURES
1. Replacing the fuses
This symbol located near the fuses indicates that the
fuse used is fast operating type. For continued protection against
fire hazard, replace with same type fuse. For fuse rating refer to
the marking adjacent to the symbol.
Ce symbole indique que le fusible utlise est a rapide.
Pour une protection permanente, n'untiliser que fusibles de
meme type. Ce darnier est la qu le present symbol est
appse.
Note: <D>:120V model only
<A>: Australian model only
2. To initialize the unit
This device employs a microprocessor to perform various
functions and operations. If interference generated by an external
power supply, radio wave, or other electrical source results in
accident which causes the specified operations and functions to
operate abnormally.
To perform a result, please follow the procedure below.
1.Press and hold down the VIDEO-1 button, then press the
STANDBY button.
2.After "Clear" is displayed, the preset memory and each
mode stored in the memory, such as surround, are
initialized and will return to the factory setting.
3. Safety-check out
(U.S.A. model only)
After correcting the original service problem, perform the
following safety check before releasing the set to the customer.
Leakage Current Check
Measure leakage current to a known earth ground(water pipe,
conduit, etc.) by connecting a leakage current tester between
the earth ground and exposed metal parts of the appliance
(input/output terminals, screwheads,metal overlays, etc.).
4. Changing the AM band step
With the exception of the worldwide models, a tuning step selector
switch is not provided. When you change the band step, change
the parts as shown below.
FOR CONTINUED PROTECTION
AGAINST FIRE HAZARD, REPLACE
ONLY WITH FUSE OF SAME TYPE
AV
AND RATING INDICATED.
ATTENTIION
AFIN D'ASSURER UNE PROTECTION
PERMANENTE CONTRE LES RISQUES
D'INCENDIE, REMPLACER UNIQUEMENT
AV
PAR UN FUSIBLE DE MEME TYPE
ET CALIBRATION COMME INDIQUE.
1
1
AC-H
AC-G
T902
NPT-1519JQ <D>
NPT-1519GQ <A>
S1+
S1H+
GND
S1H-
S1S2+
GND
S2S3+
GND
S3S4+
S4-
J901
T902
234
1
678
9
5
C902
223J
TO NAAF-8678 JL6952B
1SS133
1SS133
TO NAPS-8665 P951TO NAPS-8665 P952
D905
D906
D908
D909
1SS133
D903
1SS133
D904
1SS133
1SS133
1SS133
1SS133
BCD
F903
100K
1
3
P912
1K
APOWER
+12VTRG
+10S
POFF1
RLGND
DGND
1
2
3
4
JL911A
5
6
D901
D902
P910
103M/275
C912
4
RL902
32
J905
+
2200/35
C903
+
100/50
C904
3
1
1
D912
1SS133
D907
1SS133
100K
R909
2.5A-SE-EAK <A>
5A-UL/T-233 <D>
4
2
+
C906
3.3/50
D910
DZ5.6BSB
J907
F901
6.3A-SE-EAK<A>
10A-UL/T-233<D>
Q912
2SC1740
R913
R914
D913
1SS133
C991
222J
D991
1SS133
D992
1SS133
P991
THIS SYMBOL LOCATED NEAR THE FUSE INDICATES
THAT THE FUSE USED IS SLOW OPERATING TYPE
FOR CONTINUED PROTECTION AGAINST FIRE FUSE
HAZARD,REPLACE WITH SAME TYPE FUSE. FOR FUSE
RATING REFER TO THE MAKING ADJACENT TO THE SYMBOL.
CE SYMBOLE INDIQUE QUE LE FUSIBLE UTLISE EST
A LENT, E POUR UNE PROTECTION PERMANENTE,N'UTILISER
QUE DES FUSIBLES DE MEME TYPE. CE DARNIER EST
INDIQUE LA QU LE PRESENT SYMBOL EST APPOSE.
NOTE
REPLACE ONLY WITH PART NUMBER SPECIFIED.
ELECTROLYTIC CAPACITORSARE IN
ALL CAPACITORS ARE IN pF/50WV UNLESS OTHERWISE NOTED.
EX) 030 3pF 330 33pF 331 330pF 333 0.033uF
ALL RESISTORS ARE IN OHMS 1/4WATTS UNLESS OTHERWISE NOTED.
THE THICK LINES ON PC BOARD ARE THE PRINTING SIDE OF THE PARTS
EXPRINTING SIDE
CIRCUIT IS SUBJECT TO CHANGE FOR IMPROVEMENT.
5
NAETC-8671
U048
P908
INLET
ARE CRITICAL FOR SAFETY.THE COMPONENTS IDENTIFIED BY MARK
FOR CONTINUED PROTECTION
AGAINST FIRE HAZARD, REPLACE
ONLY WITH FUSE OF SAME TYPE
AV
AND RATING INDICATED.
ATTENTIION
AFIN D'ASSURER UNE PROTECTION
PERMANENTE CONTRE LES RISQUES
D'INCENDIE, REMPLACER UNIQUEMENT
AV
PAR UN FUSIBLE DE MEME TYPE
ET CALIBRATION COMME INDIQUE.
THIS SYMBOL LOCATED NEAR THE FUSE INDICATES
THAT THE FUSE USED IS SLOW OPERATING TYPE
FOR CONTINUED PROTECTION AGAINST FIRE FUSE
HAZARD,REPLACE WITH SAME TYPE FUSE. FOR FUSE
RATING REFER TO THE MAKING ADJACENT TO THE SYMBOL.
CE SYMBOLE INDIQUE QUE LE FUSIBLE UTLISE EST
A LENT, E POUR UNE PROTECTION PERMANENTE,N'UTILISER
QUE DES FUSIBLES DE MEME TYPE. CE DARNIER EST
INDIQUE LA QU LE PRESENT SYMBOL EST APPOSE.
NOTE
REPLACE ONLY WITH PART NUMBER SPECIFIED.
ELECTROLYTIC CAPACITORSARE IN
ALL CAPACITORS ARE IN pF/50WV UNLESS OTHERWISE NOTED.
EX) 030 3pF 330 33pF 331 330pF 333 0.033uF
ALL RESISTORS ARE IN OHMS 1/4WATTS UNLESS OTHERWISE NOTED.
THE THICK LINES ON PC BOARD ARE THE PRINTING SIDE OF THE PARTS
EXPRINTING SIDE
CIRCUIT IS SUBJECT TO CHANGE FOR IMPROVEMENT.
ARE CRITICAL FOR SAFETY.THE COMPONENTS IDENTIFIED BY MARK
COMP2
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
SCLOCK
SDATA
CLAMP
PAL_NTSC
VSO
CSO_HSO
ALSB
RESET
TTX
TTXREQ
AA
V
GND
I
8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7-P0) P0 represents the LSB.
I
TTL Clock Input. Requires a stable 27 MHz reference clock for standard operation. Alternatively,
a 24.5454 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel operation.
I/O
HSYNC (Modes 1 and 2) Control Signal. This pin may be configured to output (Master
Mode) or as an input and accept (Slave Mode) Sync signals.
I/O
Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This pin may be
configured to output (Master Mode) or as an input (Slave Mode) and accept these
control signals.
I/O
Video Blanking Control Signal. The pixel inputs are ignored when this is Logic Level "0"
This signal is optional.
I
This pin can be configured as an input by setting MR42 and MR41 of Mode Register 4. It
can be configured as a subcarrier reset pin, in which case a low-to-high transition on this
pin will reset the subcarrier phase to Field 0. Alternatively it may be configured as a RealTime Control (RTC) Input.
I/O
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
I
A 150 ohms resistor connected from this pin to GND is used to control full-scale amplitudes
the Video Signals from DACs A, B, and C (the "large" DACs).
I
A 600 ohms resistor connected from this pin to GND is used to control full-scale amplitudes
the Video Signals from DACs D, E, and F (the "small" DACs).
O
Compensation Pin for DACs A, B, and C. Connect a 0.1 uF Capacitor from COMP to
AA. For Optimum Dynamic Performance in Low Power Mode, the value of the
V
COMP1 capacitor can be lowered to as low as 2.2 nF.
Compensation Pin for DACs D, E, and F. Connect a 0.1 uF Capacitor from COMP to VAA.
O
GREEN/Composite/Y Analog Output. This DAC is capable of providing 34.66 mA output.
O
BLUE/S-Video Y/U Analog Output. This DAC is capable of providing 34.66 mA output.
O
RED/S-Video C/V Analog Output. This DAC is capable of providing 34.66 mA output.
O
GREEN/Composite/Y Analog Output. This DAC is capable of providing 8.66 mA output.
O
BLUE/S-Video Y/U Analog Output. This DAC is capable of providing 8.66 mA output.
O
RED/S-Video C/V Analog Output. This DAC is capable of providing 8.66 mA output.
O
MPU Port Serial Interface Clock Input.
I
MPU Port Serial Data Input/Output.
I/O
TTL Output Signal to external circuitry to enable clamping of all video signals.
O
Input signal to select PAL or NTSC mode of operation, pin set to Logic "1" selects PAL.
I
VSO TTL Output Sync Signal.
O
Dual Function CSO or HSO TTL Output Sync Signal.
O
TTL Address Input. This signal sets up the LSB of the MPU address.
I
The input resets the on-chip timing generator and sets the ADV7172/ADV7173 into
I
default mode. This is NTSC operation, Timing Slave Mode 0, DACs A, B, and C powered
OFF, DACs D, E, and F powered ON, Composite and S-Video out.
Teletext Data Input Pin.
I
Teletext Data Request output signal used to control teletext data transfer.
O
Power Supply (3 V to 5 V).
P
Ground Pin.
G
IC BLOCK DIAGRAMS AND DESCRIPTIONS
ADV7183 (Advanced Video Decoder with 10-Bit ADC and Component Support)
BLOCK DIAGRAM
P15-P0
PIXEL
O/P PORT
DTR-5.6
ADV7183
ISO
REFOUT
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
ANALOG I/P
MULTIPLEXING
AUTOMATIC
GAIN
CONTROL
(AGC)
CLAMP AND
DC RESTRE
PWRDN
TERMINAL DESCRIPTION
PinMnemonicInput/OutputFunction
1VS/VACTIVEOVS or Vertical Sync. A dual-function pin, (OM_SEL[1:0] = 0, 0) is an
32, 33, 73-76
9, 31, 71DVSS1-3GGround for Digital Supply
10, 30, 72DVDD1-3PDigital Supply Voltage (3.3 V)
11AFFOAlmost Full Flag. A FIFO control signal indicating when the FIFO has
12HFF/QCLK/GL I/OHalf Full Flag. A multifunction pin, (OM_SEL[1:0] = 1, 0) is a FIFO
13AEFOAlmost Empty Flag. A FIFO control signal, it indicates when the FIFO
16CLKINIAsynchronous FIFO Clock. This asynchronous clock is used to output
17, 18, 34, 35 GPO[3:0]OGeneral-Purpose Outputs controlled via I
SHAPING
AND
NOTCH LPF
10-BIT
ADC
27MHz
10-BIT
ADC
VIDEO TIMING AND
CONTROL BLOCK
HSYNC FIELD VSYNC HREF VREFCLOCK
LUMA
ANTIALIAS
LPF
SWITCH
PEAKING
HPF/LPF
SUB-
CARRIER
RECOVERY
DTO
CHROMA
ANTIALIAS
LPF
27MHz XTAL
OSCILLATOR
BLOCK
output signal that indicates a vertical sync with respect to the YUV pixel
data. The active period of this signal is six lines of video long. The polarity
of the VS signal is controlled by the PVS bit. VACTIVE (OM_SEL[1:0] =
1, 0 or 0, 1) is an output signal that is active during the active/viewable
period of a video field. The polarity of VACTIVE is controlled by PVS bit.
HS or Horizontal Sync. A dual-function pin, (OM_SEL[1:0] = 0, 0) is a
programmable horizontal sync output signal. The rising and falling edges
can be controlled by HSB[9:0] and HSE[9:0] in steps of 2 LLC1. The polarity
of the HS signal is controlled by the PHS bit. HACTIVE (OM_SEL[1:0]=
1, 0 or 0, 1) is an output signal that is active during the active/viewable
period of a video line. The active portion of a video line is programmable on
the ADV7183. The polarity of HACTIVE is controlled by PHS bit.
16-bit YCrCb pixel port (P15-P8 = Y and P7-P0 = Cb,Cr).
reached the almost full margin set by the user (use FFM[4:0]). The polarity
of this signal is controlled by the PFF bit.
control signal that indicates when the FIFO is half full. The QCLK
(OM_SEL[1:0] = 0, 1) pin function is a qualified pixel output clock when
using FIFO SCAPI mode. The GL (OM_SEL[1:0] = 0, 0) function
(Genlock output) is a signal that contains a serial stream of data that contains
information for locking the subcarrier frequency. The polarity of HFF signal
is controlled by PFF bit.
has reached the almost empty margin set by the user (use FFM[4:0]). The
polarity of this signal is controlled by PFF bit.
data onto the P19-P0 bus and other control signals.
RESAMPLING
AND
HORIZONTAL
SCALING
SYNC
DETECTION
RESAMPLING
AND
HORIZONTAL
SCALING
SHAPING
LPF
CLOCK
LUMA
DELAY
BLOCK
2H LINE
MEMORY
CHROMA
COMB
FILTER
I2C-COMPATIBLE
INTERFACE PORT
SCLOCKRESETALSB
SDATA
2
C
FIFO CONTROL
BLOCK
AND
PIXEL
OUTPUT
FORMATTER
LLC
SYNTHESIS
WITH LINE-
LOCKED
OUTPUT
CLOCK
AFF
HFF/QCLK
AEF
DV
RD
OE
GL/CLKIN
LLC1
LLC2
LLCREF
ELPF
IC BLOCK DIAGRAMS AND DESCRIPTIONS
ADV7183 (Advanced Video Decoder with 10-Bit ADC and Component Support)
TERMINAL DESCRIPTION
PinMnemonicInput/OutputFunction
25LLCREFOClock Reference Output. This is a clock qualifier distributed by the inter-
26LLC2OLine-Locked Clock System Output Clock/2 (13.5 MHz)
27LLC1/PCLKOLine-Locked Clock System Output Clock. A dual-function pin (27 MHz 5%)
28XTAL1OSecond terminal for crystal oscillator; not connected if external clock
29XTALIInput terminal for 27MHz crystal oscillator or connection for external
36PWRDNIPower-Down Enable. A logical low will place part in a power-down status.
37ELPFIThis pin is used for the External Loop Filter that is required for the LLC PLL.
38PVDD
39
40, 47, 53, 56,
63
41, 43, 45, 57,
59, 61
42, 44, 46, 58,
60, 62
48, 49
50
51
52
54, 55
64
65
66
67
68
69
70
77
78
79
80
PVSSG
AVSS
AVSS1-6
AIN1-6
CAPY1-2
AVDD
REFOUT
CML
CAPC1-2
RESET
ISO
ALSB
SDATA
SCLK
VREF/VRESET
HREF/HRESET
RD
DV
OE
FIELD
P
G
G
I
I
P
O
O
I
I/O
I
I
I/O
I
O
O
I
O
I
O
nal CGC for a data rate of LLC2. The polarity of LLCREF is controlled
by the PLLCREF bit.
or a FIFO output clock ranging from 20 MHz to 35 MHz.
source is used.
oscillator with CMOS-compatible square wave clock signal
Ground for Analog Supply
Analog Input Channels. Ground if single-ended mode is selected. These
pins should be connected directly to REFOUT when differential mode is
selected.
Video Analog Input Channels
ADC Capacitor Network
Analog Supply Voltage (5 V)
Internal Voltage Reference Output
Common-Mode Level for ADC
ADC Capacitor Network
System Reset Input. Active Low.
Input Switch Over. A low to high transition on this input indicates to the
decoder core that the input video source has been changed externally and
configures the decoder to reacquire the new timing information of the new
source. This is useful in applications where external video muxes are used.
This input gives the advantage of faster locking to the external muxed
video sources. A low to high transition triggers this input.
TTL Address Input. Selects the MPU address:
MPU address = 88h ALSB = 0, disables I C filter
MPU address = 8Ah ALSB = 1, enables I C filter
MPU Port Serial Data Input/Output
MPU Port Serial Interface Clock Input
VREF or Vertical Reference Output Signal. Indicates start of next field.
VRESET or Vertical Reset Output is a signal that indicates the beginning
of a new field. In SCAPI/CAPI mode this signal is one clock wide and
active low relative to CLKIN. It immediately follows the HRESET pixel,
and indicates that the next active pixel is the first active pixel of the next field.
HREF or Horizontal Reference Output Signal. A dual-function pin
(enabled when Line-Locked Interface is selected, OM_SEL[1:0] = 0,0),
this signal is used to indicate data on the YUV output. The positive slope
indicates the beginning of a new active line; HREF is always 720 Y samples
long. HRESET or Horizontal Reset Output (enabled when SCAPI or
CAPI is selected, OM_SEL[1:0] = 0, 1 or 1, 0) is a signal that indicates the
beginning of a new line of video. In SCAPI/CAPI this signal is one clock
cycle wide and is output relative to CLKIN. It immediately follows the last
active pixel of a line. The polarity is controlled via PHVR.
Asynchronous FIFO Read Enable Signal. A logical high on this pin enables
a read from the output of the FIFO.
DV or Data Valid Output Signal. In SCAPI/CAPI mode, DV performs to
functions, depending on whether SCAPI or CAPI is selected. It toggles
high when the FIFO has reached the AFF margin set by the user, and
remains high until the FIFO is empty. The alternative mode is where it can
be used to control FIFO reads for bursting information out of the FIFO. In
API mode DV indicates valid data in the FIFO, which includes both pixel
information and control codes. The polarity of this pin is controlled via PDV.
Output Enable Controls Pixel Port Outputs. A logic high will three-state
P19-P0.
ODD/EVEN Field Output Signal. An active state indicates that an even
field is being digitized. The polarity of this signal is controlled by the PF bit.
3 CnvssConnect to Vcc.
5 FW_CEI Port for writing flash.
6 ~RESETI Reset input
7 XoutConnect to the crystal oscillator.
8 VssGround for power supply
9 XinConnect to the crystal oscillator.
10 VccPower supply Vcc
20 MHREQI Request signal to transfer the serial data from main microprocessor. (System)
21 MSREQO Request signal to transfer the serial data to main microprocessor. (Local)
22 MCLKI Serial clock input from main microprocessor.
23 MSDII Serial data input from main microprocessor.
24 MSDOO Serial data output to main microprocessor.
25 FW_TXDO Port for writing flash.
26 FW_RXDI Port for writing flash.
27 FW_SCLKI Port for writing flash.
28 FW_BUSYO Port for writing flash.
29 DACSDOO Serial data output for DAC.
30 DACRESETO Reset output for DAC.
31 DACCSO Serial communication chip select for DAC.
32 DACCLKO Serial communication clock for DAC.
33 XMSDOO Serial data output for XM IC.
34 XMSDII Serial data input for XM IC.
43 XM_COM_SELO Command select output for XM IC.
44 XM_RESETO Reset output for XM IC.
45 XM_ERR_IRQI Error interrupt request line for XM IC.
46 FW_P16I Port for writing flash.
48 XM_PWR_CTRLO Power supply control for XM IC.
59 AVSSGround for A/D converter.
61 VrefReference power supply for A/D converter.
62 AVccPower supply for A/D converter.
IC BLOCK DIAGRAMS AND DESCRIPTIONS
K
∆Σ
AK4384(106dB 192kHz 24-Bit 2ch DAC)
DTR-5.6
SMUTE/CSN
ACKS/CCL
DIF0/CDTI
LRCK
BICK
SDTI
MCLK
Clock
Divider
∆Σ
Modulator
∆Σ
Modulator
SCF
LPF
SCF
LPF
P/S
ATT
ATT
De-emphasis
Control
8X
Interpolator
8X
Interpolator
µP
Interface
Audio
Data
Interface
PDN
No. Pin Name I/O Function
1 MCLK I Master Clock Input Pin
An external TTL clock should be input on this pin.
2 BICK I Audio Serial Data Clock Pin
3 SDTI I Audio Serial Data Input Pin
4 LRCK I L/R Clock Pin
5 PDN I Power-Down Mode Pin
When at “L”, the AK4384 is in the power-down mode and is held in reset. The
AK4384 should always be reset upon power-up.
SMUTE I Soft Mute Pin in parallel mode
6
“H”: Enable, “L”: Disable
CSN I Chip Select Pin in serial mode
7
ACKS I Auto Setting Mode Pin in parallel mode
“L”: Manual Setting Mode, “H”: Auto Setting Mode
CCLK I Control Data Clock Pin in serial mode
DIF0 I Audio Data Interface Format Pin in parallel mode 8
CDTI I Control Data Input Pin in serial mode
9 P/S I
Parallel/Serial Select Pin (Internal pull-up pin)
“L”: Serial control mode, “H”: Parallel control mode
10 AOUTR O Rch Analog Output Pin
11 AOUTL O Lch Analog Output Pin
12 VCOM O Common Voltage Pin, VDD/2
Normally connected to VSS with a 0.1µF ceramic capacitor in parallel with a
10µF electrolytic cap.
13 VSS - Ground Pin
14 VDD - Power Supply Pin
15 DZFR O Rch Data Zero Input Detect Pin
16 DZFL O Lch Data Zero Input Detect Pin
Note: All input pins except pull-up pin should not be left floating.
CX_SCLKCODEC Serial Clock (Input/Output) - Serial clock for the CODEC serial audio interface
CX_LRCK
VD
DGND
VLC
SCL/CCLK
SDA/CDOUT
AD1/CDIN
AD0/CS10Address Bit 0 (I C)/Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I C mode; CS
INT 11 Interrupt (Output) - The CS42518 will generate an interrupt condition as per the Interrupt Mask register.
Codec Serial Audio Data Input (Input) - Input for two's complement serial audio data.
64
63
62
2
3
CODEC Left Right Clock (Input/ Output) - Determines which channel, Left or Right, is currently active on
the CODEC serial audio data line.
4
Digital Power (Input) - Positive power supply for the digital section.
51
5
Digital Ground (Input) - Ground reference. Connects to digital ground.
52
6
Control Port Power (Input) - Determines the required signal level for the control port.
7
Serial Control Port Clock (Input) - Serial clock for the serial control port.
8
Serial Control Data (Input/Output) - SDA is a data I/O line in IC mode and requires an external pull-up
resistor to the logic interface voltage. CDOUT is the output
data line for the control port interface in SPI mode.
Address Bit 1 (I C)/Serial Control Data (SPI) (Input) - AD1 a chip address pin in I C mode; CDIN is
9
the input data line for control port interface in SPI mode.
is the chip select signal in SPI mode.
Pin Description
2
2
2
2
RST12Reset (Input) - The device enters a low power mode and all internal registers are reset to their default
settings when low.
AINRAINR+
AINLAINL+
VQ17Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.
FILT+18Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
REFGND19Reference Ground (Input) - Ground reference for the internal sampling circuits.
AOUTA1 +, -
RXP049S/PDIF Receiver Input (Input) - Dedicated receiver input for S/PDIF encoded data.
TXP50S/PDIF Transmitter Output (Output) - S/PDIF encoded data output, mapped directly from one of the
VLP53Serial Port Interface Power (Input) - Determines the required signal level for the serial port interfaces.
SAI_SDOUT54
RMCK55Recovered Master Clock (Output) - Recovered master clock output from the External Clock Reference
24
41
40
42
43
44
45
46
47
48
Analog Power (Input) - Positive power supply for the analog section.
Analog Ground (Input) - Ground reference. Connects to analog ground.
dition or whenever the PDN bit is set to a "1", forcing the codec into power -down mode. The signal will
remain in a high impedance state as long as the part is in power-down mode. The Mute Control pin goes
to the selected "active" state during reset, muting, or if the master clock to left/right clock frequency ratio
is incorrect. This pin is intended to be used as a control for external mute circuits to prevent the clicks
and pops that can occur in any single supply system. The use of external mute circuits are not mandatoy but may be desired for designs requiring the absolute minimum in extraneous clicks and pops.
S/PDIF Receiver Input/ General Purpose Output (Input/ Output) - Receiver inputs for S/PDIF encoded
data. The CS42518 has an internal 8:2 multiplexer to select the active receiver port, according to the
Receiver Mode Control 2 resister. These pins can also be configured as general purpose output pins,
ADC Overflow indicators or Mute Control outputs according to the RXP/General Purpose Pin Control
resisters.
receiver inputs as indicated by the Receiver Mode Control 2 resister.
Serial Audio Interface Serial Data Output (Output) - Output for two's complement serial audio PCM
data from the S/PDIF incoming stream. This pin can also be configured to transmit the output of the internal and external ADCs.
DTR-5.6
CX_SDOUT56CODEC Serial Data Output (Output) - Output for two's complement serial audio data the internal
and external ADCs.
ADCIN1
ADCIN2
OMCK
SAI_LRCK
SAI_SCLK61Serial Audio Interface Serial Clock (Input/Output) - Serial clock for the Serial Audio Interface
58
57
59
60Serial Audio Interface Left/Right Clock (Input/Output) - Determines which channel, Left of Right, is
External ADC Serial Input (Input) - The CS42528 provides for up two external stereo analog to digital
converter inputs to provide a maximum of six channels on serial data output line when the CS42528
is placed in One Line mode.
External Reference Clock (Input) - External clock reference that must be within the ranges specified in
currently active on the serial audio data line.
UHS0, GPIO18 :DSPC control mode select Bit 0, General Purpose I/O
UHS1, GPIO19 :DSPC control mode select Bit 1, General Purpose I/O
INTREQ:Control Port Interrupt Request
FA1, FSCDIN
GPIO20:General Purpose I/O can be individually configured and controlled by DSPC.
FAO, FSCCLK
FHS2, FSCDIO, FSCDOUT:Mode select bit 2 or serial control port data input and output,parallel porttype select
GPIO21:General Purpose I/O can be individually configured and controlled by DSPC.
FDAT7:DSPAB Bidirectional Data Bus input
VDD6:2.5V supply voltage.
VSS6:2.5V ground.
FHS0, FWR, FDS:Mode select bit 0 or host write strobe or host data strobe
FHS1, FRD, FR/W:Mode select bit 1 or host parallel output enable or host parallel R/W
FDAT6:DSPAB Bidirectional Data Bus input
FCS:Host parallel chip select,Host serial SPI chip select
FINTREQ:Control port interrupt request
FDBCK:Reversed input:This pin is reversed and is pulled up with an external resistor.
FDAT5:DSPAB Bidirectional Data Bus input
FDAT4:DSPAB Bidirectional Data Bus input
VDD7:2.5V supply voltage.
VSS7:2.5V ground.
FDAT3:DSPAB Bidirectional Data Bus input
FDBDAReversed input:This pin is reversed and is pulled up with an external resistor.
FDAT2:DSPAB Bidirectional Data Bus input
DBDA:Debug data
DBCK:Debug clock
FDAT1:DSPAB Bidirectional Data Bus input
TEST:This pin is connected low for normal operation.
FDAT0:DSPAB Bidirectional Data Bus input
NV_WE, GPIO16:SRAM write enable output, General Purpose I/O
NV_OE, GPIO15:SRAM output Enable output, General Purpose I/O
NV_CS, GPIO14:SRAM Chip Select output, General Purpose I/O
SD_WE
SD_DATA0, EXTD0:SDRAM data bus. SRAM external data bus input.
SD_DATA1, EXTD1:SDRAM data bus. SRAM external data bus input.
SD_DATA2, EXTD2:SDRAM data bus. SRAM external data bus input.
SD_DATA3, EXTD3:SDRAM data bus. SRAM external data bus input.
SD_DATA4, EXTD4:SDRAM data bus. SRAM external data bus input.
SD_DQM0:SDRAM data mask 0 output.
SD_DATA5, EXTD5:SDRAM data bus. SRAM external data bus input.
VSSSD4:3.3V SDRAM / SRAM / EPROM Interface ground.
VDDSD4:3.3V SDRAM / SRAM / EPROM Interface supply
SD_DATA6, EXTD6:SDRAM data bus. SRAM external data bus input.
SD_DATA7, EXTD7:SDRAM data bus. SRAM external data bus input.
SD_DQM1:SDRAM data mask 1 output.
SD_DATA15, EXTA18:SDRAM data bus output, SRAM external address bus output
SD_DATA14, EXTA17:SDRAM data bus output, SRAM external address bus output
NC5:No connect. Connect to ground.
:Host parallel address bit zero or SPI rerial control data input
:Host Parallel Address Bit Zero or Serial Control Port Clock
HDATA5, GPIO5:DSPC Bidirectional Data Bus, General Purpose I/O
SCLK1
:Audio Output Bit Clock:Bidirectional digital-audio output bit clock for AUDATA4, to AUDATA7.
As an output, SCLK1 can provide 32 fs, 64 fs, 128 fs, 256 fs, or 512 fs frequencies and is synchronous to MCLK.
MCLK:Bidirectional master audio clock. As an output, MCLK provides a low jitter oversampling clock.
VDD2:2.5V supply voltage.
VSS2:2.5V ground.
AUDATA4, GPIO28:Digital Audio Output 4, General Purpose I/O.PCM digital-audio data output.
HDATA4, GPIO4:DSPC Bidirectional Data Bus, General Purpose I/O
SCLK0
HDATA3, GPIO3:DSPC Bidirectional Data Bus, General Purpose I/O
AUDATA3, XMT958A:Digital Audio Output 3, S/PDIF Transmitter
AUDATA2:PCM digital-audio data output.
LRCLK0:Audio Output Sample Rate Clock
AUDATA1:PCM digital-audio data output.
AUDATA0:PCM digital-audio data output.
CMPCLK, FSCLKN2:PCM Audio Input Bit Clock:Digital- audio bit clock input.
HDATA2, GPIO2:DSPC Bidirectional Data Bus, General Purpose I/O
VSS3:2.5V ground.
VDD3:2.5V supply voltage.
HDATA1, GPIO1:DSPC Bidirectional Data Bus, General Purpose I/O
HDATA0, GPIO0:DSPC Bidirectional Data Bus, General Purpose I/O
CMPREQ, FLRCLKN2:PCM audio input request
CMPDAT, FSDATAN2:Digital-audio data input that can accept either one compressed line or 2 channels of PCM data.
FLRCLKN1:Digital-audio frame clock input.
WR, DS, GPIO10:Host Write Strobe, Host Data Strobe, General Purpose I/O
RD, R/W, GPIO11:Host Parallel Output Enable, Host Parallel R/W, General Purpose I/O
PLLVSS :PLL Ground Voltage
FILT2:
FILT1:
PLLVDD:2.5V PLL supply voltage.
XTALO:
CLKIN, XTALI:External Clock input / Crystal Oscillator input:12MHz crystal oscillator is connected.
CLKSEL:DSP Clock select input
CS, GPIO9:Host Parallel Chip Select, General Purpose I/O
A0, GPIO13:Host Address Bit 0, General Purpose I/O
FSDATAN1:Digital-audio data input can accept from one compressed line or 2 channels of PCM data.
VDD4:2.5V supply voltage.
VSS4:2.5V ground.
FSCLKN1, STCCLK2:Digital audio bit clock input.
SCS:Host Serial SPI Chip Select:SPI mode active-low chip-select input signal.
SCDIN:SPI Serial Control Data Input:In SPI mode this pin serves as the data input pin.
VSS5:2.5V ground.
VDD5:2.5V supply voltage.
A1, GPIO12:Host Address Bit 1, General Purpose I/O
SCDOUT, SCDIO:Serial Control Port Data Input and Output:In SPI mode this pin serves as the data output pin.
HINBSY, GPIO8:
2MCLKIMaster Clock-Clock source for the delta-si
3VLLo
4SDOUTOSerial Audio Data Out
5,14 GNDGround-Connect to the analo
6VDIDi
Mode Selection-Determines the operational mode of the device.
ma modulator and digital filters.
ic Power-Positive power supply for digital input/output.
ut-Output for two's complement serial audio data.
round.
ital Power-Positive power supply for the digital section.
7SCLKI/O Serial Clock-Serial clock for the serial audio interface.
8LRCKI/O
9RSTIReset-The device enters a low
10AINLI
12AINRI
11VQO
13VAAnalo
15FILT+O
Left Right Clock-Determines which channel, Left and Right, is currently
active on the serial audio data line.
ower mode when low.
Analog Input-The full scale analog input level is 0.56Vp-p.
Quiescent Voltage-Filter connection for the internal quiescent
reference voltage.
Power-Positive power supply for the analog section.
Positive Voltage Reference-Positive reference voltage for the internal
sampling circuits.
RST
M0
M1
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS
IC42S16100 (16-Mbit Synchronous Dynamic RAM)
BLOCK DIAGRAM
CLK
CKE
CS
RAS
CAS
WE
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
COMMAND
DECODER
&
CLOCK
GENERATOR
REFRESH
CONTROLLER
REFRESH
COUNTER
ROW
ADDRESS
LATCH
11
MODE
REGISTER
SELF
REFRESH
CONTROLLER
11
MULTIPLEXER
11
8
11
ADDRESS
BUFFER
COLUMN
ADDRESS
BUFFER
ROW
11
ADDRESS LATCH
BURST COUNTER
ROW
11
MEMORY CELL
2048
SENSE AMP I/O GATE
COLUMN DECODER
8
COLUMN
ADDRESS BUFFER
SENSE AMP I/O GATE
MEMORY CELL
2048
ROW DECODERROW DECODER
ARRAY
BANK 0
256
256
ARRAY
BANK 1
DATA IN
BUFFER
16
DATA OUT
BUFFER
1616
DTR-5.6
DQM
16
I/O 0-15
Vcc/VccQ
GND/GNDQ
VCC
I/O0
I/O1
GNDQ
I/O2
I/O3
VCCQ
I/O4
I/O5
GNDQ
I/O6
I/O7
VCCQ
LDQ
WE
CAS
RAS
A11
A10
VCC
M
CS
A0
A1
A2
A3
PIN LAYOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Pin No.Pin name Function
20 to 24
27 to 32
GND
50
I/O15
49
I/O14
48
GNDQ
47
I/O13
46
I/O12
45
44
43
42
41
40
39
38
37
36
35
4
3
33
2
3
1
3
0
3
9
2
28
7
2
6
2
VCC
I/O11
I/O10
GNDQ
I/O9
I/O8
VCC
NC
UDQ
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
GND
Q
Q
M
2, 3, 5, 6, 8, 9,
11, 12, 39, 40,
42, 43, 45, 46,
48, 49
14, 36LDQM,
7, 13, 38, 44V
1, 25V
4, 10, 41, 47GNDQGNDQ is the output buffer ground.
26, 50GNDGND is the device internal ground.
A0-A10 A0 to A10 are address inputs. A0-A10 are used as row address inputs during active command input
and A0-A7 as column address inputs during read or write command input. A10 is also used to
determine the precharge mode during other commands. If A10 is LOW during precharge command,
the bank selected by A11 is precharged, but if A10 is HIGH, both banks will be precharged.
When A10 is HIGH in read or write command cycle, the precharge starts automatically after
the burst access.
These signals become part of the OP CODE during mode register set command input.
19A11A11 is the bank selection signal. When A11 is LOW, bank 0 is selected and when high, bank 1 is
16CASCAS, in conjunction with the RAS and WE, forms the device command. See the "Command Truth
34CKEThe CKE input determines whether the CLK input is enabled within the device.
35CLKCLK is the master clock input for this device. Except for CKE, all inputs to this device are acquired
18CSThe CS input determines whether command input is enabled within the device.
17RASRAS, in conjunction with CAS and WE, forms the device command. See the "Command Truth
15WEWE, in conjunction with RAS and CAS, forms the device command. See the "Command Truth
selected. This signal becomes part of the OP CODE during mode register set command input.
Table" item for details on device commands.
When is CKE HIGH, the next rising edge of the CLK signal will be valid, and when LOW, invalid.
When CKE is LOW, the device will be in either the power-down mode, the clock suspend mode,
or the self refresh mode. The CKE is an asynchronous input.
in synchronization with the rising edge of this pin.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The device remains in
the previous state when CS is HIGH.
I/O0
I/O0 to I/O15 are I/O pins. I/O through these pins can be controlled in byte units using the LDQM and
to
UDQM pins.
I/O15
LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read mode, LDQM and
UDQM
UDQM control the output buffer. When LDQM or UDQM is LOW,
the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to theHIGH
impedance state when LDQM/UDQM is HIGH. This function corresponds to OE in conventional
DRAMs. In write mode, LDQM and UDQM control the input buffer.
When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can be written to
the device. When LDQM or UDQM is HIGH, input data is masked and cannot be written to the device.
Table" item for details on device commands.
Table" item for details on device commands.
CCQVCCQ is the output buffer power supply.
CCVCC is the device internal power supply.
IC BLOCK DIAGRAMS AND DESCRIPTIONS
LC74763-9836 (On-Screen Display IC)
BLOCK DIAGRAM
DTR-5.6
SIN
SCLK
RST
SECAM
525/625
NTSC/PAL
3.58/4.43
VDD1
VDD2
VSS
SYNCDET
VCOIN
VCOOUT
AMPIN
AMPOUT
PDOUT
CS
Serialparallel
converter
Composite
synchronization
signal
control
FC
AFC
circuit
8-bit latch
and
command
decoder
Sync
detector
Composite
synchronization
signal separator
control
Horizontal
character
size register
Horizontal
size
counter
Vertical
character
size register
Vertical
size
counter
Timing generator
Horizontal
display
position
register
Horizontal
dot counter
Horizontal
display
position
detection
Character
control
counter
Vertical
display
position
register
Vertical
dot counter
Vertical
display
position
detection
Line
control
counter
Synchronization
signal generator
Flashing/
reversal
control
register
Flashing/
reversal
control
circuit
Character output control
Background control
video output control
Display
control
register
RAM write
address
counter
Decoder
Display RAM
Decoder
Font ROM
Shift register
SYSIN
SEPC
Sync
separator
HSYNOUT
VSYNOUT
Xtal IN1
Xtal OUT1
Xtal IN2
Xtal OUT2
CVOUTCVINCVCR
IC BLOCK DIAGRAMS AND DESCRIPTIONS
LC74763-9836 (On-Screen Display IC)
TERMINAL DESCRIPTION
Pin No.SymbolFunctionDescription
1V
2Xtal
3Xtal
4HSYNC
5Xtal
6Xtal
7VSYNC
8CSEnable input
9SINData inputSerial data input (hysteresis input). Pull-up resistor built in (metal option).
10SCLKClock inputClock input for serial data input (hysteresis input). Pull-up resistor built in (metal option).
11SECAM
12525/625
13NTSC/PAL
143.58/4.433.58/4.43 switch input/outputDuring output, functions as general output port or halftone output (command switch).
15RSTReset input
16CV
17V
18CV
19CV
20SYNC
21SEP
22V
23PD
24AMP
25AMP
26FCControl voltage inputAFC control voltage input
27VCO
28VCO
29SYNC
30V
SS
OUT1
OUT2
OUT
DD2
SS
OUT
DD1
GroundGround connection
IN1
Crystal oscillator connection
Horizontal synchronization Outputs the horizontal synchronization signal (AFC). The output polarity can be selected
OUT
output(metal option). Also functions as general output port (command switch).
IN2
Crystal oscillator connection
Vertical synchronization output
OUT
SECAM mode switch input/
output (command switch)
525/625 switch input/output
(command switch)
NTSC/PAL switch input/output
(command switch)
(command switch)Low = 3.58, high = 4.43
Video signal outputComposite video output
Power supply connectionPower supply connection for composite video signal level generation
Video signal inputComposite video input
IN
Video signal inputSECAM chroma signal input
CR
Sync separator circuit inputBuilt-in sync separator circuit video signal input
GroundGround connection
Control voltage outputAFC control voltage output
IN
AFC filter connectionFilter connection
OUT
IN
LC oscillator connectionVCO LC oscillator circuit coil and capacitor connection
OUT
External synchronization signal
DET
detection output
Power supply connectionPower supply connection (+5 V: digital system power supply)
Connection for the crystal and capacitor used to form the crystal oscillator that generates
the internal synchronization signal. The oscillator can be selected with a command switch.
Connection for the crystal and capacitor used to form the crystal oscillator that generates
the internal synchronization signal.
Outputs the vertical synchronization signal. The output polarity can be selected (metal
option). Also functions as general output port (command switch).
Enables/disables serial data input. Serial data is enabled when this pin is low (hysteresis
input). Pull-up resistor built in (metal option).
During input, switches between SECAM and other modes.
During output, functions as general output port or internal V output (command switch).
Low = other modes, high = SECAM mode
During input, switches between 525 scan lines and 625 scan lines.
During output, functions as general output port or character data output (command switch).
Low = 525 lines, high = 625 lines
Switches the color mode between NTSC and PAL.
During output, functions as general output port or frame data output (command switch).
Low = NTSC, high = PAL
Switch FSC between 3.58 MHz and 4.43 MHz.
System reset input pin, low is active (hysteresis input).
Pull-up resistor built in (metal option).
Outputs the exclusive NOR of the horizontal synchronization signal (AFC) and CSYNC (sync
separator). The output polarity can be selected (metal option). Also functions as general
output port (command switch).
DTR-5.6
IC BLOCK DIAGRAM AND TERMINAL DESCRIPTIONS
LA7106M (6ch AMP + Driver)
BLOCK DIAGRAM
DTR-5.6
VIN1+
NFB1
MUTE1
VIN2+
NFB2
-VCC1
VIN3+
NFB3
1
2
3
4
5
6
7
8
6dBDR
6dBDR
6dBDR
16
15
14
13
12
11
10
9
+VCC
VOUT1
GND
VOUT2
DR CTL
VOUT3
MUTE2
-VCC2
TRUTH TABLE
Pins 3 , 10
Through
H
L
Pin 12
150 ohm Drive
75 ohm DriveMute
IC BLOCK DIAGRAMS AND DESCRIPTIONS
NJM2595M(5-INPUT 3-OUTPUT VIDEO SWITCH)
BLOCK DIAGRAM
DTR-5.6
Vin1
Vin2
Vin3
Vin4
Vin5
13
9
7
5
3
20k
20k
20k
20k
S2
S3
SW2SW1V+
1016214
S4
S1
SW5
20k
20k
20k
S5
S6
S7
6dB
Amp
6dB
Amp
6dB
Amp
75ohms
Driver
75ohms
Driver
75ohms
Driver
1
15
11
Vout1
Vout2
Vout3
81264
V-SW3SW4GND
TRUTH TABLE
Control Signal vs. Output Signal (L=VCL, H=VCH, X=L or H)
VEE
L1
L2
L-COM1
L3
L4
L-COM2
L5
L6
L-COM3
L7
L-COM4
ST
VSS
Negative Voltage Supply
Analog switch input/output
Analog switch input/output
L1, L2, Common
Analog switch input/output
Analog switch input/output
L3, L4 common
Analog switch input/output
Analog switch input/output
L5, L6 Common
Analog switch input/output
L7 Common
Chip enable
GND
Pin No. Pin NameDescription
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CK
DATA
R-COM4
R7
R-COM3
R6
R5
R-COM2
R4
R3
R-COM1
R2
R1
VDD
Clock input
Data input
R7 Common
Analog switch input/output
R5, R6 Common
Analog switch input/output
Analog switch input/output
R3, R4 Common
Analog switch input/output
Analog switch input/output
R1, R2, Common
Analog switch input/output
Analog switch input/output
Positive voltage supply
IC BLOCK DIAGRAMS AND DESCRIPTIONS
NJW1157(8-Channel Electronic Volume with Input Selector)
Multi-Channel Input A
LAIN
RAIN
CAIN
LSAIN
RSAIN
LBAIN
RBAIN
SWAIN
L1IN
R1IN
L2IN
R2IN
L3IN
R3IN
2 Channel Input
L4IN
R4IN
L5IN
R5IN
L6IN
R6IN
L7IN
R7IN
L8IN
R8IN
L9IN
R9IN
L10IN
R10N
L11IN
R11IN
L12IN
R12IN
DCLA1 DCLA2
DCRA1 DCRA2
Att Gain
Att Gain
FL+
FL-
FR+
FR-
RBIN
LBIN
LSBIN
CBIN
LBBIN
RSBIN
SWBIN
RBBIN
RECA1L
RECA1R
RECA2L
Multi-channel
RECA2R
RECA3L
Amp
Gain
RECA3R
RECB1L
TONE
TONE
FIL2_L
FIL3_L
FIL4_L
RECB1R
BSW
FIL4_R
FIL1_L
RECB2L
FIL1_R
FIL2_R
FIL3_R
RECB2R
Supply
Voltage
uCOM
Interface
TSW
SSW
DTR-5.6
V+
GND
VLATCH
DATA
CLOCK
SW
L OUT
SW
ROUT
COUT
LSOUT
RSOUT
LBOUT
RBOUT
SWOUT
Input Selector
REC Out Selector
Multi-Channel Input B
IC BLOCK DIAGRAMS AND DESCRIPTIONS
NJW1157(8-Channel Electronic Volume with Input Selector)
HNo connect
4 P96/ANEX1/SOUT4OSDSDOHData output for on-screen display.
5 P95/ANEX0/CLK4OSDCLKCLK OSD IC Serial Communication Clock Output.
6 P94/DA1/TB4INOSDCSOHOSD IC Chip Select Output
7 P93/DA0/TB3INXMRSTOLReset output to XM microprocessor.
8 P92/TB2IN/SOUT3XMSDOOHSerial data output to XM microprocessor.
9 P91/TB1IN/SIN3XMSDIIHSerial data input from XM microprocessor.
10 P90/TB0IN/CLK3XMCLKOCLK Serial clock output to XM microprocessor.
11 P141~XMREQ1LSerial data chip request input from XM microprocessor.
12 P140~XMREQ2HSerial data chip request output to XM microprocessor.
13 BYTEBYTEExternal bus width select pin. Connects to the ground.
14 CNVSSCNVssProcessor mode select pin. Connects to the ground via resistor.
15 P87/XCIN~SDETILS Video input detection pin.
16 P86/XCOUT~SYNCILSync. detection pin.
17 ~RESET~RESETILReset input
18 XOUTXoutCeramic oscillator connection pin.
19 VSSVssPower supply Ground
20 XINXinCeramic oscillator connection pin.
21 VCC1Vcc1Power supply Vcc.
22 P85/~NMI~NMIILConnect the pull-up resistor.
23 P84/~INT2~VSYNCLVertical sync signal detection input.
24 P83/~INT1~REMINILRemote control input.
25 P82/~INT0POFFIHPower failure detection input pin.
26 P81/TA4IN/~U~ADCRSTOLMulti channel AD Reset output
27 P80/TA4OUT/UDIRINTIHDIR interrupt request detection pin.
28 P77/TA3IN~DIRCSOLDIR/CODEC chip select output pin.
29 P76/TA3OUT~DIRRSTOLDIR/CODEC reset output pin.
30 P75/TA2IN/~W~DSPFCSOLChip select output pin for DSP AB
31 P74/TA2OUT/W~DSPCSOLChip select output pin for DSP C
32 P73/~CTS2/~RTS2/TA1IN/~V~VMUTOLVideo mute control output pin
33 P72/CLK2/TA1OUT/VVDM_SCKOHClock output pin to Video microprocessor.
34 P71/RXD2/SCL2/TA0IN/TB5INVDM_SIIHData output pin to Video microprocessor.
35 P70/TXD2/SDA2/TA0OUTVDM_SOOHData input pin from Video microprocessor.
36 P67/TXD1/SDA1FTXDOHPort for writing Flash./RS232 port output.
37 Vcc1
38 P66/RXD1/SCL1FRXDIHPort for writing Flash./RS232 port input.
39 Vss
40 P65/CLK1FCLKOCLK Port for writing Flash.
41
P64/~CTS1/~RTS1/~CTS0/CLKS1
FBUSYOHPort for writing Flash.
42 P63/TXD0/SDA0PLLSDA/VCSDAI/OH
Tuner I2C bus data pin/Video Dec/Enc serial communication data output pin
43 P62/RXD0/SCL0PLLSCL/VCSCLOCLK
Tuner I2C bus clock output pin/Video Dec/Enc serial communication clock output pin
44 P61/CLK0~STEREOILFM stereo broadcast defection input
45 P60/~CTS0/~RTS0~TUNEDILTuner tuned detection input pin
46 P137~VDMRSTOHReset output pin to video microprocessor.
47 P136VDM_STBIHStrobe input pin from video microprocessor.
48 P135TXMUTEOHMuting output pin to video microprocessor.
49 P134RXMUTEIHMuting input pin from video microprocessor.
50 P57/~RDY/CLKOUT~DSPINTILInterrupt request detection pin for DSP C.
51 P56/ALE~DSPFINTILInterrupt request detection pin for DSP AB.
52 P55/~HOLDConnect to the ground.
53 P54/~HLDA~DSPRSTOLDSP reset output pin
54 P133MLTSELOHMulti Ch AD and HDMI(I2S) select pin
55 P132Z2VCLKOHSerial clock output pin for Zone2 Volume IC.
56 P131Z2VDATOHSerial data output pin for Zone2 Volume IC.
57 P130Z2VMUTOHMute control output pin for Zone2 Volume IC.
58 P53/BCLKVOLSTBOHStrobe output for Volume
59 P52/~RDVOLCLKOCLK Serial clock output for Volume
60 P51/~WRH/~BHEVOLDATOHSerial data output for Volume
61 P50/~WRL/~WR~FCEIHPort for writing Flash.
62 P127~VCRSTOLVideo Dec/Enc reset control pin
63 P126
64 P125
DTR-5.6
I
O
I
Power supply
Ground
MICROPROCESSOR TERMINAL DESCRIPTIONS
No. Pin Name FunctionI/O Act. Description
65 P47/~CS3Z2MUTOHZone2 Out mute control pin
66 P46/~CS2SBZ2MUTOHSurround back/Zone2 mute control.
67 P45/~CS1AMUTOHAudio mute control pin
68 P44/~CS0SPRLFOHFront speaker relay control pin
69 P43/A19SPRLCSOHCenter/Surround back speaker relay control pin.
70 P42/A18SPRLSBOHSurround back speaker relay control pin.
71 P41/A17SPRLZ2OHZone2 speaker relay control pin
72 P40/A16DIGSDOOHSerial communication data output pin for DIR/CODEC/DSP.
73 P37/A15DIGSDIIHSerial communication data input pin for DIR/CODEC/DSP.
74 P36/A14DIGCLKOCLK Serial communication clock output pin for DIR/CODEC/DSP.
75 P35/A13DSPBUSYIHBusy detection pin for DSP C.
76 P34/A12DGSW1OHDIGITAL AUDIO MCK select 1. Not used.
77 P33/A11DGSW2OHDIGITAL AUDIO MCK select 2. Not used.
78 P32/A10VPOWEROHPower control output for video section
79 P31/A09APOWEROHPower source control output
80 P124FANHOLFan speed control pin. High: Low speed Low: High speed
81 P123FANCTRLOLFan operation control pin. High: Stop Low: Rotation
82 P122TRGAOH12V trigger output A
83 P121TRGBOH12V trigger output B
84 P120TRGZ2OH12V trigger output ZONE2
85 VCC2Vcc2Power supply
86 P30/A8(/-/D7)SEC1HOHVoltage select control pin
87 VSSVssGround
88 P27/AN27/A7(/D7/D6)VOLHIA/D Signal level detection circuit
89 P26/AN26/A6(/D6/D5)THERMALIA/D Thermal detection pin
90 P25/AN25/A5(/D5/D4)PROTECTIHProtection circuit detection circuit
91 P24/AN24/A4(/D4/D3)FSWSTBOHStrobe output pin for function switch
92 P23/AN23/A3(/D3/D2)FSWCLKOHSerial clock output pin for function switch
93 P22/AN22/A2(/D2/D1)FSWSDOOHSerial data output pin for function switch
94 P21/AN21/A1(/D1/D0)RDSDATIHSerial data input pin for RDS
95 P20/AN20/A0(/D0/-)RDSSIGIHDemodulator data input pin for RDS
96 P17/D15/~INT5SYSINIHRI input pin
97 P16/D14/~INT4~IRINILIRIN remote control input pin
98 P15/D13/~INT3~RDSCLK/POFF2 ILSerial clock input pin for RDS
99 P14/D12~SYSOUTOLRI output pin
100 P13/D11LEDPUREOHPure Audio LED control output pin
101 P12/D10
102 P11/D9LEDSTBYOHSTANDBY LED control pin
103 P10/D8HPRLOHHeadphone relay control pin
104 P07/AN07/D7HPDETIHHeadphone detection input
105 P06/AN06/D6~MICDETILMicrophone detection input
106 P05/AN05/D5VOLBI
Before Idling current adjustment, turn the trimming resistors R6040 to R6046 to counter-clockwise.
Connect the DC voltmeter at the sockets P6080 to P6086 via the carbon resistors 100 ohm 1/4W.
DC voltmeter
100 ohm
1/4watts
After turn POWER to ON, adjust the trimming resistors R6040, R6041 and R6042 so that the reading of
voltmeter becomes 2.5 mV. (Front and center channels)
Adjust the trimming resistors R6043, R6044, R6045 and R6046 so that the reading of
voltmeter becomes 1.5 mV. (Surround and surround back channels)
After adjustment, attach the top cover.
Confirm the voltage of points above after about five minutes.
Front and center channels
When less than 9.0 mV, readjust the resistors above so that the voltage becomes 9.0 mV.
When 9.0 mV to 11.0 mV, you are not necessary to adjust.
When more than 11.0 mV, readjust the resistors above so that the voltage becomes 11.0 mV.
Surround and surround back channels
When less than 6.0 mV, readjust the resistors above so that the voltage becomes 6.0 mV.
When 6.0 mV to 8.0 mV, you are not necessary to adjust.
When more than 6.0 mV, readjust the resistors above so that the voltage becomes 8.0 mV.
Note: No load and No signal
Jig terminal
Test point
ID+
ID-
DTR-5.6
NAAF-8678
JL6603A
R6041
P6081
U06
P5004B
P6002A
P6082
R6042
P3105A
P6003A
P6083
P3104A
P6004A
R6043
P6084
R6046
JL6006B
P6086
NAAF-8682
JL6200B
U064
Surround
back
amplifier
P6952A
P6000A
JL6600A
P6080
P6001A
R6040
Confirmation of protection circuit
1. Confirmation of operation of speaker relay
Confirm that the speaker relays turn ON approximate 5 seconds after the power switch is turned ON.
Confirm that the speaker relays turn OFF immediately after the power switch is turned OFF.
2. Confirmation of DC detection circuit
Press and hold down CD button, then press STANDBY/ON button to set the unit to "Test- 1".
After "Test- 1" on the FL tube light on, press DVD button to set the unit to "Test- 1-00".
Apply DC 1.5 to 3.5V to the MULTI-CH INPUT terminal with no load.
Confirm that the speaker relay turns OFF.
Apply DC -1.5 to -3.5 V to the MULTI-CH INPUT terminal with no load.
Confirm that the speaker relay turns OFF.
Caution: Don't apply DC voltage more than 1 sec..
P3103A
P6005A
R6044
P6085
P3101A
P3102A
R6045
JL6200A
ADJUSTMENT AND CONFIRMATION PROCEDURES 2
3. Confirmation of Current detection circuit
Set the unit to "Test- 1-00".
Connect the differentiating circuit and apply the 50Hz square signal to MULTI CHANNEL INPUT terminal
of each channel.
Adjust the attenuator or Volume so that the output level becomes 35V p-p.
Confirm that the speaker relay does not turn OFF when a 3.0 ohm load is connected.
Confirm that the speaker relay turns OFF when a 1.0 ohm load is connected.
MULTI
CR
OSCILLATOR
50Hz
SQUARE
INPUT
3.3k
DIFFERENTIATING
CIRCUIT
0.1 F
ATTENUATOR
1SS133x6
CHANNEL
INPUT
3.3k
SPEAKER
TERMINAL
UNIT
OSCILLOSCOPE
DTR-5.6
OUTPUT
10k
0.01 F
GND
Differentiating Circuit
Test Mode
1. Turn POWER button on.
2. Press and hold down CD button, then press STANDBY/ON button.
3. After "Test - " on the FL tube is displayed, press CD button to set the unit to the test mode of FL tube.
Note: DVD :Test- 1 VIDEO 1 :Test- 2
VIDEO 2 :Test- 3 VIDEO 3:Test- 4
Change of item
Tone + ....UP
Tone - ......DOWN
Check of unit by test mode
Voltage detection circuit
Set the unit to "Test- 4-21".
The microprocessor checks the output voltage of all channels automatically
When the output voltage is abnormal, "Protect NG" is displayed on FL tube.
When the voltage of all channels is normal, "Test- 4-35" is displayed on FL tube.
4-21:FL 4-22:FR 4-23:C 4-24:SL 4-25:SR 4-26:SBL 4-27:SBR
Current detection circuit
Set the unit to "Test- 4-35".
Connect the hollow resistor 3 ohm across the speaker terminal.
Check that the speaker relay turn On.
When connect the hollow resistor 1.5 ohm, check that the speaker relay turn Off.
Note: Check the all channels.
Test- X-YZ
35Vp-p
Item
ADJUSTMENT AND CONFIRMATION PROCEDURES 3
FL tube
Press and hold down CD button, then press STANDBY/ON button.
After "Test - " on the FL tube is displayed, press CD button to set the unit to the test mode of FL tube.
UP
direction
DOWN
direction
All segments
light on.
Press STANDBY button
to finish the test mode of FL tube.
DTR-5.6
TONE +
"FEDCBA987654321"
light on.
The segments of even
number light on .
The segments of odd
number light on .
"Model,Destination"
light on.
TONE -
Confirmation of voltage sensor and thermal protector
1. Set the unit to "Test- 4-36 " and "4-37".
Confirm that FM STEREO is displayed and Speaker relays RL6901 and RL6902 turn Off.
2. Set the unit to "Test- 4-38 ".
Confirm that FM STEREO is displayed and Speaker relays RL6901 and RL6902 turn Off.
Confirmation of cooling fan
1. Confirm that the fan does not rotate when no input signal.
2. Set the unit to "Test- 4-36 " and "4-37".
Confirm that the fan rotates at a low speed.
3. Set the unit to "Test- 4-39 ".
Confirm that the fan rotates at a high speed.
FW UPGRADE
How to check version
+
DISPLAY
Ver.1.08/05Y29a
Within 3 sec.
DSP V er .:
Within 3 sec.
DSP F/W Update
SETUP
ENTER
STANDBY/ON
FL tube
FL tube
F
L tube
1. Hold down "Display" and then press "Standby" button to show Main version.
2. Press "Setup" within 3 seconds.
When you press "Setup", another version of program is shown.
Front Display shows each version of programs in the following order:
DSP Ver.
HDM Ver. (HDMI) -- blank
Tun Ver. (XM Radio) -- blank except MDD
3. DSP Ver. is not shown easily.
To check the version of DSP FW,
3-1 When "DSP Ver. " is shown, press "Enter" within 3 seconds.
"DSP F/W Update" will be shown.
3-2 Press any input selector button to exit "DSP F/W Update".
3-3 Hold down "Display" and then press "Standby" button to show Main version.
3-4 Press "Setup" within 3 seconds.
Main FW and DSP FW
1) If both FWs need to be upgraded, DSP FW Upgrade should
DSP V er .:05Y28a
Within 3 sec.
FL tube
be done first.
2) If either of Main Board or DSP Board is replaced, certain
combinations of Main-DSP FW versions do not allow you to
upgrade DSP FW.
SETUP
In that case, rewrite a compatible version of Main FW,
upgrade DSP FW, and then upgrade Main FW.
DSP: Ver.05723a - Main: Ver. 1.04/05921a,1.06/05X06b,
HDM V er .:
Within 3 sec.
FL tube
DSP: Ver. 05Y28a - Main: Ver. 1.08/05Y25a
DTR-5.6
Selector key
SETUP
TUN V er .:05807A
FL tube
FW UPGRADE
DSP/Video FW Upgrade
0. Unzip “firmware.zip” and store the unzipped folder
& files and "Update.exe" as below.
\Updater_SR803\Update.exe
\firmware\SR803\fdist.fdf
\FW803.dcf
\DSP7803_05Y28A.s28
\05X04B_video803.hex
You can name the uppermost folder "\Updater_SR803" as you like.
1. Hold down "Display" and then press "Standby" button
to show Main version.
2. Press "Setup" within 3 seconds.
3. Press "Enter" while DSP version is shown to enter Setup mode.
"DSP F/W Update" will be shown.
4. Connect your unit and PC with Flashwriter Jig and put the unit
into Standby mode.
5. Double-click "Update.exe".
If you get the message like below, FW files are not properly stored.
Check the path.
6. Click "DSP Updade" .
DSP
DTR-5.6
PC
(Personal computer)
Flashwriter Jig
0JFLASH
RS232C
0JFLASHEX
FFC
P702
NAAR-8661
7. Update completes when Front Display stops showing the progress.
Note: Even if you try to check the DSP version, you might not be able
to get is due to the wrong combination of DSP and Main.
In this case, check the version after upgrading Main FW.
Main FW Upgrade
Write the latest main program using FlashSta.exe.
P A CKING VIEW
DTR-5.6
Accessary bag
A845
A843
A606
A607
A605
A841
A851
A822
A823
A826
A609
A603
A827
U12
A831
A846
Put the label A801 between
page 2 and page 3 of
instruction manual E.
Left
Left
Left
Left
Front
Front
Front
Zone 2
Zone 2
/
/
SP-B
SP-B
Zone 2
Zone 2
/
/
SP-B
Left
Front
Left
Front
Front
Left
SP-B
Left
1
Speaker Cable
P901
A801
Left
Left
Front
Right
Right
Right
Right
Right
Zone 2
Zone 2
/
/
Surround
Surround
Surround
SP-B
SP-B
Zone 2
Zone 2
/
/
SP-B
Right
Front
Right
Surround
Right
Surround
Left
Surround
Left
Right
SP-B
Right
2
Left
Left
Left
Left
Right
Right
Right
Right
Right
Center
Center
Zone 2
Zone 2
Zone 2
Zone 2
Surround
Surround Back
Surround Back
Surround Back
Surround Back
Zone 2
Right
Zone 2
Left
Center
Zone 2
Right
Zone 2
Left
Surround Back
Right
Surround Back
Left
Surround
Right
Center
Surround Back
Right
Surround Back
Left
3
A607
A601
A601
A610
A601
A610
A612
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