OMRON C20P, C28P, C40P, C60P User Manual

Cat. No. W168-E1-1B

SYSMAC
Programmable Controllers

C20P/C28P/C40P/C60P

P–type Programmable Controllers

OPERATION MANUAL

Revised January 1997

Notice:

OMRON products are manufactured for use according to proper procedures by a qualified operator
and only for the purposes described in this manual.

The following conventions are used to indicate and classify precautions in this manual. Always heed
the information provided with them. Failure to heed precautions can result in injury to people or dam­age to the product.

DANGER! Indicates information that, if not heeded, is likely to result in loss of life or serious injury.

!

WARNING Indicates information that, if not heeded, could possibly result in loss of life or serious injury .

!

Caution Indicates information that, if not heeded, could result in relatively serious or minor injury,

!

damage to the product, or faulty operation.

OMRON Product References

All OMRON products are capitalized in this manual. The word “Unit” is also capitalized when it refers
to an OMRON product, regardless of whether or not it appears in the proper name of the product.

The abbreviation “Ch,” which appears in some displays and on some OMRON products, often means
“word” and is abbreviated “Wd” in documentation in this sense.

The abbreviation “PC” means Programmable Controller and is not used as an abbreviation for any­thing else.

Visual Aids

The following headings appear in the left column of the manual to help you locate different types of
information.

 OMRON, 1989

All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any
form, or by any means, mechanical, electronic, photocopying, recording, or otherwise, without the prior written permis­sion of OMRON.

No patent liability is assumed with respect to the use of the information contained herein. Moreover, because OMRON is
constantly striving to improve its high–quality products, the information contained in this manual is subject to change
without notice. Every precaution has been taken in the preparation of this manual. Nevertheless, OMRON assumes no
responsibility for errors or omissions. Neither is any liability assumed for damages resulting from the use of the informa­tion contained in this publication.

Note Indicates information of particular interest for efficient and convenient operation

of the product.

1, 2, 3...

1. Indicates lists of one sort or another, such as procedures, checklists, etc.

ii

About this Manual:

The OMRON P-type Programmable Controllers offer an effective way to automate processing. man­ufacturing, assembly, packaging, and many other processes can be automated to save time and
money. Distributed control systems can also be designed to allow centralized monitoring and supervi­sion of several separate controlled systems. Monitoring and supervising can be done through a host
computer, connecting the controlled system to a data bank. It is thus possible to have adjustments in
system operation made automatically to compensate for requirement changes.

The P-type Units can utilize a number of additional Units including dedicated Special I/O Units that
can be used for specific tacks and Link Units that can be used to build more highly integrated sys­tems.

The P-types are equipped with large programming instruction sets, data areas, and other features to
control processing directly. Programming utilizes ladder-diagram programming methods, which are
described in detail for those unfamiliar with them.

This manual describes the characteristics and abilities of the P-types, programming operations and
instructions, and other aspects of operation and preparation that demand attention. Before attempting
to operate the PC, thoroughly familiarize yourself with the information contained herein. Hardware
information is provided in detail in the
combination with this manual is provided at the end of

Installation Guide

. A table of other manuals that can be used in

Section 1 Background

.

Section 1 Precautions

The information contained in this section is important for the safe and reliable application of
the PC. You must read this section and understand the information contained before attempt­ing to set up or operate a PC system.

Section 2 Background

programming. It also provides an overview of the process of programming and operating a PC and
explains basic terminology used with OMRON PCs. Descriptions of peripheral devices used with the
P-types and a table of other manuals available to use with this manual for special PC applications are
also provided.

Section 3 Hardware Considerations

scribes the indicators that are referred to in other sections of this manual.

Section 4 Memory Areas

information provided there to aid in programming. It also explains how I/O is managed in memory and
how bits in memory correspond to specific I/O points.

Section 5 Programming

ments that make up the ‘ladder’ part of a ladder-diagram program and explaining how execution of
this program is controlled.

ection 6 Instruction Set

S

gramming.

Section 7 Program Execution Timing

and tells how to coordinate inputs and outputs so that they occur at the proper times.

provides general precautions for using the Programmable Controller (PC).

explains the background and some of the basic terms used in ladder-diagram

explains basic aspects of the overall PC configuration and de-

takes a look at the way memory is divided and allocated and explains the

explains the basics of ladder-diagram programming, looking at the ele-

then goes on to describe individually all of the instructions used in pro-

explains the scanning process used to execute the program

Section 8 Program Input, Debugging, and Execution

into mnemonic code so that it can be input into the CPU through a Programming Console. This sec­tion also provides the Programming Console procedures used to input and debug the program and to
monitor and control system operation.

Section 9 Troubleshooting

ducing system down time. Information in this section is also necessary when debugging a program.

Appendice

The
tables of instructions and Programming Console operations, and other information helpful in PC op­eration.

s provide tables of standard OMRON products available for the P-types, reference

provides information on system error indications and other means of re-

explains how to convert a ladder diagram

iii

TABLE OF CONTENTS

PRECAUTIONS ix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 Intended Audience x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 General Precautions x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Safety Precautions x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Operating Environment Precautions x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Application Precautions xi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SECTION 1 – Background 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–1 Introduction 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–2 Relay Circuits: The Roots of PC Logic 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–3 PC Terminology 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–4 OMRON Product Terminology 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–5 Overview of PC Operation 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–6 Peripheral Devices 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–7 Available Manuals 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SECTION 2 – Hardware Considerations 9 . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–1 Introduction 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 Indicators 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 PC Configuration 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SECTION 3 – Memory Areas 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 Introduction 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 Data Area Structure 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–3 IR Area 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4 SR Area 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4–1 Battery Alarm Flag 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4–2 Scan Time Error Flag 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4–3 High-speed Drum Counter Reset 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4–4 Clock Pulse Bits 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4–5 Error Flag ER 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4–6 Always OFF and Always ON Flags 25 . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4–7 First Scan Flag 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4–8 Arithmetic Flags 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–5 DM Area 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–6 HR Area 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–7 TC Area 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–8 TR Area 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SECTION 4 – Programming 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–1 Introduction 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–2 Instruction Terminology 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–3 The Ladder Diagram 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–3–1 Basic Terms 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–3–2 Ladder Instructions 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–3–3 Logic Block Instructions 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–3–4 Branching Instruction Lines 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–3–5 Jumps 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

v

Table of contents

4–4 Controlling Bit Status 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–4–1 OUT and OUT NOT 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–4–2 Differentiate Up and Differentiate Down 41 . . . . . . . . . . . . . . . . . . . . . .

4–4–3 Keep 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–4–4 Self-maintaining Bits 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–5 The End Instruction 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–6 Programming Precautions 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–7 Program Execution 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SECTION 5 – Instruction Set 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–1 Introduction 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–2 Notation 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–3 Instruction Format 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–4 Data Areas, Definer Values, and Flags 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–5 Ladder Diagram Instructions 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–5–1 Load, Load NOT, AND, AND NOT, OR, and OR NOT 48 . . . . . . . . . .

5–5–2 AND Load and OR Load 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–6 Bit Control Instructions 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–6–1 Output and Output NOT – OUT and OUT NOT 49 . . . . . . . . . . . . . . . . .

5–6–2 Differentiate Up and Down – DIFU(13) and DIFD(14) 50 . . . . . . . . . . .

5–6–3 Keep – KEEP(11) 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–7 Interlock and Interlock Clear – IL(02) and ILC(03) 53 . . . . . . . . . . . . . . . . . . . . . .

5–8 Jump and Jump End – JMP(04) and JME(05) 55 . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–9 End – END(01) 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–10 No Operation – NOP(00) 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–11 Timer and Counter Instructions 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–11–1 Timer – TIM 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–11–2 High-speed Timer – TIMH(15) 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–11–3 Analog Timer Unit 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–11–4 Counter – CNT 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–11–5 Reversible Counter – CNTR(12) 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–11–6 High-speed Counter – HDM(98) 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–12 Data Shifting 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–12–1 Shift Register – SFT(10) 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–12–2 Word Shift – WSFT(16) 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–13 Data Movement 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–13–1 Move – MOV(21) 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–13–2 Move NOT – MVN(22) 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–14 Data Compare – CMP(20) 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–15 Data Conversion 84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–15–1 BCD to Binary – BIN(23) 84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–15–2 Binary to BCD – BCD(24) 85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–15–3 4-to-16 Decoder – MLPX(76) 85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–15–4 16-to-4 Encoder – DMPX(77) 87 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–16 BCD Calculations 89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–16–1 BCD Add – ADD(30) 90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–16–2 BCD Subtract – SUB(31) 92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–16–3 Set Carry – STC(40) 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–16–4 Clear Carry – CLC(41) 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi

SECTION 6 – Program Execution Timing 95 . . . . . . . . . . . . . . . . . . . . . . . . . .

6–1 Introduction 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–2 Scan Time 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–3 Calculating Scan Time 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–3–1 Single PC Unit 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–3–2 PC with Additional Units 99 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–4 Instruction Execution Times 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–5 I/O Response Time 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table of contents

SECTION 7 – Program Input, Debugging and Execution 105 . . . . . . . . . . . . .

7–1 Introduction 106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–2 Converting to Mnemonic Code 106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–2–1 Program Memory Structure 106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–2–2 Ladder Instructions 106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–2–3 Logic Block Instructions 107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–2–4 Coding Other Instructions 116 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–3 The Programming Console 121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–3–1 The Keyboard 121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–3–2 PC Modes 123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–4 Preparation for Operation 124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–4–1 Entering the Password 125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–4–2 Clearing Memory 126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–5 Inputting, Modifying, and Checking the Program 128 . . . . . . . . . . . . . . . . . . . . . . . .

7–5–1 Setting and Reading from Program Memory Address 128 . . . . . . . . . . . .

7–5–2 Inputting or Overwriting Programs 129 . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–5–3 Checking the Program 132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–5–4 Displaying the Scan Time 133 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–5–5 Program Searches 134 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–5–6 Inserting and Deleting Instructions 136 . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–6 Program Backup and Restore Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–6–1Saving Program Memory Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–6–2Restoring or Comparing Program Memory Data. . . . . . . . . . . . . . . .

7–7 Debugging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–8 Monitoring Operation and Modifying Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–8–1Bit/Digit Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–8–2Force Set/Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–8–3Hexadecimal/BCD Data Modification. . . . . . . . . . . . . . . . . . . . . . . .

7–8–4Changing Timer/Counter SV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

140

140

141
143
144

145

148

151

151

SECTION 8 – Troubleshooting 153 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–1 Introduction 154 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–2 Reading and Clearing Errors and Messages 154 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–3 Error Messages 154 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–4 Error Flags 156 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix 157 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A – Standard Models 157 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B – Programming Instructions 165 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C – Programming Console Operations 171 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D – Error and Arithmetic Flag Operation 181 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

E – Binary–Hexadecimal–Decimal Table 183 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F – Word Assignment Recording Sheets 185 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

G – Program Coding Sheet 191 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Glossary 193 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Index 207 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vii

PRECAUTIONS

This section provides general precautions for using the Programmable Controller (PC) and related devices.

The information contained in this section is important for the safe and reliable application of the PC. You must read
this section and understand the information contained before attempting to set up or operate a PC system.

1 Intended Audience x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 General Precautions x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Safety Precautions x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Operating Environment Precautions x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Application Precautions xi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ix

Operating Environment Precautions

1 Intended Audience

This manual is intended for the following personnel, who must also have knowl­edge of electrical systems (an electrical engineer or the equivalent).

• Personnel in charge of installing FA systems.

• Personnel in charge of designing FA systems.

• Personnel in charge of managing FA systems and facilities.

2 General Precautions

The user must operate the product according to the performance specifications
described in the operation manuals.

Before using the product under conditions which are not described in the manual
or applying the product to nuclear control systems, railroad systems, aviation
systems, vehicles, combustion systems, medical equipment, amusement
machines, safety equipment, and other systems, machines, and equipment that
may have a serious influence on lives and property if used improperly, consult
your OMRON representative.

Make sure that the ratings and performance characteristics of the product are
sufficient for the systems, machines, and equipment, and be sure to provide the
systems, machines, and equipment with double safety mechanisms.

This manual provides information for programming and operating OMRON PCs.
Be sure to read this manual before attempting to use the software and keep this
manual close at hand for reference during operation.

4

WARNING It is extreme important that a PC and all PC Units be used for the specified

!

purpose and under the specified conditions, especially in applications that can
directly or indirectly affect human life. You must consult with your OMRON
representative before applying a PC System to the abovementioned
applications.

3 Safety Precautions

WARNING Never attempt to disassemble any Units while power is being supplied. Doing so

!

may result in serious electrical shock or electrocution.

WARNING Never touch any of the terminals while power is being supplied. Doing so may

!

result in serious electrical shock or electrocution.

4 Operating Environment Precautions

Do not operate the control system in the following places.

• Where the PC is exposed to direct sunlight.

• Where the ambient temperature is below 0°C or over 55°C.

• Where the PC may be affected by condensation due to radical temperature

changes.

• Where the ambient humidity is below 10% or over 90%.

• Where there is any corrosive or inflammable gas.

• Where there is excessive dust, saline air, or metal powder.

• Where the PC is affected by vibration or shock.

• Where any water, oil, or chemical may splash on the PC.

x

Application Precautions

Caution The operating environment of the PC System can have a large effect on the lon-

!

gevity and reliability of the system. Improper operating environments can lead to
malfunction, failure, and other unforeseeable problems with the PC System. Be
sure that the operating environment is within the specified conditions at installa­tion and remains within the specified conditions during the life of the system.

5 Application Precautions

Observe the following precautions when using the PC.

WARNING Failure to abide by the following precautions could lead to serious or possibly

!

fatal injury. Always heed these precautions.

• Always ground the system to 100 Ω or less when installing the system to pro-
tect against electrical shock.

• Always turn off the power supply to the PC before attempting any of the follow­ing. Performing any of the following with the power supply turned on may lead
to electrical shock:

• Mounting o r removing any Units (e.g., I/O Units, CPU Unit, etc.) or memory
cassettes.

• Assembling any devices or racks.

• Connecting or disconnecting any cables or wiring.

5

Caution Failure to abide by the following precautions could lead to faulty operation or the

!

PC or the system or could damage the PC or PC Units. Always heed these pre­cautions.

• Use the Units only with the power supplies and voltages specified in the opera­tion manuals. Other power supplies and voltages may damage the Units.

• Take measures to stabilize the power supply to conform to the rated supply if it
is not stable.

• Provide circuit breakers and other safety measures to provide protection
against shorts in external wiring.

• Do not apply voltages exceeding the rated input voltage to Input Units. The
Input Units may be destroyed.

• Do not apply voltages exceeding the maximum switching capacity to Output
Units. The Output Units may be destroyed.

• Always disconnect the LG terminal when performing withstand voltage tests.

• Install all Units according to instructions in the operation manuals. Improper

installation may cause faulty operation.

• Provide proper shielding when installing in the following locations:

• Locations subject to static electricity or other sources of noise.

• Locations subject to strong electromagnetic fields.

• Locations subject to possible exposure to radiation.

• Locations near to power supply lines.

• Be sure to tighten Backplane screws, terminal screws, and cable connector

screws securely.

• Do not attempt to take any Units apart, to repair any Units, or to modify any
Units in any way.

Caution The following precautions are necessary to ensure the general safety of the sys-

!

tem. Always heed these precautions.

• Provide double safety mechanisms to handle incorrect signals that can be
generated by broken signal lines or momentary power interruptions.

• Provide external interlock circuits, limit circuits, and other safety circuits in
addition to any provided within the PC to ensure safety.

xi

SECTION 1
Background

1–1 Introduction 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–2 Relay Circuits: The Roots of PC Logic 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–3 PC Terminology 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–4 OMRON Product Terminology 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–5 Overview of PC Operation 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–6 Peripheral Devices 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–7 Available Manuals 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1

Relay Circuits: The Roots of PC Logic Section 1–2

1–1 Introduction

A Programmable Controller (PC) is basically a central processing unit (CPU)
containing a program and connected to input and output (I/O) devices (I/O
Devices). The program controls the PC so that when an input signal from an
input device turns ON, the appropriate response is made. The response nor­mally involves turning ON an output signal to some sort of output device. The
input devices could be photoelectric sensors, pushbuttons on control panels,
limit switches, or any other device that can produce a signal that can be input
into the PC. The output devices could be solenoids, switches activating indi­cator lamps, relays turning on motors, or any other devices that can be acti­vated by signals output from the PC.

For example, a sensor detecting a product passing by turns ON an input to
the PC. The PC responds by turning ON an output that activates a pusher
that pushes the product onto another conveyor for further processing. An­other sensor, positioned higher than the first, turns ON a different input to
indicate that the product is too tall. The PC responds by turning on another
pusher positioned before the pusher mentioned above to push the too-tall
product into a rejection box.

Although this example involves only two inputs and two outputs, it is typical of
the type of control operation that PCs can achieve. Actually even this exam­ple is much more complex than it may at first appear because of the timing
that would be required, i.e., “How does the PC know when to activate each
pusher?” Much more complicated operations, however, are also possible.
The problem is how to get the desired control signals from available inputs at
appropriate times.

Desired control sequences are input to the P-type PCs using a form of PC
logic called ladder-diagram programming. This manual is written to explain
ladder-diagram programming and to prepare the reader to program and oper­ate the P-type PCs.

1–2 Relay Circuits: The Roots of PC Logic

PCs historically originate in relay-based control systems. And although the
integrated circuits and internal logic of the PC have taken the place of the
discrete relays, timers, counters, and other such devices, actual PC opera­tion proceeds as if those discrete devices were still in place. PC control, how­ever, also provides computer capabilities and consistency to achieve a great
deal more flexibility and reliability than is possible with relays.

The symbols and other control concepts used to describe PC operation also
come from relay-based control and form the basis of the ladder-diagram pro­gramming method. Most of the terms used to describe these symbols and
concepts, however, originated as computer terminology.

Relay vs. PC Terminology

The terminology used throughout this manual is somewhat different from re­lay terminology, but the concepts are the same. The following table shows
the relationship between relay terms and the PC terms used for OMRON
PCs.

Relay term PC equivalent

contact input or condition
coil output or work bit
NO relay condition
NC relay inverse condition

2

PC Terminology Section 1–3

Actually there is not a total equivalence between these terms, because the
term condition is used only to describe ladder diagram programs in general
and is specifically equivalent to one of certain basic instructions. The terms
input and output are not used in programming per se, except in reference to
I/O bits that are assigned to input and output signals coming into and leaving
the PC. Conditions and inverse conditions are explained in

Diagram

.

4–3 The Ladder

1–3 PC Terminology

PC

Inputs and Outputs

Although also provided in the
ing terms are crucial to understanding PC operation and are thus explained
here as well.

When we refer to the PC, we are generally talking about the CPU and all of
the Units directly controlled by it through the program. This does not include
the I/O devices connected to PC inputs and outputs.

If you are not familiar with the terms used above to describe a PC, refer to

Hardware Considerations

A device connected to the PC that sends a signal to the PC is called an input
device; the signal it sends is called an input signal. A signal enters the PC
through terminals or through pins on a connector on a Unit. The place where
a signal enters the PC is called an input point. This input point is allocated a
location in memory that reflects its status, i.e., either ON or OFF. This mem­ory location is called an input bit. The CPU in its normal processing cycle
monitors the status of all input points and turns ON and OFF corresponding
input bits accordingly.

There are also output bits in memory that are allocated to output points on
Units through which output signals are sent to output devices, i.e., an out­put bit is turned ON to send a signal to an output device through an output
point. The CPU periodically turns output points ON and OFF according to the
status of the output bits.

Glossary

for explanations.

at the back of this manual, the follow-

2

Controlled System and
Control System

These terms are used when describing different aspects of PC operation.
When programming, one is concerned with what information is held in mem­ory, and so I/O bits are referred to. When describing the Units that connect
the PC to the controlled system and the places on these Units where signals
enter and leave the PC, I/O points are referred to. When wiring these I/O
points, the physical counterparts of the I/O points, either terminals or connec­tor pins, are referred to. When describing the signals that enter or leave the
system, reference is made to input signals and output signals, or sometimes
just inputs and outputs.

The Control System includes the PC and all I/O devices it uses to control an
external system. A sensor that provides information to achieve control is an
input device that is clearly part of the Control System. The controlled system
is the external system that is being controlled by the PC program through
these I/O devices. I/O devices can sometimes be considered part of the con­trolled system, e.g., a motor used to drive a conveyor belt.

3

Overview of PC Operation Section 1–5

1–4 OMRON Product Terminology

OMRON products are divided into several functional groups that have ge­neric names. A
The term Unit is used to refer to all OMRON PC products, depending on the
context.

The largest group of OMRON products is I/O Units. I/O Units come in a vari­ety of point quantities and specifications.

Special I/O Units are dedicated Units that are designed to meet specific
needs. These include Analog Timer Units and Analog I/O Units.

Link Units are used to create Link Systems that link more than one PC or
link a single PC to remote I/O points. Link Units include I/O Link Units that
are used to connect P-type PCs to Remote I/O Systems controlled by a larg­er PC (e.g. C1000H) and Host Link Units.

Other product groups include Programming Devices, Peripheral Devices,
and DIN Rail Products.

ppendix A Standard Models

list products by these groups.

1–5 Overview of PC Operation

The following are the basic steps involved in programming and operating a
P-type PC. Assuming you have already purchased one or more of these
PCs, you must have a reasonable idea of the required information for steps
one and two, which are discussed briefly below. This manual is written to ex­plain steps three through six, eight, and nine. The section(s) of this manual
that provide relevant information are listed with each of these steps.

1, 2, 3...

1. Determine what the controlled system must do, in what order, and at

what times.

2. Determine what Units will be required. Refer to the

a Link System is required, refer to the required

3. On paper, assign all input and output devices to I/O points on Units and

determine which I/O bits will be allocated to each. If the PC includes
Special I/O Units or Link Systems, refer to the individual

or

Manuals
Memory Areas)

4. Using relay ladder symbols, write a program that represents the se-

quence of required operations and their inter-relationships. Be sure to
also program appropriate responses for all possible emergency situ­ations. (

Program Execution Timing)

5. Input the program and all required operating parameters into the PC.

Section 7 Program Input, Debugging, and Execution

(

6. Debug the program, first to eliminate any syntax errors and then to elim-

inate execution errors. (

cution

7. Wire the PC to the controlled system. This step can actually be started

as soon as step 3 has been completed. Refer to the
and to
Units.

8. Test the program in an actual control situation and fine tune it if required.

Section 7 Program Input, Debugging, and Execution

(

Troubleshooting

9. Record two copies of the finished program on masters and store them

safely in different locations. (

Execution

System Manuals

Section 4 Programming, Section 5 Instruction Set, Section 6

and

Section 8 Troubleshooting

Operation Manuals

)

)

for details on I/O bit allocation. (

Section 7 Program Input, Debugging, and Exe-

)

and

System Manuals

Section 7 Program Input, Debugging, and

Installation Guide

System Manual(s)

Operation

Section 3

)

Installation Guide

for details on individual

and

Section 8

. If

.

4

Overview of PC Operation Section 1–5

Control System Design

Input/Output Requirements

Sequence, Timing, and
Relationships

Designing the Control System is the first step in automating any process. A
PC can be programmed and operated only after the overall Control System is
fully understood. Designing the Control System requires a thorough under­standing of the system that is to be controlled. The first step in designing a
Control System is thus determining the requirements of the controlled sys­tem.

The first thing that must be assessed is the number of input and output points
that the controlled system will require. This is done by identifying each device
that is to send an input signal to the PC or which is to receive an output sig­nal from the PC. Keep in mind that the number of I/O points available de­pends on the configuration of the PC. Refer to
capacity and assigning I/O bits to I/O points.

Next, determine the sequence in which control operations are to occur and
the relative timing of the operations. Identify the physical relationships be­tween the I/O devices as well as the kinds of responses that should occur
between them.

For instance, a photoelectric switch might be functionally tied to a motor by
way of a counter within the PC. When the PC receives an input from a start
switch, it could start the motor. The PC could then stop the motor when the
counter has received five input signals from the photoelectric switch.

Each of the related tasks must be similarly determined, throughout the entire
control operation.

3–3 IR Area

for details on I/O

Unit Requirements

The actual Units that will be mounted must be determined according to the
requirements of the I/O devices. This will include actual hardware specifica­tions, such as voltage and current levels, as well as functional considera­tions, such as those that require Special I/O Units or Link Systems. In many
cases, Special I/O Units or Link Systems can greatly reduce the program­ming burden. Details on these Units and Link Systems are available in indi-

Operation Manuals

vidual
Once the entire Control System has been designed, the task of program-

ming, debugging, and operation as described in the remaining sections of
this manual can begin.

and

System Manuals.

5

Peripheral Devices Section 1–6

1–6 Peripheral Devices

The following peripheral devices can be used in programming, either to input/
debug/monitor the PC program or to interface the PC to external devices to
output the program or memory area data. Model numbers for all devices
listed below are provided in
names have been placed in bold when introduced in the following descrip­tions.

Appendix A Standard Models

. OMRON product

Programming Console

Graphic Programming
Console: GPC

Ladder Support Software:
LSS

Factory Intelligent Terminal:
FIT

A Programming Console is the simplest form of programming device for OM­RON PCs. Although a Programming Console Adapter is sometimes re­quired, all Programming Consoles are connected directly to the CPU without
requiring a separate interface. The Programming Console also functions as
an interface to output programs to a standard cassette tape recorder.

Various types of Programming Console are available, including both
CPU-mounting and Hand-held models. Programming Console operations are
described later in this manual.

A Peripheral Interface Unit is required to interface the GPC to the PC.
The GPC also functions as an interface to output programs directly to a stan-

dard cassette tape recorder. A PROM Writer, Floppy Disk Interface Unit, or
Printer Interface Unit can be directly mounted to the GPC to output pro­grams directly to an EPROM chip, floppy disk drive, or printing device.

LSS is designed to run on IBM AT/XT compatibles to enable nearly all of the
operations available on the GPC. It also offers extensive documentation ca­pabilities.

A Host Link Unit is required to interface a computer running LSS to the PC.

The FIT is an OMRON computer with specially designed software that allows
you to perform all of the operations that are available with the GPC or LSS.
Programs can also be output directly to an EPROM chip, floppy disk drive, or
printing device without any additional interface units. The FIT has an EPROM
writer and a 3.5” floppy disk drive built in.

PROM Writer

Floppy Disk Interface Unit

Printer Interface Unit

6

A Peripheral Interface Unit or Host Link Unit is required to interface the
FIT to the PC. Using an Optical Host Link Unit also enables the use of optical
fiber cable to connect the FIT to the PC. Wired Host Link Units are available
when desired. (Although FIT does not have optical connectors, conversion to
optical fiber cable is possible by using Converting Link Adapters.)

Other than its applications described above, the PROM Writer can be
mounted to the PC’s CPU to write programs to EPROM chips.

Other than its applications described above, the Floppy Disk Interface Unit
can be mounted to the PC’s CPU to interface a floppy disk drive and write
programs onto floppy disks.

Other than its applications described above, the Printer Interface Unit can be
mounted to the PC’s CPU to interface a printer or X–Y plotter to print out pro­grams in either mnemonic or ladder-diagram form.

Available Manuals Section 1–7

1–7 Available Manuals

The following table lists other manuals that may be required to program and/
or operate the P-type PCs.

Operation Manuals

also provided with individual Units and are required for wiring and other
specifications.

Name Cat. no. Contents

Installation Guide W167 Hardware specifications
GPC Operation Manual W84 Programming procedures for the GPC (Graphics Program-

ming Console)

FIT Operation Manual W150 Programming procedures for using the FIT (Factory Intelligent

Terminal

LSS Operation Manual W113 Programming procedures for using LSS (Ladder Support Soft-

ware)
Printer Interface Unit Operation Guide W107 Procedures for interfacing a PC to a printer
PROM Writer Operation Guide W155 Procedures for writing programs to EPROM chips
Floppy Disk Interface Unit Operation Guide W119 Procedures for interfacing a PC to a floppy disk drive
Optical Remote I/O System Manual W136 Information on building an Optical Remote I/O System to en-

able remote I/O capability
Host Link System Manual W143 Information on building a Host Link System to manage PCs

from a ‘host’ computer
K-type Analog I/O Units Operation Guide W122 Hardware and software information on using Analog I/O Units

with the P-type PCs.

and/or

Operation Guides

are

7

SECTION 2

Hardware Considerations

2–1 Introduction 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 Indicators 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 PC Configuration 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9

PC Configuration Section 2–3

2–1 Introduction

This section provides information on hardware aspects of P-type PCs that
are relevant to programming and software operation. These include indica­tors on the CPU and basic PC configuration. This information is covered in
detail in the

Installation Guide

.

2–2 Indicators

CPU indicators provide visual information on the general operation of the
PC. Using the flags and other error indicators provided in the memory data
areas, although not a substitute for proper error programming, provides
ready confirmation of proper operation.

CPU Indicators

CPU indicators are located on the front right hand side of the PC adjacent to
the I/O expansion slot and are described in the following table.

Indicator Function

POWER Lights when power is supplied to the CPU.
RUN Lights when the CPU is operating normally .
ERR Lights when an error is discovered in system error diagnosis op-

ALARM Lights when an error is discovered in system error diagnosis op-

2–3 PC Configuration

The Units from which P-type PCs can be built are shown below.

Unit type Name Words

CPU C20P 2 12 points 8 points

Expansion I/O Unit C4K 2 4 input points or 4 output points

Special I/O Units Analog Timer Unit 2 4 timer inputs

erations. When this indicator lights, the RUN indicator will go off,
CPU operation will be stopped, and all outputs from the PC will
be turned OFF.

erations. PC operation will continue.

Inputs

occupied

C28P 2 16 points 12 points
C40P 4 24 points 16 points
C60P 4 32 points 24 points

C20P 2 12 points 8 points
C28P 2 16 points 12 points
C40P 4 24 points 16 points
C60P 4 32 points 24 points

C4K Analog Input Unit 2 4 analog inputs
C1K Analog Input Unit 2 1 analog input
Analog Output Unit 2 1 analog output
I/O Link Unit 2 16 input and 16 output bits

provided

Outputs

provided

10

Each PC is connected in series starting with a CPU and, if required, continu­ing on with Expansion I/O or Special I/O Units. All other Units are connected
in series following the CPU and can be in any order desired except for the
I/O Link Unit, which must always come last. Up to five Units, including the
CPU can be connected as long as the total number of words occupied does
not exceed ten. Refer to

Section 3–3 IR Area

for configuration examples.

SECTION 3

Memory Areas

3–1 Introduction 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 Data Area Structure 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–3 IR Area 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4 SR Area 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4–1 Battery Alarm Flag 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4–2 Scan Time Error Flag 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4–3 High-speed Drum Counter Reset 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4–4 Clock Pulse Bits 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4–5 Error Flag ER 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4–6 Always OFF and Always ON Flags 25 . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4–7 First Scan Flag 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4–8 Arithmetic Flags 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–5 DM Area 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–6 HR Area 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–7 TC Area 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–8 TR Area 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11

Data Area Structure Section 3–2

3–1 Introduction

Various types of data are required to achieve effective and correct control. To
facilitate managing this data, the PC is provided with various memory areas
for data, each of which performs a different function. The areas generally ac­cessible by the user for use in programming are classified as data areas.
The other memory area is the Program Memory, where the user’s program is
actually stored.

This section describes these areas individually and provides information that
will be necessary to use them. The name, acronym, range, and function of
each area are summarized in the following table. All but the last one of these
are data areas. All memory areas are normally referred to by their acronyms.

Area

Internal Relay
area

Special Relay
area

Data Memory
area

Holding Relay
area

Timer/Counter
area

Temporary Relay
area

Program Memory

Acronym

IR

SR

DM

HR

TC

TR

UM

Work Bits and Words

Range

Words: 00 to 18 (right half)
Bits: 0000 to 1807

Words: 18 (left half) and 19
Bits: 1808 to 1907

DM 00 to DM 63
(words only)

Words: HR 0 to HR 9
Bits: HR 000 to HR 915

TC 00 to TC 47 (TC numbers are
used to access other information)

TR 00 to TR 07 (bits only)

UM: 1,194 words.

Function

Used to manage I/O points, control other bits,
timers, and counters, to temporarily store data.

Contains system clocks, flags, control bits, and
status information.

Used for internal data storage and manipulation.

Used to store data and to retain the data values
when the power to the PC is turned off.

Used to define timers and counters and to ac­cess Completion Flags, PV, and SV for them.

Used to temporarily store execution conditions.

Contains the program executed by the CPU.

When some bits and words in certain data areas are not used for their in­tended purpose, they can be used in programming as required to control
other bits. Words and bits available for use in this fashion are called work bits
and work words. Most, but not all, unused bits can be used as work bits.
Those that can be are specified by area in the remainder of this section. Ac­tual application of work bits and work words is described in

gramming

.

Section 4 Pro-

Flags and Control Bits

Some data areas contain flags and/or control bits. Flags are bits that are
automatically turned ON and OFF to indicate status of one form or another.
Although some flags can be turned ON and OFF by the user, most flags can
be read only; they cannot be controlled directly.

Control bits are bits turned ON and OFF by the user to control specific as­pects of operation. Any bit given a name using the word bit rather than the
word flag is a control bit, e.g., Restart Bits are control bits.

3–2 Data Area Structure

When designating a data area, the acronym for the area is always required
for any but the IR and SR areas. Although the acronyms for the IR and SR
areas are often given for clarity, they are not required and not input when
programming. Any data area designation without an acronym is assumed to
be in either the IR and SR area. Because IR and SR addresses run consecu­tively, the word or bit addresses are sufficient to differentiate these two areas.

12

Data Area Structure Section 3–2

An actual data location within any data area but the TC area is designated by
its address. The address designates the bit and/or word within the area
where the desired data is located. The TR area consists of individual bits
used to store execution conditions at branching points in ladder diagrams.
The use of TR bits is described in

Section 4 Programming.

sists of TC numbers, each of which is used for a specific timer or counter de­fined in the program. Refer to
and to

5–11 Timer and Counter Instructions

3–7 TC Area

for more details on TC numbers

for information on actual applica-

tion.
The rest of the data areas (i.e., the IR, SR, HR and DM areas) consist of

words, each of which consists of 16 bits numbered 00 through 15 from right
to left. IR words 00 and 01 are shown below with bit numbers. Here, the con­tent of each word is shown as all zeros. Bit 00 is called the rightmost bit; bit
15, the leftmost bit.

The TC area con-

Bit number
IR word 00 0000000000000000
IR word 01 0000000000000000

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

The term least significant is often used for rightmost; the term most signifi-

Note

cant, for leftmost. These terms have not been used in this manual because a
single word is often split into two or more parts, with each part used for differ­ent parameters or operands, sometimes even with bits in another word.
When this is done, the rightmost bits in a word may actually be the most sig­nificant bits, i.e., the leftmost bits, of a value with other bits, i.e., the least sig­nificant bits, contained in another word.

The DM area is accessible by word only; you cannot designate an individual
bit within a DM word. Data in the IR, SR and HR areas is accessible either by
bit or by word, depending on the instruction in which the data is being used.

To designate one of these areas by word, all that is necessary is the acronym
(if required) and the one or two-digit word address. To designate an area by
bit, the word address is combined with the bit number as a single three- or
four-digit address. The examples in the following table should make this
clear. The two rightmost digits of a bit designation must indicate a bit be­tween 00 and 15.

The same TC number can be used to designate either a word containing the
present value (PV) of the timer or counter or a bit that functions as the Com­pletion Flag for the timer or counter. This is explained in more detail in

TC Area

Area Word designation Bit designation

IR 00 0015 (leftmost bit in word 00)
SR 19 1900 (rightmost bit in word 19)
DM DM 10 Not possible
TC TC 46 (designates PV) TC 46 (designates Completion Flag)

.

3–7

13

Data Area Structure Section 3–2

Data Structure

Digit number 3210

Bit number
Contents 0000000000000000

Word data input as decimal values is stored in binary-coded decimal (BCD)
code; word data input as hexadecimal is stored in binary form. Because each
word contains 16 bits, each four bits of a word represents one digit: either a
hexadecimal digit equivalent numerically to the binary bits or decimal. One
word of data thus contains four digits, which are numbered from right to left.
These digit numbers and the corresponding

bit numbers for one word are shown below.

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

When referring to the entire word, the digit numbered 0 is called the right­most digit; the one numbered 3, the leftmost digit.

A piece of data in memory does not necessarily require exactly one word. If a
piece of data is in 3-digit BCD, for example, only 12 bits will be required to
express it (see decimal point example below). These would most likely be in
the same word and occupy either the rightmost or leftmost three digits. Data
requiring more than four digits must be split between words: sometimes be­tween two whole words and sometimes between one word and part of an­other word.

Converting Different Forms
of Data

When inputting data into data areas, it must be input in the proper form for
the intended purpose. This is no problem when designating individual bits,
which are merely turned ON (equivalent to a binary value of 1) or OFF (a bi­nary value of 0). When inputting word data, however, it is important to input it
either as decimal or as hexadecimal, depending on what is called for by the
instruction it is to be used for.

Section 5 Instruction Set

specifies when a par-

ticular form of data is required for an instruction.

Binary and hexadecimal can be easily converted back and forth because
each four bits of a binary number is numerically equivalent to one digit of a
hexadecimal number. The binary number 0101111101011111 is converted to
hexadecimal by considering each set of four bits in order from the right. Bi­nary 1111 is hexadecimal F; binary 0101 is hexadecimal 5. The hexadecimal

3

equivalent would thus be 5F5F, or 24,415 in decimal (16

x 5 + 162 x 15 + 16

x 5 + 15).
Decimal and BCD can also be easily converted back and forth. In this case,

each BCD digit (i.e., each four BCD bits) is numerically equivalent of the cor­responding decimal digit. The BCD bits 0101011101010111 are converted to
decimal by considering each four bits from the right. Binary 0101 is decimal
5; binary 0111 is decimal 7. The decimal equivalent would thus be 5,757.
Note that this is not the same numeric value as the hexadecimal equivalent
of 0101011101010111, which would be 5,757 hexadecimal, or 22,359 in deci-

3

mal (16

x 5 + 162 x 7 + 16 x 5 + 7).

14

Because the numeric equivalent of each four BCD binary bits must be
equivalent to a decimal value, any four bit combination numerically greater
then 9 cannot be used, e.g., 1011 is not allowed because it is numerically
equivalent to 11, which cannot be expressed as a single digit in decimal nota­tion. The binary bits 1011 are of course allowed in hexadecimal and they are
equivalent to the hexadecimal digit C.

IR Area Section 3–3

There are instructions provided to convert data in either direction between
BCD and hexadecimal. Refer to

5–15 Data Conversion

binary equivalents to hexadecimal and BCD digits are provided in the appen­dices for reference.

for details. Tables of

Decimal Points

Digits Not used here. 1 5 4

Bit number
Contents 000101010100

3–3 IR Area

Decimal points are also not stored directly in memory, although some of the
parameters contained in data areas have assumed decimal points. For ex­ample, if a value is said to be in 3-decimal hexadecimal to the tenths of an
second and it occupies the rightmost three digits in a specified word (i.e., bits
00 through 11), the rightmost digit (bits 00 through 03) would contain tenths
of a second and the other two digits would contain the number of whole sec­onds. If the value was 15.4 decimal, the corresponding BCD bits in memory
would be as shown below.

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

The IR area is used both to control I/O points and as work bits to manipulate
and store data internally. It is accessible both by bit and by word. Those
words that can be used to control I/O points are called I/O words. Bits in I/O
words are called I/O bits.

The number of I/O words varies between the P-type PCs. As shown, the IR
area is comprised of three main sections. These are input words, output
words and work words (work bits). Work bits are used in programming to ma­nipulate data and control other bits. IR area work bits are reset when power
is interrupted or PC operation is stopped.

I/O Words

Input Bit Usage

Word type I/O words I/O bits

Input IR 00

through IR
04

Output IR 05

through IR
09

Work IR 10

through IR
18

I/O bits are assigned to input or output points as described in

.

tions

IR 0000 through IR 0415

IR 0500 through IR 0915

IR 1000 through IR 1807

Word Alloca-

If a Unit brings inputs into the PC, the bit assigned to it is an input bit; if the
Unit sends an output from the PC, the bit is an output bit. To turn on an out­put, the output bit assigned to it must be turned ON. When an input turns on,
the input bit assigned to it also turns ON. These facts can be used in the pro­gram to access input status and control output status through I/O bits.

I/O bits that are not assigned to I/O points can be used as work bits, unless
otherwise specified in

Word Allocations

.

Input bits can directly input external signals to the PC and can be used in any
order in programming. Each input bit can also be used in as many instruc-

15

IR Area Section 3–3

tions as required to achieve effective and proper control. They cannot be
used in instructions that control bit status, e.g., the Output, Differentiation Up,
and Keep instructions.

Output Bit Usage

Word Allocations

Output bits are used to output program execution results and can be used in
any order in programming. Because outputs are refreshed only once during
each scan (i.e., once each time the program is executed), any output bit can
be used only one instruction that controls its status, including OUT,
KEEP(11), DIFU(13), DIFD(14) and SFT(10). If an output bit is used in more
than one such instruction, only the status determined by the last one will ac­tually be output from the PC.

As outputs are refreshed only once during each scan (i.e. once each time the
program is executed), any output bit can be used in only one instruction that
controls its status, including OUT, OUT NOT, KEEP(11), DIFU(13), DIFD(14),
and SFT(10). If an output bit is used in more than one such instruction, only
the status determined by the last instruction will actually be output from the
PC. See

The maximum number of words available for I/O within the IR area is 10,
numbered 00 through 09. The remaining words (10 through 18) are to be
used for work bits. (Note that with word 18, only the bits 00 through 07 are
available for work bits although some of the remaining bits are required for
special purposes when RDM(98) is used).

The actual number of bits that can be used as I/O bits is determined by the
model of the CPU and the PC configuration. There are different models of
Expansion I/O Units and Special I/O Units and I/O Link Units which can be
connected to any of the CPUs. Each CPU model provides a particular num­ber of I/O bits and each Expansion I/O Unit, Special I/O Unit or I/O Link Unit
provides a particular number of I/O bits. Configuration charts for the possible
combinations of CPUs and Units are included later in this section. Refer to
those to determine the actual available I/O bits.

5–12–1 Shift Register – SFT(10)

for an exception to this rule.

With P-type PCs, IR 00 through IR 04 are always input bits and IR 05 through
IR 09 are always outputs bits. These are allocated in order from IR 00 (input)
and IR 05 (output) beginning from the CPU. Each Unit is allocated either one
input word and one output word or, for the C40P/C60P Units, two input words
and two output words. If the words or bits within a word are not need by the
Unit, they are not allocated to any other Unit. Unallocated input bits cannot
be used for any purpose, but unallocated output bits can be used in program­ming as work bits.

16

IR Area Section 3–3

I/O Bits Available in CPUs

Model Input bits

C20K

C28K

C40K

C60K

The following table shows which bits can be used as I/O bits in each of the
P-type CPUs. Bits in the shaded areas can be used as work bits but not as
output bits. IR 0000 and IR 0001 are used by HDM(98).

Output bits

IR 00

00
01
02
03
04
05
06
07

IR 00

00
01
02
03
04
05
06
07

IR 00

00
01
02
03
04
05
06
07

IR 00

00
01
02
03
04
05
06
07

08
09
10
11

Cannot
be used

08
09
10
11
12
13
14
15

08
09
10
11
12
13
14
15

08
09
10
11
12
13
14
15

IR 01

00
01
02
03
04
05
06
07

IR 01

00
01
02
03
04
05
06
07

Cannot
be used

08
09
10
11
12
13
14
15

IR 05

00
01
02
03
04
05
06
07

IR 05

00
01
02
03
04
05
06
07

IR 05

00
01
02
03
04
05
06
07

IR 05

00
01
02
03
04
05
06
07

08
09
10
11
12
13
14
15

08
09
10
11
12
13
14
15

IR 06

00
01
02
03
04
05
06
07

IR 06

00
01
02
03
04
05
06
07

08
09
10
11
12
13
14
15

08
09
10
11
12
13
14
15

08
09
10
11
12
13
14
15

08
09
10
11
12
13
14
15

17

IR Area Section 3–3

I/O Bits Available in
Expansion I/O Units

The following table shows which bits can be used as I/O bits in each of the
Expansion I/O Units. Bits in the shaded areas can be used as work bits but
not as output bits. The word addresses depend on the Unit(s) that the Expan­sion I/O Unit is coupled to. In all cases the first Expansion I/O Unit address
for input and output words is one more than the last address for input and
output words used by the Unit to which the Expansion I/O Unit is attached.
For example, if the last word address was IR 03, the first input or output word
address for the Expansion I/O Units will be IR 04. In the tables below “n” is
the word allocated prior to the Expansion I/O Unit.

Model Input bits Output bits Model Input bits Output bits

IR (n + 1)

00
01
02
03
04
05
06
07

IR (n + 1)

Cannot
be used

IR (n + 1)

00
01
02
03

Cannot
be used

IR (n + 1)

Cannot
be used

IR (n + 6)

08

00

08

09

01

09

10

02

10

11

03

11

12

04

12

13

05

13

14

06

14

15

07

15

IR (n + 6)

00

08

01

09

02

10

03

11

04

12

05

13

06

14

07

15

IR (n + 6)

00

08

01

09

02

10

03

11

04

12

05

13

06

14

07

15

IR (n + 6)

00

08

01

09

02

10

03

11

04

12

05

13

06

14

07

15

C20P

C28P

C40P

C60P

IR (n+1)

00
01
02
03
04
05
06
07

IR (n+1)

00
01
02
03
04
05
06
07

IR (n+1)

00
01
02
03
04
05
06
07

IR (n+1)

00
01
02
03
04
05
06
07

08
09
10
11

Cannot
be used

08
09
10
11
12
13
14
15

08
09
10
11
12
13
14
15

08
09
10
11
12
13
14
15

IR (n + 2)

00
01
02
03
04
05
06
07

IR (n + 2)

00
01
02
03
04
05
06
07

Cannot
be used

08
09
10

11
12
13
14
15

IR (n + 6)

00
01
02
03
04
05
06
07

IR (n + 6)

00
01
02
03
04
05
06
07

IR (n + 6)

00
01
02
03
04
05
06
07

IR (n + 6)

00
01
02
03
04
05
06
07

08
09
10
11
12
13
14
15

08
09
10
11
12
13
14
15

IR (n + 4)

00
01
02
03
04
05
06
07

IR (n + 4)

00
01
02
03
04
05
06
07

08
09
10

11
12
13
14
15

08
09
10

11
12
13
14
15

08
09
10
11
12
13
14
15

08
09
10
11
12
13
14
15

C16P
Input

C16P
Output

C4K
Input

C4K
Output

18

IR Area Section 3–3

I/O Bits Available in Special
I/O Units

The following table shows which bits are allocated to each of the Special I/O
Units. Bits in the shaded areas can be used as work bits but not as output
bits. The word addresses depend on the Unit(s) that the Special I/O Unit is
coupled to. In all cases the first Special I/O Unit address for input and output
words is one more than the last address for input and output words used by
the Unit to which the Special I/O Unit is attached. For example, if the last
word address was IR 03, the first input or output word address for the Special
I/O Units will be IR 04. In the tables below “n” is the word allocated prior to
the Special I/O Unit.

Model Input bits Output bits

C1K–AD

C4K–AD

C1K–DA

C20–LK
011(–P)

C4K–TM

IR (n + 1)

00
01
02
03
04
05
06
07

IR (n + 1)

00
01
02
03
04
05
06
07

IR (n + 1)

Cannot
be used

IR (n + 1)

00
01
02
03
04
05
06
07

IR (n + 1)

00
01
02
03

Cannot
be used

Cannot
be
used

08
09
10
11
12
13
14
15

08
09
10

11
12
13
14
15

IR (n + 6)

00
01
02
03
04
05
06
07

IR (n + 6)

00
01
02
03
04
05
06
07

IR (n + 6)

00
01
02
03
04
05
06
07

IR (n + 6)

00
01
02
03
04
05
06
07

IR (n + 6)

00
01
02
03
04
05
06
07

08
09
10
11
12
13
14
15

08
09
10
11
12
13
14
15

08
09
10
11
12
13
14
15

08
09
10
11
12
13
14
15

08
09
10
11
12
13
14
15

PC Configuration and I/O
Word Allocation

A P-type PC consists of a CPU Unit plus one or more of the following Units:
Expansion I/O Units, Analog Timer Units, Analog I/O Units, or an I/O Link
Unit. All of these Units are connected in series with the CPU Unit at one end.
An I/O Link Unit, if included, must be on the other end (meaning only one I/O

19

IR Area Section 3–3

Link Unit can be used) and an Analog Timer Unit cannot be used with. The
rest of the Units can be in any order desired.

The tables on the following pages show the possible configurations for a
P-type PC. Although the tables branch to show the various possibilities at
any one point, there can be no branching in the actual PC connections. You
can choose either branch at any point and go as far as required, i.e., you can
break off at any point to create a smaller PC System.When implementing a
system there is a physical restriction on the total cable length allowable. The
sum of the lengths of all cables in the system must be limited to less than 1.2
meters.

The tables also show which words will be input words and which words will
be output words. All of these are determined by the position of the Unit. With
the C4P and C16P Expansion I/O Units, the type of Unit (input or output) de­termines whether the input or output word is used.

The symbols used in the table represent the following:

C20P/C28P

Input Output

C40P/C60P

Input Output

C4K/C16P

Input or Output

C20P/C28P/TU/AN/LU

Input Output

C20P or C28P CPU Unit

Input Output

C40P or C60P CPU or
Expansion I/O Unit

C4K or C16P Expansion I/O Unit

C20P Expansion I/O Unit, C28P Expansion I/O Unit,
Analog Timer Unit, Analog I/O Unit, or I/O Link Unit

20

IR Area Section 3–3

IR 00 IR 05 IR 01 IR 06 IR 02 IR 07 IR 03 IR 08 IR 04 IR 09

C20P/C28P

Input Output

C4K/C16P

Input or Output

C4K/C16P

Input or Output

C20P/C28P/TU/AN/LU

Input Output

C4K/C16P

Input or Output

C4K/C16P

Input or Output

C20P/C28P/TU/AN/LU

Input Output

C20P/C28P/TU/AN/LU

Input Output

C4K/C16P

Input or Output

C20P/C28P/TU/AN/LU

Input Output

C40P/C60P

Input Output Input Output

C4K/C16P

Input or Output

C4K/C16P

Input or Output

C20P/C28P/TU/AN/LU

Input Output

C20P/C28P/TU/AN/LU

Input Output

C4K/C16P

Input or Output

C20P/C28P/TU/AN/LU

Input Output

C20P/C28P/TU/AN/LU

Input Output

Input Output Input Output

C40P/C60P

Input Output Input Output

C4K/C16P

Input or Output

C4K/C16P

Input or Output

C20P/C28P/TU/AN/LU

Input Output

Input Output Input Output

C40P/C60P

C4K/C16P

Input or Output

C20P/C28P/TU/AN/LU

Input Output

C4K/C16P

Input or Output

C20P/C28P/TU/AN/LU

Input Output

C4K/C16P

Input or Output

C20P/C28P/TU/AN/LU

Input Output

C40P/C60P

21

IR Area Section 3–3

IR 00 IR 05 IR 01 IR 06 IR 02 IR 07 IR 03 IR 08 IR 04 IR 09

C20P/C28P

Input Output

C20P/C28P/TU/AN/LU

Input Output

C20P/C28P/TU/AN/LU

Input Output

Input Output Input Output

C40P/C60P

Input Output Input Output

C40P/C60P

C4K/C16P

Input or Output

C4K/C16P

Input or Output

C20P/C28P/TU/AN/LU

Input Output

C20P/C28P/TU/AN/LU

Input Output

C4K/C16P

Input or Output

C20P/C28P/TU/AN/LU

Input Output

C40P/C60P

Input Output Input Output

C4K/C16P

Input or Output

C20P/C28P/TU/AN/LU

Input Output

C4K/C16P

Input or Output

C4K/C16P

Input or Output

C20P/C28P/TU/AN/LU

Input Output

C20P/C28P/TU/AN/LU

Input Output

C4K/C16P

Input or Output

C20P/C28P/TU/AN/LU

Input Output

C40P/C60P

Input Output Input Output

22

IR Area Section 3–3

IR 00 IR 05 IR 01 IR 06 IR 02 IR 07 IR 03 IR 08 IR 04 IR 09

C40P/C60P

Input Output

Input Output

C4K/C16P

Input or Output

C20P/C28P/TU/AN/LU

Input Output

C4K/C16P

Input or Output

C4K/C16P

Input or Output

C20P/C28P/TU/AN/LU

Input Output

C20P/C28P/TU/AN/LU

Input Output

C4K/C16P

Input or Output

C20P/C28P/TU/AN/LU

Input Output

C40P/C60P

Input Output Input Output

C4K/C16P

Input or Output

C4K/C16P

Input or Output

C20P/C28P/TU/AN/LU

Input Output

C20P/C28P/TU/AN/LU

Input Output

C4K/C16P

Input or Output

C40P/C60P

Input Output

Input Output

C20P/C28P/TU/AN/LU

Input Output

C20P/C28P/TU/AN/LU

Input Output

Input Output Input Output

C40P/C60P

Input Output Input Output

C20P/C28P/TU/AN/LU

Input Output

C40P/C60P

C4K/C16P

Input or Output

C20P/C28P/TU/AN/LU

Input Output

23

SR Area Section 3–4

3–4 SR Area

The SR area contains flags and control bits used for monitoring system op­eration, accessing clock pulses, and signalling errors. SR area word ad­dresses range from 18 through 19; bit addresses, from 1808 through 1907.

The following table lists the functions of SR area flags and control bits. Most
of these bits are described in more detail following the table.

Unless otherwise stated, flags are OFF until the specified condition arises,
when they are turned ON. Bits 1903 to 1907 are turned OFF when END is
executed at the end of each program scan, and thus cannot be monitored on
the Programming Console. Other control bits are OFF until set by the user.

Word Bit Function

18 08 Battery Alarm Flag

09 Scan Time Error Flag
10 High-speed Counter Reset
11 Always OFF Flag
12 Always OFF Flag
13 Always ON Flag
14 Always OFF Flag
15 First Scan Flag

19 00 0.1-second Clock Pulse

01 0.2-second Clock Pulse
02 1-second Clock Pulse
03 Error (ER) Flag
04 Carry (CY) Flag
05 Greater Than (GR) Flag
06 Equals (EQ) Flag
07 Less Than (LE) Flag

3–4–1 Battery Alarm Flag

SR 1808 turns ON if the voltage of the CPU backup battery drops. A voltage
drop can be indicated by connecting the output of this bit to an external indi­cating device such as a LED. This bit can be used in programming to activate
an external warning for a low battery.

3–4–2 Scan Time Error Flag

SR 1809 turns ON if the scan time exceeds 100 ms. This bit is turned ON
when the scan time is between 100 and 130 ms. The PC will still operate but
timing may become inaccurate. The PC will stop operating if the execution
time exceeds 130 ms.

3–4–3 High-speed Drum Counter Reset

SR 1810 turns ON for one scan time when the hard reset signal (input 0001)
is turned ON.

3–4–4 Clock Pulse Bits

Three clock pulses are available to control program timing. Each clock pulse
bit is ON for the first half of the rated pulse time, then OFF for the second
half. In other words, each clock pulse has a duty factor of 1 to 1.

24

SR Area Section 3–4

These clock pulse bits are often used with counter instructions to create tim­ers. Refer to

Pulse width 0.1 s 0.2 s 1.0 s
Bit 1900 1901 1902

5–11 Timer and Counter Instructions

for an example of this.

3–4–5 Error Flag ER

SR 1900

0.1-s clock pulse

.05 s .05 s

0.1 s

SR 1902

1.0-s clock pulse

0.5 s 0.5 s

1.0 s

0.1 s 0.1 s

Caution:
Because the 0.1-second clock
pulse bit has an ON time of 50 ms,
the CPU may not be able to accu­rately read the pulses if program
execution time is too long.

SR 1901

0.2-s clock pulse

0.2 s

SR 1903 turns ON when the results of an arithmetic operation is not output in
BCD or the value of the BIN data processed by the BIN to BCD or BCD to
BIN conversion instruction exceeds 9999. When the ER Flag is ON the cur­rent instruction is not executed.

3–4–6 Always OFF and Always ON Flags

SR 1811, SR 1812 and SR 1814 are always OFF and AR 1813 is always ON.
By connecting these bits to external indicating devices such as a LED they
can be used to monitor the PC’s operating status.

3–4–7 First Scan Flag

SR 1815 turns ON when program execution starts and turns OFF after one
scan.

3–4–8 Arithmetic Flags

The following flags are used in data shifting, arithmetic calculation, and com­parison instructions. They are generally referred to only by their two-letter
abbreviations. These flags are all reset when END is executed, and therefore
cannot be monitored from a Programming Device.

5–12 Data Shifting, 5–14 Data Comparison

for details.

Carry Flag, CY

Refer to

tions

SR 1904 turns ON when there is a carry in the result of an arithmetic opera­tion. The content of CY is also used in some arithmetic operations, e.g., it is
added or subtracted along with other operands. This flag can be set and
cleared from the program using the STC and CLC instructions. Use CLC be­fore any instruction using CY unless the current content of CY is required.

and

5–16 BCD Calcula-

Greater Than Flag, GR

SR 1905 turns ON when the result of a comparison shows the second of two
4-digit operands to be greater than the first.

25

TC Area Section 3–7

Equal Flag, EQ

Less Than Flag, LE

3–5 DM Area

3–6 HR Area

SR 1906 turns ON when the result of a comparison shows two operands to
be equal or when the result of an arithmetic operation is zero.

SR 1907 turns ON when the result of a comparison shows the second of two
4-digit operands to be less than the first.

The DM area is used for internal data storage and manipulation and is acces­sible only by word. Addresses range from DM 00 through DM 63.

Although composed of 16 bits just like any other word in memory, DM words
cannot be specified by bit for use in instructions with bit-size operands, such
as LD, OUT, AND, and OR.

When the HDM(98) (High-speed Drum Counter) is used the DM area words
32 to 63 are used as the area where the upper and lower limits of the counter
are preset and as such these words cannot be used for any other purposes.

The DM area retains status during power interruptions.

The HR area is used to store and manipulate various kinds of data and can
be accessed either by word or by bit. Word addresses range from HR 0
through HR 9; bit addresses, from HR 000 through HR 915. HR bits can be
used in any order required and can be programmed as often as required.

The HR area retains status when the system operating mode is changed, or
when power is interrupted.

3–7 TC Area

The TC area is used to create and program timers and counters and holds
the Completion Flags, set values (SV), and present values (PV) for all timers
and counters. All of these are accessed through TC numbers ranging from
TC 00 through TC 47. Each TC number is defined as either a timer or
counter using one of the following instructions: TIM, TIMH, CNT or CNTR. No
prefix is required when using a TC number as a definer in a timer or counter
instruction.

Once a TC number has been defined using one of these instructions, it can­not be redefined elsewhere in the program using the same or a different in­struction. If the same TC number is defined in more than one of these in­structions or in the same instruction twice, an error will be generated during
the program check. There are no restrictions on the order in which TC num­bers can be used.

Once defined, a TC number can be designated as an operand in one or more
instructions other than those listed above. When defined as a timer, a TC
number designated as an operand takes a TIM prefix. The TIM prefix is used
regardless of the timer instruction that was used to define the timer. Once
defined as a counter, the TC number designated as an operand takes a CNT
prefix. The CNT is also used regardless of the counter instruction that was
used to define the counter.

TC numbers can be designated for operands that require bit data or for oper­ands that require word data. When designated as an operand that requires
bit data, the TC number accesses the Completion Flag of the timer or
counter. When designated as an operand that requires word data, the TC
number accesses a memory location that holds the PV of the timer or
counter.

26

TR Area Section 3–8

TC numbers are also used to access the SV of timers and counters from a
Programming Device. The procedures for doing so from the Programming
Console are provided in

The TC area retains the SVs of both timers and counters during power inter­ruptions. The PVs of timers are reset when PC operation is begun and when
reset in interlocked program sections. Refer to

Clear – IL(02) and ILC(03)

locked program sections. The PVs of counters are not reset at these times.
Note that in programming “TIM 00” is used to designate three things: the

Timer instruction defined with TC number 00, the Completion Flag for this
timer, and the PV of this timer. The meaning in context should be clear, i.e.,
the first is always an instruction, the second is always a bit, and the third is
always a word. The same is true of all other TC numbers prefixed with TIM or
CNT. In explanations of ladder diagrams, the Completion Flag and PV ac­cessed through a TC number are generally called the Completion Flag or the
PV of the instruction (e.g., the Completion Flag of TIM 00 is the Completion
Flag accessed through TC number 00, which has been defined using TIM).

When the RDM(98) (Reversible High-speed Drum Counter) is used TC 46 is
used as the present value storage area of the counter and thus cannot be
used for any other purpose.

7–8 Monitoring Operation and Modifying Data.

5–7 Interlock and Interlock

for details on timer and counter operation in inter-

3–8 TR Area

The TR area provides eight bits that are used only with the LD and OUT in­structions to enable certain types of branching ladder diagram programming.
The use of TR bits is described in

TR addresses range from TR 0 though TR 7. Each of these bits can be used
as many times as required and in any order required as long as the same TR
bit is not used twice in the same instruction block.

Section 4 Programming

.

27

SECTION 4

Programming

4–1 Introduction 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–2 Instruction Terminology 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–3 The Ladder Diagram 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–3–1 Basic Terms 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–3–2 Ladder Instructions 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–3–3 Logic Block Instructions 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–3–4 Branching Instruction Lines 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–3–5 Jumps 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–4 Controlling Bit Status 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–4–1 OUT and OUT NOT 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–4–2 Differentiate Up and Differentiate Down 41 . . . . . . . . . . . . . . . . . . . . . . .

4–4–3 Keep 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–4–4 Self-maintaining Bits 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–5 The End Instruction 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–6 Programming Precautions 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–7 Program Execution 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

29

The Ladder Diagram Section 4–3

4–1 Introduction

This section explains the basic steps and concepts involved in programming
and introduces the instructions used to build the basic structure of the ladder
diagram and control its execution. The entire set of instructions used in pro-

1, 2, 3...

gramming is described in
There are several basic steps involved in writing a program.

1. Obtain a list of all I/O devices and the I/O points that have been as­signed to them and prepare a table that shows the I/O bit allocated to
each I/O device.

2. If the PC has any Units, i.e. Analog Timer Units, Host Link Units , and
I/O Link Units that are allocated words in data areas other than the IR
area or are allocated IR words in which the function of each bit is speci­fied by the Unit, prepare similar tables to show what words are used for
which Units and what function is served by each bit within the words.

3. Determine what words are available for work bits and prepare a table in
which you can allocate these as you use them.

4. Also prepare tables of TC numbers so that you can allocate these as
you use them. Remember, the function of a TC number can be defined
only once within the program. (TC number are described in

and Counter Instructions

5. Draw the ladder diagram.

6. Input the program into the CPU. When using the Programming Console,
this will involve converting the program to mnemonic form.

7. Check the program for syntax errors and correct these.

8. Execute the program to check for execution errors and correct these.

9. After the entire Control System has been installed and is ready for use,
execute the program and fine tune it if required.

The basics of ladder diagramming are described in the rest of this section.
Converting the program to mnemonic form and debugging are described in

Section 7 Program Input, Debugging, and Execution. Section 8 Troubleshoot-

also provides information required for debugging.

ing

Section 5 Instruction Set

.)

.

5–11 Timer

4–2 Instruction Terminology

There are basically two types of instructions used in ladder-diagram pro­gramming: instructions that correspond to conditions on the ladder diagram
and are used in instruction form only when converting a program to mne­monic code and instructions that are used on the right side of the ladder dia­gram and are executed according to the conditions on the instruction lines
leading to them.

Most instructions have at least one or more operands associated with them.
Operands indicate or provide the data on which an instruction is to be per­formed. These are sometimes input as the actual numeric values, but are
usually the addresses of data area words or bits that contain the data to be
used. For instance, a Move instruction that has IR 00 designated as the
source operand will move the contents of IR 00 to some other location. The
other location is also designated as an operand. A bit whose address is des­ignated as an operand is called an operand bit; a word whose address is
designated as an operand is called an operand word.

Other terms used in describing instructions are introduced in

struction Set

.

4–3 The Ladder Diagram

A ladder diagram consists of one line running down the left side with lines
branching off to the right. The line on the left is called the bus bar; the

Section 5 In-

30

The Ladder Diagram Section 4–3

branching lines, instruction lines. Along the instruction lines are placed condi­tions that lead to other instructions on the right side. The logical combinations
of these conditions determine when and how the instructions at the right are
executed. A simple ladder diagram is shown below.

0000 0315

0001

0100 0002

0010

0011

0003 HR 510 0007 TC 01 0515

HR 109 12031208 1200

0501 0502 0503 0504

1001 1002

1005 1007

1201

0403

Instruction

0405

Instruction

As shown in the diagram above, instruction lines can branch apart and they
can join back together. The vertical pairs of lines are called conditions. Con­ditions without diagonal lines through them are called normal conditions and
correspond to a LOAD, AND, or OR instruction. The conditions with diagonal
lines through them are called inverse or NOT conditions and correspond to a
LOAD NOT, AND NOT, or OR NOT instruction. The number above each con­dition indicates the operand bit for the instruction. It is the status of the bit
associated with each condition that determine the execution condition for fol­lowing instructions. The function of each of the instructions that correspond
to a condition is described below. Before we consider these, however, there
are some basic terms that must be explained.

Note

4–3–1 Basic Terms

Normal and NOT
Conditions

When displaying ladder diagrams with a GPC, a FIT, or LSS, a second bus
bar will be shown on the right side of the ladder diagram and will be con­nected to all instructions on the right side. This does not change the lad­der-diagram program in any functional sense. No conditions can be placed
between the instructions on the right side and the right bus bar, i.e., all in­structions on the right must be connected directly to the right bus bar. Refer
to the

GPC, FIT,

or

LSS Operation Manual

for details.

Each condition in a ladder diagram is either ON or OFF depending on the
status of the operand bit that has been assigned to it. A normal condition is
ON if the operand bit is ON; OFF if the operand bit is OFF. An inverse or
NOT condition is ON if the operand bit is OFF; OFF if the operand bit is ON.
Generally speaking, you use a normal condition when you want something to
happen when a bit is ON and an inverse condition when you want something
to happen when a bit is OFF.

0000

Instruction

Normal condition

0000

Instruction

NOT condition

Instruction is executed
when IR bit 0000 is ON.

Instruction is executed
when IR bit 0000 is OFF.

Execution Conditions

In ladder diagram programming, the logical combination of ON and OFF con­ditions before an instruction determines the compound condition under which

31

The Ladder Diagram Section 4–3

the instruction is executed. This condition, which is either ON or OFF, is
called the execution condition for the instruction. All instructions except for
LOAD instructions have execution conditions.

Operand Bits

The operands designated for any of the ladder instructions can be any bit in
the IR, SR, HR or TC area. This means that the conditions in a ladder dia­gram can be determined by I/O bits, flags, work bits, timers/counters, etc.
Load and Output instructions can also use TR area bits, but they do so only
in special applications. Refer to

Logic Blocks

What conditions correspond to what instructions is determined by the rela­tionship between the conditions established by the instruction lines that con­nect them. Any group of conditions that go together to create a logic result is
called a logic block. Although ladder diagrams can be written without actually
analyzing individual logic blocks, understanding logic blocks is necessary for
efficient programming and is essential when programs are to be input in mne­monic code. Analyzing logic blocks in ladder diagrams and converting ladder
diagrams to mnemonic code is covered in

.

Code

4–3–2 Ladder Instructions

The ladder instructions are those that correspond to the conditions on the
ladder diagram. Ladder instructions, either independently or in combination
with the logic block instructions described next, form the execution conditions
upon which all other instructions are executed.

Load and Load NOT

The first condition that starts any logic block within a ladder diagram corre­sponds to a Load or Load NOT instruction.

4–3–4 Branching Instruction Lines

7–2 Converting to Mnemonic

for details.

AND and AND NOT

0000

A Load instruction.

0000

A Load NOT instruction.

When this is the only condition on the instruction line, the execution condition
for the instruction at the right is ON when the condition is ON. For the Load
instruction (i.e., a normal condition), the execution condition would be ON
when IR 0000 was ON; for the Load NOT instruction (i.e., an inverse condi­tion), it would be ON when IR 0000 was OFF.

When two or more conditions lie in series on the same instruction line, the
first one corresponds to a Load or Load NOT instruction; the rest of the con­ditions, to AND or AND NOT instructions. The following example shows three
conditions which correspond in order from the left to a Load, an AND NOT,
and an AND instruction.

0000 0100 HR 000

Instruction

32

The instruction at the right would have an ON execution condition only when
all three conditions are ON, i.e., when IR 0000 was ON, IR 0100 was OFF,
and HR 000 was ON.

The Ladder Diagram Section 4–3

Actually, AND instructions can be considered individually in series, each of
which would take the logical AND between the execution condition (i.e., the
sum of all conditions up to that point) and the status of the AND instruction’s
operand bit. If both of these were ON, an ON execution condition would be
produced for the next instruction. The execution condition for the first AND
instruction in a series would be the first condition on the instruction line.

Each AND NOT instruction in a series would take the logical AND between
its execution condition and the inverse of its operand bit.

OR and OR NOT

Combining AND and OR
Instructions

When two or more conditions lie on separate instruction lines running in par­allel and then joining together, the first condition corresponds to a Load or
Load NOT instruction; the rest of the conditions correspond to OR or OR
NOT instructions. The following example shows three conditions which corre­spond in order from the top to a Load NOT, an OR NOT, and an OR instruc­tion.

0000

Instruction

0100

HR 000

The instruction at the right would have an ON execution condition when any
one of the three conditions was ON, i.e., when IR 0000 was OFF, when IR
0100 was OFF, or when HR 000 was ON.

OR and OR NOT instructions can also be considered individually, each tak­ing the logical OR between its execution condition and the status of the OR
instruction’s operand bit. If either one of these were ON, an ON execution
condition would be produced for the next instruction.

When AND and OR instructions are combined in more complicated dia­grams, they can sometimes be considered individually, with each instruction
performing a logic operation on the execution condition and the status of the
operand bit. The following is one example.

0200

Here, an AND is taken between the status of 0000 and that of 0001 to deter­mine the execution condition for an OR with the status of 0200. The result of
this operation determines the execution condition for an AND with the status
of 0002, which in turn determines the execution condition for an AND with the
inverse of the status of 0003. In more complicated diagrams, however, it is
necessary to consider logic blocks before an execution condition can be de­termined for the final instruction, and that’s where AND Load and OR Load
instructions are used.

4–3–3 Logic Block Instructions

Logic block instructions do not correspond to specific conditions on the lad­der diagram; rather, they describe relationships between logic blocks. The

0002 00030000 0001

Instruction

33

The Ladder Diagram Section 4–3

AND Load instruction logically ANDs the execution conditions produced by
two logic blocks. The OR Load instruction logically ORs the execution condi­tions produced by two logic blocks.

AND Load

Although simple in appearance, the diagram below requires an AND Load
instruction.

0000

0001

0002

Instruction

0003

The two logic blocks are indicated by dotted lines. Studying this example
shows that an ON execution condition would be produced when both 1)
either of the conditions in the left logic block was ON (i.e., when either 0000
or 0001 was ON) and 2) either of the conditions in the right logic block was
ON (i.e., when either 0002 was ON or 0003 was OFF).

Analyzing the diagram in terms of instructions, the condition at 0000 would
be a Load instruction and the condition below it would be an OR instruction
between the status of 0000 and that of 0001. The condition at 0002 would be
another Load instruction and the condition below this would be an OR NOT
instruction, i.e., an OR between the status or 0002 and the inverse of the
status of 0003. To arrive at the execution condition for the instruction at the
right, the logical AND of the execution conditions resulting from these two
blocks would have to be taken. AND Load allows us to do this. AND Load
always takes an AND between the current execution condition and the last
unused execution condition. An unused execution condition is produced by
using the Load or Load NOT instruction for any but the first condition on an
instruction line.

OR Load

Although we’ll not describe it in detail, the following diagram would require an
OR Load instruction between the top logic block and the bottom logic block.
An ON execution condition would be produced for the instruction at the right
either when 0000 was ON and 0001 was OFF or when 0002 and 0003 were
both ON.

0000 0001

0002 0003

Naturally, some diagrams will require both AND Load and OR Load instruc­tions.

4–3–4 Branching Instruction Lines

When an instruction line branches into two or more lines, it is sometimes
necessary to use either interlocks or TR bits to maintain the execution condi­tion that existed at a branching point. This is because instruction lines are
executed across to a terminal instruction on the right before returning to
branching points to execute instructions on the branch lines. If the execution
condition has changed during this time, the previous execution condition is
lost and proper execution will not be possible without some means of pre-

Instruction

34

The Ladder Diagram Section 4–3

serving the previous condition. The following diagrams illustrate this. In both
diagrams, instruction 1 is executed before returning to the branching point
and moving on to the branch line leading to instruction 2.

Branching

0000

0000

If, as shown in diagram A, the execution condition that existed at the branch­ing point is not changed before returning to the branch line (instructions at
the far right do not change the execution condition), then the branch line will
be executed correctly and no special programming measure is required.

point

Branching

point

Instruction 1

0002

Instruction 2

Diagram A: OK

0001

Instruction 1

0002

Instruction 2

Diagram B: Needs Correction

TR Bits

If, as shown in diagram B, a condition exists between the branching point
and the last instruction on the top instruction line, the execution condition at
the branching point and the execution condition at the end of the top line will
sometimes be different, making it impossible to ensure correct execution of
the branch line. The system remembers only the current execution condition
(i.e., the logical sum for an entire line) and does not remember partial logical
sums at points within a line.

There are two means of programming branching programs to preserve the
execution conditions. One is to use TR bits; the other, to use interlocks.

The TR area provides eight bits, TR 0 through TR 7, that can be used to tem­porarily preserve execution conditions. If a TR bit is used as the operand of
the Output instruction placed at a branching point, the current execution con­dition will be stored at the designated TR bit. Storing execution conditions is
a special application of the Output instruction. When returning to the branch­ing point, the same TR bit is then used as the operand of the Load instruction
to restore the execution condition that existed when the branching point was
first reached in program execution.

The above diagram B can be written as shown below to ensure correct exe­cution.

0000

TR 0

0001

Instruction 1

0002

Instruction 2

Diagram B: Corrected Using a TR bit

In terms of actual instructions the above diagram would be as follows: The
status of 0000 is loaded (a Load instruction) to establish the initial execution
condition. This execution condition is then output using an Output instruction
to TR 0 to store the execution condition at the branching point. The execution
condition is then ANDed with the status of 0001 and instruction 1 is executed

35

The Ladder Diagram Section 4–3

accordingly. The execution condition that was stored at the branching point is
then loaded back in (a Load instruction with TR 0 as the operand) and in­struction 2 is executed accordingly.

The following example shows an application using two TR bits.

0000 0002

TR 0

0001

0004

0005

TR 1

Instruction 1

0003

Instruction 2

Instruction 3

Instruction 4

In this example, TR 0 and TR 1 are used to store the execution conditions at
the branching points. After executing instruction 1, the execution condition
stored in TR 1 is loaded for an AND with the status 0003. The execution con­dition stored in TR 0 is loaded twice, the first time for an AND with the status
of 0004 and the second time for an AND with the inverse of the status of

0005.

TR bits can be used as many times as required as long as the same TR bit is
not used more than once in the same instruction block. Here, a new instruc­tion block is begun each time execution returns to the bus bar. If more than
eight branching points requiring that the execution condition be saved are
necessary in a single instruction block, interlocks, which are described next,
must be used.

When drawing a ladder diagram, be careful not to use TR bits unless neces­sary. Often the number of instructions required for a program can be reduced
and ease of understanding a program increased by redrawing a diagram that
would otherwise required TR bits. With both of the following pairs of dia­grams, the versions on the top require fewer instructions and do not require
TR bits. The first example achieves this by merely reorganizing the parts of
the instruction block; the second, by separating the second Output instruction
and using another Load instruction to create the proper execution condition
for it.

0000

0000

TR 0

0001

Instruction 1

Instruction 2

Instruction 2

0001

Instruction 1

36

The Ladder Diagram Section 4–3

0000

0001

TR bits are only used when programming using mnemonic code and are not

Note

TR 0

0002

0004

0001 0003

0000

0001

0002

0004

0003

Instruction 1

Instruction 2

Instruction 1

Instruction 2

necessary when inputting ladder diagrams directly, as is possible from a
GPC. The above limitations on the number of branching points requiring TR
bits and considerations on methods to reduce the number of programming
instructions still hold.

Interlocks

The problem of storing execution conditions at branching points can also be
handled by using the Interlock (IL(02)) and Interlock Clear (ILC(03)) instruc­tions. When an Interlock instruction is placed at a branching point of an in­struction line and the execution condition for the Interlock instruction is ON,
each branch line is established as an new instruction line, with the first condi­tion on each branch line corresponding to a Load or Load NOT instruction. If
the execution condition for the Interlock instruction is OFF, all instructions on
the right side of the branch lines leading from the branching point receive an
OFF execution condition through the first Interlock Clear instruction. The ef­fect that this has on particular instructions is described in

5–7 Interlock and

Interlock Clear – IL(02) and ILC(03).

Diagram B from the above example can also be corrected with an interlock.
As shown below, this requires one more instruction line for the Interlock Clear
instruction.

0000

IL(02)

0001

0002

Diagram B: Corrected with an Interlock

Instruction 1

Instruction 2

ILC(03)

If 0000 is ON in the above version of diagram B, the status of 0001 and that
of 0002 would determine the execution conditions for instructions 1 and 2,
respectively, on independent instruction lines. Because here 0000 is ON, this
would produce the same results as ANDing the status of each of these bits,
as would occur if the interlock was not used, i.e., the Interlock and Interlock

37

The Ladder Diagram Section 4–3

Clear instructions would not affect execution. If 0000 is OFF, the Interlock
instruction would produce an OFF execution condition for instructions 1 and
2 and then execution would continue with the instruction line following the
Interlock Clear instruction.

As shown in the following diagram, more than one Interlock instruction can
be used within one instruction block; each is effective from its branching point
through the next Interlock Clear instruction.

0000

IL(02)

0002

0001

IL(02)

0003

0005

0006

Instruction 1

0004

Instruction 2

Instruction 3

Instruction 4

ILC(03)

If 0000 in the above diagram was OFF (i.e., if the execution condition for the
first Interlock instruction was OFF), instructions 1 through 4 would be exe­cuted with OFF execution conditions and execution would move to the in­struction following the Interlock Clear instruction. If 0000 was ON, the status
of 0001 would be loaded to form the execution condition for instruction 1 and
then the status of 0002 would be loaded to form the first execution status for
that instruction line, i.e., the execution condition for the second Interlock in­struction. If 0002 was OFF, instructions 2 through 4 would be executed with
OFF execution conditions. If 0002 was ON, 0003, 0005, and 0006 would
each start a new instruction line.

Because all branch lines following branching points with Interlock instructions
form independent instruction lines, interlocked sections of programs can be
redrawn without branching points. The following diagram executes exactly
like the one above and would be input in exactly the same order using the
same instructions.

38

0000

0001

0002

0003

0005

0006

0004

IL(02)

Instruction 1

IL(02)

Instruction 2

Instruction 3

Instruction 4

ILC(03)

This type of interlock diagram appears when inputting ladder diagrams di­rectly, as is possible from a GPC.

The Ladder Diagram Section 4–3

It’s interesting to notice that if any instructions are added to an interlocked
section of a diagram, they in essence branch from the branching point where
the Interlock instruction is located, regardless of whether they are drawn that
way or whether they are drawn connected directly to the bus bar. If we add a
third instruction between instruction 2 and the Interlock Clear instruction to
diagram B from above, we can connected it either as another branch line fol­lowing the branch line for instruction 2 or directly to the bus bar. In either
case, the diagram, when rewritten into the type of display shown above for
GPC displays, would be the same. Both diagrams would naturally execute
exactly the same.

0000

0003

IL(02)

0001

0002

Instruction 1

0000

Instruction 2

Instruction 3

ILC(03)

0000

0001

0002

0003

IL(02)

IL(02)

Instruction 1

Instruction 2

Instruction 3

ILC(03)

0001

0002

0003

When drawing interlocked sections of ladder diagrams, either form may be
used. The non-branching form will be used in the remainder of this manual.

Instruction 1

Instruction 2

Instruction 3

ILC(03)

4–3–5 Jumps

A specific section of a program can be skipped according a designated exe­cution condition. Although this is similar to what happens when the execution
condition for an Interlock instruction is OFF, with jumps, the operands for all
instructions maintain status. Jumps can therefore be used to control devices
that require a sustained output, e.g., pneumatics and hydraulics, whereas
interlocks can be used to control devices that do not required a sustained
output, e.g., electronic instruments.

Jumps are created using the Jump (JMP(04)) and Jump End (JME(05)) in­structions. If the execution condition for a Jump instruction is ON, the pro­gram is executed normally as if the jump did not exist. If the execution condi­tion for the Jump instruction is OFF, program execution moves immediately
to a Jump End instruction without changing the status of anything between
the Jump and Jump End instruction.

In the following example, Instructions 1 and 2 would not be executed when
IR 0000 is OFF and execution would skip immediately to the Jump End in­struction without change the status of any bits or words in between. If IR
0000 is ON, the program would be executed as if the jump did not exist.

39

Controlling Bit Status Section 4–4

0000

0001

0002

JMP(04)

Instruction 1

Instruction 2

JME(05)

Diagram B: Corrected with a Jump

Execution of programs containing multiple Jump instructions for one Jump
End instruction resembles that of similar interlocked sections. The following
diagram is the same as that used for the interlock example above, except
redrawn with jumps. This diagram, however, would not execution the same,
as has already be described, i.e., interlocks would reset certain parts of the
interlocked section but jumps would not affect any status between the Jump
and Jump End instructions.

0000

0001

0002

JMP(04) 00

Instruction 1

JMP(04) 00

0003

0005

0006

Jump diagrams can also be drawn as branching instruction lines if desired
and would look exactly like their interlock equivalents. The non-branching
form, which is the form displayed on the GPC, will be used in this manual.

4–4 Controlling Bit Status

There are five instructions that can be used generally to control individual bit
status. These are the Output or OUT, Output NOT or OUT NOT, Differentiate
Up, Differentiate Down, and Keep instructions. All of these instruction appear
as the last instruction in an instruction line and take a bit address for an oper­and. Although details are provided in
structions are described here because of their importance in most programs.
Although these instructions are used to turn ON and OFF output bits in the IR
area (i.e., to send or stop output signals to external devices), they are also
used to control the status of other bits in the IR area or in other data areas.

0004

Instruction 2

Instruction 3

Instruction 4

JME(05) 00

5–6 Bit Control Instructions

, these in-

4–4–1 OUT and OUT NOT

The OUT and OUT NOT instructions are used to control the status of the
designated operand bit according to the execution condition. With the OUT
instruction, the operand bit will be turned ON as long as the execution condi-

40

Controlling Bit Status Section 4–4

tion is ON and will be turned OFF as long as the execution condition is OFF.
With the OUT NOT instruction, the operand bit will be turned ON as long as
the execution condition is OFF and turned OFF as long as the execution con­dition is ON. These appear as follows:

0000

0001

In the above examples, bit 0500 will be ON as long as 0000 is ON and bit
0501 will be OFF as long as 0001 is ON. Here, 0000 and 0001 would be in­put bits and 0500 and 0501 output bits assigned to the Units controlled by
the PC, i.e., the signals coming in through the input points assigned 0000
and 0001 are controlling the output points assigned 0500 and 0501, respec­tively.

The length of time that a bit is ON or OFF can be controlled by combining the
OUT or OUT NOT instruction with Timer instructions. Refer to Examples un-

5–11–1 Timer – TIM

der

for details.

4–4–2 Differentiate Up and Differentiate Down

Differentiate Up and Differentiate Down instructions are used to turn the op­erand bit ON for one scan at a time. The Differentiate Up turns ON the oper­and bit for one scan after the execution condition when it goes from OFF to
ON; the Differentiate Down instruction turns ON the operand bit for one scan
after the execution condition when it goes from ON to OFF. The following ex­ample shows the same I/O bits as above, but this time they are controlled by
Differentiate Up and Down instructions.

0100

0101

4–4–3 Keep

0000

DIFU(13) 0500

0001

DIFD(14) 0501

Here, 0500 will be turned ON for one scan after 0000 goes ON. The next
time DIFU(13) 0500 is executed, 0500 will be turned OFF, regardless of the
status of 0000. With the Differentiate Down instruction, 0501 will be turned
ON for one scan after 0001 goes OFF (0501 will be kept OFF until then) and
will be turned ON the next time DIFD(14) is executed.

The Keep instruction is used to maintain the status of the operand bit based
on two execution conditions. To do this, the Keep instruction is connected to
two instruction lines. When the execution condition at the end of the first in­struction line is ON, the operand bit of the Keep instruction is turned ON.
When the execution condition at the end of the second instruction line is ON,
the operand bit of the Keep instruction is turned OFF. The operand bit for the
Keep instruction will maintain its ON or OFF status even if it is located in an
interlocked section of the diagram and the execution condition for the Inter­lock instruction is ON.

41

The End Instruction Section 4–5

In the following example, HR 000 will be turned ON when 0002 is ON and
0003 is OFF. HR 000 will then remain ON until either 0004 or 0005 turns ON.

4–4–4 Self-maintaining Bits

Although the Keep instruction can be used to create self-maintaining bits, it is
sometimes necessary to create self-maintaining bits in another way so that
they can be turned OFF when in an interlocked section of a program.

To create a self-maintaining bit, the operand bit of an Output instruction is
used as a condition for the same Output instruction in an OR setup so that
the operand bit of the Output instruction will remain ON or OFF until changes
in other bits occur. At least one other condition is used just before the Output
instruction to function as a reset. Without this reset, there would be no way to
control the operand bit of the Output instruction.

The above diagram for the Keep instruction can be rewritten as shown below.
The only difference in these diagrams would be their operation in an inter­locked program section when the execution condition for the Interlock in­struction was ON. Here, just as in the same diagram using the Keep instruc­tion, two reset bits are used, i.e., HR 000 is turned OFF by turning ON both
0004 and 0005.

0002

0004

0005

0003

S: set input

R: reset input

KEEP(11)

HR 000

0002 0003

HR 000

4–5 The End Instruction

The last instruction in any program must be the End instruction. When the
CPU scans the program, it executes all instructions up to the first End in­struction before returning to the beginning of the program and beginning exe­cution again. Although an End instruction can be placed at any point in a pro­gram, which is sometimes done when debugging, no instructions past the
first End instruction will be executed until it is removed.

0000 0001

0004

0005

Instruction

END(01)

HR 000

Program execution
ends here.

42

Programming Precautions Section 4–6

If there is no End instruction anywhere in the program, the program will not
be executed at all.

4–6 Programming Precautions

The number of conditions that can be used in series or parallel is unlimited.
Therefore, use as many conditions as required to draw a clear diagram. Al­though very complicated diagrams can be drawn with instruction lines almost
forming mazes, there must not be any conditions on instruction lines running
vertically between two other instruction lines. Diagram A shown below, for
example, is not possible, and should be redrawn as diagram B.

0000

0004

0001

0002

Instruction 1

0003

Instruction 2

Diagram A

0001

0000

0001

0004

00040000

0002

Instruction 1

0003

Instruction 2

Diagram B

The number of times any particular bit can be assigned to conditions is not
limited, so use them as many times as required to simplify your program.
Often, complicated programs are the result of attempts to reduce the number
of times a bit is used.

Every instruction line must also have at least one condition on it to determine
the execution condition for the instruction at the right. Again, diagram A , be­low, must be redrawn as diagram B. If an instruction must always be exe­cuted (e.g., if an output must always be kept ON while the program is being
executed), the Always ON Flag (1813) in the SR area can be used.

Instruction

Diagram A

1813

Instruction

Diagram B

There are, however, a few exceptions to this rule, including the Interlock
Clear, Jump End, and Step Instructions. Each of these instructions is used as
the second of a pair of instructions and is controlled by the execution condi-

43

Program Execution Section 4–7

tion of the first of the pair. Conditions should not be placed on the instruction
lines leading to these instructions. Refer to

Section 5 Instruction Set

tails.
When drawing ladder diagrams, it is important to keep in mind the number of

instructions that will be required to input it. In diagram A, below, an OR Load
instruction will be required to combine the top and bottom instruction lines.
This can be avoided by redrawing as shown in diagram B so that no AND
Load or OR Load instructions are required. Refer to

OR Load
Program

for more details and

for further examples.

7–5 Inputting, Modifying and Checking the

5–5–2 AND Load and

for de-

0000

0001 0207

0001

0207

0000

4–7 Program Execution

When program execution is started, the CPU scans the program from top to
bottom, checking all conditions and executing all instructions accordingly as it
moves down the bus bar. It is important that instructions be placed in the
proper order so that, for example, the desired data is moved to a word before
that word is used as the operand for an instruction. Remember that an in­struction line is completed to the terminal instruction at the right before exe­cuting any instruction lines branching from the first instruction line to other
terminal instructions at the right.

0207

Diagram A:

0207

Diagram B:

44

Program execution is only one of the tasks carried out by the CPU as part of
the scan time. Refer to

Section 6 Program Execution Timing

for details.

SECTION 5

Instruction Set

5–1 Introduction 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–2 Notation 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–3 Instruction Format 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–4 Data Areas, Definer Values, and Flags 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–5 Ladder Diagram Instructions 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–5–1 Load, Load NOT, AND, AND NOT, OR, and OR NOT 48 . . . . . . . . . . .

5–5–2 AND Load and OR Load 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–6 Bit Control Instructions 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–6–1 Output and Output NOT – OUT and OUT NOT 49 . . . . . . . . . . . . . . . . .

5–6–2 Differentiate Up and Down – DIFU(13) and DIFD(14) 50 . . . . . . . . . . . .

5–6–3 Keep – KEEP(11) 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–7 Interlock and Interlock Clear – IL(02) and ILC(03) 53 . . . . . . . . . . . . . . . . . . . . . . .

5–8 Jump and Jump End – JMP(04) and JME(05) 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–9 End – END(01) 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–10 No Operation – NOP(00) 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–11 Timer and Counter Instructions 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–11–1 Timer – TIM 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–11–2 High-speed Timer – TIMH(15) 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–11–3 Analog Timer Unit 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–11–4 Counter – CNT 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–11–5 Reversible Counter – CNTR(12) 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–11–6 High-speed Counter – HDM(98) 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–12 Data Shifting 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–12–1 Shift Register – SFT(10) 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–12–2 Word Shift – WSFT(16) 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–13 Data Movement 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–13–1 Move – MOV(21) 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–13–2 Move NOT – MVN(22) 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–14 Data Compare – CMP(20) 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–15 Data Conversion 84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–15–1 BCD to Binary – BIN(23) 84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–15–2 Binary to BCD – BCD(24) 85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–15–3 4-to-16 Decoder – MLPX(76) 85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–15–4 16-to-4 Encoder – DMPX(77) 87 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–16 BCD Calculations 89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–16–1 BCD Add – ADD(30) 90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–16–2 BCD Subtract – SUB(31) 92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–16–3 Set Carry – STC(40) 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–16–4 Clear Carry – CLC(41) 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

45

Instruction Format Section 5–3

5–1 Introduction

The P-type PCs have large programming instruction sets that allow for easy
programming of complicated control processes. This section explains each
instruction individually and provides the ladder diagram symbol, data areas,
and flags used with each. Basic application examples are also provided as
required in describing the instructions.

The many instructions provided by the P-type PCs are described in following
subsections by instruction group. These groups include Ladder Diagram In­structions, Bit Control Instructions, Timer and Counter Instructions, Data
Shifting, Data Movement, Data Comparison, Data Conversion, BCD Calcula­tions, Subroutines, Step Instructions, and Special Instructions.

Some instructions, such as Timer and Counter instructions, are used to con­trol execution of other instructions, e.g., a TIM Completion Flag might be
used to turn ON a bit when the time period set for the timer has expired. Al­though these other instructions are often used to control output bits through
the Output instruction, they can be used to control execution of other instruc­tions as well. The Output instructions used in examples in this manual can
therefore generally be replaced by other instructions to modify the program
for specific applications other than controlling output bits directly.

5–2 Notation

In the remainder of this manual, all instructions will be referred to by their
mnemonics. For example, the Output instruction will be called OUT; the AND
NOT instruction, AND NOT. If you’re not sure of what instruction a mnemonic
is used for, refer to

If an instruction is assigned a function code, it will be given in parentheses
after the mnemonic. These function codes, which are 2-digit decimal num­bers, are used to input most instructions into the CPU and are described
briefly below and in more detail in

Program

vided in

. A table of instructions listed in order of function codes is also pro-

Appendix B Programming Instructions

5–3 Instruction Format

Most instructions have at least one or more operands associated with them.
Operands indicate or provide the data on which an instruction is to be per­formed. These are sometimes input as the actual numeric values (i.e., as
constants), but are usually the addresses of data area words or bits that con­tain the data to be used. A bit whose address is designated as an operand is
called an operand bit; a word whose address is designated as an operand is
called an operand word. In some instructions, the word address designated
in an instruction indicates the first of multiple words containing the desired
data.

Each instruction requires one or more words in Program Memory. The first
word is the instruction word, which specifies the instruction and contains any
definers (described below) or operand bits required by the instruction. Other
operands required by the instruction are contained in following words, one
operand per word. Some instructions require up to four words.

A definer is an operand associated with an instruction and contained in the
same word as the instruction itself. These operands define the instruction
rather than telling what data it is to be used. Examples of definers are TC
numbers, which are used in timer and counter instructions to create timer
and counter. Bit operands are also contained in the same word as the in­struction itself, although these are not considered definers.

Appendix B Programming Instructions

7–5 Inputting, Modifying and Checking the

.

.

46

Ladder Diagram Instructions Section 5–5

5–4 Data Areas, Definer Values, and Flags

Each instruction is introduced with the ladder diagram symbol(s), the data
areas that can be used with any operand(s), and the values that can be used
for definers. With the data areas is also specified the operand names and the
type of data required for each operand (i.e., word or bit and, for words, hexa­decimal or BCD).

Not all addresses in a specified data area are necessarily allowed in an oper­and, e.g., if an operand requires two words, the last word in a data area can­not be designated because all words for a single operand must be in the
same data area. Unless a limit is specified, any bit/word in the area can be
used. Specific limitations for operands and definers are specified in a

subsection. Refer to

tions

tions and the addresses of flags and control bits.
The IR and SR areas are considered as separate areas and both are not

Note

necessarily allowed for an operand just because one of them is. The boarder
between the IR and SR area can, however, be crossed for a single operand,
i.e., the last bit in the IR area may be specified for an operand that requires
more than one word as long as the SR area is also allowed for that operand.

Section 3 Memory Areas

for addressing conven-

Limita-

Designating Constants

Flags

The
tion. These flags include the following SR area flags.

Abbreviation Name Bit

ER Instruction Execution Error Flag 1903
CY Carry Flag 1904
EQ Equals Flag 1906
GR Greater Than Flag 1905
LE Less Than Flag 1907

ER is the flag most often used for monitoring an instruction’s execution.
When ER goes ON, it indicates that an error has occurred in attempting to
execute the current instruction. The
possible reasons for ER being ON. ER will turn ON for any instruction if oper­ands are not input within established parameters. Instructions are not exe­cuted when ER is ON. A table of instructions and the flags they affect is pro­vided in

Although data area addresses are most often given as operands, many oper­ands can be input and all definers are input as constants. The range in which
a number can be specified for a given definer or operand depends on the
particular instruction that uses it. Constants must also be input in the form
required by the instruction, i.e., in BCD or in hexadecimal.

subsection lists flags that are affected by execution of the instruc-

Flags

subsection of each instruction lists

Appendix D Error and Arithmetic Flag Operation

.

5–5 Ladder Diagram Instructions

Ladder diagram instructions include ladder instructions and logic block in­structions. Ladder instructions correspond to the conditions on the ladder
diagram. Logic block instructions are used to relate more complex parts of
the diagram that cannot be programmed with ladder instructions alone.

47

Ladder Diagram Instructions Section 5–5

5–5–1 Load, Load NOT, AND, AND NOT, OR, and OR NOT

Load – LD

Load NOT – LD NOT

AND – AND

AND NOT – AND NOT

Ladder Symbol Operand Data Areas

B

B: Bit

IR, SR, HR, TC, TR

Ladder Symbol Operand Data Areas

B

B: Bit

IR, SR, HR, TC, TR

Ladder Symbol Operand Data Areas

B

B: Bit

IR, SR, HR, TC, TR

Ladder Symbol Operand Data Areas

B

B: Bit

IR, SR, HR, TC, TR

OR – OR

OR NOT – OR NOT

Limitations

Description

Ladder Symbol Operand Data Areas

B: Bit

B

IR, SR, HR, TC, TR

Ladder Symbol Operand Data Areas

B: Bit

B

IR, SR, HR, TC, TR

There is no limit in the number of any of these instructions or in the order in
which they must be used as long as the capacity of the PC is not exceeded.

These six basic instructions correspond to the conditions on a ladder dia­gram. As described in

Section 4 Programming

, the status of the bits assigned
to each instruction determines the execution conditions for all other instruc­tions. Each of these instructions can be used as many times and a bit ad­dress can be used in as many of these instructions as required.

The status of the bit operand (B) assigned to LD or LD NOT determines the
first execution condition. AND takes the logical AND between the execution
condition and the status of its bit operand; AND NOT, the logical AND be­tween the execution condition and the inverse of the status of its bit operand.
OR takes the logical OR between the execution condition and the status of its
bit operand; OR NOT, the logical OR between the execution condition and
the inverse of the status of its bit operand. The ladder symbol for loading TR
bits is different from that shown. See

4–3–2 Ladder Instructions

for details.

Flags

48

There are no flags affected by these instructions.

Bit Control Instructions Section 5–6

5–5–2 AND Load and OR Load

AND Load – AND LD

OR Load – OR LD

Description

0002

0003

Ladder Symbol

Ladder Symbol

0000

0001

0000 0001

0002 0003

When the above instructions are combined into blocks that cannot be logi­cally combined using only OR and AND operations, AND LD and OR LD are
used. Whereas AND and OR operations logically combine a bit status and an
execution condition, AND LD and OR LD logically combine two execution
conditions, the current one and the last unused one.

AND LD and OR LD instruction are not necessary to draw ladder diagrams,
nor are they necessary when inputting ladder diagrams directly, as is possi­ble from the GPC. They are required, however, to convert the program to and
input it in mnemonic form. The procedures for these, limitations for different
procedures, and examples are provided in

Checking the Program

.

7–5 Inputting, Modifying and

In order to reduce the number of programming instruction required, a basic
understanding of logic block instructions is required. For an introduction to
logic blocks, refer to

7–2–3 Logic Block Instructions

.

Flags

There are no flags affected by these instructions.

5–6 Bit Control Instructions

There are five instructions that can be used generally to control individual bit
status. These are OUT, OUT NOT, DIFU(13), DIFD(14), and KEEP(11).
These instructions are used to turn bits ON and OFF in different ways.

5–6–1 Output and Output NOT – OUT and OUT NOT

Output – OUT

Output NOT –
OUT NOT

Limitations

Ladder Symbol Operand Data Areas

B

Ladder Symbol Operand Data Areas

B

Any output bit can be used in only one instruction that controls its status. See

3–3–1 I/O Words

for details.

B: Bit

IR, HR, TR

B: Bit

IR, HR, TR

Description

OUT and OUT NOT are used to control the status of the designated bit ac­cording to the execution condition.

49

Bit Control Instructions Section 5–6

OUT turns ON the designated bit for a ON execution condition, and turns
OFF the designated bit for an OFF execution condition. OUT with a TR bit
appears at a branching point rather than at the end of an instruction line. Re-

4–3–4 Branching Instruction Lines

fer to
OUT NOT turns ON the designated bit for a OFF execution condition, and

turns OFF the designated bit for an ON execution condition.
OUT and OUT NOT can be used to control execution by turning ON and OFF

bits that are assigned to conditions on the ladder diagram, thus determining
execution conditions for other instructions. This is particularly helpful when a
complex set of conditions can be used to control the status of a single work
bit, and then that work bit can be used to control other instructions.

The length of time that a bit is ON or OFF can be controlled by combining the
OUT or OUT NOT with TIM. Refer to Examples under
for details.

for details.

5–11–1 Timer – TIM

Flags

There are no flags affected by these instructions.

5–6–2 Differentiate Up and Down – DIFU(13) and DIFD(14)

Ladder Symbol Operand Data Areas

DIFU(13) B

Ladder Symbol Operand Data Areas

DIFD(14) B

Limitations

Description

Any output bit can be used in only one instruction that controls its status. See

3–3–1 I/O Words

DIFU(13) and DIFD(14) are used to turn the designated bit ON for one scan
only.

Whenever executed, DIFU(13) compares its current execution with the previ­ous execution condition. If the previous execution condition was OFF and
and current one is ON, DIFU(13) will turn ON the designated bit. If the previ­ous execution condition was ON and the current execution condition is either
ON or OFF, DIFU(13) will turn the designated bit OFF or do nothing (i.e., if
the designated bit is already OFF). The designated bit will thus never be ON
for longer than one scan assuming it is executed each scan (see Precau­tions, below).

for details.

B: Bit

IR, HR

B: Bit

IR, HR

50

Whenever executed, DIFD(14) compares its current execution with the previ­ous execution condition. If the previous execution condition was ON and the
current one is OFF, DIFD(14) will turn ON the designated bit. If the previous
execution condition was OFF and the current execution condition is either
ON or OFF, DIFD(14) will turn the designated bit OFF or do nothing (i.e., if
the designated bit is already OFF). The designated bit will thus never be ON
for longer than one scan.

These instructions are used when a single-scan execution of a particular in­struction is desired. Examples of these are shown below.

Bit Control Instructions Section 5–6

DIFU(13) and DIFD(14) operation can be tricky when used in programming
between IL and ILC, between JMP and JME, or in subroutines. Refer to

and

Interlock and Interlock Clear – IL(02) and ILC(03)
End – JMP(04)/JME(05)

for details. A total of 48 DIFU(13)/DIFD(14) can be

5–8 Jump and Jump

used in a program. If more than 48 are used in a program only the first 48 will
be executed and all others will be ignored. DIFU(13)/DIFD(14) are useful
when used in conjunction with CMP(20) or MOV(21), see

Example

5–7

below.

Flags

Example

There are no flags affected by these instructions.

In diagram A, below, CMP(20) will compare the contents of the two operand
words (HR 1 and DM 00) whenever it is executed with an ON execution con­dition and set the arithmetic flags (GR, EQ, and LE) accordingly. If the execu­tion condition remains ON, flag status may be changed each scan if the con­tents of one or both operands change. Diagram B, however, shows how
DIFU(13) can be used to ensure that CMP(20) is executed only once each
time the desired execution condition goes ON.

0000

Diagram A

0000

1000

Diagram B

CMP(20)

HR 1

DM 00

DIFU(13) 1000

CMP(20)

HR 1

DM 00

5–6–3 Keep – KEEP(11)

Limitations

Description

Any output bit can be used in only one instruction that controls its status. See

3–3–1 I/O Words

KEEP(11) is used to maintain the status of the designated bit based on two
execution conditions. These execution conditions are labeled S and R. S is
the set input; R, the reset input. KEEP(11) operates like a latching relay that
is set by S and reset by R.

When S turns ON, the designated bit will go ON and stay ON until reset, re­gardless of whether S stays ON or goes OFF. When R turns ON, the desig­nated bit will go OFF and stay OFF until reset, regardless of whether R stays
ON or goes OFF. The relationship between execution conditions and
KEEP(11) bit status is shown below.

Ladder Symbol Operand Data Areas

KEEP(11)

S

B

R

B: Bit

IR, HR

for details.

51

Bit Control Instructions Section 5–6

S execution condition

R execution condition

Status of B

Notice that KEEP(11) operates like a self-maintaining bit. The following two
diagrams would function identically, though the one using KEEP(11) requires
one less instruction to program and would maintain status even in an inter­locked program section.

Flags

Precautions

0002 0003

0500

0002

0003

0500

S

KEEP

0500

R

There are no flags affected by this instruction.

Never use an input bit in an inverse condition on the reset (R) for KEEP(11)
when the input device uses an AC power supply. The delay in shutting down
the PC’s DC power supply (relative to the AC power supply to the input de­vice) can cause the designated bit of KEEP(11) to be reset. This situation is
shown below.

Input Unit

A

NEVER

KEEP

S

HR

000

A

R

Example

52

Bits used in KEEP are not reset in interlocks. Refer to the

IL(02) and ILC(03

) for details.

5–7 Interlock –

If a HR bit is used, bit status will be retained even during a power interrup­tion. KEEP(11) can thus be used to program bits that will maintain status af­ter restarting the PC following a power interruption. An example of this that
can be used to produce a warning display following a system shutdown for
an emergency situation is shown below. Bits 0002, 0003, and 0004 would be
turned ON to indicate some type of system error. Bit 0005 would be turned
ON to reset the warning display. HR 000, which is turned ON for any of the
three bits which indicates emergency situation, is used to turn ON the warn­ing indicator through 0500.

Interlock and Interlock Clear Section 5–7

0002

0003

0004

Reset input

0005

HR 000

Indicates
emergency
situation

S

KEEP

HR 000

0500

KEEP(11) can also be combined with TIM to produce delays in turning bits
ON and OFF. Refer to

5–11–1 Timer – TIM

for details.

5–7 Interlock and Interlock Clear – IL(02) and ILC(03)

Ladder Symbol

IL(02)

R

Activates
warning
display

Description

Ladder Symbol

ILC(03)

IL(02) is always used in conjunction with ILC(03) to create interlocks. Inter­locks are used to enable branching in the same way as can be achieved with
TR bits, but treatment of instructions between IL(02) and ILC(03) differs from
that with TR bits when the execution condition for IL(02) is OFF. If the execu­tion condition of IL(02) is ON, the program will be executed as written, with
an ON execution condition used to start each instruction line from the point
where IL(02) is located through ILC(03). Refer to

tion Lines

for basic descriptions of both methods.

4–3–4 Branching Instruc-

If the execution condition for IL(02) condition is OFF, the interlocked section
between IL(02) and ILC(03) will be treated as shown in the following table:

Instruction Treatment

OUT and OUT NOT Designated bit turned OFF.
TIM and TIMH(15) Reset.
CNT, CNTR(12) PV maintained.
KEEP(11) Bit status maintained.
DIFU(13) and DIFD(14) Not executed (see below).
All others Not executed.

DIFU(13) and DIFD(14) in
Interlocks

IL(02) and ILC(03) do not necessarily have to be used in pairs. IL(02) can be
used several times in a row, with each IL(02) creating an interlocked section
through the next ILC(03). ILC(03) cannot be used unless there is at least one
IL(02) between it and any previous ILC(03).

Changes in the execution condition for a DIFU(13) or DIFD(14) are not re­corded if the DIFU(13) or DIFD(14) is in an interlocked section and the exe-

53

Interlock and Interlock Clear Section 5–7

cution condition for the IL(02) is OFF. When DIFU(13) or DIFD(14) is ex­ecuted in an interlocked section immediately after the execution condition for
the IL(02) has gone ON, the execution condition for the DIFU(13) or
DIFD(14) will be compared to the execution condition that existed before the
interlock became effective (i.e., before the interlock condition for IL(02) went
OFF). The ladder diagram and bit status changes for this are shown below.
The interlock is in effect while 0000 is OFF. Notice that 1000 is not turned ON
at the point labeled A even though 0001 has turned OFF and then back ON.

Precautions

0000

0001

IL(02)

DIFU(13) 1000

ILC(03)

A

ON

0000

0001

1000

OFF

ON
OFF

ON
OFF

There must be an ILC(03) following any one or more IL(02).
Although as many IL(02) as necessary can be used with one ILC(03),

ILC(03) cannot be used consecutively without at least one IL(02) in between,
i.e., nesting is not possible. Whenever a ILC(03) is executed, all interlocks
are cleared.

When more than one IL(02) is used with a single ILC(03), an error message
will appear when the program check is performed, but execution will proceed
normally.

Flags

Example

54

There are no flags affected by these instructions.

The following diagram shows IL(02) being used twice with one ILC(03).

0000

0001

0002

0003

0100

0005

0004

CP

R

IL(02)

TIM 11

IL(02)

CNT 01

0502

ILC(03)

001.5 s

10

Jump and Jump End Section 5–8

When the execution condition for the first IL(02) is OFF, TIM 11 will be reset
to 1.5 s, CNT 01 will not be changed, and 0502 will be turned OFF. When the
execution condition for the first IL(02) is ON and the execution condition for
the second IL(02) is OFF, TIM 11 will be executed according to the status of
0001, CNT 01 will not be changed, and 0502 will be turned OFF. When the
execution conditions for both the IL(02) are ON, the program will execute as
written.

5–8 Jump and Jump End – JMP(04) and JME(05)

Ladder Symbols

JMP(04) JME(05)

Limitations

Description

DIFU(13) and DIFD(14) in
Jumps

A maximum of eight jumps are allowable in any program.

JMP(04) is always used in conjunction with JME(05) to create jumps, i.e., to
skip from one point in a ladder diagram to another point. JMP(04) defines the
point from which the jump will be made; JME(05) defines the destination of
the jump. When the execution condition for JMP(04) in ON, no jump is made
and the program is executed as written. When the execution condition for
JMP(04) is OFF, a jump is made to the the JME(05) with the same jump
number and the instruction following JME(05) is executed next.

Jumps, when made, will go immediately from JMP(04) to JME(05) without
executing any instructions in between. The status of timers, counters, bits
used in OUT, bits used in OUT NOT, and all other status controlled by the
instructions between JMP(04) and JME(05) will not be changed. As all of the
instructions between JMP(04) and JME(05) are skipped, jumps can be used
to reduce scan time.

Although DIFU(13) and DIFD(14) are designed to turn ON the designated bit
for one scan, they will not necessarily do so when written between JMP(04)
and JMP (05). Once either DIFU(13) or DIFD(14) has turned ON a bit, it will
remain ON until the next time DIFU(13) or DIFD(14) is executed again. In
normal programming, this means the next scan. In a jump, it means the next
time the jump from JMP(04) to JME(05) is not made, i.e., if a bit is turned ON
by DIFU(13) or DIFD(14) and then a jump is made that skips the DIFU(13) or
DIFD(14), the designated bit will remain ON until the next time the execution
condition for the JMP(04) controlling the jump is ON.

Precautions

Flags

Examples

When JMP(04) and JME(05) are not used in pairs, an error message will ap­pear when the program check is performed. Although this message also ap­pears if JMP(04) 00 and JME(05) 00 are not used in pairs, the program will
execute properly as written.

The High-speed Counter (HDM(98) should not be used within a
JMP(04)–JME(05) portion of the program.

There are no flags affected by these instructions.

Examples of jump programs are provided in

4–3–5 Jumps

.

55

Timer and Counter Instructions Section 5–11

5–9 End – END(01)

Ladder Symbol

Description

Flags

END(01) is required as the last instruction in any program. No instruction
written after END(01) will be executed. END(01) can be placed anywhere in
the program to execute all instructions up to that point, as is sometimes done
to debug a program, but it must be removed to execute the remainder of the
program.

If there is no END(01) in the program, no instructions will be executed and
the error message “NO END INST” will appear.

END(01) turns OFF ER, CY, GR, EQ, and LE.

5–10 No Operation – NOP(00)

Description

Flags

NOP(00) is not generally required in programming and there is no ladder
symbol for it. When NOP(00) is found in a program, nothing is executed and
the next instruction is moved to. When memory is cleared prior to program­ming, NOP(00) is written at all addresses. NOP(00) can be input through the
00 function code.

There are no flags affected by NOP(00).

END(01)

5–11 Timer and Counter Instructions

TIM and TIMH are decrementing ON-delay timer instructions which require a
TC number and a set value (SV).

CNT is a decrementing counter instruction and CNTR is a reversible counter
instruction. Both require a TC number and a SV. Both are also connected to
multiple instruction lines which serve as an input signal(s) and a reset.

Any one TC number cannot be defined twice, i.e., once it has been used as
the definer in any of the timer or counter instructions it cannot be used again.
Once defined, TC numbers can be used as many times as required as oper­ands in instructions other than timer and counter instructions.

TC numbers run from 00 through 47. No prefix is required when using a TC
number as a definer in a timer or counter instruction. Once defined as a tim­er, a TC number can be prefixed with TIM for use as an operand in certain
instructions. The TIM prefix is used regardless of the timer instruction that
was used to define the timer. Once defined as a counter, a TC number can
be prefixed with CNT for use as an operand in certain instructions. The CNT
is also used regardless of the counter instruction that was used to define the
counter.

TC numbers can be designated for operands that require bit data or for oper­ands that require word data. When designated as an operand that requires
bit data, the TC number accesses a bit that functions as a “Completion Flag”
that indicates when the time/count has expired, i.e., the bit, which is normally
OFF, will turn ON when the designated SV has expired. When designated as
an operand that requires word data, the TC number accesses a memory lo­cation that holds the present value (PV) of the timer or counter. The PV of a
timer or counter can thus be used as an operand in CMP(20) or any other
instruction for which the TC area is allowed by designating the TC number

56

Timer and Counter Instructions Section 5–11

used to define that timer or counter to access the memory location that holds
the PV.

Note that “TIM 00” is used to designate the Timer instruction defined with TC
number 00, to designate the Completion Flag for this timer, and to designate
the PV of this timer. The meaning of the term in context should be clear, i.e.,
the first is always an instruction, the second is always a bit operand, and the
third is always a word operand. The same is true of all other TC numbers
prefixed with TIM or CNT. In explanations of ladder diagrams, the Completion
Flag and PV accessed through a TC number are generally called the Com­pletion Flag or the PV of the instruction (e.g., the Completion Flag of TIM 00
is the Completion Flag of TC number 00, which has been defined using TIM).

An SV can be input as a constant or as a word address in a data area. If an
IR area word assigned to an Input Unit is designated as the word address,
the Input Unit can be wired so that the SV can be set externally through
thumbwheel switches or similar devices. Timers and counter wired in this
way can be set externally only during RUN or MONITOR mode. All SVs, in­cluding those set externally, must be in BCD.

5–11–1 Timer – TIM

Limitations

Description

Definer Values

Ladder Symbol

TIM N

SV

N: TC number

# (00 through 47)

Operand Data Areas

SV: Set value (word, BCD)

IR, HR, #

SV may be between 000.0 and 999.9 seconds. The decimal point of SV is
not input.

Each TC number can be used as the definer in only one timer or counter in­struction.

TC 00 through TC 47 should not be used in TIM if they are required for
TIMH(15). Refer to

5–11–2 High–Speed Timer – TIMH(15)

for details.

A timer is activated when its execution condition goes ON and is reset (to
SV) when the execution condition goes OFF. Once activated, TIM measures
in units of 0.1 second from the SV. TIM accuracy is +0.0/–0.1 second.

If the execution condition remains ON long enough for TIM to time down to
zero, the Completion Flag for the TC number used will turn ON and will re­main ON until TIM is reset (i.e., until its execution condition goes OFF).

The following figure illustrates the relationship between the execution condi­tion for TIM and the Completion Flag assigned to it.

57

Timer and Counter Instructions Section 5–11

ON

Execution condition

Completion Flag

OFF

ON
OFF

SV SV

Precautions

Flags

Examples

Example 1:
Basic Application

Timers in interlocked program sections are reset when the execution condi­tion for IL(02) is OFF. Power interruptions also reset timers. If a timer that is
not reset under these conditions is desired, SR area clock pulse bits can be
counted to produce timers using CNT. Refer to

5–11–4 Counter – CNT

for

details.
Program execution will continue even if a non-BCD SV is used, but timing will

not be accurate.
ER: SV is not in BCD.
All of the following examples use OUT in diagrams that would generally be

used to control output bits in the IR area. There is no reason, however, why
these diagrams cannot be modified to control execution of other instructions.

The following example shows two timers, one set with a constant and one set
via input word 01. Here, 0200 will be turned ON 15 seconds after 0000 goes
ON and stays ON for at least 15 seconds. When 0000 goes OFF, the timer
will be reset and 0200 will be turned OFF. When 0001 goes ON, TIM 01 is
started from the SV provided through IR word 01. Bit 0201 is also turned ON
when 0001 goes ON. When the SV in 01 has expired, 0201 is turned OFF.
This bit will also be turned OFF when TIM 01 is reset, regardless of whether
or not SV has expired.

0000

TIM 00

TIM

00

0200

015.0 s

Example 2:
Extended Timers

58

0001

TIM 01

TIM

01

0201

01

Timers operating longer than 999.9 seconds can be formed in two ways. One
is by programming consecutive timers, with the Completion Flag of each tim­er used to activate the next timer. A simple example with two 900.0-second
(15-minute) timers combined to functionally form a 30-minute timer.

0000

TIM 01

TIM 02

TIM

01

TIM

02

0200

900.0 s

900.0 s

Timer and Counter Instructions Section 5–11

In this example, 0200 will be turned ON 30 minutes after 0000 goes ON.
TIM can also be combined with CNT or CNT can be used to count SR area

clock pulse bits to produce longer timers. An example is provided in

Counter – CNT

.

5–11–4

Example 3:
ON/OFF Delays

TIM can be combined with KEEP(11) to delay turning a bit ON and OFF in
reference to a desired execution condition. KEEP(11) is described in

Keep – KEEP(11)

.

5–6–3

To create delays, the Completion Flags for two timers are used to determine
the execution conditions for setting and resetting the bit designated for
KEEP(11). The bit whose manipulation is to be delayed is used in KEEP(11).
Turning ON and OFF the bit designated for KEEP(11) is thus delayed by the
SV for the two timers. The two SV could naturally be the same if desired.

In the following example, 0500 would be turned ON 5.0 seconds after 0000
goes ON and then turned OFF 3.0 seconds after 0000 goes OFF. It is neces­sary to use both 0500 and 0000 to determine the execution condition for TIM
02; 0000 in an inverse condition is necessary to reset TIM 02 when 0000
goes ON and 0500 is necessary to activate TIM 02 when 0000 goes OFF,
setting 0500 by resetting TIM 01.

0000

0500 0000

TIM 01

TIM 02

S

TIM 01

TIM 02

KEEP
0500

5.0 s

3.0 s

R

Example 4:
One-shot Bits

The length of time that a bit is kept ON or OFF can be controlled by combin­ing TIM with OUT or OUT NOT. The following diagram demonstrates how
this is possible. In this example, 0204 would remain ON for 1.5 seconds after
0000 goes ON regardless of the time 0000 stays ON. This is achieved by
using 1000, activated by 0000, to turn ON 0204 . When TIM 01 comes ON
(i.e., when the SV of TIM 01 has expired), 0204 will be turned OFF through
TIM 01 (i.e., TIM 01 will turn ON for an inverse condition, creating an OFF
execution condition for OUT 0204). TIM 01 will also turn OFF 1000 the next
scan, resetting the one-shot.

59

Timer and Counter Instructions Section 5–11

1000

Example 5:
Flicker Bits

1.5 s

0000

1.5 s

TIM 0100

0204

1.5 s

1000 TIM 01

1000

1000 TIM 01

0000

0204

Bits can be programmed to turn ON and OFF at a regular interval while a
designated execution condition is ON by using TIM twice. One TIM functions
to turn ON and OFF a specified bit, i.e., the Completion Flag of this TIM turns
the specified bit ON and OFF. The other TIM functions to control the opera­tion of the first TIM, i.e., when the first TIM’s Completion Flag goes ON, the
second TIM is started and when the second TIM’s Completion Flag goes ON,
the first TIM is started.

TIM 02

0000

TIM 01

TIM 01

0000

0205

1.0 s 1.5 s1.0 s

1.5 s

TIM 01

TIM 02

0205

1.0 s

1.5 s

An easier but more limited method of creating a flicker bit is to AND one of
the SR area clock pulse bits with the execution condition that is to be ON
when the flicker bit is operating. Although this method does not use TIM, it is
included here for comparison. This method is more limited because the ON
and OFF times must be the same and they depend on the clock pulse bits
available in the SR area.

60

Timer and Counter Instructions Section 5–11

5–11–2 High-speed Timer – TIMH(15)

Definer Values

Limitations

Description

Ladder Symbol

TIMH(15)

N

SV

N: TC number

# (00 though 47 )

Operand Data Areas

SV: Set value (word, BCD)

IR, HR, #

SV may be between 00.00 and 99.99 seconds. The decimal point of SV is
not input.

Each TC number can be used as the definer in only one timer or counter in­struction.

A scan time of greater than 10 ms may affect the accuracy of the timer.

TIMH(15) operates the same as TIM except that TIMH measures in units of

0.01 second and accuracy is +0.00/–0.01 second.
Refer to

5–11–1 Timer – TIM

for operational details and examples. All as-

pects except for the above considerations are the same.

Precautions

Timers in interlocked program sections are reset when the execution condi­tion for IL(02) is OFF. Power interruptions also reset timers. If a timer that is
not reset under these conditions is desired, SR area clock pulse bits can be
counted to produce timers using CNT. Refer to
details.

Program execution will continue even if a non-BCD SV is used, but timing will
not be accurate.

Flags

ER: SV is not in BCD.

5–11–3 Analog Timer Unit

The Analog Timer Unit uses two I/O words to provide four timers (T0 to T3).
Each of the four timers may be set to a specific timer value (SV) within one of
four ranges. The SV for each timer may be set using either a variable resistor
on the Analog Timer Unit or from an external variable resistor.

Each timer is allocated five bits within the IR words allocated to the Analog
Timer Units. The function of these is shown below. The words shown in the
table are as seen from the CPU, i.e., the input word goes from the Analog
Timer Unit to the CPU, the output word, from the CPU to the Analog Timer
Unit. The CPU receives the Time Expired Flag from the Unit and sends the
Start Control Bit, Pause Control Bit and Range Bits to the Unit.

5–11–4 Counter – CNT

for

61

Timer and Counter Instructions Section 5–11

Bit Input word Output word

00 T0 Time Expired Flag T0 Start Control Bit
01 T
02 T2 Time Expired Flag T2 Start Control Bit
03 T3 Time Expired Flag T3 Start Control Bit
04 T0 Pause Control Bit
05
06 T
07 T3 Pause Control Bit
08 T0 Range Bits
09 Cannot be used.
10 T1 Range Bits
11
12 T2 Range Bits
13
14 T3 Range Bits
15

Time Expired Flag T

1

Start Control Bit

1

T1 Pause Control Bit

Pause Control Bit

2

There is a SET indicator and a time expired indicator on the Analog Timer
Unit for each timer. These indicators are lit when the corresponding timer’s
Start Control Bit or Time Expired Flag is ON.

When the Start Control Bit is turned ON, the timer begins operation and the
SET indicator is lit.

When the time set with the internal or external adjustment has expired, the
corresponding Time Expired Flag is set. The time up indicator also lights.

If the Pause Control Bit for a timer is turned ON from the PC, the timer will
cease timing and the present value (PV) will be retained. Timing will resume
when the Pause Control Bit is turned OFF. If the Start Control Bit is turned
OFF before the set value (SV) of the timer has expired, the Time Expired
Flag will not be turned ON.

Timer ranges are set in the output words as shown in the following table.

Timer

Output

0.1 to 1s 1 to 10s 10 to 60s 1 to 10m

word bit

T

0

08 OFF ON OFF ON
09 OFF OFF ON ON

T

1

10 OFF ON OFF ON
11 OFF OFF ON ON

T

2

12 OFF ON OFF ON
13 OFF OFF ON ON

T

3

14 OFF ON OFF ON
15 OFF ON OFF ON

Example

Setup

62

This example uses an Analog Timer Unit connected to a C28K CPU. Word
allocations are shown in the following table.

Timer and Counter Instructions Section 5–11

Unit Input word Output word

CPU 00 01
Analog Timer Unit 02 03

All four time’s are used. Times for two of them are adjusted on the variable
resistors provided on the Analog Timer Unit. The other two times are ad­justed using external resistors. These adjustments are made as follows. Re­fer to the

Analog Timer Unit Installation Guide

for hardware details.

Programming

1, 2, 3...

Timer

T

0

T

1

T

2

T

3

SV Range Resistor adjustment

Approx. 0.6 s 0.1 to 1 s 6/10th turn clockwise
Approx. 3 s 1 to 10 s 3/10th turn clockwise
Approx. 2.6 s 10 to 60 s 2/10th turn clockwise
Approx. 8 min 1 to 10 min 8/10th turn clockwise

The following program sections are used to set up the required data and pro­duce outputs from the four timers. The first section moves E400 into IR 06 to
set the desired ranges (see table above). The second program section
achieves the following operation.

1. IR 0500 is turned ON approximately 0.6 seconds after IR 0002 turns ON

as the result of the action of T

.

0

2. IR 0501 is turned ON approximately 3 seconds after IR 0003 turns ON

as the result of the action of T

.

1

3. IR 0502 is turned ON approximately 20 seconds after IR 0004 turns ON

as the result of the action of T

.

2

4. IR 0503 is turned ON approximately 8 minutes after IR 0004 turns ON

as the result of the action of T

5. T

and T3 are made inoperative if IR 0015 is turned ON.

2

First Scan Flag

1815

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

MOV(21)

#E400

06

.

3

Content of IR O6 after MOV(21)

1110010000000000

Range settings

63

Timer and Counter Instructions Section 5–11

0015

0002

T

Time Expired

0

Flag

0100

0003

T

Time Expired

1

Flag

0101

0004

Start Control Bit

T

0

T

Start Control Bit

1

T

Start Control Bit

2

T

Start Control Bit

3

0606

0607

0600

0500

0601

0501

0602

0603

Used to inhibit operation of T2 and T3.

started.

T

0

0500 turned ON when time for T0 expires.

T1 started.

0501 turned ON when time for T

and T3 started.

T

2

expires.

1

5–11–4 Counter – CNT

T

Time Expired

2

Flag

0102

T

Time Expired

3

Flag

0103

Ladder Symbol

CP

R

CNT N

SV

0502

0503

0502 turned ON when time for T

0502 turned ON when time for T

Definer Values

N: TC number

# (00 through 47)

Operand Data Areas

SV: Set value (word, BCD)

IR, HR, #

expires.

2

expires.

3

Limitations

Description

64

Each TC number can be used as the definer in only one timer or counter in­struction.

CNT is used to count down from SV when the execution condition on the
count pulse, CP, goes from OFF to ON, i.e., the present value (PV) will be
decremented by one whenever CNT is executed with an ON execution condi-

Timer and Counter Instructions Section 5–11

tion for CP and the execution condition was OFF for the last execution. If the
execution condition has not changed or has changed from ON to OFF, the
PV of CNT will not be changed. Counter is turned ON when the PV reaches
zero and will remain ON until the counter is reset.

CNT is reset with a reset input, R. When R goes from OFF to ON, the PV is
reset to SV. The PV will not be decremented while R is ON. Counting down
from SV will begin again when R goes OFF. The PV for CNT will not be reset
in interlocked program sections or for power interruptions.

Changes in execution conditions, the Completion Flag, and the PV are illus­trated below. PV line height is meant to indicate changes in the PV only.

Precautions

Flags

Example 1:
Basic Application

Execution condition
on count pulse (CP)

Execution condition
on reset (R)

Completion Flag

PV

ON
OFF

ON
OFF

ON
OFF

SV

SV – 1

SV – 2

0002

0001

0000

Program execution will continue even if a non-BCD SV is used, but the SV
will not be correct.

ER: SV is not in BCD.

In the following example, the PV will be decremented whenever both 0000
and 0001 are ON provided that 0002 is OFF and either 0000 or 0001 was
OFF the last time CNT 04 was executed. When 150 pulses have been
counted down (i.e., when PV reaches zero), 0205 will be turned ON.

0000

0002

0001

CP

R

CNT 04

#0150

SV

CNT 04

0205

Here, 0000 can be used to control when CNT is operative and 0001 can be
used as the bit whose OFF to ON changes are being counted.

The above CNT can be modified to restart from SV each time power is
turned ON to the PC. This is done by using the First Scan Flag in the SR
area (1815) to reset CNT as shown below.

0000

0002

1815

CNT 04

0001

CP

R

CNT 04

#0150

0205

65

Timer and Counter Instructions Section 5–11

Example 2:
Extended Counter

Counters that can count past 9,999 can be programmed by using one CNT to
count the number of times another CNT has reached zero from SV.

In the following example, 0000 is used to control when CNT 01 operates and
CNT 01, when 0000 is ON, counts down the number of OFF to ON changes
in 0001. CNT 01 is reset by its Completion Flag, i.e., it starts counting again
as soon as its PV reaches zero. CNT 02 counts the number of times the
Completion Flag for CNT 01 goes ON. Bit 0002 serves as a reset for the en­tire extended counter, resetting both CNT 01 and CNT 02 when it is OFF.
The Completion Flag for CNT 02 is also used to reset CNT 01 to inhibit CNT
01 operation once PV for CNT 02 has been reached until the entire extended
counter is reset via 0002.

Because in this example the SV for CNT 01 is 100 and the SV for CNT 02 is
200, the Completion Flag for CNT 02 turns ON when 100 x 200 or 20,000
OFF to ON changes have been counted in 0001. This would result in 0203
being turned ON.

0000 0001

0002

CNT 01

CP

R

CNT 01

#0100

Example 3:
Extended Timers

CNT 02

CNT 01

0002

CNT 02

CP

R

CNT 02

#0200

0203

CNT can be used in sequence as many times as required to produce count­ers capable of counting down even higher values.

CNT can be used to create extended timers in two ways: by combining TIM
with CNT and by counting SR area clock pulse bits.

In the following example, CNT 02 counts the number of times TIM 01
reaches zero from its SV. The Completion Flag for TIM 01 is used to reset
TIM 01 so that is runs continuously and CNT 02 counts the number of times
the Completion Flag for TIM 01 goes ON (CNT 02 would be executed once
each time between when the Completion Flag for TIM 01 goes ON and TIM
01 is reset by its Completion Flag). TIM 01 is also reset by the Completion
Flag for CNT 02 so that the extended timer would not start again until CNT
02 was reset by 0001, which serves as the reset for the entire extended tim­er.

66

As the SV for TIM 01 is 5.0 seconds and the SV for CNT 02 is 100, the Com­pletion Flag for CNT 02 turns ON when 5 seconds x 100 times, or 8 minutes
and 20 seconds have expired. This would result in 0201 being turned ON.

Timer and Counter Instructions Section 5–11

0000 TIM 01 CNT 02

TIM 01

0001

CNT 00

CP

R

TIM

0100

CNT 02

#0100

0200

5.0 s

In the following example, CNT 01 counts the number of times the 1-second
clock pulse bit (1902) goes from OFF to ON. Here again, 0000 is used to
control when CNT is operating.

As the SV for CNT 01 is 700, the Completion Flag for CNT 02 turns ON when
1 second x 700 times, or 10 minutes and 40 seconds have expired. This
would result in 0202 being turned ON.

0000 1902

0001

CNT 01

CP

R

CNT 01

#0700

0202

The shorter clock pulses may not produce accurate timers because their

Note

short ON times may not be read accurately for longer scan times. In particu­lar the 0.02-second and 0.1-second clock pulses should not be used to cre­ate timers with CNT.

5–11–5 Reversible Counter – CNTR(12)

Ladder Symbol

II

CNTR(12)

DI

R

Limitations

Description

Each TC number can be used as the definer in only one timer or counter in­struction.

The CNTR(12) is a reversible, up-down circular counter, i.e., it is used to
count between zero and SV according to changes in two execution condi­tions, those in the increment input (II) and those in the decrement input (DI).

SV

Definer Values

N: TC number

# (00 through 47)

N

Operand Data Areas

SV: Set value (word, BCD)

IR, HR, #

The present value (PV) will be incremented by one whenever CNTR(12) is
executed with an ON execution condition for II and the execution condition

67

Timer and Counter Instructions Section 5–11

was OFF for II for the last execution. The present value (PV) will be decre­mented by one whenever CNTR(12) is executed with an ON execution condi­tion for DI and the execution condition was OFF for DI for the last execution.
If OFF to ON changes have occurred in both II and DI since the last execu­tion, the PV will not be changed.

If the execution conditions have not changed or has changed from ON to
OFF for both II and DI, the PV of CNT will not be changed.

When decremented from 0000, the present value is set to SV and the Com­pletion Flag is turned ON until the PV is decremented again. When incre­mented past the SV, the PV is set to 0000 and the Completion Flag is turned
ON until the PV is incremented again.

CNTR(12) is reset with a reset input, R. When R goes from OFF to ON, the
PV is reset to zero. The PV will not be incremented or decremented while R
is ON. Counting will begin again when R goes OFF. The PV for CNTR(12)
will not be reset in interlocked program sections or for power interruptions.

Changes in II and DI execution conditions, the Completion Flag, and the PV
are illustrated below starting from part way through CNTR(12) operation (i.e.,
when reset, counting begins from zero). PV line height is meant to indicate
changes in the PV only.

ON
OFF

ON
OFF

ON
OFF

Precautions

Execution condition
on increment (II)

Execution condition
on decrement (DI)

Completion Flag

PV

Program execution will continue even if a non-BCD SV is used, but the SV
will not be correct.

Flags

ER: SV is not in BCD.

5–11–6 High-speed Counter – HDM(98)

Ladder Symbol

HDM(98) N

R

SV – 2

SV – 1

SV

0001

0000

0000

Definer Values

N: TC number

Must be 47

Operand Data Areas

SV

SV – 1

SV – 2

Limitations

68

R: Result word

IR, HR, DM

If any of the lower limits for the DM ranges are set to “0000”, the correspond­ing output bits are turned ON when the high-speed counter is reset.

Timer and Counter Instructions Section 5–11

If the time it takes to count through some range is less than the scan time of
the CPU, the high-speed counter may count past between scans and thus
the output bit for this range may not be turned ON.

Counting Time

Lower Limit Upper Limit

The count signal must be at least 250 µs (2 kHz) wide and have a duty factor
of 1:1, as shown below.

Input
0000

250 µs 250 µs

In the hard reset mode, the reset signal must have an ON time of at least 250
µs.

Description

General

Input
0001

250 µs max.

The high-speed counter counts the signals input from an external device con­nected to input 0000 and, when the high-speed counter instruction is ex­ecuted, compares the current value with a set of ranges which have been
preset in DM words 32 through 63. If the current value is within any of the
preset ranges, the corresponding bit of a specified result word is turned ON.
The bit in the result word remains ON until the current value is no longer
within the specified range.

An internal buffer is incremented whenever bit 0000 goes from OFF to ON.
When the high-speed counter instruction is executed, the value in the count­er buffer is transferred to counter 47 which serves as the count value storage
area.

When using the high-speed counter, the following bits are reserved and can­not be used for any other purpose:

• Input 0000 (count input)

• Input 0001 (hard reset)

• IR bit 1807 (soft reset)

• TC 47 (present count value)

• DM 32 to 63 (upper and lower limits)

If a power failure occurs, the count value of the high speed counter immedi-

Note

ately before the power failure is retained.
The high-speed counter is programmed differently depending on how it is to

be reset. Two resetting modes are possible: hard-reset and soft-reset. The
hard reset is made effective or ineffective with the DIP switch in the CPU.

69

Timer and Counter Instructions Section 5–11

Hard Reset

Soft Reset

To use the hard reset, turn pins 7 and 8 ON. In this mode, input 0001 is the
reset input. When it is turned ON, the present value in the high-speed count­er buffer is reset to “0000”. When the reset is ON, the count signal from input
0000 is not accepted. When programmed with the hard reset, the high-speed
counter would appear as below.

0002

HDM(98)

10

IR 1807 is the soft reset. When it is turned ON, the present value in the
high-speed counter buffer is reset to “0000”. As for the hard reset, when the
soft reset is ON, the count signal from input 0000 is not accepted. When pro­grammed with the soft reset, the high-speed counter would appear as below.
Note that when the soft reset is used, the timing at which the counter buffer is
reset may be delayed due to the scan time of the CPU.

0003

0002

1807

HDM(98)

10

If required, both the hard reset and the soft reset can be used together.

70

Timer and Counter Instructions Section 5–11

Upper and Lower Limit
Setting

The following table shows the upper and lower limits that need to be set in
DM 32 through DM 63. In this table, “S” denotes the present value of counter
47 and R is the results word.

Lower
limit

DM 32 DM 33 Value of DM 32 ≤ S ≤ value of DM 33 00
DM 34 DM 35 Value of DM 34
DM 36 DM 37 Value of DM 36
DM 38 DM 39 Value of DM 38
DM 40 DM 41 Value of DM 40
DM 42 DM 43 Value of DM 42
DM 44 DM 45 Value of DM 44
DM 46 DM 47 Value of DM 46
DM 48 DM 49 Value of DM 48
DM 50 DM 51 Value of DM 50

Upper
limit

Present value of the counter Bit of R

that turns
ON

≤ S ≤ value of DM 35 01
≤ S ≤ value of DM 37 02
≤ S ≤ value of DM 39 03
≤ S ≤ value of DM 41 04
≤ S ≤ value of DM 43 05
≤ S ≤ value of DM 45 06
≤ S ≤ value of DM 47 07
≤ S ≤ value of DM 49 08
≤ S ≤ value of DM 51 09

DM 52 DM 53 Value of DM 52
DM 54 DM 55 Value of DM 54
DM 56 DM 57 Value of DM 56
DM 58 DM 59 Value of DM 58
DM 60 DM 61 Value of DM 60
DM 62 DM 63 Value of DM 62

≤ S ≤ value of DM 53 10
≤ S ≤ value of DM 55 11
≤ S ≤ value of DM 57 12
≤ S ≤ value of DM 59 13
≤ S ≤ value of DM 61 14
≤ S ≤ value of DM 63 15

The values must be four-digit BCD in the range 0000 to 9999. Note that fail­ure to enter BCD values will not activate the ERR Flag. Always set a lower
limit which is less than the corresponding upper limit. MOV is useful in setting
limits. The following ladder diagram shows the use of MOV for setting limits
and the associated timing diagram shows the state of the relevant bits of the
result word (IR 05) as the counter is incremented.

71

Timer and Counter Instructions Section 5–11

1813 (normally ON)

0002 (start input)

MOV(21)

#0200

DM 32

MOV(21)

#1500
DM 33

MOV(21)

#0600
DM 34

MOV(21)

#2000
DM 35

HDM(98)

05

Corresponding
result word is 05

Transfers
preset
value to
DM 32 to
35

Response Speed

Precautions

Start input 0002

Count input 0000

200

Output 0500

600

Output 0501

1500

2000

The maximum response speed of the high-speed counter hardware is 2 kHz.
Note however that the start signal, reset signal (in the case of soft reset), and
corresponding outputs are all processed by software. Because of this, re­sponse may be delayed by the scan time.

When programming the high-speed counter with the GPC, “00” is displayed
on each of the three lines below the instruction code (HDM(60)). Do not alter
the second and third lines; if they are not “00”, an error occurs when an at­tempt is made to transfer the program from the GPC to the PC.

Do not program the high-speed counter between JMP and JME. The
high-speed counter can be programmed between IL and ILC. However, the
hard reset signal remains active, causing the corresponding output(s) to turn
ON or OFF, even when the IL condition is OFF.

Examples

Extending the Counter

72

The high-speed counter normally provides 16 output bits. If more than 16 are
required, the high-speed counter may be programmed more than once. In
the following program example, the high-speed counter is used twice to pro­vide 32 output bits.

Timer and Counter Instructions Section 5–11

1813 (normally ON)

0002

1813 (normally ON)

Transfers limit values
S1 to S32 to DM.
Output thru HR 0

MOV(21)

“S1”

DM 32

MOV(21)

“S2”

DM 33

MOV(21)

“S32”

DM 35

HDM(98)

HR 0

MOV(21)

“S33”

DM 32

A

Transfers limit values
S33 to S64 to DM.
Output thru HR 1

0002

MOV(21)

“S34”

DM 33

MOV(21)

“S64”

DM 35

HDM(98)

HR 1

B

In this program, each bit in the specified words, HR 0 and HR 1 are turned
ON under the following conditions (where S is the present count value of the
high-speed counter stored as the data of CNT 47):
Where S1 ≤ S ≤ S2, HR 000 is ON.
Where S3 ≤ S ≤ S4, HR 001 is ON.
Where S31 ≤ S ≤ S32, HR 015 is ON.
Where S33 ≤ S ≤ S34, HR 100 is ON.
Where S63 ≤ S ≤ S64, HR 115 is ON.

Note that in the program just mentioned, the present value in the counter
buffer is transferred to counter number 47 at points A and B. In this case, if
S31 (=1,000) < S < S32 (=2,000) and S33 (=2,000) < S < S34 (=3,000), and
if the present count value of the first high-speed counter (at point A) is 1,999
and that of the second counter (at point B) is 2,003, HR 015 and HR100 may
be simultaneously turned ON. If it is necessary to avoid this, set the values of

73

Timer and Counter Instructions Section 5–11

S32 and S33 so that there is a value difference equivalent to the time lag
from points A to B. For example, set the value of S32 to 2,000 and that of
S33 to 2,010.

More than 16 output bits may be obtained using CMP.

1813 (normally ON)

1905 (GR)

CMP(20)

CNT 47

#6850

0600

In the above program, output 0600 is turned ON when the following condition
is satisfied, where S is the present count value of the high-speed counter:
6,850 < S ≤ 9,999.

1813 (normally ON)

1905 (GR)

1813 (normally ON)

CMP(20)

CNT 47

#0300

1000

CMP(20)

CNT 47

#2300

Cascade Connection
(Counting Past 9,999)

1907 (LE)

1000 1001

1001

0601

In the above program, output 0601 is turned ON when the following condition
is satisfied, where S is the present count value of the high-speed counter:
300 < S < 2,300.

The number of digits of the upper and lower limits of the high-speed counter
can be increased from four to eight by using the high-speed counter together
with CNTR and CMP.

The high-speed counter is a ring counter and thus when its present count
value is incremented from 9999 to 0000, the Completion Flag of CNT 47 is
turned ON for one scan. By using this flag as an input to the UP input of the
reversible counter (i.e., cascade connection) you can increase the number of
digits to eight. Although an ordinary counter can be cascade-connected to

74

Timer and Counter Instructions Section 5–11

the high-speed counter, programming is easier with CNTR since an ordinary
counter is decrementing.

1813 (normally ON)

0002 (start input)

CNT 47

1814 (normally OFF)

1810 (turns On for 1 scan upon hard reset)

1813 (normally ON)

1906 (EQ)

HR 000

MOV(21)

#0000

DM 32

MOV(21)

#5000

DM 33

HDM(98)

HR 0

II

CNTR(12)

DI

R

46

#9999

CMP(20)

CNT 46

#0002

0500

Packaging Machine

In the above program example, output 0500 is turned ON when the following
condition is satisfied (where S is the present count value of the high-speed
counter):
20,000 ≤ S ≤ 25,000.

In hard reset mode, program SR 1810, which turns ON for one scan time

Note

upon input of the hard reset signal, to CNTR as the reset input. Unless CNTR
and CMP are programmed immediately after the high-speed counter, the cor­rect corresponding outputs may not be produced.

The high-speed counter is very useful in the following application. Here,
packages are being carried on a conveyor belt at random intervals. Some of
them are spaced far apart and others are clustered together, making it im­possible to accurately detect and count them with photoelectric switches
alone.

By presetting the number of pulses generated when a single package is de­tected and by counting those pulses, the number of packages can be accu­rately counted, regardless of whether the packages are spaced or clustered.

The following diagram shows the packaging system and the corresponding
timing chart.

75

Timer and Counter Instructions Section 5–11

Reflective photoelectric
switch PH1 (0002)

Rotary encoder E6A
(0000)

Packages

PH1
(0002)

E6A
(0000)

M1 rise
(0100)

LS4
(0006)

LS3
(0005)

M2
forward
(0102)

LS2
(0004)

LS1
(0003)

M2
backward
(0103)

M1 fall
(0101)

Motor 2 (M2)

Pusher

Upper limit switch for stopper LS3 (0005)

Moving stopper

Lower limit switch for stopper LS4 (0006)Motor 1 (M1)

Rear limit switch for
pusher LS1 (0003)

Fixed stopper

Front limit switch for
pusher LS2 (0004)

76

In this example, “x” is the number of pulses per package. To detect four pack­ages therefore, 4x must be set as the preset value of the high-speed counter.

Here is the program example for the application.

Data Shifting Section 5–12

1813 (normally ON)

MOV(21)

#0905

DM 32

MOV(21)

#1150

1815

0005

DM 33

MOV(21)

#1450

DM 34

MOV(21)

#1550

DM 35

1807

Transfer limit values

Resets counter
upon power
application or at
stopper
operation

0002

HR 000 0011 0006 0005

HR 001

0100

0005 0003 0100 0004

0102

0004 0102 0003

0103

0003

1000 0005 0006

0101

0011

HDM(60)

HR 0

0100

0102

0103

DIFU(13) 1000

0101

Counts pulses
from encoder
only when PH1
is ON

Normally counts 4
packages. When
input 0011 is ON,
counts 6 packages.
Pushes stopper up
at count-up to stop
following packages

Pushes
packages
out

Returns pusher
to original
position after
operation

Pushes stopper
down and
continues
operating when
pusher returns
to original
position

5–12 Data Shifting

This section describes the instructions that are used to create and manipu­late shift registers. SFT(10) creates a single- or multiple-word register that
shift in a second execution condition when executed with an ON execution

77

Data Shifting Section 5–12

condition. SFTR(84) creates a reversible shift register that is controlled
through the bits in a control word. WSFT(16) creates a multiple-word register
that shifts by word.

5–12–1 Shift Register – SFT(10)

Limitations

Description

Ladder Symbol

I

SFT(10)

P

R

St

E

Operand Data Areas

St : Starting word

IR, HR

E : End word

IR, HR

E must be less than or equal to St, and St and E must be in the same data
area.

If a bit address in one of the words used in a shift register is also used in an
instruction that controls individual bit status (e.g., OUT, KEEP(11)), an error
(“COIL DUPL”) will be generated when program syntax is checked on the
Programming Console or another Programming Device. The program, how­ever, will be executed as written. See

Registers

for a programming example that does this.

Example 2: Controlling Bits in Shift

SFT(10) shifts an execution condition into a shift register. SFT(10) is con­trolled by three execution conditions, I, P, and R. If SFT(10) is executed and

1) execution condition P is ON and was OFF the last execution and 2) R is
OFF, then execution condition I is shifted into the rightmost bit of a shift regis­ter defined between St and E, i.e., if I is ON, a 1 is shifted into the register; if I
is OFF, a 0 is shifted in. When I is shifted into the register, all bits previously
in the register are shifted to the left and the leftmost bit of the register is lost.

Lost
data

Flags

78

E St + 1, St + 2, ... St

The execution condition on P functions like a differentiated instruction, i.e., I
will be shifted into the register only when P is ON and was OFF the last time
SFT(10) was executed. If execution condition P has not changed or has gone
from ON to OFF, the shift register will remain unaffected.

St designates the rightmost word of the shift register; E designates the left­most. The shift register includes both of these words and all words between
them. The same word may be designated for St and E to create a 16-bit (i.e.,
1-word) shift register.

When execution condition R goes ON, all bits in the shift register will be
turned OFF (i.e., set to 0) and the shift register will not operate until R goes
OFF again.

There are no flags affected by SFT(10).

Execution
condition I

Data Shifting Section 5–12

Example 1:
Basic Application

Example 2:
Controlling Bits in Shift
Registers

The following example uses the 1-second clock pulse bit (1902) to so that the
execution condition produced by 0005 is shifted into a 3-word register be­tween 10 and 12 every second.

0005

1902

0006

I

SFT(10)

P

R

10

12

The following program is used to control the status of the 17th bit of a shift
register running from IR 00 through IR 01 (i.e. bit 00 of IR 01). When the 17th
bit is to be set, 0204 is turned ON. This causes the jump for JMP(04) 00 not
to be made for that one scan and IR 0100 (the 17th bit) will be turned ON.
When 1280 is OFF (all times but the first scan after 0204 has changed from
OFF to ON), the jump is taken and the status of 0100 will not be changed.

0200

0201

0202

0203

I

SFT(10)

P

R

00

01

Example 3:
Control Action

0204

DIFU(13) 1280

1280

JMP(04) 00

1280

0100

JME(05) 00

When a bit that is part of a shift register is used in OUT (or any other instruc­tion that controls bit status), a syntax error will be generated during the pro­gram check, but the program will execute properly (i.e., as written).

The following program controls the conveyor line shown below so that faulty
products detected at the sensor are pushed down a chute. To do this, the
execution condition determined by inputs from the first sensor (0001) are
stored in a shift register: ON for good products; OFF for faulty ones. Con­veyor speed has been adjusted so that HR 003 of the shift register can be
used to activate a pusher (0500) when a faulty product reaches it, i.e., when
HR 003 turns ON, 0500 is turned ON to activate the pusher.

The program is set up so that a rotary encoder (0000) controls execution of
SFT(10) through a DIFU(13), the rotary encoder is set up to turn ON and
OFF each time a product passes the first sensor. Another sensor (0002) is
used to detect faulty products in the chute so that the pusher output and HR
003 of the shift register can be reset as required.

79

Data Shifting Section 5–12

Sensor

(0001)

Rotary Encoder
(0000)

Sensor
(0002)

Pusher
(0500)

Chute

0001

0000

0003

HR 003

0002

5–12–2 Word Shift – WSFT(16)

Ladder Symbols Operand Data Areas

I

SFT(10)

P

HR 0

R

HR 1

0500

0500

HR 003

Limitations

Description

80

WSFT(16)

St : Start word

IR, DM, HR

St

E : End word

E

IR, DM, HR

St and E must be in the same data area and St must be less than E.

When the execution condition is OFF, WSFT(16) is not executed and the
next instruction is moved to. When the execution condition is ON, 0000 is
moved into St, the content of St is moved to St + 1, the content of St + 1 is
moved to St + 2, etc., and the content of E is lost.

Data Movement Section 5–13

E St + 1 St

F0C234521029

Lost

0000

E St + 1 St

345210290000

Flags

ER: St and E are not in the same data area.

5–13 Data Movement

This section describes the instructions used for moving data between differ­ent addresses in data areas. These movements can be programmed within
the same data area or between different data areas. Data movement is es­sential for utilizing all of the data areas of the PC. All of these instructions
change only the content of the words to which data is being moved, i.e., the
content of source words is the same before and after execution of any of the
move instructions.

5–13–1 Move – MOV(21)

Indirectly addressed DM word is non-existent. (Content of *DM word
is not BCD, or the DM area boundary has been exceeded.)

Ladder Symbol Operand Data Areas

MOV(21)

S

D

S : Source word

IR, SR, DM, HR, TC, #

D : Destination word

IR, DM, HR

Description

Precautions

Flags

When the execution condition is OFF, MOV(21) is not executed and the next
instruction is moved to. When the execution condition is ON, MOV(21) trans­fers the content of S (specified word or four-digit hexadecimal constant) to D.

Source word Destination word

Bit status
not changed.

TC numbers cannot be designated as D to change the PV of the timer or
counter.

EQ: ON when all zeros are transferred to D.

81

Data Comparison Section 5–14

5–13–2 Move NOT – MVN(22)

Ladder Symbol Operand Data Areas

Description

Precautions

MVN(22)

S

D

S : Source word

IR, SR, DM, HR, TC, #

D : Destination word

IR, DM, HR

When the execution condition is OFF, MVN(22) is not executed and the next
instruction is moved to. When the execution condition is ON, MOV(21) trans­fers the inverted content of S (specified word or four-digit hexadecimal con­stant) to D, i.e., for each ON bit in S, the corresponding bit in D is turned
OFF, and for each OFF bit in S, the corresponding bit in D is turned ON.

Source word Destination word

Bit status
inverted.

TC numbers cannot be designated as D to change the PV of the timer or
counter.

Flags

EQ: ON when all zeros are transferred to D.

5–14 Data Compare – CMP(20)

This section describes the instruction used for comparing data. CMP(20) is
used to compare the contents of two words.

Ladder Symbols Operand Data Areas

CMP(20)

Cp1
Cp2

Limitations

Description

When comparing a value to the PV of a timer or counter, the value must be
four-digit BCD.

When the execution condition is OFF, CMP(20) is not executed and the next
instruction is moved to. When the execution condition is ON, CMP(20) com­pares Cp1 and Cp2 and outputs the result to GR, EQ, and LE in the SR area.

Cp1 : First compare word

IR, SR, DM, HR, TC, #

Cp2 : Second compare word

IR, SR, DM, HR, TC, #

82

Data Comparison Section 5–14

Precautions

Flags

Example 1:
Saving CMP(20) Results

Placing other instructions between CMP(20) and accessing EQ, LE, and GR
may change the status of these flags. Be sure to access them before the de­sired status is changed.

EQ: ON if Cp1 equals Cp2.
LE: ON if Cp1 is less than Cp2.
GR: ON if Cp1 is greater than Cp2.

The following example shows how to save the comparison result immedi­ately. If the content of HR 8 is greater than that of 9, 0200 is turned ON; if the
two contents are equal, 0201 is turned ON; if content of HR 8 is less than
that of HR 9, 0202 is turned ON. In some applications, only one of the three
OUTs would be necessary, making the use of TR 0 unnecessary. With this
type of programming, 0200, 0201, and 0202 are changed only then CMP(20)
is executed.

TR

0

0000

1905

CMP(20)

HR 8
HR 9

0200

Greater Than

Example 2:
Obtaining Indications
during Timer Operation

1906

1907

0201

0202

Equal

Less Than

The following example uses TIM, CMP(20), and LE (SR 1907) to produce
outputs at particular times in the timer’s countdown. The timer is started by
turning ON 0000. When 0000 is OFF, the TIM (10) is reset and the second
two CMP(20)s are not executed (i.e., executed with OFF execution condi­tions). Output 0200 is output after 100 seconds; output 0201, after 200 sec­onds; output 0202, after 300 seconds; and output 0204, after 500 seconds.

The branching structure of this diagram is important so that 0200, 0201, and
0202 are controlled properly as the timer counts down. Because all of the
comparisons here are to the timer’s PV, the other operand for each CMP(20)
must be in 4-digit BCD.

83

Data Conversion Section 5–15

0000

0200

0201

TIM 10

1907

1907

1907

TIM 10

CMP(20)

TIM 10

#4000

CMP(20)

TIM 10
#3000

CMP(20)

TIM 10
#2000

0200

0201

0202

0204

0500 s.

Output at
100 s.

Output at
200 s.

Output at
300 s.

Output at
500 s.

5–15 Data Conversion

The conversion instructions convert word data that is in one format into an­other format and output the converted data to specified result word(s). Con­versions are available to convert between binary (hexadecimal) and BCD
and between multiplexed and non-multiplexed data. All of these instructions
change only the content of the words to which converted data is being
moved, i.e., the content of source words is the same before and after execu­tion of any of the conversion instructions.

5–15–1 BCD to Binary – BIN(23)

Ladder Symbol Operand Data Areas

BIN(23)

S

R

Description

BIN(23) can be used to convert BCD to binary so that displays on the Pro­gramming Console or any other programming device will appear in hexadeci­mal rather than decimal. It can also be used to convert to binary to perform
binary arithmetic operations rather than BCD arithmetic operations, e.g.,
when BCD and binary values must be added.

S : Source word (BCD)

IR, SR, DM, HR, TC

R : Result word

IR, DM, HR

84

Data Conversion Section 5–15

Flags

ER: The content S is not BCD
EQ: ON when 0000 is placed in R.

5–15–2 Binary to BCD – BCD(24)

Ladder Symbol Operand Data Areas

BCD(24)

S
R

Limitations

Description

If the content of S exceeds 270F, the converted result would exceed 9999
and BCD(24) will not be executed. When the instruction is not executed, the
content of R remains unchanged.

BCD(24) converts the binary (hexadecimal) content of S into the numerically
equivalent BCD bits, and outputs the BCD bits to R. Only the content of R is
changed; the content of S is left unchanged.

BCD(24) can be used to convert binary to BCD so that displays on the Pro­gramming Console or any other programming device will appear in decimal
rather than hexadecimal. It can also be used to convert to BCD to perform
BCD arithmetic operations rather than binary arithmetic operations, e.g.,
when BCD and binary values must be added.

S : Source word (binary)

IR, SR, DM, HR, TC

R : Result word

IR, DM, HR

Flags

ER: S is greater than 270F.
EQ: ON when 0000 is placed in R.

5–15–3 4-to-16 Decoder – MLPX(76)

Ladder Symbol

MLPX(76)

S

Di

R

Limitations

Description

The rightmost two digits of Di must each be between D and 3.
All result words must be in the same data area.

When the execution condition is OFF, MLPX(76) is not executed and the next
instruction is moved to. When the execution condition is ON, MLPX(76) con­verts up to four, four-bit hexadecimal digits from S into decimal values from 0
to 15, each of which is used to indicate a bit position. The bit whose number
corresponds to each converted value is then turned ON in a result word. If
more than one digit is specified, then one bit will be turned ON in each of
consecutive words beginning with R. (See examples, below.)

Operand Data Areas

S : Source word

IR, SR, DM, HR, TC

Di : Digit designator

IR, DM, HR, TC, #

R : First result word

IR, DM, HR

85

Data Conversion Section 5–15

The following is an example of a one-digit decode operation from digit num­ber 1 of S, i.e., here Di would be 0001.

S

C

Bit C (i.e., bit number 12) turned ON.

R

0001000000000000

The first digit and the number of digits to be converted are designated in Di. If
more digits are designated than remain in S (counting from the designated
first digit), the remaining digits will be taken starting back at the beginning of
S. The final word required to store the converted result (R plus the number of
digits to be converted) must be in the same data area as R, e.g., if two digits
are converted, the last word address in a data area cannot be designated; if
three digits are converted, the last two words in a data area cannot be desig­nated.

Digit Designator

The digits of Di are set as shown below.

Digit numbers: 0 1 2 3

Specifies the first digit to be converted (0 to 3)
Number of digits to be converted (0 to 3)

Not used.

0: 1 digits
1: 2 digits
2: 3 digits
3: 4 digits

Some example Di values and the digit-to-word conversions that they produce
are shown below.

Di : 0030Di : 0010

S
0

1
2
3

R
R + 1

S
0

1
2
3

R
R + 1
R + 2
R + 3

86

Di : 0031 Di : 0023

S

0
1
2
3

R
R + 1
R + 2
R + 3

S
0

1
2
3

R
R + 1
R + 2

Data Conversion Section 5–15

Flags

ER: Undefined digit designator, or R plus number of digits exceeds a data

area.

Example

The following program converts three digits of data from DM 20 to bit posi­tions and turns ON the corresponding bits in three consecutive words starting
with HR 1.

0000

S : DM 20 R : HR 1 R+1 : HR 2 R+2 : HR 3

DM 00 2
DM 01 2
DM 02 2
DM 03 2
DM 04 1 2
DM 05 1 2
DM 06 1 2
DM 07 1 2
DM 08 0 2
DM 09 1 2
DM 10 1 2
DM 11 0 2
DM 12 0 2
DM 13 0 2
DM 14 0 2
DM 15 0 2

0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3

Not
Converted

15

1 HR 105 0 HR 205 0 HR 305 0

6

2 HR 109 0 HR 209 0 HR 309 0

0

3 HR 113 0 HR 213 0 HR 313 0

HR 100 0 HR 200 0 HR 300 1
HR 101 0 HR 201 0 HR 301 0
HR 102 0 HR 202 0 HR 302 0
HR 103 0 HR 203 0 HR 303 0
HR 104 0 HR 204 0 HR 304 0

HR 106 0 HR 206 1 HR 306 0
HR 107 0 HR 207 0 HR 307 0
HR 108 0 HR 208 0 HR 308 0

HR 110 0 HR 210 0 HR 310 0
HR 111 0 HR 211 0 HR 311 0
HR 112 0 HR 212 0 HR 312 0

HR 114 0 HR 214 0 HR 314 0
HR 115 1 HR 215 0 HR 315 0

MLPX(76)

DM 20
#0021

HR 1

5–15–4 16-to-4 Encoder – DMPX(77)

Ladder Symbol

DMPX(77)

S
R

Di

Limitations

The rightmost two digits of Di must each be between 0 and 3. All source
words must be in the same data area.

Operand Data Areas

S : First source word

IR, SR, DM, HR, TC

R : Result word

IR, DM, HR

Di : Digit designator

IR, DM, HR, TC, #

87

Data Conversion Section 5–15

Description

When the execution condition is OFF, DMPX(77) is not executed and the
next instruction is moved to. When the execution condition is ON, DMPX(77)
determines the position of the highest ON bit in S, encodes it into single-digit
hexadecimal value corresponding to the bit number of the highest ON bit
number, then transfers the hexadecimal value to the specified digit in R. The
digits to receive the results are specified in Di, which also specifies the num­ber of digits to be encoded.

The following is an example of a one-digit encode operation to digit number 1
of R, i.e., here Di would be 0001.

S

0001000100010110

C transferred to indicate bit number 12 as
the highest ON bit.

R

C

Digit Designator

Up to four digits from four consecutive source words starting with S may be
encoded and the digits written to R in order from the designated first digit. If
more digits are designated than remain in R (counting from the designated
first digit), the remaining digits will be placed at digits starting back at the be­ginning of R.

The final word to be converted (S plus the number of digits to be converted)
must be in the same data area as SB.

The digits of Di are set as shown below.

Digit Numbers: 0 1 2 3

Specifies the first digit to receive converted data (0 to 3).
Number of words to be converted (0 to 3)

Not used.

0: 1 word
1: 2 words
2: 3 words
3: 4 words

88

Some example Di values and the word-to-digit conversions that they produce
are shown below.

BCD Calculations Section 5–16

Flags

Example

S
S + 1

S
S + 1

Di : 0011

R
0

1
2
3

Di : 0013

R
0

1
2
3

S
S + 1
S + 2
S + 3

S
S + 1
S + 2
S + 3

Di : 0030

R
0

1
2
3

Di : 0032

R

0
1
2
3

ER: Undefined digit designator, or S plus number of digits exceeds a data

area.
Content of a source word is 0000.

When 0000 is ON, the following diagram encodes IR words 10 and 11 to the
first two digits of HR 2 and then encodes DM 10 and 11 to the last two digits
of HR 2. Although the status of each source word bit is not shown, it is as­sumed that the bit with status 1 (ON) shown is the highest bit that is ON in
the word.

0000

IR 010
1000
:
1011 1
1012 0
: :
1015 0

DM 10
DM1000
:
DM1001 1
DM1002 0
: :
DM1015 0

IR 011
1100
:
1109 1
1110 0
: :
1115 0

DM 11
DM1100
:
DM1108 1
DM1109 0
: :
DM1115 0

HR 2

Digit 0
Digit 1
Digit 2
Digit 3

DMPX(77)

10

HR 2

#0010

DMPX(77)

DM10

HR 2

#0012

B
9
1
8

5–16 BCD Calculations

The BCD calculation instructions perform mathematic operations on BCD
data.

89

BCD Calculations Section 5–16

These instructions change only the content of the words in which results are
placed, i.e., the contents of source words are the same before and after exe­cution of any of the BCD calculation instructions.

STC(40) and CLC(41), which set and clear the Carry Flag, are included in
this group because most of the BCD operations make use of the Carry Flag
(CY) in their results. Binary arithmetic and shift operations also use CY.

The addition and subtraction instructions use CY in the calculation as well as
in the result. Be sure to clear CY if its previous status is not required in the
calculation, and to use the result placed in CY, if required, before it is
changed by execution of any other instruction.

5–16–1 BCD Add – ADD(30)

Operand Data Areas

Description

Ladder Symbol

ADD(30)

Au
Ad

R

When the execution condition is OFF, ADD(30) is not executed and the next
instruction is moved to. When the execution condition is ON, ADD(30) adds
the contents of Au, Ad, and CY, and places the result in R. CY will be set if
the result is greater than 9999. Au and Ad should not be designated as con­stants. This instruction will be executed every scan as long as the execution
condition remains ON. If the instruction is to be executed only once for a giv­en ON execution condition then it must be used in conjunction with DIFU(13)
or DIFD(14).

Au : Augend word (BCD)

IR, SR, DM, HR, TC, #

Ad : Addend word (BCD)

IR, SR, DM, HR, TC, #

R : Result word

IR, DM, HR

Au + Ad + CY CY R

Flags

Example

90

ER: Au and/or Ad is not BCD.
CY: ON when there is a carry in the result.
EQ: ON when the result is 0.

If 0002 is ON, the following diagram clears CY with CLC(41), adds the con­tent of IR 02 to a constant (6103), places the result in DM 01, and then
moves either all zeros or 0001 into DM 02 depending on the status of CY
(1904). This ensures that any carry from the last digit is preserved in R + 1
so that the entire result can be later handled as eight-digit data.

BCD Calculations Section 5–16

TR 0

0002

1904

1904

Consecutive ADD(30)s can be used to perform eight-digit BCD addition. By
using two ADD(30)s and combining the augend and the addend words of one
ADD(30) with those of the other, two 8-digit values can be added. The result
may or may not be 9 digits depending on whether a carry is generated.

CLC(41)

ADD(30)

02

#6103

DM 01

MOV(21)

#0001

DM 02

MOV(21)

#0000

DM 02

0002

1000

DIFU(13) 1000

TR 0

CLC(41)

ADD(30)

DM 00
DM 02
DM 04

ADD(30)

DM 01
DM 03
DM 05

1904

MOV(21)

#0001

DM 06

1904

MOV(21)

#0000

DM 06

In the above program the 8 digit augend consists of two words: DM 00 and
DM 01, with DM 01 being used for the 4 left digits and 00 for the 4 right dig­its. Similarly the 8-digit addend consist of DM 02 and 03. Three words are
used to hold the results of the addition: DM 04, DM 05, and DM 06. In this
case DM 05 and DM 04 are used to represent the intermediate 4 digits and
the 4 right digits respectively. DM 06 represents the leftmost digit, the 9th dig­it.

91

BCD Calculations Section 5–16

If a carry is generated, SR 1904 (CY) is turned ON and the constant 0001 is
transferred to DM 06. If a carry is not generated SR 1904 remains OFF and
the constant 0000 is transferred to DM 06.

5–16–2 BCD Subtract – SUB(31)

Operand Data Areas

Description

Ladder Symbol

SUB(31)

Mi

Su

R

When the execution condition is OFF, SUB(31) is not executed and the next
instruction is moved to. When the execution condition is ON, SUB(31) sub­tracts the contents of Su and CY from Mi and places the result in R. If the
result is negative, CY is set and the 10’s complement of the actual result is
placed in R. To convert the 10’s complement to the true result, subtract the
content of R from zero (see example below).. This instruction will be ex­ecuted every scan as long as the execution condition remains ON. If the in­struction is to be executed only once then it must be used in conjunction with
DIFU(13) or DIFD(14).

Mi : Minuend word (BCD)

IR, SR, DM, HR, TC, #

Su : Subtrahend word (BCD)

IR, SR, DM, HR, TC, #

R : Result word

IR, DM, HR

Mi – Su – CY CY R

Flags

Example

Caution

ER: Mi and/or Su is not BCD.
CY: ON when the result is negative, i.e., when Mi is less than Su plus CY.
EQ: ON when the result is 0.

Be sure to clear the Carry Flag (CY) with CLC(41) before executing SUB(31)
if its previous status is not required, and check the status of CY after doing a
subtraction with SUB(31). If CY is ON as a result of executing SUB(31) (i.e.,
if the result is negative), the result is output as the 10’s complement of the
true answer. To convert the output result to the true value, subtract the value
in R from 0.

When 0002 is ON, the following diagram clears CY, subtracts the contents of
DM 01 and CY from the content of IR 10 and places the result in HR 2.

If CY is set by executing SUB(31), the result in HR 2 is subtracted from zero
(note that CLC(41) is again required to obtain an accurate result), the result
is placed back in HR 2, and HR 300 is turned ON to indicate a negative re­sult.

If CY is not set by executing SUB(31), the result is positive, the second sub­traction is not performed and HR 300 is not turned ON. HR 300 is pro­grammed as a self-maintaining bit so that a change in the status of CY will
not turn it OFF when the program is rescanned.

92