Cat. No. W146-E1-5
SYSMAC
C20K/C28K/C40K/C60K
Programmable Controllers
K-type
Programmable Controllers
OPERATION MANUAL
Revised July 1999
Notice:
OMRON products are manufactured for use according to proper procedures by a qualified operator
and only for the purposes described in this manual.
The following conventions are used to indicate and classify precautions in this manual. Always heed
the information provided with them. Failure to heed precautions can result in injury to people or damage to property.
DANGER Indicates an imminently hazardous situation which, if not avoided, will result in death or
!
serious injury.
WARNING Indicates a potentially hazardous situation which, if not avoided, could result in death or
!
serious injury.
Caution Indicates a potentially hazardous situation which, if not avoided, may result in minor or
!
moderate injury, or property damage.
OMRON Product References
All OMRON products are capitalized in this manual. The word “Unit” is also capitalized when it refers
to an OMRON product, regardless of whether or not it appears in the proper name of the product.
The abbreviation “Ch,” which appears in some displays and on some OMRON products, often means
“word” and is abbreviated “Wd” in documentation in this sense.
The abbreviation “PC” means Programmable Controller and is not used as an abbreviation for anything else.
Visual Aids
The following headings appear in the left column of the manual to help you locate different types of
information.
OMRON, 1992
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any
form, or by any means, mechanical, electronic, photocopying, recording, or otherwise, without the prior written permission of OMRON.
No patent liability is assumed with respect to the use of the information contained herein. Moreover, because OMRON is
constantly striving to improve its high-quality products, the information contained in this manual is subject to change
without notice. Every precaution has been taken in the preparation of this manual. Nevertheless, OMRON assumes no
responsibility for errors or omissions. Neither is any liability assumed for damages resulting from the use of the information contained in this publication.
Note Indicates information of particular interest for efficient and convenient operation
of the product.
1, 2, 3...
1. Indicates lists of one sort or another, such as procedures, checklists, etc.
ii
About this Manual:
The OMRON K-type Programmable Controllers offer an effective way to automate processing, manufacturing, assembly, packaging, and many other processes to save time and money. Distributed control systems can also be designed to allow centralized monitoring and supervision of several separate
controlled systems. Monitoring and supervising can be done through a host computer, connecting the
controlled system to a data bank. It is thus possible to have adjustments in system operation made
automatically to compensate for requirement changes.
The K-type Units can utilize a number of additional Units including dedicated Special I/O Units that
can be used for specific tasks and Link Units that can be used to build more highly integrated systems.
The K-types are equipped with large programming instruction sets, data areas, and other features to
control processing directly. Programming utilizes ladder-diagram programming methods, which are
described in detail for those unfamiliar with them.
This manual describes the characteristics and abilities of the K-types programming operations, instructions, and other aspects of operation and preparation that demand attention. Before attempting
to operate the PC, thoroughly familiarize yourself with the information contained herein. Hardware
information is provided in detail in the
combination with this manual is provided at the end of
Section 1 Introduction
programming. It also provides an overview of the process of programming and operating a PC and
explains basic terminology used with OMRON PCs. Descriptions of peripheral devices used with the
K-types and a table of other manuals available to use with this manual for special PC applications are
also provided.
Section 2 Hardware Considerations
scribes the indicators that are referred to in other sections of this manual.
Section 3 Memory Areas
information provided there to aid in programming. It also explains how I/O is managed in memory and
how bits in memory correspond to specific I/O points.
Section 4 Programming
looking at the elements that make up the ‘ladder’ part of a ladder-diagram program and explaining
how execution of this program is controlled and the methods required to input it input the PC. S
tion 5 Instruction Set
ming, while
the program and tells how to coordinate inputs and outputs so that they occur at the proper times.
Section 6 Program Execution Timing
Section 7 Debugging and Execution
the program and to monitor and control system operation.
Finally,
means of reducing system down time. Information in this section is also necessary when debugging a
program.
The
tables of instructions and Programming Console operations, and other information helpful in PC operation.
Section 8 Troubleshooting
Appendices
explains the background and some of the basic terms used in ladder-diagram
takes a look at the way memory is divided and allocated and explains the
explains the basics of writing and inputting the ladder-diagram program,
then goes on to describe individually all of the instructions used in program-
provide tables of standard OMRON products available for the K-types, reference
Installation Guide
explains basic aspects of the overall PC configuration and de-
. A table of other manuals that can be used in
Section 1 Introduction
.
ec-
explains the scanning process used to execute
provides the Programming Console procedures used to debug
provides information on system error indications and other
WARNING Failure to read and understand the information provided in this manual may result in
!
personal injury or death, damage to the product, or product failure. Please read each
section in its entirety and be sure you understand the information provided in the section
and related sections before attempting any of the procedures or operations given.
iii
TABLE OF CONTENTS
PRECAUTIONS ix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 Intended Audience x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 General Precautions x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Safety Precautions x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Operating Environment Precautions x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Application Precautions xi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SECTION 1 – Background 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-1 Introduction 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-2 Relay Circuits: The Roots of PC Logic 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-3 PC Terminology 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-4 OMRON Product Terminology 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-5 Overview of PC Operation 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-6 Peripheral Devices 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-7 Available Manuals 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SECTION 2 – Hardware Considerations 7. . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1 Introduction 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-2 Indicators 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-3 PC Configuration 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SECTION 3 – Memory Areas 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1 Introduction 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-2 Data Area Structure 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3 Internal Relay (IR) Area 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4 Special Relay (SR) Area 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-1 Battery Alarm Flag 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-2 Cycle Time Error Flag 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-3 High-speed Drum Counter Reset 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-4 Clock Pulse Bits 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-5 Error Flag (ER) 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-6 Step Flag 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-7 Always OFF, Always ON Flags 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-8 First Cycle Flag 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-9 Arithmetic Flags 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5 Data Memory (DM) Area 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-6 Holding Relay (HR) Area 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-7 Timer/Counter (TC) Area 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-8 Temporary Relay (TR) Area 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SECTION 4 – Writing and Inputting the Program 25. . . . . . . . . . . . . . . . . . .
4-1 Introduction 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-2 Instruction Terminology 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3 The Ladder Diagram 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3-1 Basic Terms 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3-2 Mnemonic Code 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3-3 Ladder Instructions 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3-4 OUT and OUT NOT 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3-5 The END Instruction 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3-6 Logic Block Instructions 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3-7 Coding Multiple Right-hand Instructions 39. . . . . . . . . . . . . . . . . . . . . .
4-3-8 Branching Instruction Lines 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3-9 Jumps 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of contents
4-4 The Programming Console 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4-1 The Keyboard 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4-2 PC Modes 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-5 Preparation for Operation 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-5-1 Entering the Password 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-5-2 Clearing Memory 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-5-3 Clearing Error Messages 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6 Inputting, Modifying, and Checking the Program 49. . . . . . . . . . . . . . . . . . . . . . . .
4-6-1 Setting and Reading from Program Memory Address 50. . . . . . . . . . . .
4-6-2 Inputting or Overwriting Programs 51. . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-3 Checking the Program 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-4 Displaying the Cycle Time 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-5 Program Searches 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-6 Inserting and Deleting Instructions 57. . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7 Controlling Bit Status 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7-1 DIFFERENTIATE UP and DIFFERENTIATE DOWN 59. . . . . . . . . . .
4-7-2 KEEP 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7-3 Self-maintaining Bits (Seal) 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-8 Work Bits (Internal Relays) 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-9 Programming Precautions 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-10 Program Execution 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SECTION 5 – Instruction Set 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-1 Introduction 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-2 Notation 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-3 Instruction Format 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-4 Data Areas, Definer Values, and Flags 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-4-1 Coding Other Instructions 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-5 Ladder Diagram Instructions 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-5-1 LOAD, LOAD NOT, AND, AND NOT, OR, and OR NOT 73. . . . . . . .
5-5-2 AND LOAD and OR LOAD 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-6 Bit Control Instructions 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-6-1 OUTPUT and OUTPUT NOT – OUT and OUT NOT 75. . . . . . . . . . . .
5-6-2 DIFFERENTIATE UP and DIFFERENTIATE DOWN –
5-6-3 KEEP – KEEP(11) 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-7 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03) 78. . . . . . . . . . . .
5-8 JUMP and JUMP END – JMP(04) and JME(05) 80. . . . . . . . . . . . . . . . . . . . . . . . .
5-9 END – END(01) 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-10 NO OPERATION – NOP(00) 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-11 Timer and Counter Instructions 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-11-1 TIMER – TIM 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-11-2 HIGH-SPEED TIMER – TIMH(15) 86. . . . . . . . . . . . . . . . . . . . . . . . . .
5-11-3 Analog Timer Unit 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-11-4 COUNTER – CNT 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-11-5 REVERSIBLE COUNTER – CNTR(12) 93. . . . . . . . . . . . . . . . . . . . . .
5-11-6 HIGH-SPEED DRUM COUNTER – HDM(61) 94. . . . . . . . . . . . . . . . .
5-11-7 REVERSIBLE DRUM COUNTER – RDM(60) 103. . . . . . . . . . . . . . . . .
5-12 Data Shifting 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-12-1 SHIFT REGISTER – SFT(10) 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-12-2 REVERSIBLE SHIFT REGISTER – SFTR(84) 109. . . . . . . . . . . . . . . . .
5-12-3 WORD SHIFT – WSFT(16) 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-13 Data Movement 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-13-1 MOVE – MOV(21) 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-13-2 MOVE NOT – MVN(22) 112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-14 DATA COMPARE – CMP(20) 112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15 Data Conversion 115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15-1 BCD-TO- BINARY – BIN(23) 115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DIFU(13) and DIFD(14) 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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5-15-2 BINARY-TO-BCD – BCD(24) 115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15-3 4-TO-16 DECODER – MLPX(76) 116. . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15-4 16-TO-4 ENCODER – DMPX(77) 118. . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16 BCD Calculations 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-1 BCD ADD – ADD(30) 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-2 BCD SUBTRACT – SUB(31) 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-3 BCD MULTIPLY – MUL(32) 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-4 BCD DIVIDE – DIV(33) 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-5 SET CARRY – STC(40) 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-6 CLEAR CARRY – CLC(41) 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-17 Subroutines 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-17-1 SUBROUTINE DEFINE and SUBROUTINE RETURN
5-17-2 SUBROUTINE ENTRY – SBS(91) 126. . . . . . . . . . . . . . . . . . . . . . . . . .
5-18 Step Instructions 128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-1 STEP DEFINE and STEP START – STEP(08)/SNXT(09) 128. . . . . . . .
5-19 Special Instructions 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-1 I/O REFRESH – IORF(97) 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-2 END WAIT – ENDW(62) 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-3 NOTATION INSERT – NETW(63) 136. . . . . . . . . . . . . . . . . . . . . . . . . .
SBN(92)/RET(93) 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SECTION 6 – Program Execution Timing 137. . . . . . . . . . . . . . . . . . . . . . . . . .
6-1 Introduction 138. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-2 Cycle Time 139. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-3 Calculating Cycle Time 141. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-3-1 Single PC Unit 141. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-3-2 PC with Additional Units 142. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-4 Instruction Execution Times 143. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-5 I/O Response Time 145. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SECTION 7 – Program Debugging and Execution 147. . . . . . . . . . . . . . . . . . .
7-1 Introduction 148. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-2 Debugging 148. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-3 Monitoring Operation and Modifying Data 149. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-3-1 Bit/Digit Monitor 150. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-3-2 Force Set/Reset 153. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-3-3 Hexadecimal/BCD Data Modification 155. . . . . . . . . . . . . . . . . . . . . . . .
7-3-4 Changing Timer/Counter SV 156. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-4 Program Backup and Restore Operations 157. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-4-1 Saving Program Memory Data 158. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-4-2 Restoring or Comparing Program Memory Data 159. . . . . . . . . . . . . . . .
SECTION 8 – Troubleshooting 161. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-1 Introduction 162. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-2 Reading and Clearing Errors and Messages 162. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-3 Error Messages 162. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-4 Error Flags 164. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix 165. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A – Standard Models 165. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B – Programming Instructions and Execution Times 171. . . . . . . . . . . . . . . . . . . . . . . . . . .
C – Programming Console Operations 183. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D – Error and Arithmetic Flag Operation 189. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E – Binary–Hexadecimal–Decimal Table 191. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F – Word Assignment Recording Sheets 193. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
G – Program Coding Sheet 199. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Glossary 201. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Index 215. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vii
PRECAUTIONS
This section provides general precautions for using the K-type Programmable Controllers (PCs) and related devices.
The information contained in this section is important for the safe and reliable application of Programmable Controllers. You must read this section and understand the information contained before attempting to set up or operate a PC
system.
1 Intended Audience x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 General Precautions x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Safety Precautions x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Operating Environment Precautions x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Application Precautions xi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ix
1 Intended Audience
This manual is intended for the following personnel, who must also have knowledge of electrical systems (an electrical engineer or the equivalent).
• Personnel in charge of installing FA systems.
• Personnel in charge of designing FA systems.
• Personnel in charge of managing FA systems and facilities.
2 General Precautions
The user must operate the product according to the performance specifications
described in the operation manuals.
Before using the product under conditions which are not described in the manual
or applying the product to nuclear control systems, railroad systems, aviation
systems, vehicles, combustion systems, medical equipment, amusement machines, safety equipment, and other systems, machines, and equipment that
may have a serious influence on lives and property if used improperly, consult
your OMRON representative.
Make sure that the ratings and performance characteristics of the product are
sufficient for the systems, machines, and equipment, and be sure to provide the
systems, machines, and equipment with double safety mechanisms.
This manual provides information for programming and operating the Unit. Be
sure to read this manual before attempting to use the Unit and keep this manual
close at hand for reference during operation.
5Application Precautions
WARNING It is extremely important that a PC and all PC Units be used for the specified
!
purpose and under the specified conditions, especially in applications that can
directly or indirectly affect human life. You must consult with your OMRON
representative before applying a PC System to the above-mentioned
applications.
3 Safety Precautions
WARNING Do not attempt to take any Unit apart while the power is being supplied. Doing so
!
may result in electric shock.
WARNING Do not touch any of the terminals or terminal blocks while the power is being
!
supplied. Doing so may result in electric shock.
WARNING Do not attempt to disassemble, repair, or modify any Units. Any attempt to do so
!
may result in malfunction, fire, or electric shock.
4 Operating Environment Precautions
Caution Do not operate the control system in the following locations:
!
• Locations subject to direct sunlight.
• Locations subject to temperatures or humidity outside the range specified in
the specifications.
• Locations subject to condensation as the result of severe changes in temperature.
x
• Locations subject to corrosive or flammable gases.
• Locations subject to dust (especially iron dust) or salts.
• Locations subject to exposure to water, oil, or chemicals.
• Locations subject to shock or vibration.
Caution Take appropriate and sufficient countermeasures when installing systems in the
!
following locations:
• Locations subject to static electricity or other forms of noise.
• Locations subject to strong electromagnetic fields.
• Locations subject to possible exposure to radioactivity.
• Locations close to power supplies.
Caution The operating environment of the PC System can have a large effect on the lon-
!
gevity and reliability of the system. Improper operating environments can lead to
malfunction, failure, and other unforeseeable problems with the PC System. Be
sure that the operating environment is within the specified conditions at installation and remains within the specified conditions during the life of the system.
5 Application Precautions
Observe the following precautions when using the PC System.
5Application Precautions
WARNING Always heed these precautions. Failure to abide by the following precautions
!
could lead to serious or possibly fatal injury.
• Always ground the system to 100 Ω or less when installing the Units. Not con-
necting to a ground of 100 Ω or less may result in electric shock.
• Always turn OFF the power supply to the PC before attempting any of the following. Not turning OFF the power supply may result in malfunction or electric
shock.
• Mounting or dismounting I/O Units, CPU Units, Memory Cassettes, or any
other Units.
• Assembling the Units.
• Setting DIP switches or rotary switches.
• Connecting cables or wiring the system.
• Connecting or disconnecting the connectors.
Caution Failure to abide by the following precautions could lead to faulty operation of the
!
PC or the system, or could damage the PC or PC Units. Always heed these precautions.
• Fail-safe measures must be taken by the customer to ensure safety in the
event of incorrect, missing, or abnormal signals caused by broken signal lines,
momentary power interruptions, or other causes.
• Interlock circuits, limit circuits, and similar safety measures in external circuits
(i.e., not in the Programmable Controller) must be provided by the customer.
• Always use the power supply voltages specified in the operation manuals. An
incorrect voltage may result in malfunction or burning.
• Take appropriate measures to ensure that the specified power with the rated
voltage and frequency is supplied. Be particularly careful in places where the
power supply is unstable. An incorrect power supply may result in malfunction.
• Install external breakers and take other safety measures against short-circuiting in external wiring. Insufficient safety measures against short-circuiting may
result in burning.
xi
• Do not apply voltages to the Input Units in excess of the rated input voltage.
Excess voltages may result in burning.
• Do not apply voltages or connect loads to the Output Units in excess of the
maximum switching capacity . Excess voltages or loads may result in burning.
• Disconnect the functional ground terminal when performing withstand voltage
tests. Not disconnecting the functional ground terminal may result in burning.
• Be sure that all the mounting screws, terminal screws, and cable connector
screws are tightened to the torque specified in the relevant manuals. Incorrect
tightening torque may result in malfunction.
• Leave the label attached to the Unit when wiring. Removing the label may result in malfunction if foreign matter enters the Unit.
• Remove the label after the completion of wiring to ensure proper heat dissipation. Leaving the label attached may result in malfunction.
• Use crimp terminals for wiring. Do not connect bare stranded wires directly to
terminals. Connection of bare stranded wires may result in burning.
• Wire all connections correctly.
• Double-check all wiring and switch settings before turning ON the power sup-
ply. Incorrect wiring may result in burning.
• Be sure that the terminal blocks, Memory Units, expansion cables, and other
items with locking devices are properly locked into place. Improper locking
may result in malfunction.
• Check the user program for proper execution before actually running it on the
Unit. Not checking the program may result in an unexpected operation.
• Confirm that no adverse ef fect will occur in the system before attempting any of
the following. Not doing so may result in an unexpected operation.
• Changing the operating mode of the PC.
• Force-setting/force-resetting any bit in memory.
• Changing the present value of any word or any set value in memory.
• Resume operation only after transferring to the new CPU Unit the contents of
the DM Area, HR Area, and other data required for resuming operation. Not
doing so may result in an unexpected operation.
• Do not pull on the cables or bend the cables beyond their natural limit. Doing
either of these may break the cables.
• Do not place objects on top of the cables or other wiring lines. Doing so may
break the cables.
• When replacing parts, be sure to confirm that the rating of a new part is correct.
Not doing so may result in malfunction or burning.
• Before touching a Unit, be sure to first touch a grounded metallic object in order
to discharge any static built-up. Not doing so may result in malfunction or damage.
• Install the Units properly as specified in the operation manuals. Improper
installation of the Units may result in malfunction.
5Application Precautions
xii
SECTION 1
Background
1-1 Introduction 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-2 Relay Circuits: The Roots of PC Logic 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-3 PC Terminology 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-4 OMRON Product Terminology 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-5 Overview of PC Operation 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-6 Peripheral Devices 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-7 Available Manuals 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
Relay Circuits: The Roots of PC Logic Section 1-2
1-1 Introduction
A Programmable Controller (PC) is basically a central processing unit (CPU)
containing a program and connected to input and output (I/O) devices (I/O
Devices). The program controls the PC so that when an input signal from an
input device turns ON, the appropriate response is made. The response normally involves turning ON an output signal to some sort of output device. The
input devices could be photoelectric sensors, pushbuttons on control panels,
limit switches, or any other device that can produce a signal that can be input
into the PC. The output devices could be solenoids, switches activating indicator lamps, relays turning on motors, or any other devices that can be activated by signals output from the PC.
For example, a sensor detecting a product passing by turns ON an input to
the PC. The PC responds by turning ON an output that activates a pusher
that pushes the product onto another conveyor for further processing. Another sensor, positioned higher than the first, turns ON a different input to
indicate that the product is too tall. The PC responds by turning on another
pusher positioned before the pusher mentioned above to push the too-tall
product into a rejection box.
Although this example involves only two inputs and two outputs, it is typical of
the type of control operation that PCs can achieve. Actually even this example is much more complex than it may at first appear because of the timing
that would be required, i.e., “How does the PC know when to activate each
pusher?” Much more complicated operations, however, are also possible.
The problem is how to get the desired control signals from available inputs at
appropriate times.
Desired control sequences are input to the K-type PCs using a form of PC
logic called ladder-diagram programming. This manual is written to explain
ladder-diagram programming and to prepare the reader to program and operate the K-type PCs.
1-2 Relay Circuits: The Roots of PC Logic
PCs historically originate in relay-based control systems. And although the
integrated circuits and internal logic of the PC have taken the place of the
discrete relays, timers, counters, and other such devices, actual PC operation proceeds as if those discrete devices were still in place. PC control, however, also provides computer capabilities and consistency to achieve a great
deal more flexibility and reliability than is possible with relays.
The symbols and other control concepts used to describe PC operation also
come from relay-based control and form the basis of the ladder-diagram programming method. Most of the terms used to describe these symbols and
concepts, however, originated as computer terminology.
Relay vs. PC Terminology
The terminology used throughout this manual is somewhat different from relay terminology, but the concepts are the same. The following table shows
the relationship between relay terms and the PC terms used for OMRON
PCs.
Relay term PC equivalent
contact input or condition
coil output or work bit
NO relay normally open condition
NC relay normally closed condition
2
OMRON Product Terminology Section 1-4
Actually there is not a total equivalence between these terms, because the
term condition is used only to describe ladder diagram programs in general
and is specifically equivalent to one of certain basic instructions. The terms
input and output are not used in programming per se, except in reference to
I/O bits that are assigned to input and output signals coming into and leaving
the PC. Normally open conditions and normally closed conditions are explained in
4-3 The Ladder Diagram
.
1-3 PC Terminology
Although also provided in the
ing terms are crucial to understanding PC operation and are thus explained
here as well.
Glossary
at the back of this manual, the follow-
PC
Inputs and Outputs
When we refer to the PC, we are generally talking about the CPU and all of
the Units directly controlled by it through the program. This does not include
the I/O devices connected to PC inputs and outputs.
If you are not familiar with the terms used above to describe a PC, refer to
Section 2 Hardware Considerations
A device connected to the PC that sends a signal to the PC is called an input
device; the signal it sends is called an input signal. A signal enters the PC
through terminals or through pins on a connector on a Unit. The place where
a signal enters the PC is called an input point. This input point is allocated a
location in memory that reflects its status, i.e., either ON or OFF. This memory location is called an input bit. The CPU in its normal processing cycle
monitors the status of all input points and turns ON and OFF corresponding
input bits accordingly.
There are also output bits in memory that are allocated to output points on
Units through which output signals are sent to output devices, i.e., an output bit is turned ON to send a signal to an output device through an output
point. The CPU periodically turns output points ON and OFF according to the
status of the output bits.
These terms are used when describing different aspects of PC operation.
When programming, one is concerned with what information is held in memory, and so I/O bits are referred to. When describing the Units that connect
the PC to the controlled system and the places on these Units where signals
enter and leave the PC, I/O points are referred to. When wiring these I/O
points, the physical counterparts of the I/O points, either terminals or connector pins, are referred to. When describing the signals that enter or leave the
system, reference is made to input signals and output signals, or sometimes
just inputs and outputs.
for explanations.
Controlled System and
Control System
The Control System includes the PC and all I/O devices it uses to control an
external system. A sensor that provides information to achieve control is an
input device that is clearly part of the Control System. The controlled system
is the external system that is being controlled by the PC program through
these I/O devices. I/O devices can sometimes be considered part of the controlled system, e.g., a motor used to drive a conveyor belt.
1-4 OMRON Product Terminology
OMRON products are divided into several functional groups that have generic names.
The term Unit is used to refer to all OMRON PC products, depending on the
context.
The largest group of OMRON products is I/O Units. I/O Units come in a variety of point quantities and specifications.
Appendix A Standard Models
list products by these groups.
3
Overview of PC Operation Section 1-5
Special I/O Units are dedicated Units that are designed to meet specific
needs. These include Analog Timer Units and Analog I/O Units.
Link Units are used to create Link Systems that link more than one PC or
link a single PC to remote I/O points. Link Units include I/O Link Units that
are used to connect K-type PCs to Remote I/O Systems controlled by a larger PC (e.g. C1000H) and Host Link Units.
Other product groups include Programming Devices and Peripheral De-
vices.
1-5 Overview of PC Operation
The following are the basic steps involved in programming and operating a
K-type PC. Assuming you have already purchased one or more of these
PCs, you must have a reasonable idea of the required information for steps
one and two, which are discussed briefly below. This manual is written to explain steps three through six, eight, and nine. The section(s) of this manual
that provide relevant information are listed with each of these steps.
1, 2, 3...
1. Determine what the controlled system must do, in what order, and at
what times.
2. Determine what Units will be required. Refer to the
a Link System is required, refer to the required
3. On paper, assign all input and output devices to I/O points on Units and
determine which I/O bits will be allocated to each. If the PC includes
Special I/O Units or Link Systems, refer to the individual
or
Manuals
Memory Areas
4. Using relay ladder symbols, write a program that represents the se-
quence of required operations and their inter-relationships. Be sure to
also program appropriate responses for all possible emergency situations. (
tion Set
5. Input the program and all required operating parameters into the PC.
Section 4 Writing and Inputting the Program
(
6. Debug the program, first to eliminate any syntax errors and then to elim-
inate execution errors. (
System Manuals
)
Section 4 Writing and Inputting the Program, Section 5 Instruc-
, and
Section 6 Program Execution Timing)
for details on I/O bit allocation. (
Section 4 Writing and Inputting the Program,
Section 7 Program Debugging and Execution
Troubleshooting
7. Wire the PC to the controlled system. This step can actually be started
as soon as step 3 has been completed. Refer to the
and to
Operation Manuals
Units.
8. Test the program in an actual control situation and fine tune it if required.
Section 7 Program Debugging and Execution
(
Troubleshooting
9. Record two copies of the finished program on masters and store them
safely in different locations. (
)
tion
)
and
System Manuals
)
Section 7 Program Debugging and Execu-
Installation Guide
System Manual(s)
Operation
Section 3
)
, and
Section 8
Installation Guide
for details on individual
and
Section 8
. If
.
Control System Design
4
Designing the Control System is the first step in automating any process. A
PC can be programmed and operated only after the overall Control System is
fully understood. Designing the Control System requires a thorough understanding of the system that is to be controlled. The first step in designing a
Control System is thus determining the requirements of the controlled system.
Peripheral Devices Section 1-6
Input/Output Requirements
Sequence, Timing, and
Relationships
Unit Requirements
The first thing that must be assessed is the number of input and output points
that the controlled system will require. This is done by identifying each device
that is to send an input signal to the PC or which is to receive an output signal from the PC. Keep in mind that the number of I/O points available depends on the configuration of the PC. Refer to
for details on I/O capacity and assigning I/O bits to I/O points.
Next, determine the sequence in which control operations are to occur and
the relative timing of the operations. Identify the physical relationships between the I/O devices as well as the kinds of responses that should occur
between them.
For instance, a photoelectric switch might be functionally tied to a motor by
way of a counter within the PC. When the PC receives an input from a start
switch, it could start the motor. The PC could then stop the motor when the
counter has received five input signals from the photoelectric switch.
Each of the related tasks must be similarly determined, throughout the entire
control operation.
The actual Units that will be mounted must be determined according to the
requirements of the I/O devices. This will include actual hardware specifications, such as voltage and current levels, as well as functional considerations, such as those that require Special I/O Units or Link Systems. In many
cases, Special I/O Units or Link Systems can greatly reduce the programming burden. Details on these Units and Link Systems are available in indi-
Operation Manuals
vidual
Once the entire Control System has been designed, the task of program-
ming, debugging, and operation as described in the remaining sections of
this manual can begin.
and
System Manuals.
3-3 Internal Relay (IR) Area
1-6 Peripheral Devices
The following peripheral devices can be used in programming, either to input/
debug/monitor the PC program or to interface the PC to external devices to
output the program or memory area data. Model numbers for all devices
listed below are provided in
names have been placed in bold when introduced in the following descriptions.
Programming Console
Graphic Programming
Console: GPC
Ladder Support Software:
LSS
A Programming Console is the simplest form of programming device for OMRON PCs. Although a Programming Console Adapter is sometimes required, all Programming Consoles are connected directly to the CPU without
requiring a separate interface. The Programming Console also functions as
an interface to output programs to a standard cassette tape recorder.
Various types of Programming Console are available, including both
CPU-mounting and Handheld models. Programming Console operations are
described later in this manual.
A Peripheral Interface Unit is required to interface the GPC to the PC.
The GPC also functions as an interface to output programs directly to a stan-
dard cassette tape recorder. A PROM Writer, Floppy Disk Interface Unit, or
Printer Interface Unit can be directly mounted to the GPC to output programs directly to an EPROM chip, floppy disk drive, or printing device.
LSS is designed to run on IBM AT/XT compatibles to enable nearly all of the
operations available on the GPC. It also offers extensive documentation capabilities.
Appendix A Standard Models
. OMRON product
5
Available Manuals Section 1-7
A Host Link Unit is required to interface a computer running LSS to the PC.
Using an Optical Host Link Unit also enables the use of optical fiber cable to
connect the FIT to the PC. Wired Host Link Units are available when desired.
(Although FIT does not have optical connectors, conversion to optical fiber
cable is possible by using Converting Link Adapters.)
Factory Intelligent Terminal:
FIT
PROM Writer
Floppy Disk Interface Unit
Printer Interface Unit
The FIT is an OMRON computer with specially designed software that allows
you to perform all of the operations that are available with the GPC or LSS.
Programs can also be output directly to an EPROM chip, floppy disk drive, or
printing device without any additional interface units. The FIT has an EPROM
writer and two 3.5” floppy disk drives built in.
A Peripheral Interface Unit or Host Link Unit is required to interface the
FIT to the PC. Using an Optical Host Link Unit also enables the use of optical
fiber cable to connect the FIT to the PC. Wired Host Link Units are available
when desired. (Although FIT does not have optical connectors, conversion to
optical fiber cable is possible by using Converting Link Adapters.)
Other than its applications described above, the PROM Writer can be
mounted to the PC’s CPU to write programs to EPROM chips.
Other than its applications described above, the Floppy Disk Interface Unit
can be mounted to the PC’s CPU to interface a floppy disk drive and write
programs onto floppy disks.
Other than its applications described above, the Printer Interface Unit can be
mounted to the PC’s CPU to interface a printer or X-Y plotter to print out programs in either mnemonic or ladder-diagram form.
1-7 Available Manuals
The following table lists other manuals that may be required to program and/
or operate the K-type PCs.
Operation Manuals
also provided with individual Units and are required for wiring and other
specifications.
Name Cat. No. Contents
Installation Guide W147 Hardware specifications
Data Access Console Operation Guide W173 Procedures for monitoring and manipulating data.
GPC Operation Manual W84 Programming procedures for the GPC (Graphics
Programming Console)
FIT Operation Manual W150 Programming procedures for using the FIT (Factory Intelligent
Terminal
LSS Operation Manual W237 Programming procedures for using LSS (Ladder Support
Software)
Printer Interface Unit Operation Guide W107 Procedures for interfacing a PC to a printer
PROM Writer Operation Guide W155 Procedures for writing programs to EPROM chips
Floppy Disk Interface Unit Operation Guide W119 Procedures for interfacing a PC to a floppy disk drive
Optical Remote I/O System Manual W136 Information on building an Optical Remote I/O System to
enable remote I/O capability
Host Link System Manual W143 Information on building a Host Link System to manage PCs
from a ‘host’ computer
K-type Analog I/O Units Operation Guide W122 Hardware and software information on using Analog I/O Units
with the K-type PCs.
and/or
Operation Guides
are
6
SECTION 2
Hardware Considerations
2-1 Introduction 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-2 Indicators 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-3 PC Configuration 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
PC Configuration Section 2-3
2-1 Introduction
This section provides information on hardware aspects of K-type PCs that
are relevant to programming and software operation. These include indicators on the CPU and basic PC configuration. This information is covered in
detail in the
Installation Guide
.
2-2 Indicators
CPU indicators provide visual information on the general operation of the PC.
Using the flags and other error indicators provided in the memory data areas,
although not a substitute for proper error programming, provides ready confirmation of proper operation.
CPU Indicators
CPU indicators are located on the front right hand side of the PC adjacent to
the I/O expansion slot and are described in the following table.
Indicator Function
POWER Lights when power is supplied to the CPU.
RUN Lights when the CPU is operating normally .
ERR Lights when an error is discovered in system error diagnosis
ALARM Lights when an error is discovered in system error diagnosis
2-3 PC Configuration
The system must contain a K-type CPU and may additionally contain an Expansion I/O Unit, Special I/O Units and/or I/O Link Units.
The Expansion I/O Units are not a required part of the basic system and are
used to increase the number of I/O points available. Special I/O Units and I/O
Link Units are used to reduce programming complexity.
operations. When this indicator lights, the RUN indicator will go
off, CPU operation will be stopped, and all outputs from the PC
will be turned OFF.
operations. PC operation will continue.
8
SECTION 3
Memory Areas
3-1 Introduction 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-2 Data Area Structure 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3 Internal Relay (IR) Area 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4 Special Relay (SR) Area 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-1 Battery Alarm Flag 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-2 Cycle Time Error Flag 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-3 High-speed Drum Counter Reset 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-4 Clock Pulse Bits 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-5 Error Flag (ER) 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-6 Step Flag 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-7 Always OFF, Always ON Flags 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-8 First Cycle Flag 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-9 Arithmetic Flags 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5 Data Memory (DM) Area 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-6 Holding Relay (HR) Area 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-7 Timer/Counter (TC) Area 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-8 Temporary Relay (TR) Area 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
Data Area Structure Section 3-2
3-1 Introduction
Various types of data are required to achieve effective and correct control. To
facilitate managing this data, the PC is provided with various memory areas
for data, each of which performs a different function. The areas generally accessible by the user for use in programming are classified as data areas.
The other memory area is the Program Memory, where the user’s program is
actually stored.
This section describes these areas individually and provides information that
will be necessary to use them. The name, acronym, range, and function of
each area are summarized in the following table. All but the last one of these
are data areas. All memory areas are normally referred to by their acronyms.
Area Acronym Range Function
Internal Relay
area
Special Relay
area
Data Memory
area
Holding Relay
area
Timer/Counter
area
Temporary Relay
area
Program Memory UM UM: 1,194 words. Contains the program executed by the CPU.
IR Words: 00 to 18 (bits 00 to 07)
Bits: 0000 to 1807
SR Words: 18 (bits 08 to 15) and
19 (bits 00 to 07)
Bits: 1808 to 1907
DM DM 00 to DM 63
(words only)
HR Words: HR 0 to HR 9
Bits: HR 000 to HR 915
TC TC 00 to TC 47 (TC numbers are
used to access other information)
TR TR 00 to TR 07 (bits only) Used to temporarily store execution conditions.
Used to manage I/O points, control other bits,
timers, and counters, to temporarily store data.
Contains system clocks, flags, control bits, and
status information.
Used for internal data storage and manipulation.
Used to store data and to retain the data values
when the power to the PC is turned off.
Used to define timers and counters and to access
completion flags, PV, and SV for them.
Work Bits and Words
When some bits and words in certain data areas are not used for their intended purpose, they can be used in programming as required to control
other bits. Words and bits available for use in this fashion are called work bits
and work words. Most, but not all, unused bits can be used as work bits.
Those that can be are specified by area in the remainder of this section. Actual application of work bits and work words is described in
and Inputting the Program
Flags and Control Bits
Some data areas contain flags and/or control bits. Flags are bits that are
automatically turned ON and OFF to indicate status of one form or another.
Although some flags can be turned ON and OFF by the user, most flags can
be read only; they cannot be controlled directly.
Control bits are bits turned ON and OFF by the user to control specific aspects of operation. Any bit given a name using the word bit rather than the
word flag is a control bit, e.g., Restart Bits are control bits.
3-2 Data Area Structure
When designating a data area, the acronym for the area is always required
for any but the IR and SR areas. Although the acronyms for the IR and SR
areas are often given for clarity, they are not required and not input when
programming. Any data area designation without an acronym is assumed to
be in either the IR and SR area. Because IR and SR addresses run consecutively, the word or bit addresses are sufficient to differentiate these two areas.
Section 4 Writing
.
10
An actual data location within any data area but the TC area is designated by
its address. The address designates the bit and/or word within the area
where the desired data is located. The TR area consists of individual bits
Data Area Structure Section 3-2
used to store execution conditions at branching points in ladder diagrams.
The use of TR bits is described in
The TC area consists of TC numbers, each of which is used for a spe-
gram.
cific timer or counter defined in the program. Refer to
for more details on TC numbers and to
Area
for information on actual application.
tions
The rest of the data areas (i.e., the IR, SR, HR and DM areas) consist of
words, each of which consists of 16 bits numbered 00 through 15 from right
to left. IR words 00 and 01 are shown below with bit numbers. Here, the content of each word is shown as all zeros. Bit 00 is called the rightmost bit; bit
15, the leftmost bit.
Bit number 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
IR word 00 0000000000000000
IR word 01 0000000000000000
The term least significant is often used for rightmost; the term most signifi-
Note
cant, for leftmost. These terms have not been used in this manual because a
single word is often split into two or more parts, with each part used for different parameters or operands, sometimes even with bits in another word.
When this is done, the rightmost bits in a word may actually be the most significant bits, i.e., the leftmost bits, of a value with other bits, i.e., the least significant bits, contained in another word.
Section 4 Writing and Inputting the Pro-
3-7 Timer/Counter (TC)
5-11 Timer and Counter Instruc-
Data Structure
Digit number 3210
The DM area is accessible by word only; you cannot designate an individual
bit within a DM word. Data in the IR, SR and HR areas is accessible either by
bit or by word, depending on the instruction in which the data is being used.
To designate one of these areas by word, all that is necessary is the acronym
(if required) and the one or two-digit word address. To designate an area by
bit, the word address is combined with the bit number as a single three- or
four-digit address. The examples in the following table should make this
clear. The two rightmost digits of a bit designation must indicate a bit between 00 and 15.
The same TC number can be used to designate either a word containing the
present value (PV) of the timer or counter or a bit that functions as the completion flag for the timer or counter. This is explained in more detail in
Timer/Counter (TC) Area
Area Word designation Bit designation
IR 00 0015 (leftmost bit in word 00)
SR 19 1900 (rightmost bit in word 19)
DM DM 10 Not possible
TC TC 46 (designates PV) TC 46 (designates completion flag)
.
3-7
Word data input as decimal values is stored in binary-coded decimal (BCD)
code; word data input as hexadecimal is stored in binary form. Because each
word contains 16 bits, each four bits of a word represents one digit: either a
hexadecimal digit equivalent numerically to the binary bits or decimal. One
word of data thus contains four digits, which are numbered from right to left.
These digit numbers and the corresponding bit numbers for one word are
shown below.
Bit number
Contents 0000000000000000
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
11
Internal Relay (IR) Area Section 3-3
When referring to the entire word, the digit numbered 0 is called the rightmost digit; the one numbered 3, the leftmost digit.
When inputting data into data areas, it must be input in the proper form for
the intended purpose. This is no problem when designating individual bits,
which are merely turned ON (equivalent to a binary value of 1) or OFF (a binary value of 0). When inputting word data, however, it is important to input it
either as decimal or as hexadecimal, depending on what is called for by the
instruction it is to be used for.
ticular form of data is required for an instruction.
Section 5 Instruction Set
specifies when a par-
Converting Different Forms
of Data
Binary and hexadecimal can be easily converted back and forth because
each four bits of a binary number is numerically equivalent to one digit of a
hexadecimal number. The binary number 0101111101011111 is converted to
hexadecimal by considering each set of four bits in order from the right. Binary 1111 is hexadecimal F; binary 0101 is hexadecimal 5. The hexadecimal
equivalent would thus be 5F5F, or 24,415 in decimal (16
x 5 + 15).
Decimal and BCD can also be easily converted back and forth. In this case,
each BCD digit (i.e., each four BCD bits) is numerically equivalent of the corresponding decimal digit. The BCD bits 0101011101010111 are converted to
decimal by considering each four bits from the right. Binary 0101 is decimal
5; binary 0111 is decimal 7. The decimal equivalent would thus be 5,757.
Note that this is not the same numeric value as the hexadecimal equivalent
of 0101011101010111, which would be 5,757 hexadecimal, or 22,359 in decimal (16
Because the numeric equivalent of each four BCD binary bits must be
equivalent to a decimal value, any four bit combination numerically greater
then 9 cannot be used, e.g., 1011 is not allowed because it is numerically
equivalent to 11, which cannot be expressed as a single digit in decimal notation. The binary bits 1011 are of course allowed in hexadecimal and they are
equivalent to the hexadecimal digit C.
There are instructions provided to convert data in either direction between
BCD and hexadecimal. Refer to
binary equivalents to hexadecimal and BCD digits are provided in the appendices for reference.
3
x 5 + 162 x 7 + 16 x 5 + 7).
5-15 Data Conversion
3
x 5 + 162 x 15 + 16
for details. Tables of
Decimal Points
Decimal points are used in timers only. The least significant digit represents
tenths of a second. All arithmetic instructions operate on integers only.
3-3 Internal Relay (IR) Area
The IR area is used both to control I/O points and as work bits to manipulate
and store data internally. It is accessible both by bit and by word. Those
words that can be used to control I/O points are called I/O words. Bits in I/O
words are called I/O bits.
The number of I/O words varies between the K-type PCs. As shown, the IR
area is comprised of three main sections. These are input words, output
words and work words (work bits). Work bits are used in programming to manipulate data and control other bits. IR area work bits are reset when power
is interrupted or PC operation is stopped.
12
Internal Relay (IR) Area Section 3-3
I/O Words
Input Bit Usage
Output Bit Usage
The maximum number of available I/O bits is 16 (bits/word) times the number
of I/O words. I/O bits are assigned to input or output points as described in
Word Allocations
If a Unit brings inputs into the PC, the bit assigned to it is an input bit; if the
Unit sends an output from the PC, the bit is an output bit. To turn on an output, the output bit assigned to it must be turned ON. When an input turns on,
the input bit assigned to it also turns ON. These facts can be used in the program to access input status and control output status through I/O bits.
I/O bits that are not assigned to I/O points can be used as work bits, unless
otherwise specified in
Input bits can directly input external signals to the PC and can be used in any
order in programming. Each input bit can also be used in as many instructions as required to achieve effective and proper control. They cannot be
used in instructions that control bit status, e.g., the OUTPUT, DIFFERENTIATION UP, and KEEP instructions.
Output bits are used to output program execution results and can be used in
any order in programming. Because outputs are refreshed only once during
each cycle (i.e. once each time the program is executed), any output bit can
be used in only one instruction that controls its status, including OUT, OUT
NOT, KEEP(11), DIFU(13), DIFD(14), and SFT(10). If an output bit is used in
more than one such instruction, only the status determined by the last instruction will actually be output from the PC. See
SFT(10)
for an example of an output bit controlled by two instructions.
.
Word Allocations
.
5-12-1 SHIFT REGISTER -
Word Allocations
The maximum number of words available for I/O within the IR area is 10,
numbered 00 through 09. The remaining words (10 through 18) are to be
used for work bits. (Note that with word 18, only the bits 00 through 07 are
available for work bits although some of the remaining bits are required for
special purposes when RDM is used).
The actual number of bits that can be used as I/O bits is determined by the
model of the CPU and the PC configuration. There are different models of
Expansion I/O Units and Special I/O Units and I/O Link Units which can be
connected to any of the CPUs. Each CPU model provides a particular number of I/O bits and each Expansion I/O Unit, Special I/O Unit or I/O Link Unit
provides a particular number of I/O bits. Configuration charts for the possible
combinations of CPUs and Units are included later in this section. Refer to
those to determine the actual available I/O bits.
Within CPUs the I/O input words are always even numbered and the output
words are always odd numbered. The general rule when connecting Expansion I/O Units to CPUs is that the first available word for the Expansion I/O
Unit (whether input or output or a combination) is one more than the last I/O
word of the CPU. If the Expansion I/O Unit is only either input or output (and
not both) then the I/O words provided by the Expansion I/O Unit are allocated
consecutively and the remaining words up to word 09 may be used for work
bits. If the Expansion I/O Unit provides both input and output words then the
words are allocated alternatively (input words always having even numbers)
until all I/O words provided by the Expansion I/O Unit are allocated. The remaining words up to word 09 may then be used for work bits. Note that when
a portion of an input word is not allocated to an input point then that portion
may be used for work bits.
13
Internal Relay (IR) Area Section 3-3
I/O Bits Available in CPUs
The following table shows which bits can be used as I/O bits in each of the
K-type CPUs. Bits in the shaded areas can be used as work bits but not as
output bits.
Model Input bits
Word 00
00
08
01
09
02
C20K
C28K
C40K
C60K
03
04
05
06
07
Word 00
00
01
02
03
04
05
06
07
Word 00
00
01
02
03
04
05
06
07
Word 00
00
01
02
03
04
05
06
07
10
11
Cannot
be
used.
08
09
10
11
12
13
14
15
08
09
10
11
12
13
14
15
08
09
10
11
12
13
14
15
indicates words that cannot be used for I/O,
but can be used as work bits.
Word 02
00
01
02
03
04
05
06
07
Word 02
00
01
02
03
04
05
06
07
Cannot
be
used.
08
09
10
11
12
13
14
15
Output bits
Word 01
00
01
02
03
04
05
06
07
Word 01
00
01
02
03
04
05
06
07
Word 01
00
01
02
03
04
05
06
07
Word 01
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
08
09
10
11
12
13
14
15
Word 03
00
01
02
03
04
05
06
07
Word 03
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
08
09
10
11
12
13
14
15
08
09
10
11
12
13
14
15
08
09
10
11
12
13
14
15
14
Internal Relay (IR) Area Section 3-3
I/O Bits Available in
Expansion I/O Units
The following table shows which bits can be used as I/O bits in each of the
Expansion I/O Units. Bits in the shaded areas can be used as work bits but
not as output bits. The word addresses depend on the CPU that the Expansion I/O Unit is coupled to. In all cases the first Expansion I/O Unit address
for input and output words is one more than the last CPU address for input
and output words. For example, the last CPU word address for a C40K CPU
is 03 and hence the first input or output word address for any of the Expansion I/O Units coupled to a C40K CPU will be 04. In the tables below “n” is
the last CPU word allocated as an input or output word.
There are several models for some of the Units listed below. A blank space
(_) in the model number indicates that any of the applicable model numbers
could be inserted here.
Model Input bits Output bits Model Input bits Output bits
Word (n + 1)
00
01
02
03
04
05
06
07
Word (n + 1)
00
01
02
03
Cannot
be used
Word (n + 1)
00
01
02
03
Cannot
be used
08
09
10
11
12
13
14
15
Word (n + 1)
00
08
01
09
02
10
03
11
04
12
05
13
06
14
07
15
Word (n + 1)
00
08
01
09
02
10
03
11
04
12
05
13
06
14
07
15
Word (n + 2)
00
08
01
09
02
10
03
11
04
12
05
13
06
14
07
15
C20P
C28P
C40P
C60P
Word (n+1)
00
01
02
03
04
05
06
07
Word (n+1)
00
01
02
03
04
05
06
07
Word (n+1)
00
01
02
03
04
05
06
07
Word (n+1)
00
01
02
03
04
05
06
07
08
09
10
11
Cannot
be
used.
08
09
10
11
12
13
14
15
08
09
10
11
12
13
14
15
08
09
10
11
12
13
14
15
Word (n + 2)
00
08
01
09
02
10
03
11
04
12
05
13
06
14
07
15
Word (n + 2)
00
08
01
09
02
10
03
11
04
12
05
13
06
14
07
15
Word (n + 3)
00
01
02
Cannot
03
used.
04
05
06
07
Word (n + 3)
00
01
02
03
04
05
06
07
Word (n + 2)
00
01
02
03
be
04
05
06
07
Word (n + 2)
08
00
09
01
10
02
11
03
12
04
13
05
14
06
15
07
Word (n + 4)
00
01
02
03
04
05
06
07
Word (n + 4)
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
08
09
10
11
12
13
14
15
08
09
10
11
12
13
14
15
08
09
10
11
12
13
14
15
indicates words that cannot be used for I/O,
but can be used as work bits.
C16P
-Ij-j
C16P
-Oj-j
C4K-Ij
C4K-Oj
C4K-TM
15
Internal Relay (IR) Area Section 3-3
PC Configuration
A K-type PC can be configured with a CPU Unit and one or more of the following Units: Expansion I/O Units, Analog Timer Units, or an I/O Link Unit. All
of these Units are connected in series with the CPU Unit at one end. An I/O
Link Unit, if included, must be on the other end (meaning only one I/O Link
Unit can be used) and an Analog Timer Unit cannot be used. The rest of the
Units can be in any order desired.
There is also a restriction in the number of Units which can be included. To
compute the number of Units for this restriction, add up all of the Units counting the C40K CPU Unit, C60K CPU Unit, C40K Expansion I/O Unit and C60K
Expansion I/O Unit as two Units each and any other Units as one Unit each.
This total must be no more than five.
The following table shows some of the combinations that can be used to
achieve specific numbers of I/O points. The numbers in the table indicate the
number of Units of that size to be used as either the CPU or Expansion I/O
Unit; any one of the Units can be the CPU Unit. This table does not include
the C4P or C16P Expansion I/O Units, the Analog Timer Unit, or the I/O Link
Unit, which can be used for greater system versatility or special applications.
Refer to the remaining tables in this section for other combinations.
I/O points Count as 2
each
Total In Out C60j
(32/28)
20 12 8 --- --- --- 1
28 16 12 --- --- 1 --40 24 16
48 28 20 --- --- 1 1
56 32 24 --- --- 2 --60
32 28 1 --- --- --36 24
68 40 28
76 44 32 --- --- 2 1
80 48 32
84 48 36 --- --- 3 --88
48 40 1 --- 1 --52 36
96 56 40
100 56 44
--- --- --- 2
--- 1 --- ---
--- --- --- 3
--- 1 --- 1
--- --- 1 2
--- 1 1 ---
--- --- --- 4
--- 1 --- 2
--- 2 --- ---
--- --- 1 3
--- 1 1 1
--- --- 2 2
--- 1 2 ---
C40j
(24/16)
1 --- --- 2
1 --- --- 2
1 1 --- ---
Count as 1
each
C28j
(16/12)
C20j
(12/8)
I/O points Count as 2
each
Total In Out C60j
(32/28)
100 60 40
104 60 44 --- --- 3 1
108
60 48 1 --- 1 1
64 44
112 64 48 --- --- 4 --116
64 52 1 --- 2 --68 48
120
64 56 2 --- --- --68 52
124 72 52
128 72 56
132 76 56 --- --- 4 1
136 76 60 1 --- 2 1
140
76 64 2 --- --- 1
80 60 --- --- 5 --144 80 64 1 --- 3 --148 80 68 2 --- 1 ---
--- --- --- 5
--- 1 --- 3
--- 2 --- 1
--- --- 1 4
--- 1 1 2
--- 2 1 ---
--- --- 2 3
--- 1 2 1
--- --- 3 2
--- 1 3 ---
C40j
(24/16)
1 --- --- 3
1 1 --- 1
1 --- 1 2
1 1 1 ---
Count as 1
each
C28j
(16/12)
C20j
(12/8)
16
Internal Relay (IR) Area Section 3-3
The tables on the following pages show the possible configurations for a
K-type PC. Although the tables branch to show the various possibilities at
any one point, there can be no branching in the actual PC connections. You
can choose either branch at any point and go as far as required, i.e., you can
break off at any point to create a smaller PC System.When implementing a
system there is a physical restriction on the total cable length allowable. The
sum of the lengths of all cables in the system must be limited to less than 1.2
meters.
The tables also show which words will be input words and which words will
be output words. All of these are determined by the position of the Unit in the
configuration except for the C4P and C16P Expansion I/O Units, in which
case the model of the Unit determines whether the words are input or output.
The symbols used in the table represent the following:
C20K/C28K
Input Output
Input Output
C4K/C16P
In/Output
C20P/C28P/TU/LU,
Input Output
Input Output Input Output
C4P or C16P Expansion I/O Unit
C20K or C28K CPU Unit
C40K/C60K
Input Output
C20P Expansion I/O Unit, C28K Expansion I/O Unit,
Analog Timer Unit, or I/O Link Unit
C40P/C60P
C40K or C60K CPU Unit
C40P or C60P Expansion I/O Unit
17
Internal Relay (IR) Area Section 3-3
IR 00 IR 01 IR 02 IR 03 IR 04 IR 05 IR 06 IR 07 IR 08 IR 09
C20K/C28K
Input Output
C4K/C16P
In/Output
C4K/C16P
In/Output
C20P/C28P/TU/LU
Input Output
C4K/C16P
In/Output
C4K/C16P
In/Output
C20P/C28P/TU/LU
Input Output
C20P/C28P/TU/LU
Input Output
Input Output Input Output
C4K/C16P
In/Output
C20P/C28P/TU/LU
Input Output
C4K/C16P
In/Output
C20P/C28P/TU/LU
Input Output
C40P/C60P
C4K/C16P
In/Output
C20P/C28P/TU/LU
Input Output
C4K/C16P
In/Output
C20P/C28P/TU/LU
Input Output
Input Output Input Output
C20P/C28P/TU/LU
Input Output
C40P/C60P
C4K/C16P
In/Output
C40P/C60P
Input Output Input Output
C4K/C16P
In/Output
C20P/C28P/TU/LU
Input Output
C4K/C16P
In/Output
C20P/C28P/TU/LU
Input Output
Input Output Input Output
C4K/C16P
In/Output
C20P/C28P/TU/LU
Input Output
C4K/C16P
In/Output
C20P/C28P/TU/LU
Input Output
C40P/C60P
18
Internal Relay (IR) Area Section 3-3
IR 00 IR 01 IR 02 IR 03 IR 04 IR 05 IR 06 IR 07 IR 08 IR 09
C20K/C28K
Input Output
C20P/C28P/TU/LU
Input Output
C40P/C60P
Input Output Input Output
C20P/C28P/TU/LU
Input Output
Input Output Input Output
C4K/C16P
In/Output
C40P/C60P
C4K/C16P
In/Output
C4K/C16P
In/Output
C20P/C28P/TU/LU
Input Output
C20P/C28P/TU/LU
Input Output
Input Output Input Output
C4K/C16P
In/Output
C20P/C28P/TU/LU
Input Output
C4K/C16P
In/Output
C20P/C28P/TU/LU
Input Output
C40P/C60P
C4K/C16P
In/Output
C20P/C28P/TU/LU
Input Output
C20P/C28P/TU/LU
Input Output
Input Output Input Output
C4K/C16P
In/Output
C20P/C28P/TU/LU
Input Output
C40P/C60P
19
Internal Relay (IR) Area Section 3-3
IR 00 IR 01 IR 02 IR 03 IR 04 IR 05 IR 06 IR 07 IR 08 IR 09
C40K/C60K
Input Output
Input Output
C4K/C16P
In/Output
C20P/C28P/TU/LU
Input Output
C4K/C16P
In/Output
C4K/C16P
In/Output
C20P/C28P/TU/LU
Input Output
C20P/C28P/TU/LU
Input Output
Input Output Input Output
C4K/C16P
In/Output
C20P/C28P/TU/LU
Input Output
C4K/C16P
In/Output
C20P/C28P/TU/LU
Input Output
C40P/C60P
C4K/C16P
In/Output
C20P/C28P/TU/LU
Input Output
C4K/C16P
In/Output
C40K/C60K
Input Output
Input Output
C20P/C28P/TU/LU
Input Output
C40P/C60P
Input Output Input Output
C20P/C28P/TU/LU
Input Output
Input Output Input Output
C20P/C28P/TU/LU
Input Output
C40P/C60P
C4K/C16P
In/Output
C20P/C28P/TU/LU
Input Output
20
Special Relay (SR) Area Section 3-4
3-4 Special Relay (SR) Area
The SR area contains flags and control bits used for monitoring system operation, accessing clock pulses, and signalling errors. SR area word addresses range from 18 through 19; bit addresses, from 1804 through 1907.
The following table lists the functions of SR area flags and control bits. Most
of these bits are described in more detail following the table.
Unless otherwise stated, flags are OFF until the specified condition arises,
when they are turned ON. Bits 1903 to 1907 are turned OFF when END is
executed at the end of each program cycle, and thus cannot be monitored on
the Programming Console. Other control bits are OFF until set by the user.
Word Bit Function
18 04 RDM(60) Reset Bit
05 RDM(60) Count Input Bit
06 RDM(60) Up/Down Selection Bit
07 HDM(61) Reset Bit
08 Battery Alarm flag
09 Cycle Time Error flag
10 High Speed Counter Reset
11 Step flag
12 Always OFF flag
13 Always ON flag
14 Always OFF flag
15 First Cycle flag
19 00 0.1-second Clock Pulse
01 0.2-second Clock Pulse
02 1-second Clock Pulse
03 Error (ER) flag
04 Carry (CY) flag
05 Greater Than (GR) flag
06 Equals (EQ) flag
07 Less Than (LE) flag
3-4-1 Battery Alarm Flag
SR bit 1808 turns ON if the voltage of the CPU backup battery drops. A voltage drop can be indicated by connecting the output of this bit to an external
indicating device such as a LED. This bit can be used in programming to activate an external warning for a low battery.
3-4-2 Cycle Time Error Flag
SR bit 1809 turns ON if the cycle time exceeds 100 ms. This bit is turned ON
when the cycle time is between 100 and 130 ms. The PC will still operate but
timing may become inaccurate. The PC will stop operating if the execution
time exceeds 130 ms.
3-4-3 High-speed Drum Counter Reset
SR bit 1810 turns ON for one cycle time when the hard reset signal (input
0001) is turned ON.
3-4-4 Clock Pulse Bits
Three clock pulses are available to control program timing. Each clock pulse
bit is ON for the first half of the rated pulse time, then OFF for the second
half. In other words, each clock pulse has a duty factor of 50%.
21
Special Relay (SR) Area Section 3-4
These clock pulse bits are often used with counter instructions to create timers. Refer to
Pulse width 0.1 s 0.2 s 1.0 s
Bit 1900 1901 1902
5-11 Timer and Counter Instructions
for an example of this.
Caution Because the 0.1-second clock pulse bit has an ON time of 50 ms, the CPU may
!
not be able to accurately read the pulses if program execution time is too long.
3-4-5 Error Flag (ER)
SR bit 1903 turns ON when the results of an arithmetic operation is not output in BCD or the value of the BIN data processed by the BIN to BCD or BCD
to BIN conversion instruction exceeds 9999. When the ER flag is ON the current instruction is not executed.
Bit 1900
0.1-s clock pulse
.05 s .05 s
0.1 s
Bit 1902
1.0-s clock pulse
0.5 s 0.5 s
1.0 s
Bit 1901
0.2-s clock pulse
0.1 s 0.1 s
0.2 s
3-4-6 Step Flag
SR bit 1811 turns ON for one cycle when single-step execution is started with
the STEP instruction.
3-4-7 Always OFF, Always ON Flags
SR bits 1812 and 1814 are always OFF and 1813 is always ON. By connecting these bits to external indicating devices such as a LED they can be used
to monitor the PC’s operating status.
3-4-8 First Cycle Flag
SR bit 1815 turns ON when program execution starts and turns OFF after
one cycle.
3-4-9 Arithmetic Flags
The following flags are used in data shifting, arithmetic calculation, and comparison instructions. They are generally referred to only by their two-letter
abbreviations. Refer to
and
5-16 BCD Calculations
Caution These flags are all reset when END is executed, and therefore cannot be moni-
!
tored from a Programming Device.
5-12 Data Shifting, 5-14 DATA COMPARE - CMP(20)
for details.
22
Timer/Counter (TC) Area Section 3-7
Carry Flag, CY
Greater Than Flag, GR
Equal Flag, EQ
Less Than Flag, LE
SR bit 1904 turns ON when there is a carry in the result of an arithmetic operation. The content of CY is also used in some arithmetic operations, e.g., it
is added or subtracted along with other operands. This flag can be set and
cleared from the program using the SET CARRY and CLEAR CARRY instructions. Use CLC before any instruction using CY unless the current content of CY is required.
SR bit 1905 turns ON when the result of a comparison shows the second of
two 4-digit operands to be greater than the first.
SR bit 1906 turns ON when the result of a comparison shows two operands
to be equal or when the result of an arithmetic operation is zero.
SR bit 1907 turns ON when the result of a comparison shows the second of
two 4-digit operands to be less than the first.
Note
Remember that the previous four flags, CY, GR, EQ, and LE, are cleared by
the END instruction.
3-5 Data Memory (DM) Area
The DM area is used for internal data storage and manipulation and is accessible only by word. Addresses range from DM 00 through DM 63.
Although composed of 16 bits just like any other word in memory, DM words
cannot be specified by bit for use in instructions with bit-size operands, such
as LD, OUT, AND, and OR.
When the RDM (REVERSIBLE DRUM COUNTER) is used the DM area
words 00 to 31 are used as the area where the upper and lower limits of the
counter are preset and as such these words cannot be used for any other
purposes.
When the HDM (HIGH-SPEED DRUM COUNTER) is used the DM area
words 32 to 63 are used as the area where the upper and lower limits of the
counter are preset and as such these words cannot be used for any other
purposes.
The DM area retains status during power interruptions.
3-6 Holding Relay (HR) Area
The HR area is used to store and manipulate various kinds of data and can
be accessed either by word or by bit. Word addresses range from HR 0
through HR 9; bit addresses, from HR 000 through HR 915. HR bits can be
used in any order required and can be programmed as often as required.
The HR area retains status when the system operating mode is changed, or
when power is interrupted.
3-7 Timer/Counter (TC) Area
The TC area is used to create and program timers and counters and holds
the completion flags, set values (SV), and present values (PV) for all timers
and counters. All of these are accessed through TC numbers ranging from
TC 00 through TC 47. Each TC number is defined as either a timer or
counter using one of the following instructions: TIM, TIMH, CNT or CNTR. No
prefix is required when using a TC number in a timer or counter instruction.
23
Temporary Relay (TR) Area Section 3-8
Once a TC number has been defined using one of these instructions, it cannot be redefined elsewhere in the program using the same or a different instruction. If the same TC number is defined in more than one of these instructions or in the same instruction twice, an error will be generated during
the program check. There are no restrictions on the order in which TC numbers can be used.
Once defined, a TC number can be designated as an operand in one or more
instructions other than those listed above. When defined as a timer, a TC
number designated as an operand takes a TIM prefix. The TIM prefix is used
regardless of the timer instruction that was used to define the timer. Once
defined as a counter, the TC number designated as an operand takes a CNT
prefix. The CNT is also used regardless of the counter instruction that was
used to define the counter.
TC numbers can be designated for operands that require bit data or for operands that require word data. When designated as an operand that requires
bit data, the TC number accesses the completion flag of the timer or counter.
When designated as an operand that requires word data, the TC number accesses a memory location that holds the PV of the timer or counter.
TC numbers are also used to access the SV of timers and counters from a
Programming Device. The procedures for doing so from the Programming
Console are provided in
7-3 Monitoring Operation and Modifying Data.
The TC area retains the SVs of both timers and counters during power interruptions. The PVs of timers are reset when PC operation is begun and when
reset in interlocked program sections. Refer to
LOCK CLEAR - IL(02) and ILC(03)
in interlocked program sections. The PVs of counters are not reset at these
times.
Note that in programming “TIM 00” is used to designate three things: the
TIMER instruction defined with TC number 00, the completion flag for this
timer, and the PV of this timer. The meaning in context should be clear, i.e.,
the first is always an instruction, the second is always a bit, and the third is
always a word. The same is true of all other TC numbers prefixed with TIM or
CNT. In explanations of ladder diagrams, the completion flag and PV accessed through a TC number are generally called the completion flag or the
PV of the instruction (e.g., the completion flag of TIM 00 is the completion
flag accessed through TC number 00, which has been defined using TIM).
When the RDM (REVERSIBLE DRUM COUNTER) is used, TC 46 is used as
the present value storage area of the counter and thus cannot be used for
any other purpose.
When the HDM (HIGH-SPEED DRUM COUNTER) is used, TC 47 is used as
the present value storage area of the counter and thus cannot be used for
any other purpose.
for details on timer and counter operation
5-7 INTERLOCK AND INTER-
3-8 Temporary Relay (TR) Area
The TR area provides eight bits that are used only with the LD and OUT instructions to enable certain types of branching ladder diagram programming.
The use of TR bits is described in
.
gram
TR addresses range from TR 0 though TR 7. Each of these bits can be used
as many times as required and in any order required as long as the same TR
bit is not used twice in the same instruction block.
24
Section 4 Writing and Inputting the Pro-
SECTION 4
Writing and Inputting the Program
4-1 Introduction 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-2 Instruction Terminology 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3 The Ladder Diagram 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3-1 Basic Terms 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3-2 Mnemonic Code 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3-3 Ladder Instructions 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3-4 OUT and OUT NOT 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3-5 The END Instruction 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3-6 Logic Block Instructions 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3-7 Coding Multiple Right-hand Instructions 39. . . . . . . . . . . . . . . . . . . . . . .
4-3-8 Branching Instruction Lines 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3-9 Jumps 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4 The Programming Console 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4-1 The Keyboard 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4-2 PC Modes 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-5 Preparation for Operation 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-5-1 Entering the Password 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-5-2 Clearing Memory 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-5-3 Clearing Error Messages 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6 Inputting, Modifying, and Checking the Program 49. . . . . . . . . . . . . . . . . . . . . . . . .
4-6-1 Setting and Reading from Program Memory Address 50. . . . . . . . . . . . .
4-6-2 Inputting or Overwriting Programs 51. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-3 Checking the Program 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-4 Displaying the Cycle Time 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-5 Program Searches 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-6 Inserting and Deleting Instructions 57. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7 Controlling Bit Status 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7-1 DIFFERENTIATE UP and DIFFERENTIATE DOWN 59. . . . . . . . . . . .
4-7-2 KEEP 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7-3 Self-maintaining Bits (Seal) 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-8 Work Bits (Internal Relays) 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-9 Programming Precautions 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-10 Program Execution 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
Instruction Terminology Section 4-2
4-1 Introduction
This section explains how to convert ladder diagrams to mnemonic code and
input them into the PC. It then describes the basic steps and concepts involved in programming and introduces the instructions used to build the basic
structure of the ladder diagram and control its execution. The entire set of
instructions used in programming is described in
There are several basic steps involved in writing a program.
Section 5 Instruction Set
.
1, 2, 3...
1. Obtain a list of all I/O devices and the I/O points that have been assigned to them and prepare a table that shows the I/O bit allocated to
each I/O device.
2. If the PC has any Units, i.e. Analog Timer Units, Host Link Units , and
I/O Link Units that are allocated words in data areas other than the IR
area or are allocated IR words in which the function of each bit is specified by the Unit, prepare similar tables to show what words are used for
which Units and what function is served by each bit within the words.
3. Determine what words are available for work bits and prepare a table in
which you can allocate these as you use them.
4. Also prepare tables of TC numbers and jump numbers so that you can
allocate these as you use them. Remember, the function of a TC number can be defined only once within the program; jump numbers 01
through 08 can be used only once each. (TC numbers are described in
5-11 Timer and Counter Instructions
in this section.)
5. Draw the ladder diagram.
6. Input the program into the CPU. When using the Programming Console,
this will involve converting the program to mnemonic form.
7. Check the program for syntax errors and correct these.
8. Execute the program to check for execution errors and correct these.
9. After the entire Control System has been installed and is ready for use,
execute the program and fine tune it if required.
; jump numbers are described later
The basics of writing the ladder diagram and inputting it into memory are described in the rest of this section. Debugging and monitoring operation of the
program are described in
tion 8 Troubleshooting
This section provides the procedures for inputting and debugging a program
and monitoring and controlling the PC through a Programming Console. The
Programming Console is the most commonly used Programming Device for
the K-type PCs. It is compact and available both in handheld models or
CPU-mounted models. Refer to
bers and other details.
If you are using a GPC, FIT, or a computer running LSS, refer to the
tion Manual
for corresponding procedures on these.
4-2 Instruction Terminology
There are basically two types of instructions used in ladder diagram programming: instructions that correspond to conditions on the ladder diagram and
are used in instruction form only when converting a program to mnemonic
code and instructions that are used on the right side of the ladder diagram
and are executed according to the conditions on the instruction lines leading
to them.
Section 7 Program Debugging and Execution. Sec-
also provides information required for debugging.
Appendix A Standard Models
for model num-
Opera-
26
The Ladder Diagram Section 4-3
Most instructions have at least one or more operands associated with them.
Operands indicate or provide the data on which an instruction is to be performed. These are sometimes input as the actual numeric values, but are
usually the addresses of data area words or bits that contain the data to be
used. For instance, a MOVE instruction that has IR 00 designated as the
source operand will move the contents of IR 00 to some other location. The
other location is also designated as an operand. A bit whose address is designated as an operand is called an operand bit; a word whose address is
designated as an operand is called an operand word.
Other terms used in describing instructions are introduced in
struction Set
4-3 The Ladder Diagram
A ladder diagram consists of one line running down the left side with lines
branching off to the right. The line on the left is called the bus bar; the
branching lines, instruction lines or rungs. Along the instruction lines are
placed conditions that lead to other instructions on the right side. The logical
combinations of these conditions determine when and how the instructions at
the right are executed. A simple ladder diagram is shown below.
0000 0315
0001
0100 0002
0010
0011
.
HR 109 12031208 1200
0501 0502 0503 0504
0003 HR 510 0007 TC 01 0515
1001 1002
1005 1007
1201
0403
Section 5 In-
Instruction
0405
Instruction
As shown in the diagram above, instruction lines can branch apart and they
can join back together. The vertical pairs of lines are called conditions. Conditions without diagonal lines through them are called normally open conditions and correspond to a LOAD, AND, or OR instruction. The conditions with
diagonal lines through them are called normally closed conditions and correspond to a LOAD NOT, AND NOT, or OR NOT instruction. The number
above each condition indicates the operand bit for the instruction. It is the
status of the bit associated with each condition that determine the execution
condition for following instructions. The function of each of the instructions
that correspond to a condition is described below. Before we consider these,
however, there are some basic terms that must be explained.
Note When displaying ladder diagrams with a GPC, a FIT, or LSS, a second bus
bar will be shown on the right side of the ladder diagram and will be connected to all instructions on the right side. This does not change the ladder
diagram program in any functional sense. No conditions can be placed between the instructions on the right side and the right bus bar, i.e., all instructions on the right must be connected directly to the right bus bar. Refer to the
GPC, FIT
, or
LSS Operation Manual
for details.
27
The Ladder Diagram Section 4-3
4-3-1 Basic Terms
Normally Open and
Normally Closed
Conditions
Execution Conditions
Operand Bits
Each condition in a ladder diagram is either ON or OFF depending on the
status of the operand bit that has been assigned to it. A normally open condition is ON if the operand bit is ON; OFF if the operand bit is OFF. An normally
closed condition is ON if the operand bit is OFF; OFF if the operand bit is
ON. Generally speaking, you use a normally open condition when you want
something to happen when a bit is ON and an normally closed condition
when you want something to happen when a bit is OFF.
0000
Instruction
Normally open condition
0000
Instruction
Normally closed condition
Instruction is executed
when IR 0000 is ON.
Instruction is executed
when IR 0000 is OFF.
In ladder diagram programming, the logical combination of ON and OFF conditions before an instruction determines the compound condition under which
the instruction is executed. This condition, which is either ON or OFF, is
called the execution condition for the instruction. All instructions except for
LOAD instructions have execution conditions.
The operands designated for any of the ladder instructions can be any bit in
the IR, SR, HR or TC area. This means that the conditions in a ladder diagram can be determined by I/O bits, flags, work bits, timers/counters, etc.
LOAD and OUTPUT instructions can also use TR area bits, but they do so
only in special applications.
Logic Blocks
What conditions correspond to what instructions is determined by the relationship between the conditions established by the instruction lines that connect them. Any group of conditions that go together to create a logic result is
called a logic block. Although ladder diagrams can be written without actually
analyzing individual logic blocks, understanding logic blocks is necessary for
efficient programming and is essential when programs are to be input in mnemonic code.
4-3-2 Mnemonic Code
The ladder diagram cannot be directly input into the PC via a Programming
Console; a GPC, a FIT, or LSS is required. To input from a Programming
Console, it is necessary to convert the ladder diagram to mnemonic code.
The mnemonic code provides exactly the same information as the ladder diagram, but in a form that can be typed directly into the PC. Actually you can
program directly in mnemonic code, although it in not recommended for beginners or for complex programs. Also, regardless of the Programming Device used, the program is stored in memory in mnemonic form, making it important to understand mnemonic code.
Because of the importance of the Programming Console as a peripheral device and because of the importance of mnemonic code in complete understanding of a program, we will introduce and describe the mnemonic code
along with the ladder diagram. Remember, you will not need to use the mnemonic code if you are inputting via a GPC, a FIT, or LSS (although you can
use it with these devices too, if you prefer).
28
The Ladder Diagram Section 4-3
Program Memory Structure
The program is input into addresses in Program Memory. Addresses in Program Memory are slightly different to those in other memory areas because
each address does not necessarily hold the same amount of data. Rather,
each address holds one instruction and all of the definers and operands (described in more detail later) required for that instruction. Because some instructions require no operands, while others require up to three operands,
Program Memory addresses can be from one to four words long.
Program Memory addresses start at 0000 and run until the capacity of Program Memory has been exhausted. The first word at each address defines
the instruction. Any definers used by the instruction are also contained in the
first word. Also, if an instruction requires only a single bit operand (with no
definer), the bit operand is also programmed on the same line as the instruction. The rest of the words required by an instruction contain the operands
that specify what data is to be used. When converting to mnemonic code, all
but ladder diagram instructions are written in the same form, one word to a
line, just as they appear in the ladder diagram symbols. An example of mnemonic code is shown below. The instructions used in it are described later in
the manual.
Address Instruction Operands
0000 LD HR 001
0001 AND 0001
0002 OR 0002
0003 LD NOT 0200
0004 AND 0201
0005 AND LD 0102
0006 MOV(21)
00
DM 00
0007 CMP(20)
DM 00
HR 0
0008 LD 0205
0009 OUT 0101
0010 MOV(21)
DM 00
DM 05
0011 DIFU(13) 0002
0012 AND 0005
0013 OUT 0103
The address and instruction columns of the mnemonic code table are filled in
for the instruction word only. For all other lines, the left two columns are left
blank. If the instruction requires no definer or bit operand, the operand column is left blank for first line. It is a good idea to cross through any blank
data column spaces (for all instruction words that do not require data) so that
the data column can be quickly cycled to see if any addresses have been left
out.
When programming, addresses are automatically displayed and do not have
to be input unless for some reason a different location is desired for the instruction. When converting to mnemonic code, it is best to start at Program
Memory address 0000 unless there is a specific reason for starting elsewhere.
29
The Ladder Diagram Section 4-3
4-3-3 Ladder Instructions
The ladder instructions are those that correspond to the conditions on the
ladder diagram. Ladder instructions, either independently or in combination
with the logic block instructions described next, form the execution conditions
upon which all other instructions are executed.
LOAD and LOAD NOT
AND and AND NOT
The first condition that starts any logic block within a ladder diagram corresponds to a LOAD or LOAD NOT instruction.
0000
A LOAD instruction.
0000
A LOAD NOT instruction.
Address Instruction Operands
0000 LD 0000
0001 Instruction
0002 LD NOT 0000
0003 Instruction
When this is the only condition on the instruction line, the execution condition
for the instruction at the right is ON when the condition is ON. For the LOAD
instruction (i.e., a normally open condition), the execution condition would be
ON when IR 0000 was ON; for the LOAD NOT instruction (i.e., an normally
closed condition), it would be ON when IR 0000 was OFF.
When two or more conditions lie in series on the same instruction line, the
first one corresponds to a LOAD or LOAD NOT instruction; the rest of the
conditions, to AND or AND NOT instructions. The following example shows
three conditions which correspond in order from the left to a LOAD, an AND
NOT, and an AND instruction.
30
0000 0100 HR 000
The instruction at the right would have an ON execution condition only when
all three conditions are ON, i.e., when IR 0000 was ON, IR 0100 was OFF,
and HR 000 was ON.
Actually, AND instructions can be considered individually in series, each of
which would take the logical AND between the execution condition (i.e., the
sum of all conditions up to that point) and the status of the AND instruction’s
operand bit. If both of these were ON, an ON execution condition would be
produced for the next instruction. The execution condition for the first AND
instruction in a series would be the first condition on the instruction line.
Each AND NOT instruction in a series would take the logical AND between
its execution condition and the inverse of its operand bit.
Instruction
Address Instruction Operands
0000 LD 0000
0001 AND NOT 0100
0002 AND HR 000
0003 Instruction
The Ladder Diagram Section 4-3
OR and OR NOT
0000
0100
HR 000
Combining AND and OR
Instructions
When two or more conditions lie on separate instruction lines running in parallel and then joining together, the first condition corresponds to a LOAD or
LOAD NOT instruction; the rest of the conditions correspond to OR or OR
NOT instructions. The following example shows three conditions which correspond in order from the top to a LOAD NOT, an OR NOT, and an OR instruction.
Instruction
Address Instruction Operands
0000 LD 0000
0001 OR NOT 0100
0002 OR HR 000
0003 Instruction
The instruction at the right would have an ON execution condition when any
one of the three conditions was ON, i.e., when IR 0000 was OFF, when IR
0100 was OFF, or when HR 000 was ON.
OR and OR NOT instructions can also be considered individually, each taking the logical OR between its execution condition and the status of the OR
instruction’s operand bit. If either one of these were ON, an ON execution
condition would be produced for the next instruction.
When AND and OR instructions are combined in more complicated diagrams, they can sometimes be considered individually, with each instruction
performing a logic operation on the execution condition and the status of the
operand bit. The following is one example.
0200
0002 00030000 0001
Instruction
Address Instruction Operands
0000 LD 0000
0001 AND 0001
0002 OR 0200
0003 AND 0002
0004 AND NOT 0003
0005 Instruction
Here, an AND is taken between the status of 0000 and that of 0001 to determine the execution condition for an OR with the status of 0200. The result of
this operation determines the execution condition for an AND with the status
of 0002, which in turn determines the execution condition for an AND with the
inverse of the status of 0003. In more complicated diagrams, however, it is
necessary to consider logic blocks before an execution condition can be determined for the final instruction, and that’s where AND LOAD and OR LOAD
instructions are used.
31
The Ladder Diagram Section 4-3
4-3-4 OUT and OUT NOT
The OUT and OUT NOT instructions are used to control the status of the
designated operand bit according to the execution condition. With the OUT
instruction, the operand bit will be turned ON as long as the execution condition is ON and will be turned OFF as long as the execution condition is OFF.
With the OUT NOT instruction, the operand bit will be turned ON as long as
the execution condition is OFF and turned OFF as long as the execution condition is ON. These appear as follows:
0000
0001
In the above examples, bit 0100 will be ON as long as 0000 is ON and bit
0101 will be OFF as long as 0001 is ON. Here, 0000 and 0001 would be input bits and 0100 and 0101 output bits assigned to the Units controlled by
the PC, i.e., the signals coming in through the input points assigned 0000
and 0001 are controlling the output points assigned 0100 and 0101, respectively.
The length of time that a bit is ON or OFF can be controlled by combining the
OUT or OUT NOT instruction with timer instructions. Refer to Examples un-
5-11-1 TIMER - TIM
der
4-3-5 The END Instruction
The last instruction in any program must be the END instruction. When the
CPU cycles the program, it executes all instructions up to the first END instruction before returning to the beginning of the program and beginning execution again. Although an END instruction can be placed at any point in a
program, which is sometimes done when debugging, no instructions past the
first END instruction will be executed until it is removed.
0100
0101
for details.
Address Instruction Operands
0000 LD 0000
0001 OUT 0100
Address Instruction Operands
0000 LD 0001
0001 OUT NOT 0101
0000 0001
Address Instruction Operands
0500 LD 0000
0501 AND NOT 0001
0502 Instruction
0503 END(01) ---
If there is no END instruction anywhere in the program, the program will not
be executed at all.
4-3-6 Logic Block Instructions
Logic block instructions do not correspond to specific conditions on the ladder diagram; rather, they describe relationships between logic blocks. The
AND LOAD instruction logically ANDs the execution conditions produced by
two logic blocks. The OR LOAD instruction logically ORs the execution conditions produced by two logic blocks.
32
Instruction
END(01)
Program execution
ends here.
The Ladder Diagram Section 4-3
AND LOAD
0000
0001
0002
0003
Although simple in appearance, the diagram below requires an AND LOAD
instruction.
Instruction
Address Instruction Operands
0000 LD 0000
0001 OR 0001
0002 LD 0002
0003 OR NOT 0003
0004 AND LD ---
The two logic blocks are indicated by dotted lines. Studying this example
shows that an ON execution condition would be produced when both 1)
either of the conditions in the left logic block was ON (i.e., when either 0000
or 0001 was ON) and 2) either of the conditions in the right logic block was
ON (i.e., when either 0002 was ON or 0003 was OFF).
Analyzing the diagram in terms of instructions, the condition at 0000 would
be a LOAD instruction and the condition below it would be an OR instruction
between the status of 0000 and that of 0001. The condition at 0002 would be
another LOAD instruction and the condition below this would be an OR NOT
instruction, i.e., an OR between the status or 0002 and the inverse of the
status of 0003. To arrive at the execution condition for the instruction at the
right, the logical AND of the execution conditions resulting from these two
blocks would have to be taken. AND LOAD allows us to do this. AND LOAD
always takes an AND between the current execution condition and the last
unused execution condition. An unused execution condition is produced by
using the LOAD or LOAD NOT instruction for any but the first condition on an
instruction line.
OR LOAD
0000 0001
0002 0003
Logic Block Instructions in
Series
Although we’ll not describe it in detail, the following diagram would require an
OR LOAD instruction between the top logic block and the bottom logic block.
An ON execution condition would be produced for the instruction at the right
either when 0000 was ON and 0001 was OFF or when 0002 and 0003 were
both ON.
Instruction
Address Instruction Operands
0000 LD 0000
0001 AND NOT 0001
0002 LD 0002
0003 AND 0003
0004 OR LD ---
Naturally, some diagrams will require both AND LOAD and OR LOAD instructions.
To code diagrams with logic block instructions in series, the diagram must be
divided into logic blocks. Each block is coded using a LOAD instruction to
code the first condition, and then AND LOAD or OR LOAD is used to logically
combine the blocks. With both AND LOAD and OR LOAD there are two ways
to achieve this. One is to code the logic block instruction after the first two
blocks and then after each additional block. The other is to code all of the
blocks to be combined, starting each block with LOAD or LOAD NOT, and
then to code the logic block instructions which combine them. In this case,
the instructions for the last pair of blocks should be combined first, and then
each preceding block should be combined, working progressively back to the
first block. Although either of these methods will produce exactly the same
result, the second method, that of coding all logic block instructions together,
can be used only if eight or fewer blocks are being combined, i.e., if seven or
fewer logic block instructions are required.
33
The Ladder Diagram Section 4-3
The following diagram requires AND LOAD to be converted to mnemonic
code because three pairs of parallel conditions lie in series. The two means
of coding the programs are also shown.
0000 0002 0004
0001 0003 0005
Address Instruction Operands Address Instruction Operands
0000 LD 0000
0001 OR NOT 0001
0002 LD NOT 0002
0003 OR 0003
0004 AND LD --0005 LD 0004
0006 OR 0005
0007 AND LD --0008 OUT 0100
0000 LD 0000
0001 OR NOT 0001
0002 LD NOT 0002
0003 OR 0003
0004 LD 0004
0005 OR 0005
0006 AND LD --0007 AND LD --0008 OUT 0100
Again, with the method on the right, a maximum of eight blocks can be combined. There is no limit to the number of blocks that can be combined with
the first method.
The following diagram requires OR LOAD instructions to be converted to
mnemonic code because three pairs of conditions in series lie in parallel to
each other.
0100
0000 0001
0002 0003
0040 0005
The first of each pair of conditions is converted to LOAD with the assigned bit
operand and then ANDed with the other condition. The first two blocks can
be coded first, followed by OR LOAD, the last block, and another OR LOAD,
or the three blocks can be coded first followed by two OR LOADs. The mnemonic code for both methods is shown below.
Address Instruction Operands Address Instruction Operands
0000 LD 0000
0001 AND NOT 0001
0002 LD NOT 0002
0003 AND NOT 0003
0004 OR LD --0005 LD 0004
0006 AND 0005
0007 OR LD --0008 OUT 0101
0000 LD 0000
0001 AND NOT 0001
0002 LD NOT 0002
0003 AND NOT 0003
0004 LD 0004
0005 AND 0005
0006 OR LD --0007 OR LD --0008 OUT 0101
0101
34
Again, with the method on the right, a maximum of eight blocks can be combined. There is no limit to the number of blocks that can be combined with
the first method.
The Ladder Diagram Section 4-3
Combining AND LD and
OR LD
0000 0001 0002 0003
0201
0004
Block
a
Block
b
Both of the coding methods described above can also be used when using
both AND LD and OR LD, as long as the number of blocks being combined
does not exceed eight.
The following diagram contains only two logic blocks as shown. It is not necessary to break block b down further, because it can coded directly using
only AND and OR.
0101
Address Instruction Operands
0000 LD 0000
0001 AND NOT 0001
0002 LD 0002
0003 AND 0003
0004 OR 0201
0005 OR 0004
0006 AND LD --0007 OUT 0101
Although the following diagram is similar to the one above, block b in the diagram below cannot be coded without being broken down into two blocks
combined with OR LD. In this example, the three blocks have been coded
first and then OR LD has been used to combine the last two blocks followed
by AND LD to combine the execution condition produced by the OR LD with
the execution condition of block a.
Block
b1
0000 0001 0002 0003
0004 0202
Block
b2
Block
a
Block
b
Complicated Diagrams
When coding the logic block instructions together at the end of the logic
blocks they are combining, they must, as shown below, be coded in reverse
order, i.e., the logic block instruction for the last two blocks is coded first, followed by the one to combine the execution condition resulting from the first
logic block instruction and the execution condition of the logic block third from
the end, and on back to the first logic block that is being combined.
Address Instruction Operands
0000 LD NOT 0000
0102
0001 AND 0001
0002 LD 0002
0003 AND NOT 0003
0004 LD NOT 0004
0005 AND 0202
0006 OR LD --0007 AND LD --0008 OUT 0102
When determining what logic block instructions will be required to code a diagram, it is sometimes necessary to break the diagram into large blocks and
then continue breaking the large blocks down until logic blocks that can be
coded without logic block instructions have been formed. These blocks are
then coded, combining the small blocks first, and then combining the larger
blocks. AND LD and OR LD is used to combine either, i.e., AND LD or OR
LD always combines the last two execution conditions that existed, regardless of whether the execution conditions resulted from a single condition,
from logic blocks, or from previous logic block instructions.
When working with complicated diagrams, blocks will ultimately be coded
starting at the top left and moving down before moving across. This will generally mean that, when there might be a choice, OR LD will be coded before
AND LD.
35
The Ladder Diagram Section 4-3
The following diagram must be broken down into two blocks and each of
these then broken into two blocks before it can be coded. As shown below,
blocks a and b require an AND LD. Before AND LD can be used, however,
OR LD must be used to combine the top and bottom blocks on both sides,
i.e., to combine a1 and a2; b1 and b2.
Block
a1
0000 0001 0004 0005
0002 0003
Block
a2
Block
a
Block
b1
0006 0007
Block
b2
Block
b
Address Instruction Operands
0000 LD 0000
0001 AND NOT 0001
0002 LD NOT 0002
0003 AND 0003
0004 OR LD --0005 LD 0004
0006 AND 0005
0007 LD 0006
0008 AND 0007
0009 OR LD --0010 AND LD --0011 OUT 0103
0103
Blocks a1 and a2
Blocks b1 and b2
Blocks a and b
This type of diagram can be coded easily if each block is worked with in order first top to bottom and then left to right. In the following diagram, blocks a
and b would be combined with AND LD as shown above, and then block c
would be coded and a second AND LD would be used to combine it with the
execution condition from the first AND LD, and so on through to block n.
00
Block
a
Block
b
Block
c
Block
n
36
The Ladder Diagram Section 4-3
The following diagram requires first an OR LD and an AND LD to code the
top of the three blocks, and then two more OR LDs to complete the mnemonic code.
0000
0004 0005
0006 0007
0002 0003
0001
0004 0005
0006 0007
0001
0002 0003
0000
0105
Address Instruction Operands
0000 LD 0000
0001 LD 0001
0002 LD 0002
0003 AND NOT 0003
0004 OR LD --0005 AND LD --0006 LD NOT 0004
0007 AND 0005
0008 OR LD --0009 LD NOT 0006
0010 AND 0007
0011 OR LD --0012 OUT 0105
Although the program will execute as written, this diagram could be redrawn
as shown below to eliminate the need for the first OR LD and the AND LD,
simplifying the program and saving memory space.
0105
Address Instruction Operands
0000 LD 0002
0001 AND NOT 0003
0002 OR 0001
0003 AND 0000
0004 LD NOT 0004
0005 AND 0005
0006 OR LD --0007 LD NOT 0006
0008 AND 0007
0009 OR LD --0010 OUT 0105
0000
Block a
0001
0003
Block b
0002
0004
The following diagram requires five blocks, which here are coded in order
before using OR LD and AND LD to combine them starting from the last two
blocks and working forward. The OR LD at address 0008 combines blocks d
and e, the following AND LD combines the resulting execution condition with
that of block c, etc.
Address Instruction Operands
0000 LD 0000
0001 LD 0001
0002 AND 0002
0003 LD 0003
0004 AND 0004
0005 LD 0005
0006 LD 0006
0007 AND 0007
0008 OR LD --0009 AND LD --0010 OR LD --0011 AND LD --0012 OUT 0105
Block dBlock c
0005
0006 0007
Block e
0105
Blocks d and e
Block c with result of above
Block b with result of above
Block a with result of above
37
The Ladder Diagram Section 4-3
Again, this diagram can be redrawn as follows to simplify program structure
and coding and to save memory space.
0006 0007
0005
0001 0002
0003 0004 0000
Our last example may at first appear very complicated but can be coded using only two logic block instructions. The diagram appears as follows:
0000 0001
0100 0101
0500
Block a
0002 0003
Block b
0105
Address Instruction Operands
0000 LD 0006
0001 AND 0007
0002 OR 0005
0003 AND 0003
0004 AND 0004
0005 LD 0001
0006 AND 0002
0007 OR LD --0008 AND 0000
0009 OUT 0105
0004 0005
0105
0006
Block c
0000 0001
LD 0000
AND 0001
OR LD
0500
OR 0500
0002 0003
AND 0002
AND NOT 0003
The first logic block instruction is used to combine the execution conditions
resulting from blocks a and b, and the second one is used to combine the
execution condition of block c with the execution condition resulting from the
normally closed condition assigned 0003. The rest of the diagram can be
coded with ladder instructions. The logical flow for this and the resulting code
are shown below.
Block bBlock a
0100 0101
LD 0100
AND 0101
Block c
AND LD
0105
0004 0005
LD 0004
AND 0005
0006
OR 0006
Address Instruction Operands
0000 LD 0000
0001 AND 0001
0002 LD 0100
0003 AND 0101
0004 OR LD --0005 OR 0500
0006 AND 0002
0007 AND NOT 0003
0008 LD 0004
0009 AND 0005
0010 OR 0006
0011 AND LD --0012 OUT 0105
38
The Ladder Diagram Section 4-3
4-3-7 Coding Multiple Right-hand Instructions
If there is more than one right-hand instruction executed with the same execution condition, they are coded consecutively following the last condition on
the instruction line. In the following example, the last instruction line contains
one more condition that corresponds to an AND.
0000 0003
0001
0002
HR 002
HR 000
4-3-8 Branching Instruction Lines
When an instruction line branches into two or more lines, it is sometimes
necessary to use either interlocks or TR bits to maintain the execution condition that existed at a branching point. This is because instruction lines are
executed across to a terminal instruction on the right before returning to
branching points to execute instructions on the branch lines. If the execution
condition has changed during this time, the previous execution condition is
lost and proper execution will not be possible without some means of preserving the previous condition. The following diagrams illustrate this. In both
diagrams, instruction 1 is executed before returning to the branching point
and moving on to the branch line leading to instruction 2.
HR
001
0107
0106
Address Instruction Operands
0000 LD 0000
0001 OR 0001
0002 OR 0002
0003 OR HR 000
0004 AND 0003
0005 OUT HR 001
0006 OUT 0107
0007 AND HR 002
0008 OUT 0106
0000
0000
Branching
point
Branching
point
0002
Diagram A: OK
0001
0002
Diagram B: Needs Correction
If, as shown in diagram A, the execution condition that existed at the branching point is not changed before returning to the branch line (instructions at
the far right do not change the execution condition), then the branch line will
be executed correctly and no special programming measure is required.
If, as shown in diagram B, a condition exists between the branching point
and the last instruction on the top instruction line, the execution condition at
the branching point and the execution condition at the end of the top line will
sometimes be different, making it impossible to ensure correct execution of
the branch line. The system remembers only the current execution condition
(i.e., the logical sum for an entire line) and does not remember partial logical
sums at points within a line.
Instruction 1
Instruction 2
Instruction 1
Instruction 2
Address Instruction Operands
0000 LD 0000
0001 Instruction 1
0002 AND 0002
0003 Instruction 2
Address Instruction Operands
0000 LD 0000
0001 AND 0001
0002 Instruction 1
0003 AND 0002
0004 Instruction 2
39
The Ladder Diagram Section 4-3
There are two means of programming branching programs to preserve the
execution conditions. One is to use TR bits; the other, to use interlocks
(IL(02)/ILC(03)).
TR Bits
0000
The TR area provides eight bits, TR 0 through TR 7, that can be used to temporarily preserve execution conditions. If a TR bit is used as the operand of
the OUTPUT instruction placed at a branching point, the current execution
condition will be stored at the designated TR bit. Storing execution conditions
is a special application of the OUTPUT instruction. When returning to the
branching point, the same TR bit is then used as the operand of the LOAD
instruction to restore the execution condition that existed when the branching
point was first reached in program execution.
The above diagram B can be written as shown below to ensure correct execution.
TR 0
Diagram B: Corrected Using a TR bit
0001
0002
In terms of actual instructions the above diagram would be as follows: The
status of 0000 is loaded (a LOAD instruction) to establish the initial execution
condition. This execution condition is then output using an OUTPUT instruction to TR 0 to store the execution condition at the branching point. The execution condition is then ANDed with the status of 0001 and instruction 1 is
executed accordingly. The execution condition that was stored at the branching point is then loaded back in (a LOAD instruction with TR 0 as the operand) and instruction 2 is executed accordingly.
The following example shows an application using two TR bits.
Instruction 1
Instruction 2
Address Instruction Operands
0000 LD 0000
0001 OUT TR 0
0002 AND 0001
0003 Instruction 1
0004 LD TR 0
0005 AND 0002
0006 Instruction 2
0000 0002
TR 0
0001
0004
0005
TR 1
0003
In this example, TR 0 and TR 1 are used to store the execution conditions at
the branching points. After executing instruction 1, the execution condition
stored in TR 1 is loaded for an AND with the status 0003. The execution condition stored in TR 0 is loaded twice, the first time for an AND with the status
of 0004 and the second time for an AND with the inverse of the status of
0005.
Instruction 1
Instruction 2
Instruction 3
Instruction 4
Address Instruction Operands
0000 LD 0000
0001 OUT TR 0
0002 AND 0001
0003 OUT TR 1
0004 AND 0002
0005 OUT 0500
0006 LD TR 1
0007 AND 0003
0008 OUT 0501
0009 LD TR 0
0010 AND 0004
0011 OUT 0502
0012 LD TR 0
0013 AND NOT 0005
0014 OUT 0503
40
The Ladder Diagram Section 4-3
TR bits can be used as many times as required as long as the same TR bit is
not used more than once in the same instruction block. Here, a new instruction block is begun each time execution returns to the bus bar. If more than
eight branching points requiring that the execution condition be saved are
necessary in a single instruction block, interlocks, which are described next,
must be used.
When drawing a ladder diagram, be careful not to use TR bits unless necessary. Often the number of instructions required for a program can be reduced
and ease of understanding a program increased by redrawing a diagram that
would otherwise required TR bits. With both of the following pairs of diagrams, the versions on the top require fewer instructions and do not require
TR bits. The first example achieves this by merely reorganizing the parts of
the instruction block; the second, by separating the second OUTPUT instruction and using another LOAD instruction to create the proper execution condition for it.
TR 0
0000
0001
Instruction 1
Instruction 2
0000
0001
0000
0001
TR 0
0002
0004
0001 0003
0000
0001
0002
0004
Instruction 2
Instruction 1
0003
Instruction 1
Instruction 2
Instruction 1
Instruction 2
Note TR bits are only used when programming using mnemonic code and are not
necessary when inputting ladder diagrams directly, as is possible from a
GPC. The above limitations on the number of branching points requiring TR
bits and considerations on methods to reduce the number of programming
instructions still hold.
41
The Ladder Diagram Section 4-3
Interlocks
0000
0001
0002
The problem of storing execution conditions at branching points can also be
handled by using the INTERLOCK (IL(02)) and INTERLOCK CLEAR
(ILC(03)) instructions. The branching point and all the conditions leading to it
are placed on a separate line followed by all of the lines from the branching
point. Each branch line is thus established as an new instruction line, with the
first condition on each branch line corresponding to a LOAD or LOAD NOT
instruction. If the execution condition for the INTERLOCK instruction is OFF,
all instructions on the right side of the branch lines leading from the branching point receive an OFF execution condition through the first INTERLOCK
CLEAR instruction. The effect that this has on particular instructions is described in
5-7 INTERLOCK and INTERLOCK CLEAR - IL(02) and ILC(03)
Diagram B from the initial example can also be corrected with an interlock.
As shown below, this requires two more instruction lines for the interlock instructions.
Diagram B: Corrected with an Interlock
IL(02)
Instruction 1
Instruction 2
ILC(03)
.
Address Instruction Operands
0000 LD 0000
0001 IL(02) --0002 LD 0001
0003 Instruction 1
0004 LD 0002
0005 Instruction 2
0006 ILC(03) ---
0000
0001
0002
0003
0005
0006
0004
If 0000 is ON in the revised version of diagram B, above, the status of 0001
and that of 0002 would determine the execution conditions for instructions 1
and 2, respectively, on independent instruction lines. Because here 0000 is
ON, this would produce the same results as ANDing the status of each of
these bits, as would occur if the interlock was not used, i.e., the INTERLOCK
and INTERLOCK CLEAR instructions would not affect execution. If 0000 is
OFF, the INTERLOCK instruction would produce an OFF execution condition
for instructions 1 and 2 and then execution would continue with the instruction line following the INTERLOCK CLEAR instruction.
As shown in the following diagram, more than one INTERLOCK instruction
can be used within one instruction block; each is effective through the next
INTERLOCK CLEAR instruction.
IL(02)
Instruction 1
IL(02)
Instruction 2
Instruction 3
Instruction 4
ILC(03)
Address Instruction Operands
0000 LD 0000
0001 IL(02) --0002 LD 0001
0003 Instruction 1
0004 LD 0002
0005 IL(02) --0006 LD 0003
0007 AND NOT 0004
0008 Instruction 2
0009 LD 0005
0010 Instruction 3
0011 LD 0006
0012 Instruction 4
0013 ILC(03) ---
42
The Ladder Diagram Section 4-3
If 0000 in the above diagram was OFF (i.e., if the execution condition for the
first INTERLOCK instruction was OFF), instructions 1 through 4 would be
executed with OFF execution conditions and execution would move to the
instruction following the INTERLOCK CLEAR instruction. If 0000 was ON, the
status of 0001 would be loaded to form the execution condition for instruction
1 and then the status of 0002 would be loaded to form the first execution
status for that instruction line, i.e., the execution condition for the second INTERLOCK instruction. If 0002 was OFF, instructions 2 through 4 would be
executed with OFF execution conditions. If 0002 was ON, 0003, 0005, and
0006 would be executed as written.
4-3-9 Jumps
A specific section of a program can be skipped according to a designated
execution condition. Although this is similar to what happens when the execution condition for an INTERLOCK instruction is OFF, with jumps, the operands for all instructions maintain status. Jumps can therefore be used to control devices that require a sustained output, e.g., pneumatics and hydraulics,
whereas interlocks can be used to control devices that do not required a sustained output, e.g., electronic instruments.
Jumps are created using the JUMP (JMP(04)) and JUMP END (JME(05))
instructions. If the execution condition for a JUMP instruction is ON, the program is executed normally as if the jump did not exist. If the execution condition for the JUMP instruction is OFF, program execution moves immediately
to a JUMP END instruction without changing the status of anything between
the JUMP and JUMP END instruction. Actually there are two types of jumps.
All JUMP and JUMP END instructions are assigned jump numbers ranging
between 00 and 08. The jump number used determines the type of jump.
A jump can be defined using jump numbers 01 through 08 only once, i.e.,
each of these numbers can be used once in a JUMP instruction and once in
a JUMP END instruction. When a JUMP instruction assigned one of these
numbers is executed, execution moves immediately to the JUMP END instruction that has the same number as if all of the instruction between them
did not exist. Diagram B from the TR bit and interlock example could be
redrawn as shown below using a jump. Although 01 has been used as the
jump number, any number between 01 and 08 could be used as long as it
has not already been used in a different part of the program.
0000
0001
0002
Diagram B: Corrected with a Jump
This version of diagram B would have a shorter execution time when 0000
was OFF than any of the other versions.
JMP(04) 01
Instruction 1
Instruction 2
JME(05) 01
Address Instruction Operands
0000 LD 0000
0001 JMP(04) 01
0002 LD 0001
0003 Instruction 1
0004 LD 0002
0005 Instruction 2
0006 JME(05) 01
The other type of jump is created with a jump number of 00. As many jumps
as desired can be created using jump number 00 and JUMP instructions using 00 can be used consecutively without a JUMP END using 00 between
them. In the extreme, only one JUMP END 00 instruction is required for all
JUMP 00 instructions. When 00 is used as the jump number for a JUMP instruction, program execution moves to the instruction following the next
43
The Programming Console Section 4-4
JUMP END instruction with a jump number of 00. Although, as in all jumps,
no status is changed and no instructions are executed between the JUMP 00
and JUMP END 00 instructions, the program must search for the next JUMP
END 00 instruction, producing a slightly longer execution time.
Execution of programs containing multiple JUMP 00 instructions for one
JUMP END 00 instruction resembles that of similar interlocked sections. The
following diagram is the same as that used for the interlock example above,
except redrawn with jumps. This diagram, however, would not execute the
same, as has already be described, i.e., interlocks would reset certain parts
of the interlocked section but jumps would not affect any status between the
JUMP and JUMP END instructions.
0000
0001
0002
0003
0005
0006
0004
Jump diagrams can also be drawn as branching instruction lines if desired
and would look exactly like their interlock equivalents. The non-branching
form, which is the form displayed on the GPC, will be used in this manual.
4-4 The Programming Console
Depending on the model of Programming Console used, it is either connected to the CPU via a Programming Console Adapter and Connecting Cable or it is mounted directly to the CPU.
JMP(04) 00
Instruction 1
JMP(04) 00
Instruction 2
Instruction 3
Instruction 4
JME(05) 00
Address Instruction Operands
0000 LD 0000
0001 JMP(04) 00
0002 LD 0001
0003 Instruction 1
0004 LD 0002
0005 JMP(04) 00
0006 LD 0003
0007 AND NOT 0004
0008 Instruction 2
0009 LD 0005
0010 Instruction 3
0011 LD 0006
0012 Instruction 4
0013 JME(05) 00
4-4-1 The Keyboard
White Numeric Keys
Red CLR Key
Yellow Operation Keys
44
The keyboard of the Programming Console is functionally divided by key
color into the following four areas:
The ten white keys are used to input numeric program data such as program
addresses, data area addresses, and operand values. The numeric keys are
also used in combination with the function key (FUN) to enter instructions
with function codes.
The CLR key clears the display and cancels current Programming Console
operations. It is also used when you key in the password at the beginning of
programming operations. Any Programming Console operation can be cancelled by pressing the CLR key, although the CLR key may have to be
pressed two or three times to cancel the operation and clear the display.
The yellow keys are used for writing and correcting programs. Detailed explanations of their functions are given later in this section.
The Programming Console Section 4-4
Gray Instruction and Data
Area Keys
Pressed before the function code when inputting an instruction via its function code.
Pressed to enter SFT (the Shift Register
instruction).
Input after a ladder instruction to designate
an normally closed condition.
Pressed to enter AND (the AND instruction) or used with NOT to enter AND NOT.
Pressed to enter OR (the OR instruction)
or used with NOT to enter OR NOT.
Pressed to enter CNT (the Counter instruction) or to designate a TC number that has
already been defined as a counter.
Except for the SHIFT key on the upper right, the gray keys are used to input
instructions and designate data area prefixes when inputting or changing a
program. The SHIFT key is similar to the shift key of a typewriter, and is used
to alter the function of the next key pressed. (It is not necessary to hold the
SHIFT key down; just press it once and then press the key to be used with
it.)
The gray keys other than the SHIFT key have either the mnemonic name of
the instruction or the abbreviation of the data area written on them. The functions of these keys are described below.
Pressed before designating an address in
the TR area.
Pressed before designating an address in
the LR area. Cannot be used with the K-type
PCs.
Pressed before designating an address in
the HR area.
Pressed before designating an address in
the DM area.
Pressed before designating an indirect DM
address. Cannot be used with the K-type
PCs.
Pressed before designating a word address.
Pressed to enter LD (the Load instruction)
or used with NOT to enter LD NOT. Also
pressed to indicate an input bit.
Pressed to enter OUT (the Output instruction) or used with NOT to enter OUT NOT.
Also pressed to indicate an output bit.
Pressed to enter TIM (the Timer instruction) or to designate a TC number that has
already been defined as a timer.
4-4-2 PC Modes
Pressed before designating an operand as a
constant.
Pressed before designating a bit address.
The Programming Console is equipped with a switch to control the PC mode.
To select one of three operating modes—RUN, MONITOR, or PROGRAM—
use the mode switch. The mode that you select will determine PC operation
as well as the procedures that are possible from the Programming Console.
RUN mode is the mode used for normal program execution. When the switch
is set to RUN and the START input on the CPU Power Supply Unit is ON, the
CPU will begin executing the program according to the program written in its
Program Memory. Although monitoring PC operation from the Programming
Console is possible in RUN mode, no data in any of the memory areas can
be input or changed.
MONITOR mode allows you to visually monitor in-progress program execution while controlling I/O status, changing PV (present values) or SV (set values), etc. In MONITOR mode, I/O processing is handled in the same way as
in RUN mode. MONITOR mode is generally used for trial system operation
and final program adjustments.
45
Preparation for Operation Section 4-5
In PROGRAM mode, the PC does not execute the program. PROGRAM
mode is for creating and changing programs, clearing memory areas, and
registering and changing the I/O table. A special Debug operation is also
available within PROGRAM mode that enables checking a program for correct execution before trial operation of the system.
DANGER Do not leave the Programming Console connected to the PC by an extension
!
cable when in RUN mode. Noise entering via the extension cable can affect the
program in the PC and thus the controlled system.
Mode Changes
When the PC is turned on, the mode it is in will depend on what Peripheral
Device, if any, is connected or mounted to the CPU.
• No Peripheral Device Connected
When power is applied to the PC without a Peripheral Device connected,
the PC is automatically set to RUN mode. Program execution is then controlled through the CPU Power Supply Unit’s START terminal.
• Programming Console Connected
If the Programming Console is connected to the PC when PC power is applied, the PC is set to the mode set on the Programming Console’s mode
switch.
• Other Peripheral Connected
If a Peripheral Interface Unit, PROM Writer, Printer Interface Unit, or a
Floppy Disk Interface Unit is attached to the PC when PC power is turned
on, the PC is automatically set to PROGRAM mode.
If the PC power supply is already turned on when a peripheral device is attached to the PC, the PC will stay in the same mode it was in before the peripheral device was attached. The mode can be changed with the mode
switch on the Programming Console once the password has been entered. If
it is necessary to have the PC in PROGRAM mode, (for the PROM Writer,
Floppy Disk Interface Unit, etc.), be sure to select this mode before connecting the peripheral device, or alternatively, apply power to the PC after the peripheral device is connected.
The mode will also not change when a Peripheral Device is removed from
the PC after PC power is turned on.
DANGER Always confirm that the Programming Console is in PROGRAM mode when
!
turning on the PC with a Programming Console connected unless another mode
is desired for a specific purpose. If the Programming Console is in RUN mode
when PC power is turned on, any program in Program Memory will be executed,
possibly causing any PC-controlled system to begin operation. Also be sure that
starting operation is safe and appropriate whenever turning on the PC without a
device mounted to the CPU when the START input on the CPU Power Supply
Unit is ON.
4-5 Preparation for Operation
This section describes the procedures required to begin Programming Console operation. These include password entry, clearing memory, and error
message clearing.
The following sequence of operations must be performed before beginning
initial program input.
1, 2, 3...
46
1. Confirm that all wiring for the PC has been installed and checked properly.
2. Confirm that a RAM Unit is mounted as the Memory Unit and that the
write-protect switch is OFF.
Preparation for Operation Section 4-5
3. Connect the Programming Console to the PC. Make sure that the Programming Console is securely connected or mounted to the CPU; improper connection may inhibit operation.
4. Set the mode switch to PROGRAM mode.
5. Turn on PC power.
6. Enter the password.
7. Clear memory.
Each of these operations from entering the password on is described in detail
in the following subsections. All operations should be done in PROGRAM
mode unless otherwise noted.
4-5-1 Entering the Password
To gain access to the PC’s programming functions, you must first enter the
password. The password prevents unauthorized access to the program.
The PC prompts you for a password when PC power is turned on or, if PC
power is already on, after the Programming Console has been connected to
the PC. To gain access to the system when the “Password!” message appears, press CLR and then MONTR. Then press CLR to clear the display.
If the Programming Console is connected to the PC when PC power is already on, the first display below will indicate the mode the PC was in before
the Programming Console was connected. Be sure that the PC is in PRO-
GRAM mode before you enter the password. When the password is entered, the PC will shift to the mode set on the mode switch, causing PC operation to begin if the mode is set to RUN or MONITOR. You can change the
mode to RUN or MONITOR with the mode switch after entering the password.
4-5-2 Clearing Memory
Using the Memory Clear operation it is possible to clear all or part of the Program Memory, and the IR, HR, DM and TC areas. Unless otherwise specified, the clear operation will clear all memory areas above provided that the
Memory Unit attached to the PC is a RAM Unit or an EEPROM Unit and the
write-protect switch is OFF. If the write-protect switch is ON, or the Memory
Unit is an EPROM Unit, Program Memory cannot be cleared.
Before beginning to programming for the first time or when installing a new
program, all areas should normally be cleared. Before clearing memory,
check to see if a program is already loaded that you need. If you need the
program, clear only the memory areas that you do not need, and be sure to
check the existing program with the program check key sequence before using it. The check sequence is provided later in this section. Further debugging methods are provided in
To clear all memory areas, press CLR until all zeros are displayed and then
the top line of the following sequence. The branch lines in the sequence are
used when clearing only part of the memory areas, which is described below.
Memory can be cleared in PROGRAM mode only.
<PROGRAM>
PASSWORD
<PROGRAM>
Indicates the mode set by the mode selector switch.
Section 7 Program Debugging and Execution
.
47
Preparation for Operation Section 4-5
Key Sequence
All Clear
Partial Clear
The following procedure is used to clear memory completely.
0000
0000
0000
0000MEMORY CLR?
HR CNT DM
0000MEMORY CLR
END HR CNT DM
It is possible to retain the data in specified areas and/or part of the Program
Memory. To retain the data in the HR and TC, and/or DM areas, press the
appropriate key after entering REC/RESET. The CNT key is used for the entire TC area. The display will show those areas that will be cleared.
It is also possible to retain a portion of the Program Memory from the beginning to a specified address. After designating the data areas to be retained,
specify the first Program Memory address to be cleared. For example, to
leave addresses 0000 to 0122 untouched, but to clear addresses from 0123
to the end of Program Memory, input 0123.
48
Inputting, Modifying, and Checking the Program Section 4-6
For example, to leave the TC area uncleared and retaining Program Memory
addresses 0000 through 0122, input as follows:
0000
0000
0000
0000MEMORY CLR?
HR CNT DM
0000MEMORY CLR?
HR DM
0123MEMORY CLR?
HR DM
0000MEMORY CLR
END HR DM
4-5-3 Clearing Error Messages
Any error messages recorded in memory should also be cleared. It is assumed here that the causes of any of the errors for which error messages
appear have already been taken care of. If the beeper sounds when an attempt is made to clear an error message, eliminate the cause of the error,
and then clear the error message (refer to
To display any recorded error messages, press CLR, FUN, and then
MONTR. The first message will appear. Pressing MONTR again will clear the
present message and display the next error message. Continue pressing
MONTR until all messages have been cleared.
Although error messages can be accessed in any mode, they can be cleared
only in PROGRAM mode.
Key Sequence
Section 8 Troubleshooting
4-6 Inputting, Modifying, and Checking the Program
Once a program is written in mnemonic code, it can be input directly into the
PC from a Programming Console. Mnemonic code is keyed into Program
Memory addresses from the Programming Console. Checking the program
involves a syntax check to see that the program has been written according
to syntax rules before trial execution and finally correction under actual conditions can begin.
).
The operations required to input a program are explained below. Operations
to modify programs that already exist in memory are also provided in this
section, as well as the procedure to obtain the current cycle time.
49
Inputting, Modifying, and Checking the Program Section 4-6
Before starting to input a program, check to see whether there is a program
already loaded. If there is a program already loaded that you do not need,
clear it first using the program memory clear key sequence, then input the
new program. If you need the previous program, be sure to check it with the
program check key sequence and correct it as required. Further debugging
methods are provided in
Section 7 Program Debugging and Execution
.
4-6-1 Setting and Reading from Program Memory Address
When inputting a program for the first time, it is generally input from Program
Memory address 0000. As this address appears when the display is cleared,
it is not necessary to input it.
When inputting a program starting from other than 0000 or to read or modify
a program that already exists in memory, the desired address must be designated. To designate an address, press CLR and then input the desired address. Leading zeros of the address need not be input, i.e., when specifying
an address such as 0053 you need to enter only 53. The contents of the designated address will not be displayed until the down key is pressed.
Once the down key has been pressed to display the contents of the designated address, the up and down keys can be used to scroll through Program
Memory. Each time one of these keys is pressed, the next or previous word
in Program Memory will be displayed.
If Program Memory is read in RUN or MONITOR mode, the ON/OFF status
of any bit displayed will also be shown.
Key Sequence
Example
If the following mnemonic code has already been input into Program Memory,
the key inputs below would produce the displays shown.
0000
0200
Address Instruction Operands
0200 LD 0000
0201 AND 0001
0202 TIM 00
# 0123
0203 LD 0100
0200READ OFF
LD 0000
0201READ ON
AND 0001
0202READ OFF
TIM 00
50
0202TIM DATA
#0123
0203READ ON
LD 0100
Inputting, Modifying, and Checking the Program Section 4-6
4-6-2 Inputting or Overwriting Programs
Programs can be input or overwritten only in PROGRAM mode.
The same procedure is used to either input a program for the first time or to
overwrite a program that already exists. In either case, the current contents
of Program Memory are overwritten, i.e., if there is no previous program, the
NOP(00) instruction, which will be written at every address, will be overwritten.
To input a program, just follow the mnemonic code that was produced from
the ladder diagram, making sure that the proper address is set before starting. Once the proper address is displayed, input the first instruction word,
press WRITE, and then input any operands required, pressing WRITE after
each, i.e., WRITE is pressed at the end of each line of the mnemonic code.
When WRITE is pressed, the designated instruction will be input and the next
display will appear. If the instruction requires two or more words, the next
display will indicate the next operand required and provide a default value for
it. If the instruction requires only one word, the next address will be displayed. Continue inputting each line of the mnemonic code until the entire
program has been input.
Inputting SV for Counters
and Timers
Designating Instructions
When inputting numeric values for operands, it is not necessary to input leading zeros. Leading zeros are required only when inputting function codes
(see below). When designating operands, be sure to designate the data area
for all but IR and SR addresses by pressing the corresponding data area key
or to designate a constant by pressing CONT/#. CONT/# is not required for
counter or timer SV (see below). TC numbers as bit operands (i.e., completion flags) are designated by pressing either TIM or CNT before the address,
depending on whether the TC number has been used to define a timer or a
counter.
The SV (set value) for a timer or counter is generally input as a constant, although inputting the address of a word that holds the SV is also possible.
When inputting an SV as a constant, CONT/# is not required; just input the
numeric value and press WRITE. To designate a word, press CLR and then
input the word address as described above.
The most basic instructions are input using the Programming Console keys
provided for them. All other instructions are input using function codes.
These function codes are always written after the instruction’s mnemonic. If
no function code is given, there should be a Programming Console key for
that instruction.
To input an instruction word using a function code, set the address, press
FUN, input the function code including any leading zero, input any bit operands or definers required on the instruction line, and then press WRITE.
Caution Enter function codes with care.
!
51
Inputting, Modifying, and Checking the Program Section 4-6
Example
The following ladder diagram can be input using the key inputs shown below.
Displays will appear as indicated.
0000
0200
Address Instruction Operands
0200 LD 0002
0201 TIM 00
# 0123
0202 TIMH(15) 01
# 0500
0200
LD 0002
0201READ
NOP (00)
0201
TIM 00
0201 TIM DATA
#0000
0201 TIM
#0123
0202READ
NOP (00)
0202
FUN (??)
0202
TIMH (15) 01
0202 TIMH DATA
#0000
0202 TIMH
#0500
0203READ
NOP (00)
Error Messages
The following error messages may appear when inputting a program. Correct
the error as indicated and continue with the input operation. The asterisks in
the displays shown below will be replaced with numeric data, normally an
address, in the actual display.
Message Cause and correction
****REPL ROM An attempt was made to write to ROM or to write-protected RAM. Be sure a RAM Unit is mounted
and that its write-protect switch is set to OFF.
****PROG OVER The instruction at the last address in memory is not NOP(00). Erase all unnecessary instructions
at the end of the program or use a larger Memory Unit.
****ADDR OVER An address was set that is larger than the highest memory in Program Memory. Input a smaller
address
****SETDATA ERR Data has been input in the wrong format or beyond defined limits, e.g., a hexadecimal value has
been input for BCD. Reinput the data.
****I/O NO. ERR A data area address has been designated that exceeds the limit of the data area, e.g., an
address is too large. Confirm the requirements for the instruction and reinput the address.
52
Inputting, Modifying, and Checking the Program Section 4-6
4-6-3 Checking the Program
Once a program has been input, it should be checked for syntax to be sure
that no programming rules have been violated. This check should also be
performed if the program has been changed in any way that might create a
syntax error.
To check the program, input the key sequence shown below. If an error is
discovered, the check will stop and a display indicating the error will appear.
Press SRCH to continue the check. If an error is not found, the program will
be checked through the first END(01), with a display indicating when each 64
instructions have been checked (e.g., display #1 below).
CLR can be pressed to cancel the check after it has been started, and a display like display #2, in the example, will appear. When the check has reached
the first END, a display like display #3 will appear.
A syntax check can be performed on a program only in PROGRAM mode.
Key Sequence
Error Messages
The following table provides the error types, displays, and explanations of all
syntax errors. The address where the error was generated will also be displayed.
Many of the following errors are for instructions that have not been introduced yet. Refer to
4-7 Controlling Bit Status
or to
Section 5 Instruction Set
for details on these.
Message Meaning and appropriate response
????? The program has been destroyed. Reinput the program.
NO END INSTR There is no END(01) in the program. Write END(01) at the final address in the program.
CIRCUIT ERR The number of logic blocks and logic block instructions does not agree, i.e., either LD or LD NOT
has been used to start a logic block whose execution condition has not been used by another
instruction or a logic block instruction has been used that does not have the required number of
logic blocks (i.e., unused execution conditions). Check your program.
IL-ILC ERR IL(02) and ILC(03) are not used in pairs. Correct the program so that each IL(02) has a unique
ILC(03). Although this error message will appear if more than one IL(02) is used with the same
ILC(03), the program will be executed as written. Make sure your program is written as desired
before proceeding.
JMP-JME ERR JMP(04) and JME(05) are not used in pairs. Match each JMP(04) to a JME(05).
COIL DUPL The same bit is being controlled (i.e., turned ON and/or OFF) by more than one instruction (e.g.,
OUT, OUT NOT, DIFU(13), DIFD(14), KEEP(11), SFT(10)). Although this is allowed for certain
instructions, check instruction requirements to confirm that the program is correct or rewrite the
program so that each bit is controlled by only one instruction.
DIF OVER More than 48 DIFU and DIFDs are used in the program. Reduce the number of DIFU(13) and
DIFD(14) used to 48 or less.
LOCN ERR The instruction currently displayed is in the wrong area. Correct the program.
JME UNDEFD The corresponding JME for a given JMP does not exist. Correct the program.
JMP UNDEFD The corresponding JMP for a given JME does not exist. Correct the program.
DUPL The number of the currently displayed instruction has already been programmed. Correct the
program.
SBN-RET ERR Incorrect usage of the displayed instruction (SBN or RET). Incorrect SBN usage is caused by
more than one SBN having the same subroutine number. Correct the program.
SBN UNDEFD The subroutine called by SBS does not exist. Correct the program.
53
Inputting, Modifying, and Checking the Program Section 4-6
Message Meaning and appropriate response
SBS UNDEFD A defined subroutine is not called by the main program. When this message is displayed because
of interrupt routine definition, there is no problem. In all other cases, correct the program.
STEP OVER STEP is used for more than 16 program sections. Correct the program to decrease the number of
sections to 16 or less. When the GPC is used the message “CPU WAITG” is displayed.
SNXT OVER More than 48 SNTXs are used in the program. Correct the program to decrease the number to 48
or less.
STEP ERR STEP and SNXT are not correctly used. Correct the program.
Example
The following examples shows some of the displays that can appear as a
result of a program check.
0000
0064PROG CHK
Display #1
Halts program check
0128PROG CHKEND
Display
#2
Check continues until END(01)
1150PROG CHK
END (01)
When errors are found
Display
#3
0178CIRCUIT ERR
OUT 0200
0196COIL DUPL
OUT 0500
4-6-4 Displaying the Cycle Time
Once the program has been cleared of syntax errors, the cycle time should
be checked. This is possible only in RUN or MONITOR mode while the program is being executed. See
on the cycle time.
To display the current average cycle time, press CLR then MONTR. The time
displayed by this operation is an average cycle time. The differences in displayed values depend on the execution conditions that exist when MONTR is
pressed.
Note Cycle time is displayed as scan time.
54
0200IL-ILC ERR
ILC (03)
1193NO ENDINSTR
END
Section 6 Program Execution Timing
for details
Inputting, Modifying, and Checking the Program Section 4-6
Example
0000
0000SCAN TIME
AVG 054.1MS
0000SCAN TIME
AVG 053.9MS
4-6-5 Program Searches
The program can be searched for occurrences of any designated instruction
or data area bit address used in an instruction. Searches can be performed
from any currently displayed address or from a cleared display.
To designate a bit address, press SHIFT, press CONT/#, then input the address, including any data area designation required, and press SRCH. To
designate an instruction, input the instruction just as when inputting the program and press SRCH. Once an occurrence of an instruction or bit address
has been found, any additional occurrences of the same instruction or bit can
be found by pressing SRCH again. SRCHG will be displayed while a search
is in progress.
Key Sequence
When the first word of a multiword instruction is displayed for a search operation, the other words of the instruction can be displayed by pressing the down
key before continuing the search.
If Program Memory is read in RUN or MONITOR mode, the ON/OFF status
of any bit displayed will also be shown.
55
Inputting, Modifying, and Checking the Program Section 4-6
Example: Instruction Search
0000
0000
LD 0000
0200SRCH
LD 0000
0202
LD 0000
1082SRCH
END (01)
0000
Example: Bit Search
0100
0100
TIM 01
0203SRCH
TIM 01
0203 TIM DATA
#0123
0000
0000
CONT 0005
56
0200CONT SRCH
LD 0005
0203CONT SRCH
AND 0005
1078CONT SRCH
END (01)
Inputting, Modifying, and Checking the Program Section 4-6
4-6-6 Inserting and Deleting Instructions
In PROGRAM mode, any instruction that is currently displayed can be deleted or another instruction can be inserted before it. These are not possible
in RUN or MONITOR modes.
To insert an instruction, display the instruction before which you want the new
instruction to be placed, input the instruction word in the same way as when
inputting a program initially, and then press INS and the down key. If other
words are required for the instruction, input these in the same way as when
inputting a program initially.
To delete an instruction, display the instruction word of the instruction to be
deleted and then press DEL and the up key. All the words for the designated
instruction will be deleted.
Caution Be careful not to inadvertently delete instructions; there is no way to recover
!
them without reinputting them completely.
Key Sequence
Example
Before Insertion:
0101
0100
0201
0102
When an instruction is inserted or deleted, all addresses in Program Memory
following the operation are adjusted automatically so that there are no blank
addresses and no unaddressed instructions.
The following mnemonic code shows the changes that are achieved in a program through the key sequences and displays shown below.
Original Program
Address Instruction Operands
0000 LD 0100
0001 AND 0101
0002 LD 0201
0003 AND NOT 0102
0004 OR LD --0005 AND 0103
0006 AND NOT 0104
0007 OUT 0201
0008 END(01) ---
Before Deletion:
0104
0103
0105
0201
0100 0103 01040101
0201
0102
0105
Delete
0201
END(01)
END(01)
57
Inputting, Modifying, and Checking the Program Section 4-6
The following key inputs and displays show the procedure for achieving the
program changes shown above.
Inserting an Instruction
0000
0000
OUT 0000
0000
OUT 0201
0207SRCH
OUT 0201
0206READ
AND NOT 0104
0206
AND 0000
0206
AND 0105
0206INSERT?
AND 0105
0207INSERT END
AND NOT 0104
0206READ
AND 0105
Find the address prior
to the insertion point
Program After Insertion
Address Instruction Operands
0000 LD 0100
0001 AND 0101
0002 LD 0201
0003 AND NOT 0102
0004 OR LD --0005 AND 0103
0006 AND 0105
0007 AND NOT 0104
0008 OUT 0201
0009 END(01) ---
Insert the
instruction
58
Controlling Bit Status Section 4-7
Deleting an Instruction
0000
0000
OUT 0000
0000
OUT 0201
0208SRCH
OUT 0201
0207READ
AND NOT 0104
0207 DELETE?
AND NOT 0104
0207DELETE END
OUT 0201
0206READ
AND 0105
4-7 Controlling Bit Status
Find the instruction
that requires deletion.
Program After Deletion
Address Instruction Operands
0000 LD 0100
0001 AND NOT 0101
0002 LD 0201
0003 AND NOT 0102
0004 OR LD --0005 AND 0103
0006 AND 0105
0007 AND NOT 0104
0008 OUT 0201
Confirm that this is the
instruction to be deleted.
There are five instructions that can be used generally to control individual bit
status. These are the OUTPUT or OUT, OUTPUT NOT or OUT NOT, DIFFERENTIATE UP, DIFFERENTIATE DOWN, and KEEP instructions. All of
these instruction appear as the last instruction in an instruction line and take
a bit address for an operand. Although details are provided in
Instructions
, these instructions are described here because of their importance in most programs. Although these instructions are used to turn ON and
OFF output bits in the IR area (i.e., to send or stop output signals to external
devices), they are also used to control the status of other bits in the IR area
or in other data areas.
4-7-1 DIFFERENTIATE UP and DIFFERENTIATE DOWN
DIFFERENTIATE UP (DIFU(13)) and DIFFERENTIATE DOWN (DIFD(14))
instructions are used to turn the operand bit ON for one cycle at a time. The
DIFFERENTIATE UP turns ON the operand bit for one cycle after the execution condition when it goes from OFF to ON; the DIFFERENTIATE DOWN
instruction turns ON the operand bit for one cycle after the execution condition when it goes from ON to OFF.
0000
DIFU(13) 0500
0001
DIFD(14) 0501
Address Instruction Operands
0000 LD 0000
0001 DIFU(13) 0500
Address Instruction Operands
0000 LD 0001
0001 DIFD(14) 0501
5-6 Bit Control
59
Controlling Bit Status Section 4-7
Here, 0500 will be turned ON for one cycle after 0000 goes ON. The next
time DIFU(13) 0500 is executed, 0500 will be turned OFF, regardless of the
status of 0000. With the DIFFERENTIATE DOWN instruction, 0501 will be
turned ON for one cycle after 0001 goes OFF (0501 will be kept OFF until
then) and will be turned ON the next time DIFD(14) is executed.
4-7-2 KEEP
The KEEP instruction is used to maintain the status of the operand bit based
on two execution conditions. To do this, the KEEP instruction is connected to
two instruction lines. When the execution condition at the end of the first instruction line is ON, the operand bit of the KEEP instruction is turned ON.
When the execution condition at the end of the second instruction line is ON,
the operand bit of the KEEP instruction is turned OFF. The operand bit for the
KEEP instruction will maintain its ON or OFF status even if it is located in an
interlocked section of the diagram and the execution condition for the INTERLOCK instruction is ON.
In the following example, HR 000 will be turned ON when 0002 is ON and
0003 is OFF. HR 000 will then remain ON until either 0004 or 0005 turns ON.
0002
0004
0005
0003
S:set
R: reset
4-7-3 Self-maintaining Bits (Seal)
Although the KEEP instruction can be used to create self maintaining bits, it
is sometimes necessary to create self maintaining bits in another way so that
they can be turned OFF when in an interlocked section of a program.
To create a self maintaining bit, the operand bit of an OUTPUT instruction is
used as a condition for the same OUTPUT instruction in an OR setup so that
the operand bit of the OUTPUT instruction will remain ON or OFF until
changes in other bits occur. At least one other condition is used just before
the OUTPUT instruction to function as a reset. Without this reset, there would
be no way to control the operand bit of the OUTPUT instruction.
The above diagram for the KEEP instruction can be rewritten as shown below. The only difference in these diagrams would be their operation in an interlocked program section when the execution condition for the INTERLOCK
instruction was ON. Here, just as in the same diagram using the KEEP instruction, two reset bits are used, i.e., HR 000 is turned OFF by turning ON
both 0004 and 0005.
KEEP(11)
HR 000
Address Instruction Operands
0000 LD 0002
0001 AND NOT 0003
0002 LD 0004
0003 OR 0005
0004 KEEP(11) HR 000
60
0002 0003
HR 000
0004
0005
HR 000
Address Instruction Operands
0000 LD 0002
0001 AND NOT 0003
0002 OR HR 000
0003 AND NOT 0004
0004 OR NOT 0005
0005 OUT HR 000
Work Bits (Internal Relays) Section 4-8
4-8 Work Bits (Internal Relays)
In programming, combining conditions to directly produce execution conditions is often extremely difficult. These difficulties are easily overcome, however, by using certain bits to trigger other instructions indirectly. Such programming is achieved by using work bits. Sometimes entire words are required for these purposes. These words are referred to as work words.
Work bits are not transferred to or from the PC. They are bits selected by the
programmer to facilitate programming as described above. I/O bits and other
dedicated bits cannot be used as works bits. All bits in the IR area that are
not allocated as I/O bits, and certain unused bits in the AR area, are available for use as work bits. Be careful to keep an accurate record of how and
where you use work bits. This helps in program planning and writing, and
also aids in debugging operations.
Work Bit Applications Examples given later in this subsection show two of the most common ways
to employ work bits. These should act as a guide to the almost limitless number of ways in which the work bits can be used. Whenever difficulties arise in
programming a control action, consideration should be given to work bits and
how they might be used to simplify programming.
Work bits are often used with the OUTPUT, OUTPUT NOT, DIFFERENTIATE
UP, DIFFERENTIATE DOWN, and KEEP instructions. The work bit is used
first as the operand for one of these instructions so that later it can be used
as a condition that will determine how other instructions will be executed.
Work bits can also be used with other instructions, e.g., with the SHIFT REGISTER instruction (SFT(10)). An example of the use of work words and bits
with the SHIFT REGISTER instruction is provided in
TER - SFT(10)
.
5-12-1 SHIFT REGIS-
Although they are not always specifically referred to as work bits, many of the
bits used in the examples in
standing the use of these bits is essential to effective programming.
Section 5 Instruction Set
use work bits. Under-
61
Work Bits (Internal Relays) Section 4-8
Reducing Complex
Conditions
0000
0002
0003
0112
0004
0112
0001
0004
Work bits can be used to simplify programming when a certain combination
of conditions is repeatedly used in combination with other conditions. In the
following example, IR 0000, IR 0001, IR 0002, and IR 0003 are combined in
a logic block that stores the resulting execution condition as the status of IR
0112. IR 0112 is then combined with various other conditions to determine
output conditions for IR 0100, IR 0101, and IR 0102, i.e., to turn the outputs
allocated to these bits ON or OFF.
Address Instruction Operands
00050112
0005
0112
0100
0101
0102
0000 LD 0000
0001 AND NOT 0001
0002 OR 0002
0003 OR NOT 0003
0004 OUT 0112
0005 LD 0112
0006 AND 0004
0007 AND NOT 0005
0008 OUT 0100
0009 LD 0112
0010 OR NOT 0004
0011 AND 0005
0012 OUT 0101
0013 LD NOT 0112
0014 OR 0006
0015 OR 0007
0016 OUT 0102
0006
0007
62
Programming Precautions Section 4-9
Differentiated Conditions Work bits can also be used if differential treatment is necessary for some, but
not all, of the conditions required for execution of an instruction. In this example, IR 0100 must be left on continuously as long as IR 0001 is ON and both
IR 0002 and IR 0003 are OFF, or as long as IR 0004 is ON and IR 0005 is
OFF. It must be turned ON for only one cycle each time IR 0000 turns ON
(unless one of the preceding conditions is keeping it ON continuously).
This action is easily programmed by using IR 0112 as a work bit as the operand of the DIFFERENTIATE UP instruction (DIFU(13)). When IR 0000 turns
ON, IR 0112 will be turned ON for one cycle and then be turned OFF the next
cycle by DIFU(13). Assuming the other conditions controlling IR 0100 are not
keeping it ON, the work bit IR 0112 will turn IR 0100 ON for one cycle only.
0000
0112
0001 0002 0003
0004 0005
4-9 Programming Precautions
The number of conditions that can be used in series or parallel is unlimited.
Therefore, use as many conditions as required to draw a clear diagram. Although very complicated diagrams can be drawn with instruction lines almost
forming mazes, there must not be any conditions on instruction lines running
vertically between two other instruction lines. Diagram A shown below, for
example, is not possible, and should be redrawn as diagram B.
0000
0004
0001
0002
0003
DIFU(13) 0112
0100
Instruction 1
Instruction 2
Address Instruction Operands
0000 LD 0000
0001 DIFU(13) 0112
0002 LD 0112
0003 LD 0001
0004 AND NOT 0002
0005 AND NOT 0003
0006 OR LD --0007 LD 0004
0008 AND NOT 0005
0009 OR LD --0010 OUT 0100
0001
0000
0001
0004
00040000
Diagram A
0002
Instruction 1
0003
Instruction 2
Diagram B
Address Instruction Operands
0000 LD 0001
0001 AND 0004
0002 OR 0000
0003 AND 0002
0004 Instruction 1
0005 LD 0000
0006 AND 0004
0007 OR 0001
0008 AND NOT 0003
0009 Instruction 2
The number of times any particular bit can be assigned to conditions is not
limited, so use them as many times as required to simplify your program.
63
Programming Precautions Section 4-9
Often, complicated programs are the result of attempts to reduce the number
of times a bit is used.
Every instruction line must also have at least one condition on it to determine
the execution condition for the instruction at the right. Again, diagram A , below, must be redrawn as diagram B. If an instruction must always be executed (e.g., if an output must always be kept ON while the program is being
executed), the Always ON Flag (1813) in the SR area can be used.
Instruction
Diagram A
0000
0001 0207
1813
Instruction
Address Instruction Operands
0000 LD 1813
0001 Instruction
Diagram B
There are, however, a few exceptions to this rule, including the INTERLOCK
CLEAR, JUMP END, and STEP Instructions. Each of these instructions is
used as the second of a pair of instructions and is controlled by the execution
condition of the first of the pair. Conditions should not be placed on the instruction lines leading to these instructions. Refer to
Section 5 Instruction Set
for details.
When drawing ladder diagrams, it is important to keep in mind the number of
instructions that will be required to input it. In diagram A, below, an OR Load
instruction will be required to combine the top and bottom instruction lines.
This can be avoided by redrawing as shown in diagram B so that no AND
LOAD or OR LOAD instructions are required. Refer to
OR LOAD
Program
Diagram A:
for more details and
for further examples.
4-6 Inputting, Modifying and Checking the
0207
Address Instruction Operands
0000 LD 0000
0001 LD 0001
0002 AND 0207
0003 OR LD --0004 OUT 0207
5-5-2 AND LOAD and
64
0001
0000
0207
Diagram B:
0207
Address Instruction Operands
0000 LD 0001
0001 AND 0207
0002 OR 0000
0003 OUT 0207
Program Execution Section 4-10
4-10 Program Execution
When program execution is started, the CPU cycles the program from top to
bottom, checking all conditions and executing all instructions accordingly as it
moves down the bus bar. It is important that instructions be placed in the
proper order so that, for example, the desired data is moved to a word before
that word is used as the operand for an instruction. Remember that an instruction line is completed to the terminal instruction at the right before executing any instruction lines branching from the first instruction line to other
terminal instructions at the right.
Program execution is only one of the tasks carried out by the CPU as part of
the cycle time. Refer to
Section 6 Program Execution Timing
for details.
65
SECTION 5
Instruction Set
5-1 Introduction 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-2 Notation 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-3 Instruction Format 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-4 Data Areas, Definer Values, and Flags 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-4-1 Coding Other Instructions 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-5 Ladder Diagram Instructions 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-5-1 LOAD, LOAD NOT, AND, AND NOT, OR, and OR NOT 73. . . . . . . .
5-5-2 AND LOAD and OR LOAD 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-6 Bit Control Instructions 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-6-1 OUTPUT and OUTPUT NOT – OUT and OUT NOT 75. . . . . . . . . . . . .
5-6-2 DIFFERENTIATE UP and DIFFERENTIATE DOWN –
5-6-3 KEEP – KEEP(11) 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-7 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03) 78. . . . . . . . . . . . .
5-8 JUMP and JUMP END – JMP(04) and JME(05) 80. . . . . . . . . . . . . . . . . . . . . . . . . .
5-9 END – END(01) 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-10 NO OPERATION – NOP(00) 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-11 Timer and Counter Instructions 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-11-1 TIMER – TIM 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-11-2 HIGH-SPEED TIMER – TIMH(15) 86. . . . . . . . . . . . . . . . . . . . . . . . . . .
5-11-3 Analog Timer Unit 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-11-4 COUNTER – CNT 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-11-5 REVERSIBLE COUNTER – CNTR(12) 93. . . . . . . . . . . . . . . . . . . . . . .
5-11-6 HIGH-SPEED DRUM COUNTER – HDM(61) 94. . . . . . . . . . . . . . . . .
5-11-7 REVERSIBLE DRUM COUNTER – RDM(60) 103. . . . . . . . . . . . . . . . .
5-12 Data Shifting 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-12-1 SHIFT REGISTER – SFT(10) 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-12-2 REVERSIBLE SHIFT REGISTER – SFTR(84) 109. . . . . . . . . . . . . . . . .
5-12-3 WORD SHIFT – WSFT(16) 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-13 Data Movement 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-13-1 MOVE – MOV(21) 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-13-2 MOVE NOT – MVN(22) 112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-14 DATA COMPARE – CMP(20) 112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15 Data Conversion 115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15-1 BCD-TO- BINARY – BIN(23) 115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15-2 BINARY-TO-BCD – BCD(24) 115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15-3 4-TO-16 DECODER – MLPX(76) 116. . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15-4 16-TO-4 ENCODER – DMPX(77) 118. . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16 BCD Calculations 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-1 BCD ADD – ADD(30) 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-2 BCD SUBTRACT – SUB(31) 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-3 BCD MULTIPLY – MUL(32) 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-4 BCD DIVIDE – DIV(33) 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-5 SET CARRY – STC(40) 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-6 CLEAR CARRY – CLC(41) 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-17 Subroutines 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-17-1 SUBROUTINE DEFINE and SUBROUTINE RETURN
5-17-2 SUBROUTINE ENTRY – SBS(91) 126. . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18 Step Instructions 128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-1 STEP DEFINE and STEP START – STEP(08)/SNXT(09) 128. . . . . . . . .
5-19 Special Instructions 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-1 I/O REFRESH – IORF(97) 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-2 END WAIT – ENDW(62) 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-3 NOTATION INSERT – NETW(63) 136. . . . . . . . . . . . . . . . . . . . . . . . . . .
DIFU(13) and DIFD(14) 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SBN(92)/RET(93) 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
Instruction Format Section 5-3
5-1 Introduction
The K-type PCs have large programming instruction sets that allow for easy
programming of complicated control processes. This section explains each
instruction individually and provides the ladder diagram symbol, data areas,
and flags used with each. Basic application examples are also provided as
required in describing the instructions.
The many instructions provided by the K-type PCs are described in following
subsections by instruction group. These groups include Ladder Diagram Instructions, Bit Control Instructions, Timer and Counter Instructions, Data
Shifting, Data Movement, Data Comparison, Data Conversion, BCD Calculations, Subroutines, Step Instructions, and Special Instructions.
Some instructions, such as timer and counter instructions, are used to control
execution of other instructions, e.g., a TIM completion flag might be used to
turn ON a bit when the time period set for the timer has expired. Although
these other instructions are often used to control output bits through the
OUTPUT instruction, they can be used to control execution of other instructions as well. The OUTPUT instructions used in examples in this manual can
therefore generally be replaced by other instructions to modify the program
for specific applications other than controlling output bits directly.
5-2 Notation
In the remainder of this manual, all instructions will be referred to by their
mnemonics. For example, the OUTPUT instruction will be called OUT; the
AND NOT instruction, AND NOT. If you’re not sure of what instruction a mnemonic is used for, refer to
tion Times
If an instruction is assigned a function code, it will be given in parentheses
after the mnemonic. These function codes, which are 2-digit decimal numbers, are used to input most instructions into the CPU. A table of instructions
listed in order of function codes is also provided in
Instructions and Execution Times
5-3 Instruction Format
Most instructions have at least one or more operands associated with them.
Operands indicate or provide the data on which an instruction is to be performed. These are sometimes input as the actual numeric values (i.e., as
constants), but are usually the addresses of data area words or bits that contain the data to be used. A bit whose address is designated as an operand is
called an operand bit; a word whose address is designated as an operand is
called an operand word. In some instructions, the word address designated
in an instruction indicates the first of multiple words containing the desired
data.
Appendix B Programming Instructions and Execu-
.
Appendix B Programming
.
68
Each instruction requires one or more words in Program Memory. The first
word is the instruction word, which specifies the instruction and contains any
definers (described below) or operand bits required by the instruction. Other
operands required by the instruction are contained in following words, one
operand per word. Some instructions require up to four words.
A definer is an operand associated with an instruction and contained in the
same word as the instruction itself. These operands define the instruction
rather than telling what data it is to be used. Examples of definers are TC
numbers, which are used in timer and counter instructions to create timer
and counters, and jump numbers, which define which JUMP instruction is
Data Areas, Definer Values, and Flags Section 5-4
paired with which JUMP END instruction. Bit operands are also contained in
the same word as the instruction itself, although these are not considered
definers.
5-4 Data Areas, Definer Values, and Flags
Each instruction is introduced with the ladder diagram symbol(s), the data
areas that can be used with any operand(s), and the values that can be used
for definers. With the data areas is also specified the operand names and the
type of data required for each operand (i.e., word or bit and, for words, hexadecimal or BCD).
Not all addresses in a specified data area are necessarily allowed in an operand, e.g., if an operand requires two words, the last word in a data area cannot be designated because all words for a single operand must be in the
same data area. Unless a limit is specified, any bit/word in the area can be
used. Specific limitations for operands and definers are specified in a
subsection. Refer to
tions
tions and the addresses of flags and control bits.
Caution The IR and SR areas are considered as separate areas and both are not neces-
!
sarily allowed for an operand just because one of them is. The border between
the IR and SR area can, however, be crossed for a single operand, i.e., the last
bit in the IR area may be specified for an operand that requires more than one
word as long as the SR area is also allowed for that operand.
Section 3 Memory Areas
for addressing conven-
Limita-
Designating Constants
Flags
The
tion. These flags include the following SR area flags.
Abbreviation Name Bit
ER Instruction Execution Error flag 1903
CY Carry flag 1904
EQ Equals flag 1906
GR Greater Than flag 1905
LE Less Than flag 1907
ER is the flag most often used for monitoring an instruction’s execution.
When ER goes ON, it indicates that an error has occurred in attempting to
execute the current instruction. The
possible reasons for ER being ON. ER will turn ON for any instruction if operands are not input within established parameters. Instructions are not executed when ER is ON. A table of instructions and the flags they affect is provided in
Although data area addresses are most often given as operands, many operands can be input and all definers are input as constants. The range in which
a number can be specified for a given definer or operand depends on the
particular instruction that uses it. Constants must also be input in the form
required by the instruction, i.e., in BCD or in hexadecimal.
subsection lists flags that are affected by execution of the instruc-
Flags
subsection of each instruction lists
Appendix D Error and Arithmetic Flag Operation
.
5-4-1 Coding Other Instructions
When combining other right-hand instructions with ladder diagram instructions, they would appear in the same place as the OUTs used in the example
in the preceding section. Many of these instructions, however, require more
than one word to code.
69
Data Areas, Definer Values, and Flags Section 5-4
The first word of any instruction defines the instruction and provides any definers and sometimes bit operands required by the instruction. All other operands (i.e., operand words) are placed in words after the instruction word, one
operand to a word, in the same order as these appear in the ladder symbol
for the instruction. Although the SV for TIM and CNT are written to the left of
the symbol on the same line as the instruction, these are the only instructions
for which one line in the ladder symbol must be coded as two words (i.e., two
lines) in the mnemonic code. Also the TC number for TIMH(15) is placed on
a second line even though it is part of the instruction word. For all other instructions, each line of the ladder diagram will go into one word of mnemonic
code.
The address and instruction columns of the mnemonic code table are filled in
for the instruction word only. For all other words, the left two columns are left
blank. If the instruction word requires no definer or bit operand, the data column for it is left blank. It is a good idea to cross though the blank data column for all instruction words not requiring data so that the data column can
be quickly scanned to see if any addresses have been left out.
If an IR or SR address is used in the data column, the left side of the column
is left blank. If any other data area is used, the data area abbreviation is
placed on the left side and the address is place on the right side. If a constant is to be input, the number symbol (#) is placed on the left side of the
data column and the number to be input is placed on the right side. Any numbers input as definers in the instruction word do not require the number symbol on the right side. Remember, TR bits, once defined as a timer or counter,
take a TIM (timer) or CNT (counter) prefix.
0000 0001
0002
0003 0200
0006 0007 1505
00005
TIM 00
HR 015
When coding an instruction that has a function code, be sure to write in the
function code, which will be necessary when inputting the instruction.
The following diagram and corresponding mnemonic code illustrate the
points described above.
Address Instruction Operands
DIFU(13) 1500
1500
ADD(30)
#0001
0004
HR 0
TIM 00
# 0150
MOV(21)
HR 0
HR 2
0100
0000 LD 0000
0001 AND 0001
0002 OR 0002
0003 DIFU(13) 1500
0004 LD 0003
0005 AND NOT 0200
0006 LD 0006
0007 AND NOT 0007
0008 AND NOT 1505
0009 OR LD
0010 AND 1500
0011 ADD(30)
# 0001
HR 0
0012 LD 0005
0013 TIM 00
# 0150
0014 LD TIM 00
0015 MOV(21)
HR 0
HR 2
0016 LD HR 015
0017 OUT NOT 0100
0004
70
Data Areas, Definer Values, and Flags Section 5-4
Multiple Instruction Lines
0000 0001
0002
0200 0203
0201 0202 1501
HR 015
If a right-hand instruction requires multiple instruction lines, all of the lines for
the instruction are coded before the right-hand instruction. Each of the lines
for the instruction are coded starting with LD or LD NOT to form ‘logic blocks’
that are combined by the right-hand instruction. An example of this for
CNTR(12) is shown below.
Address Instruction Operands
0000 LD 0000
0001 AND 0001
0002 LD 0002
0003 LD 0200
0004 AND NOT 0203
0005 LD 0201
0006 AND NOT 0202
0007 AND NOT 1501
0008 OR LD
0009 AND 1500
0010 CNTR(12)
# 5000
0011 LD HR 015
0012 OUT NOT 0100
1500
I
CNTR(12)
P
R
02
#5000
0100
02
TR Bits
TR
0
0000 0001 0002
0004
0005
TR bits in a program are used to output (OUT) the execution condition at the
branching point and then to load back (LD) the execution condition when it is
required after returning to the branch lines. Within any one instruction block,
OUT cannot be used with the same TR address. The same TR address can,
however, be used with LD as many times as required. The following example
shows an instruction block using two TR bits. TR 1 is used in LD once; TR 0,
twice.
TR
1
0100
0003
0101
0102
0103
Address Instruction Operands
0000 LD 0000
0001 OUT TR 0
0002 AND 0001
0003 OUT TR 1
0004 AND 0002
0005 OUT 0100
0006 LD TR 1
0007 AND 0003
0008 OUT 0101
0009 LD TR 0
0010 AND 0004
0011 OUT 0102
0012 LD TR 0
0013 AND NOT 0005
0014 OUT 0103
71
Data Areas, Definer Values, and Flags Section 5-4
If the condition assigned 0004 was not in the diagram, the second LD using
TR 0 would not be necessary because OUT with 0102 and the AND NOT
with 0005 both require the same execution condition, i.e., the execution condition stored in TR 0. The diagram and mnemonic code for this program are
shown below.
TR
0
0000 0001 0002
0005
Interlocks
0000
IL(02)
TR
1
0100
0003
0101
Address Instruction Operands
0000 LD 0000
0001 OUT TR 0
0002 AND 0001
0003 OUT TR 1
0004 AND 0002
0005 OUT 0100
0102
0006 LD TR 1
0007 AND 0003
0103
0008 OUT 0101
0009 LD TR 0
0010 OUT 0102
0011 AND NOT 0005
0012 OUT 0103
When coding IL(02) and ILC(03), the mnemonic code will be the same regardless of whether the instruction is drawn as branching instruction lines or
whether IL(02) is placed on its own instruction line. If drawn as branching
instruction lines, each branch line is coded as if it were connected to the bus
bar, i.e., the first condition on each branch line corresponds to a LD or LD
NOT instruction.
Address Instruction Operands
0000 LD 0000
0001 IL(02)
0002 LD 0001
0003 OUT 0100
0004 LD 0002
0005 IL(02)
0006 LD 0003
0007 AND NOT 0004
0008 OUT 0101
0009 LD 0005
0010 OUT 0102
0011 LD 0006
0012 OUT 0103
0013 ILC(03)
0002
0001
IL(02)
0003
0005
0006
0100
0004
0101
0102
0103
ILC(03)
72
Ladder Diagram Instructions Section 5-5
5-5 Ladder Diagram Instructions
Ladder diagram instructions include ladder instructions and logic block instructions. Ladder instructions correspond to the conditions on the ladder
diagram. Logic block instructions are used to relate more complex parts of
the diagram that cannot be programmed with ladder instructions alone.
5-5-1 LOAD, LOAD NOT, AND, AND NOT, OR, and OR NOT
LOAD – LD
LOAD NOT – LD NOT
AND – AND
AND NOT – AND NOT
Ladder Symbol Operand Data Areas
B
B: Bit
IR, SR, HR, TC, TR
Ladder Symbol Operand Data Areas
B
B: Bit
IR, SR, HR, TC, TR
Ladder Symbol Operand Data Areas
B
B: Bit
IR, SR, HR, TC, TR
Ladder Symbol Operand Data Areas
OR – OR
OR NOT – OR NOT
Limitations
B
B: Bit
IR, SR, HR, TC, TR
Ladder Symbol Operand Data Areas
B: Bit
B
IR, SR, HR, TC, TR
Ladder Symbol Operand Data Areas
B: Bit
B
IR, SR, HR, TC, TR
There is no limit in the number of any of these instructions or in the order in
which they must be used as long as the memory capacity of the PC is not
exceeded.
73
Ladder Diagram Instructions Section 5-5
Description
These six basic instructions correspond to the conditions on a ladder diagram. As described in
status of the bits assigned to each instruction determines the execution conditions for all other instructions. Each of these instructions can be used as
many times and a bit address can be used in as many of these instructions
as required.
The status of the bit operand (B) assigned to LD or LD NOT determines the
first execution condition. AND takes the logical AND between the execution
condition and the status of its bit operand; AND NOT, the logical AND between the execution condition and the inverse of the status of its bit operand.
OR takes the logical OR between the execution condition and the status of its
bit operand; OR NOT, the logical OR between the execution condition and
the inverse of the status of its bit operand. The ladder symbol for loading TR
bits is different from that shown above. Refer to
.
Flags
ting the Program
There are no flags affected by these instructions.
5-5-2 AND LOAD and OR LOAD
AND LOAD – AND LD
Section 4 Writing and Inputting the Program
Section 4 Writing and Input-
0000
0002
, the
OR LOAD – OR LD
Description
Ladder Symbol
Ladder Symbol
0001
0000 0001
0002 0003
0003
When the above instructions are combined into blocks that cannot be logically combined using only OR and AND operations, AND LD and OR LD are
used. Whereas AND and OR operations logically combine a bit status and an
execution condition, AND LD and OR LD logically combine two execution
conditions, the current one and the last unused one.
AND LD and OR LD instruction are not necessary to draw ladder diagrams,
nor are they necessary when inputting ladder diagrams directly, as is possible from the GPC. They are required, however, to convert the program to and
input it in mnemonic form.
Flags
74
In order to reduce the number of programming instruction required, a basic
understanding of logic block instructions is required.
There are no flags affected by these instructions.
Bit Control Instructions Section 5-6
5-6 Bit Control Instructions
There are five instructions that can be used generally to control individual bit
status. These are OUT, OUT NOT, DIFU(13), DIFD(14), and KEEP(11).
These instructions are used to turn bits ON and OFF in different ways.
5-6-1 OUTPUT and OUTPUT NOT – OUT and OUT NOT
OUTPUT – OUT
OUTPUT NOT –
OUT NOT
Limitations
Description
Ladder Symbol Operand Data Areas
B: Bit
B
Ladder Symbol Operand Data Areas
B
Any output bit can be used in only one instruction that controls its status. See
3-3 Internal Relay (IR) Area
OUT and OUT NOT are used to control the status of the designated bit according to the execution condition.
OUT turns ON the designated bit for a ON execution condition, and turns
OFF the designated bit for an OFF execution condition. OUT with a TR bit
appears at a branching point rather than at the end of an instruction line.
OUT NOT turns ON the designated bit for a OFF execution condition, and
turns OFF the designated bit for an ON execution condition.
OUT and OUT NOT can be used to control execution by turning ON and OFF
bits that are assigned to conditions on the ladder diagram, thus determining
execution conditions for other instructions. This is particularly helpful when a
complex set of conditions can be used to control the status of a single work
bit, and then that work bit can be used to control other instructions.
The length of time that a bit is ON or OFF can be controlled by combining the
OUT or OUT NOT with TIM. Refer to Examples under
for details.
for details.
IR, HR, TR
B: Bit
IR, HR, TR
5-11-1 TIMER – TIM
Flags
There are no flags affected by these instructions.
5-6-2 DIFFERENTIATE UP and DIFFERENTIATE DOWN –
DIFU(13) and DIFD(14)
Ladder Symbol Operand Data Areas
DIFU(13) B
Ladder Symbol Operand Data Areas
DIFD(14) B
B: Bit
IR, HR
B: Bit
IR, HR
75
Bit Control Instructions Section 5-6
Limitations
Description
Any output bit can be used in only one instruction that controls its status. See
3-3 Internal Relay (IR) Area
for details.
DIFU(13) and DIFD(14) are used to turn the designated bit ON for one cycle
only.
Whenever executed, DIFU(13) compares its current execution with the previous execution condition. If the previous execution condition was OFF and
and current one is ON, DIFU(13) will turn ON the designated bit. If the previous execution condition was ON and the current execution condition is either
ON or OFF, DIFU(13) will turn the designated bit OFF or do nothing (i.e., if
the designated bit is already OFF). The designated bit will thus never be ON
for longer than one cycle assuming it is executed each cycle (see Precautions, below).
Whenever executed, DIFD(14) compares its current execution with the previous execution condition. If the previous execution condition was ON and the
current one is OFF, DIFD(14) will turn ON the designated bit. If the previous
execution condition was OFF and the current execution condition is either
ON or OFF, DIFD(14) will turn the designated bit OFF or do nothing (i.e., if
the designated bit is already OFF). The designated bit will thus never be ON
for longer than one cycle.
These instructions are used when a single-cycle execution of a particular instruction is desired. Examples of these are shown below.
DIFU(13) and DIFD(14) operation can be tricky when used in programming
between IL and ILC, between JMP and JME, or in subroutines. Refer to
and
INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03)
and JUMP END – JMP(04)/JME(05)
for details. A total of 48
5-8 JUMP
5-7
DIFU(13)/DIFD(14) can be used in a program. If more than 48 are used in a
program only the first 48 will be executed and all others will be ignored.
DIFU(13)/DIFD(14) are useful when used in conjunction with CMP(20) or
MOV(21), see
Example
below.
Flags
Example
0000
0000
1000
There are no flags affected by these instructions.
In diagram A, below, CMP(20) will compare the contents of the two operand
words (HR 1 and DM 00) whenever it is executed with an ON execution condition and set the arithmetic flags (GR, EQ, and LE) accordingly. If the execution condition remains ON, flag status may be changed each cycle if the contents of one or both operands change. Diagram B, however, shows how
DIFU(13) can be used to ensure that CMP(20) is executed only once each
time the desired execution condition goes ON.
Address Instruction Operands
0000 LD 0000
0001 CMP(20)
HR 1
DM 00
Address Instruction Operands
0000 LD 0000
0001 DIFU(13) 1000
0002 LD 1000
0003 CMP(20)
HR 1
DM 00
Diagram A
Diagram B
CMP(20)
HR 1
DM 00
DIFU(13) 1000
CMP(20)
HR 1
DM 00
76
Bit Control Instructions Section 5-6
5-6-3 KEEP – KEEP(11)
Description
Ladder Symbol Operand Data Areas
S
R
KEEP(11)
B
B: Bit
IR, HR
KEEP(11) is used to maintain the status of the designated bit based on two
execution conditions. These execution conditions are labeled S and R. S is
the set input; R, the reset input. KEEP(11) operates like a latching relay that
is set by S and reset by R.
When S turns ON, the designated bit will go ON and stay ON until reset, regardless of whether S stays ON or goes OFF. When R turns ON, the designated bit will go OFF and stay OFF until reset, regardless of whether R stays
ON or goes OFF. The relationship between execution conditions and
KEEP(11) bit status is shown below.
S execution condition
0002 0003
0500
0002
0003
R execution condition
Status of B
Notice that KEEP(11) operates like a self-maintaining bit. The following two
diagrams would function identically, though the one using KEEP(11) requires
one less instruction to program and would maintain status even in an interlocked program section.
Address Instruction Operands
0000 LD 0002
0001 OR 0500
0002 AND NOT 0003
0003 OUT 0500
Address Instruction Operands
0000 LD 0002
0001 LD 0003
0002 KEEP(11) 0500
S
R
0500
KEEP(11)
0500
Flags
There are no flags affected by this instruction.
77
INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03) Section 5-7
Precautions
Example
Never use an input bit in an normally closed condition on the reset (R) for
KEEP(11) when the input device uses an AC power supply. The delay in
shutting down the PC’s DC power supply (relative to the AC power supply to
the input device) can cause the designated bit of KEEP(11) to be reset. This
situation is shown below.
Input Unit
A
NEVER
A
Bits used in KEEP are not reset in interlocks. Refer to the
and INTERLOCK CLEAR – IL(02) and ILC(03
S
KEEP(11)
R
) for details.
HR 000
5-7 INTERLOCK
If a HR bit is used, bit status will be retained even during a power interruption. KEEP(11) can thus be used to program bits that will maintain status after restarting the PC following a power interruption. An example of this that
can be used to produce a warning display following a system shutdown for
an emergency situation is shown below. Bits 0002, 0003, and 0004 would be
turned ON to indicate some type of system error. Bit 0005 would be turned
ON to reset the warning display. HR 000, which is turned ON for any of the
three bits which indicates emergency situation, is used to turn ON the warning indicator through 0500.
0002
0003
0004
Reset input
0005
HR 000
Indicates
emergency
situation
S
KEEP(11)
HR 000
R
0500
Activates
warning
display
Address Instruction Operands
0000 LD 0002
0001 OR 0003
0002 OR 0004
0003 LD 0005
0004 KEEP(11) HR 000
0005 LD HR 000
0006 OUT 0500
KEEP(11) can also be combined with TIM to produce delays in turning bits
ON and OFF. Refer to
5-11-1 TIMER – TIM
for details.
5-7 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03)
Ladder Symbol
Ladder Symbol
IL(02)
ILC(03)
Description
78
IL(02) is always used in conjunction with ILC(03) to create interlocks. Interlocks are used to enable branching in the same way as can be achieved with
TR bits, but treatment of instructions between IL(02) and ILC(03) differs from
that with TR bits when the execution condition for IL(02) is OFF. If the execution condition of IL(02) is ON, the program will be executed as written, with
an ON execution condition used to start each instruction line from the point
where IL(02) is located through ILC(03).
INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03) Section 5-7
If the execution condition for IL(02) condition is OFF, the interlocked section
between IL(02) and ILC(03) will be treated as shown in the following table:
Instruction Treatment
OUT and OUT NOT Designated bit turned OFF.
TIM and TIMH(15) Reset.
CNT, CNTR(12) PV maintained.
KEEP(11) Bit status maintained.
DIFU(13) and DIFD(14) Not executed (see below).
All others Not executed.
IL(02) and ILC(03) do not necessarily have to be used in pairs. IL(02) can be
used several times in a row, with each IL(02) creating an interlocked section
through the next ILC(03). ILC(03) cannot be used unless there is at least one
IL(02) between it and any previous ILC(03).
DIFU(13) and DIFD(14) in
Interlocks
0000
0001
ON
0000
0001
1000
OFF
ON
OFF
ON
OFF
Changes in the execution condition for a DIFU(13) or DIFD(14) are not recorded if the DIFU(13) or DIFD(14) is in an interlocked section and the execution condition for the IL(02) is OFF. When DIFU(13) or DIFD(14) is executed in an interlocked section immediately after the execution condition for
the IL(02) has gone ON, the execution condition for the DIFU(13) or
DIFD(14) will be compared to the execution condition that existed before the
interlock became effective (i.e., before the interlock condition for IL(02) went
OFF). The ladder diagram and bit status changes for this are shown below.
The interlock is in effect while 0000 is OFF. Notice that 1000 is not turned ON
at the point labeled A even though 0001 has turned OFF and then back ON.
IL(02)
DIFU(13) 1000
ILC(03)
A
Address Instruction Operands
0000 LD 0000
0001 IL(02)
0002 LD 0001
0003 DIFU(13) 1000
0004 ILC(03)
Precautions
Flags
There must be an ILC(03) following any one or more IL(02).
Although as many IL(02) as necessary can be used with one ILC(03),
ILC(03) cannot be used consecutively without at least one IL(02) in between,
i.e., nesting is not possible. Whenever a ILC(03) is executed, all interlocks
are cleared.
When more than one IL(02) is used with a single ILC(03), an error message
will appear when the program check is performed, but execution will proceed
normally.
There are no flags affected by these instructions.
79
JUMP and JUMP END – JMP(04) and JME(05) Section 5-8
Example
0000
0001
0002
0003
0100
0005
0004
The following diagram shows IL(02) being used twice with one ILC(03).
Address Instruction Operands
0000 LD 0000
0001 IL(02)
1.5 s
0002 LD 0001
0003 TIM 11
0004 LD 0002
0005 IL(02)
0006 LD 0003
0007 AND NOT 0004
0008 LD 0100
0009 CNT 01
0010 LD 0005
0011 OUT 0502
0012 ILC(03)
# 0015
10
CP
R
IL(02)
TIM 11
#0015
IL(02)
CNT 01
IR 10
0502
ILC(03)
When the execution condition for the first IL(02) is OFF, TIM 11 will be reset
to 1.5 s, CNT 01 will not be changed, and 0502 will be turned OFF. When the
execution condition for the first IL(02) is ON and the execution condition for
the second IL(02) is OFF, TIM 11 will be executed according to the status of
0001, CNT 01 will not be changed, and 0502 will be turned OFF. When the
execution conditions for both the IL(02) are ON, the program will execute as
written.
5-8 JUMP and JUMP END – JMP(04) and JME(05)
Ladder Symbols Definer Values
N: Jump number
# (00 to 08)
N: Jump number
# (00 to 08)
Limitations
Description
JMP(04) N
Ladder Symbols Definer Values
JME(05) N
Jump numbers 01 through 08 may be used only once in JMP(04) and once in
JME(05), i.e., each can be used to define one jump only. Jump number 00
can be used as many times as desired.
JMP(04) is always used in conjunction with JME(05) to create jumps, i.e., to
skip from one point in a ladder diagram to another point. JMP(04) defines the
point from which the jump will be made; JME(05) defines the destination of
the jump. When the execution condition for JMP(04) in ON, no jump is made
and the program is executed as written. When the execution condition for
JMP(04) is OFF, a jump is made to the JME(05) with the same jump number
and the instruction following JME(05) is executed next.
80
If the jump number for JMP(04) is between 01 and 08, jumps, when made,
will go immediately to JME(05) without executing any instructions in between.
The status of timers, counters, bits used in OUT, bits used in OUT NOT, and
all other status controlled by the instructions between JMP(04) and JMP(05)
NO OPERATION – NOP(00) Section 5-10
will not be changed. Each of these jump numbers can be used to define one
jump. Because all of instructions between JMP(04) and JME(05) are skipped,
jump numbers 01 through 08 can be used to reduce cycle time.
If the jump number for JMP(04) is 00, the CPU will look for the next JME(05)
with a Jump number of 00. To do so, it must search through the program,
causing a longer cycle time than for other jumps (i.e., longer when the execution condition is OFF). The status of timers, counters, bits used in OUT, bits
used in OUT NOT, and all other status controlled by the instructions between
JMP(04) 00 and JMP(05) 00 will not be changed. Jump number 00 can be
used as many times as desired. A jump from JMP(04) 00 will always go to
the next JME(05) 00 in the program. It is thus possible to use JMP(04) 00
consecutively and match them all with the same JME(05) 00. It makes no
sense, however, to used JME(05) 00 consecutively, because all jumps made
to them will end at the first JME(05) 00.
DIFU(13) and DIFD(14)
in Jumps
Precautions
Flags
Although DIFU(13) and DIFD(14) are designed to turn ON the designated bit
for one cycle, they will not necessarily do so when written between JMP(04)
and JMP (05). Once either DIFU(13) or DIFD(14) has turned ON a bit, it will
remain ON until the next time DIFU(13) or DIFD(14) is executed again. In
normal programming, this means the next cycle. In a jump, it means the next
time the jump from JMP(04) to JME(05) is not made, i.e., if a bit is turned ON
by DIFU(13) or DIFD(14) and then a jump is made that skips the DIFU(13) or
DIFD(14), the designated bit will remain ON until the next time the execution
condition for the JMP(04) controlling the jump is ON.
When JMP(04) and JME(05) are not used in pairs, an error message will appear when the program check is performed. Although this message also appears if JMP(04) 00 and JME(05) 00 are not used in pairs, the program will
execute properly as written.
There are no flags affected by these instructions.
5-9 END – END(01)
Description
END(01) is required as the last instruction in any program. No instruction
written after END(01) will be executed. END(01) can be placed anywhere in
the program to execute all instructions up to that point, as is sometimes done
to debug a program, but it must be removed to execute the remainder of the
program.
Ladder Symbol
END(01)
If there is no END(01) in the program, no instructions will be executed and
the error message “NO END INST” will appear.
Flags
END(01) turns OFF ER, CY, GR, EQ, and LE.
5-10 NO OPERATION – NOP(00)
Description
Flags
NOP(00) is not generally required in programming and there is no ladder
symbol for it. When NOP(00) is found in a program, nothing is executed and
the next instruction is moved to. When memory is cleared prior to programming, NOP(00) is written at all addresses. NOP(00) can be input through the
00 function code.
There are no flags affected by NOP(00).
81
Timer and Counter Instructions Section 5-11
5-11 Timer and Counter Instructions
TIM and TIMH are decrementing ON-delay timer instructions which require a
TC number and a set value (SV).
CNT is a decrementing counter instruction and CNTR is a reversible counter
instruction. Both require a TC number and a SV. Both are also connected to
multiple instruction lines which serve as an input signal(s) and a reset.
HDM(61) is used to create a 2-kHz high-speed drum counter; RDM(60) is
used to create a reversible drum counter. RDM(60) cannot be used to create
a high-speed counter. If you require a high-speed counter, use HDM(61).
Any one TC number cannot be defined twice, i.e., once it has been used as
the definer in any of the timer or counter instructions it cannot be used again.
Once defined, TC numbers can be used as many times as required as operands in instructions other than timer and counter instructions.
TC numbers run from 00 through 47. No prefix is required when using a TC
number as a definer in a timer or counter instruction. Once defined as a timer, a TC number can be prefixed with TIM for use as an operand in certain
instructions. The TIM prefix is used regardless of the timer instruction that
was used to define the timer. Once defined as a counter, a TC number can
be prefixed with CNT for use as an operand in certain instructions. The CNT
is also used regardless of the counter instruction that was used to define the
counter.
TC numbers can be designated for operands that require bit data or for operands that require word data. When designated as an operand that requires
bit data, the TC number accesses a bit that functions as a “completion flag”
that indicates when the time/count has expired, i.e., the bit, which is normally
OFF, will turn ON when the designated SV has expired. When designated as
an operand that requires word data, the TC number accesses a memory location that holds the present value (PV) of the timer or counter. The PV of a
timer or counter can thus be used as an operand in CMP(20) or any other
instruction for which the TC area is allowed by designating the TC number
used to define that timer or counter to access the memory location that holds
the PV.
Note that “TIM 00” is used to designate the Timer instruction defined with TC
number 00, to designate the completion flag for this timer, and to designate
the PV of this timer. The meaning of the term in context should be clear, i.e.,
the first is always an instruction, the second is always a bit operand, and the
third is always a word operand. The same is true of all other TC numbers
prefixed with TIM or CNT. In explanations of ladder diagrams, the completion
flag and PV accessed through a TC number are generally called the completion flag or the PV of the instruction (e.g., the completion flag of TIM 00 is the
completion flag of TC number 00, which has been defined using TIM).
An SV can be input as a constant or as a word address in a data area. If an
IR area word assigned to an Input Unit is designated as the word address,
the Input Unit can be wired so that the SV can be set externally through
thumbwheel switches or similar devices. Timers and counter wired in this
way can be set externally only during RUN or MONITOR mode. All SVs, including those set externally, must be in BCD.
82
Timer and Counter Instructions Section 5-11
5-11-1 TIMER – TIM
Definer Values
Limitations
Description
Ladder Symbol
TIM N
SV
N: TC number
# (00 through 47)
Operand Data Areas
SV: Set value (word, BCD)
IR, HR, #
SV may be between 000.0 and 999.9 seconds. The decimal point of SV is
not input.
Each TC number can be used as the definer in only one timer or counter instruction.
TC 00 through TC 47 should not be used in TIM if they are required for
TIMH(15). Refer to
5-11-2 HIGH-SPEED TIMER – TIMH(15)
for details.
A timer is activated when its execution condition goes ON and is reset (to
SV) when the execution condition goes OFF. Once activated, TIM measures
in units of 0.1 second from the SV. TIM accuracy is +0.0/-0.1 second.
Precautions
If the execution condition remains ON long enough for TIM to time down to
zero, the completion flag for the TC number used will turn ON and will remain
ON until TIM is reset (i.e., until its execution condition goes OFF).
The following figure illustrates the relationship between the execution condition for TIM and the completion flag assigned to it.
ON
Execution condition
Completion flag
OFF
ON
OFF
SV SV
Timers in interlocked program sections are reset when the execution condition for IL(02) is OFF. Power interruptions also reset timers. If a timer that is
not reset under these conditions is desired, SR area clock pulse bits can be
counted to produce timers using CNT. Refer to
5-11-4 COUNTER – CNT
for
details.
Program execution will continue even if a non-BCD SV is used, but timing will
not be accurate.
Flags
ER: SV is not in BCD.
83
Timer and Counter Instructions Section 5-11
Examples
Example 1:
Basic Application
0000
TIM 00
0001
TIM 01
All of the following examples use OUT in diagrams that would generally be
used to control output bits in the IR area. There is no reason, however, why
these diagrams cannot be modified to control execution of other instructions.
The following example shows two timers, one set with a constant and one set
via input word 01. Here, 0200 will be turned ON 15 seconds after 0000 goes
ON and stays ON for at least 15 seconds. When 0000 goes OFF, the timer
will be reset and 0200 will be turned OFF. When 0001 goes ON, TIM 01 is
started from the SV provided through IR word 01. Bit 0201 is also turned ON
when 0001 goes ON. When the SV in 01 has expired, 0201 is turned OFF.
This bit will also be turned OFF when TIM 01 is reset, regardless of whether
or not SV has expired.
TIM 00
#0150
0200
TIM 01
01
0201
Address Instruction Operands
0000 LD 0000
0001 TIM 00
# 0150
0002 LD TIM 00
0003 OUT 0200
0004 LD 0001
0005 TIM 01
01
0006 AND NOT TIM 01
0007 OUT 0201
Example 2:
Extended Timers
0000
TIM 01
TIM 02
Example 3:
ON/OFF Delays
Timers operating longer than 999.9 seconds can be formed in two ways. One
is by programming consecutive timers, with the completion flag of each timer
used to activate the next timer. A simple example with two 900.0-second
(15-minute) timers combined to functionally form a 30-minute timer.
TIM 01
TIM 02
#9000
#9000
0200
900.0 s
900.0 s
Address Instruction Operands
0000 LD 0000
0001 TIM 01
# 9000
0002 LD TIM 01
0003 TIM 02
# 9000
0004 LD TIM 02
0005 OUT 0200
In this example, 0200 will be turned ON 30 minutes after 0000 goes ON.
TIM can also be combined with CNT or CNT can be used to count SR area
clock pulse bits to produce longer timers. An example is provided in
COUNTER – CNT
.
5-11-4
TIM can be combined with KEEP(11) to delay turning a bit ON and OFF in
reference to a desired execution condition. KEEP(11) is described in
KEEP – KEEP(11)
.
5-6-3
84
To create delays, the completion flags for two timers are used to determine
the execution conditions for setting and resetting the bit designated for
KEEP(11). The bit whose manipulation is to be delayed is used in KEEP(11).
Turning ON and OFF the bit designated for KEEP(11) is thus delayed by the
SV for the two timers. The two SV could naturally be the same if desired.
Timer and Counter Instructions Section 5-11
In the following example, 0500 would be turned ON 5.0 seconds after 0000
goes ON and then turned OFF 3.0 seconds after 0000 goes OFF. It is necessary to use both 0500 and 0000 to determine the execution condition for TIM
02; 0000 in an normally closed condition is necessary to reset TIM 02 when
0000 goes ON and 0500 is necessary to activate TIM 02 when 0000 goes
OFF, setting 0500 by resetting TIM 01.
0000
0500 0000
TIM 01
TIM 02
0000
0500
Example 4:
One-shot Bits
5.0 s
TIM 01
#0050
Address Instruction Operands
0000 LD 0000
5.0 s
0001 TIM 01
# 0050
S
R
TIM 02
#0030
KEEP(11)
0500
0002 LD 0500
3.0 s
0003 AND NOT 0000
0004 TIM 02
# 0030
0005 LD TIM 01
0006 LD TIM 02
0007 KEEP(11) 0500
3.0 s
The length of time that a bit is kept ON or OFF can be controlled by combining TIM with OUT or OUT NOT. The following diagram demonstrates how
this is possible. In this example, 0204 would remain ON for 1.5 seconds after
0000 goes ON regardless of the time 0000 stays ON. This is achieved by
using 1000, activated by 0000, to turn ON 0204. When TIM 01 comes ON
(i.e., when the SV of TIM 01 has expired), 0204 will be turned OFF through
TIM 01 (i.e., TIM 01 will turn ON for an normally closed condition, creating an
OFF execution condition for OUT 0204). TIM 01 will also turn OFF 1000 the
next cycle, resetting the one-shot.
1000
0000
1000
1000 TIM 01
0000
0204
TIM 01
1.5 s
1.5 s
TIM 01
#0015
1000
0204
1.5 s
Address Instruction Operands
0000 LD 1000
0001 AND NOT TIM 01
0002 OR 0000
0003 OUT 1000
0004 LD 1000
0005 TIM 01
# 0015
0006 LD 1000
0007 AND NOT TIM 01
0008 OUT 0204
85
Timer and Counter Instructions Section 5-11
Example 5:
Flicker Bits
TIM 02
0000
TIM 01
TIM 01
0000
0205
1.5 s1.0 s 1.5 s1.0 s
Bits can be programmed to turn ON and OFF at a regular interval while a
designated execution condition is ON by using TIM twice. One TIM functions
to turn ON and OFF a specified bit, i.e., the completion flag of this TIM turns
the specified bit ON and OFF. The other TIM functions to control the operation of the first TIM, i.e., when the first TIM’s completion flag goes ON, the
second TIM is started and when the second TIM’s completion flag goes ON,
the first TIM is started.
TIM 01
TIM 02
#0010
#0015
0205
1.0 s
1.5 s
Address Instruction Operands
0000 LD 0000
0001 AND TIM 02
0002 TIM 01
# 0010
0003 LD TIM 01
0004 TIM 02
# 0015
0005 LD TIM 01
0006 OUT 0205
An easier but more limited method of creating a flicker bit is to AND one of
the SR area clock pulse bits with the execution condition that is to be ON
when the flicker bit is operating. Although this method does not use TIM, it is
included here for comparison. This method is more limited because the ON
and OFF times must be the same and they depend on the clock pulse bits
available in the SR area.
5-11-2 HIGH-SPEED TIMER – TIMH(15)
Ladder Symbol
TIMH(15) N
SV
Limitations
Description
SV may be between 00.02 and 99.99 seconds. (Actually settings of 00.00
and 00.01 are allowed, but 00.00 is meaningless and 00.01 is not reliable.)
The decimal point of SV is not input.
Each TC number can be used as the definer in only one timer or counter instruction.
A cycle time of greater than 10 ms will affect the accuracy of the timer.
TIMH(15) operates the same as TIM except that TIMH measures in units of
0.01 second.
Definer Values
N: TC number
# (00 though 47 )
Operand Data Areas
SV: Set value (word, BCD)
IR, HR, #
86
Refer to
5-11-1 TIMER – TIM
for operational details and examples. All as-
pects except for the above considerations are the same.
Timer and Counter Instructions Section 5-11
Precautions
Timers in interlocked program sections are reset when the execution condition for IL(02) is OFF. Power interruptions also reset timers. If a timer that is
not reset under these conditions is desired, SR area clock pulse bits can be
counted to produce timers using CNT. Refer to
details.
Program execution will continue even if a non-BCD SV is used, but timing will
not be accurate.
Flags
ER: SV is not in BCD.
5-11-3 Analog Timer Unit
The Analog Timer Unit uses two I/O words to provide four timers (T0 to T3).
Each of the four timers may be set to a specific timer value (SV) within one of
four ranges. The SV for each timer may be set using either a variable resistor
on the Analog Timer Unit or from an external variable resistor.
Each timer is allocated five bits within the IR words allocated to the Analog
Timer Units. The function of these is shown below. The words shown in the
table are as seen from the CPU, i.e., the input word goes from the Analog
Timer Unit to the CPU, the output word, from the CPU to the Analog Timer
Unit. The CPU receives the Time Expired flag from the Unit and sends the
Start control bit Pause control bit and Range bits to the Unit.
Bit Input word Output word
00 T0 Time Expired flag T0 Start control bit
01 T
02 T2 Time Expired flag T2 Start control bit
03 T3 Time Expired flag T3 Start control bit
04 T0 Pause control bit
05
06 T
07 T3 Pause control bit
08 T0 Range bits
09 Cannot be used.
10 T1 Range bits
11
12 T2 Range bits
13
14 T3 Range bits
15
Time Expired flag T
1
5-11-4 COUNTER – CNT
Start control bit
1
T1 Pause control bit
Pause control bit
2
for
There is a SET indicator and a time expired indicator on the Analog Timer
Unit for each timer. These indicators are lit when the corresponding timer’s
Start control bit or Time Expired flag is ON.
When the Start control bit is turned ON, the timer begins operation and the
SET indicator is lit.
When the time set with the internal or external adjustment has expired, the
corresponding Time Expired flag is set. The time up indicator also lights.
If the Pause control bit for a timer is turned ON from the PC, the timer will
cease timing and the present value (PV) will be retained. Timing will resume
when the Pause control bit is turned OFF. If the Start control bit is turned
OFF before the set value (SV) of the timer has expired, the Time Expired flag
will not be turned ON.
87
Timer and Counter Instructions Section 5-11
Timer ranges are set in the output words as shown in the following table.
Example
Setup
Timer Output
word bit
T
0
T
1
T
2
T
3
08 OFF ON OFF ON
09 OFF OFF ON ON
10 OFF ON OFF ON
11 OFF OFF ON ON
12 OFF ON OFF ON
13 OFF OFF ON ON
14 OFF ON OFF ON
15 OFF ON OFF ON
0.1 to 1s 1 to 10s 10 to 60s 1 to 10m
This example uses an Analog Timer Unit connected to a C28K CPU. Word
allocations are shown in the following table.
Unit Input word Output word
CPU 00 01
Analog Timer Unit 02 03
Programming
1, 2, 3...
All four time’s are used. Times for two of them are adjusted on the variable
resistors provided on the Analog Timer Unit. The other two times are adjusted using external resistors. These adjustments are made as follows. Refer to the
T
0
T
1
T
2
T
3
Analog Timer Unit Installation Guide
Timer SV Range Resistor adjustment
Approx. 0.6 s 0.1 to 1 s 6/10th turn clockwise
Approx. 3 s 1 to 10 s 3/10th turn clockwise
Approx. 2.6 s 10 to 60 s 2/10th turn clockwise
Approx. 8 min 1 to 10 min 8/10th turn clockwise
for hardware details.
The following program sections are used to set up the required data and produce outputs from the four timers. The first section moves E400 into IR 06 to
set the desired ranges (see table above). The second program section
achieves the following operation.
1. IR 0500 is turned ON approximately 0.6 seconds after IR 0002 turns ON
as the result of the action of T
.
0
2. IR 0501 is turned ON approximately 3 seconds after IR 0003 turns ON
as the result of the action of T
.
1
3. IR 0502 is turned ON approximately 20 seconds after IR 0004 turns ON
as the result of the action of T
.
2
4. IR 0503 is turned ON approximately 8 minutes after IR 0004 turns ON
as the result of the action of T
.
3
88
Timer and Counter Instructions Section 5-11
5. T2 and T3 are made inoperative if IR 0015 is turned ON.
First Cycle Flag
1815
Content of IR O6 after MOV(21)
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
1110010000000000
Range settings
0015
0606
Used to inhibit operation of T2 and T3.
0607
Start Control Bit
T
0002
T
Time Expired
0
Flag
0100
0003
T
Time Expired
1
Flag
0101
0
T
Start Control Bit
1
0600
0500
0601
0501
0
0500 turned ON when time for T0 expires.
T1 started.
0501 turned ON when time for T
started.
T
MOV(21)
#0400
06
expires.
1
Address Instruction Operands
0000 LD 1815
0001 MOV(21)
# 0400
06
Address Instruction Operands
0000 LD 0015
0001 OUT 0606
0002 OUT 0607
0003 LD 0002
0004 OUT 0600
0005 LD 0100
0006 OUT 0500
0007 LD 0003
0008 OUT 0601
0009 LD 0101
0010 OUT 0501
0011 LD 0004
0012 OUT 0602
0013 OUT 0603
0014 LD 0102
0015 OUT 0502
0016 LD 0103
0017 OUT 0503
0004
T
Time Expired
2
Flag
0102
T
Time Expired
3
Flag
0103
T
Start Control Bit
2
T
Start Control Bit
3
0602
and T3 started.
T
2
0603
0502 turned ON when time for T
0502
0502 turned ON when time for T3 expires.
0503
expires.
2
89
Timer and Counter Instructions Section 5-11
5-11-4 COUNTER – CNT
Definer Values
Limitations
Description
Ladder Symbol
CP
R
CNT N
SV
N: TC number
# (00 through 47)
Operand Data Areas
SV: Set value (word, BCD)
IR, HR, #
Each TC number can be used as the definer in only one timer or counter instruction.
CNT is used to count down from SV when the execution condition on the
count pulse, CP, goes from OFF to ON, i.e., the present value (PV) will be
decremented by one whenever CNT is executed with an ON execution condition for CP and the execution condition was OFF for the last execution. If the
execution condition has not changed or has changed from ON to OFF, the
PV of CNT will not be changed. Counter is turned ON when the PV reaches
zero and will remain ON until the counter is reset.
CNT is reset with a reset input, R. When R goes from OFF to ON, the PV is
reset to SV. The PV will not be decremented while R is ON. Counting down
from SV will begin again when R goes OFF. The PV for CNT will not be reset
in interlocked program sections or for power interruptions.
Precautions
Flags
Changes in execution conditions, the completion flag, and the PV are illustrated below. PV line height is meant to indicate changes in the PV only.
Execution condition
on count pulse (CP)
Execution condition
on reset (R)
Completion flag
PV
ON
OFF
ON
OFF
ON
OFF
SV
SV - 1
SV - 2
0002
0001
0000
Program execution will continue even if a non-BCD SV is used, but the SV
will not be correct.
ER: SV is not in BCD.
SV
90
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