Cat. No. W235-E1-5
SYSMAC
C200HS
Programmable Controllers
C200HS Programmable Controllers
Operation Manual
Revised February 2002
Notice:
OMRON products are manufactured for use according to proper procedures by a qualified operator
and only for the purposes described in this manual.
The following conventions are used to indicate and classify precautions in this manual. Always heed
the information provided with them. Failure to heed precautions can result in injury to people or damage to property.
DANGER Indicates an imminently hazardous situation which, if not avoided, will result in death or
!
serious injury.
WARNING Indicates a potentially hazardous situation which, if not avoided, could result in death or
!
serious injury.
Caution Indicates a potentially hazardous situation which, if not avoided, may result in minor or
!
moderate injury, or property damage.
OMRON Product References
All OMRON products are capitalized in this manual. The word “Unit” is also capitalized when it refers
to an OMRON product, regardless of whether or not it appears in the proper name of the product.
The abbreviation “Ch,” which appears in some displays and on some OMRON products, often means
“word” and is abbreviated “Wd” in documentation in this sense.
The abbreviation “PC” means Programmable Controller and is not used as an abbreviation for anything else.
Visual Aids
The following headings appear in the left column of the manual to help you locate different types of
information.
OMRON, 1994
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any
form, or by any means, mechanical, electronic, photocopying, recording, or otherwise, without the prior written permission of OMRON.
No patent liability is assumed with respect to the use of the information contained herein. Moreover, because OMRON is
constantly striving to improve its high-quality products, the information contained in this manual is subject to change
without notice. Every precaution has been taken in the preparation of this manual. Nevertheless, OMRON assumes no
responsibility for errors or omissions. Neither is any liability assumed for damages resulting from the use of the information contained in this publication.
Note Indicates information of particular interest for efficient and convenient operation
of the product.
1, 2, 3...
1. Indicates lists of one sort or another, such as procedures, checklists, etc.
ii
About this Manual:
This manual describes the operation of the C200HS C-series Programmable Controllers, and it includes
the sections described below. Installation information is provided in the
ler Installation Guide
Section 1 Introduction
in
ences between the older CPUs and the new CPUs described in this manual.
Please read this manual completely and be sure you understand the information provided before attempting to operate the C200HS. Be sure to read the precautions in the following section.
. A table of other manuals that can be used in conjunction with this manual is provided
. Provided in
C200HS Programmable Control-
Section 2 Hardware Considerations
is a description of the differ-
Section 1 Introduction
programming. It also provides an overview of the process of programming and operating a PC and explains basic terminology used with OMRON PCs. Descriptions of Peripheral Devices used with the
C200HS PCs and a table of other manuals available to use with this manual for special PC applications
are also provided.
Section 2 Hardware Considerations
scribes the indicators that are referred to in other sections of this manual.
Section 3 Memory Areas
mation provided there to aid in programming. It explains how I/O is managed in memory and how bits in
memory correspond to specific I/O points. It also provides information on System DM, a special area in
C200HS PCs that provides the user with flexible control of PC operating parameters.
Section 4 Writing and Entering Programs
at the elements that make up the parts of a ladder-diagram program and explaining how execution of this
program is controlled. It also explains how to convert ladder diagrams into mnemonic code so that the
programs can be entered using a Programming Console.
ection 5 Instruction Set
S
Section 6 Program Execution Timing
tells how to coordinate inputs and outputs so that they occur at the proper times.
Section 7 Program Debugging and Execution
input and debug the program and to monitor and control operation.
Section 8 Communications
C200HS.
Section 9 Memory Cassette Operations
Memory Cassettes. mounted in the CPU.
Section 10 T roubleshooting
time. Information in this section is also useful when debugging programs.
Section 11 Host Link Commands
which can be used for host link communications via the C200HS ports.
The
Appendices
tables of instructions and Programming Console operations, coding sheet to help in programming and
parameter input, and other information helpful in PC operation.
explains the background and some of the basic terms used in ladder-diagram
explains basic aspects of the overall PC configuration and de-
takes a look at the way memory is divided and allocated and explains the infor-
explains the basics of ladder-diagram programming, looking
describes all of the instructions used in programming.
explains the cycling process used to execute the program and
explains the Programming Console procedures used to
provides an overview of the communications features provided by the
describes how to manage both UM Area and IOM data via
provides information on error indications and other means of reducing down-
explains the methods and procedures for using host link commands,
provide tables of standard OMRON products available for the C200HS PCs, reference
!
WARNING Failure to read and understand the information provided in this manual may result in
personal injury or death, damage to the product, or product failure. Please read each
section in its entirety and be sure you understand the information provided in the section
and related sections before attempting any of the procedures or operations given.
iii
TABLE OF CONTENTS
PRECAUTIONS xiii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 Intended Audience xiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 General Precautions xiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Safety Precautions xiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Operating Environment Precautions xiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Application Precautions xv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Conformance to EC Directives xvi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SECTION 1 – Introduction 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-1 Overview 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-2 The Origins of PC Logic 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-3 PC Terminology 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-4 OMRON Product Terminology 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-5 Overview of PC Operation 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-6 Peripheral Devices 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-7 Available Manuals 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-8 New C200HS Features 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-8-1 Improved Memory Capabilities 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-8-2 Faster Execution Times 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-8-3 Larger Instruction Set 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-8-4 Wide Selection of Special I/O Units 9 . . . . . . . . . . . . . . . . . . . . . . . . . .
1-8-5 Improved Interrupt Functions 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-8-6 SYSMAC NET Link and SYSMAC LINK Capabilities 9 . . . . . . . . . . .
1-8-7 Built-in RS-232C Connector 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-8-8 More Flexible PC Settings 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-8-9 Debugging and Maintenance 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-8-10 New Programming Console Operations 10 . . . . . . . . . . . . . . . . . . . . . . .
1-8-11 Peripheral Devices 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-8-12 Using C200H Programs 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SECTION 2 – Hardware Considerations 15 . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1 CPU Components 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1-1 CPU Indicators 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1-2 Peripheral Device Connection 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-2 PC Configuration 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-3 CPU Capabilities 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-4 Memory Cassettes 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-5 Installing Memory Cassettes 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-6 CPU DIP Switch 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SECTION 3 – Memory Areas 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1 Introduction 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-2 Data Area Structure 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3 IR (Internal Relay) Area 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4 SR (Special Relay) Area 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-1 SYSMAC NET/SYSMAC LINK System 37 . . . . . . . . . . . . . . . . . . . . . .
3-4-2 Remote I/O Systems 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-3 Link System Flags and Control Bits 39 . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-4 Forced Status Hold Bit 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-5 I/O Status Hold Bit 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-6 Output OFF Bit 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-7 FAL (Failure Alarm) Area 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-8 Low Battery Flag 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-9 Cycle Time Error Flag 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
v
Table of contents
3-4-10 I/O Verification Error Flag 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-11 First Cycle Flag 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-12 Clock Pulse Bits 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-13 Step Flag 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-14 Group-2 Error Flag 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-15 Special Unit Error Flag 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-16 Instruction Execution Error Flag, ER 44 . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-17 Arithmetic Flags 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-18 Interrupt Subroutine Areas 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-19 RS-232C Port Communications Areas 45 . . . . . . . . . . . . . . . . . . . . . . . .
3-4-20 Peripheral Port Communications Areas 46 . . . . . . . . . . . . . . . . . . . . . . .
3-4-21 Memory Cassette Areas 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-22 Data Transfer Error Bits 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-23 Ladder Diagram Memory Areas 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-24 Memory Error Flags 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-25 Data Save Flags 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-26 Transfer Error Flags 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-27 PC Setup Error Flags 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5 AR (Auxiliary Relay) Area 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-1 Restarting Special I/O Units 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-2 Slave Rack Error Flags 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-3 Group-2 Error Flags 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-4 Optical I/O Unit and I/O Terminal Error Flags 50 . . . . . . . . . . . . . . . . . .
3-5-5 SYSMAC LINK System Data Link Settings 51 . . . . . . . . . . . . . . . . . . . .
3-5-6 Error History Bits 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-7 Active Node Flags 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-8 SYSMAC LINK/SYSMAC NET Link System Service Time 52 . . . . . .
3-5-9 Calendar/Clock Area and Bits 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-10 TERMINAL Mode Key Bits 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-11 Power OFF Counter 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-12 Cycle Time Flag 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-13 Link Unit Mounted Flags 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-14 CPU-mounting Device Mounted Flag 54 . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-15 FPD Trigger Bit 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-16 Data Tracing Flags and Control Bits 54 . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-17 Cycle Time Indicators 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-6 DM (Data Memory) Area 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-6-1 Expansion DM Area 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-6-2 Special I/O Unit Data 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-6-3 Error History Area 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-6-4 PC Setup 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-7 HR (Holding Relay) Area 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-8 TC (Timer/Counter) Area 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-9 LR (Link Relay) Area 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-10 UM Area 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-11 TR (Temporary Relay) Area 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
SECTION 4 – Writing and Inputting the Program 63 . . . . . . . . . . . . . . . . . .
4-1 Basic Procedure 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-2 Instruction Terminology 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3 Program Capacity 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4 Basic Ladder Diagrams 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4-1 Basic Terms 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4-2 Mnemonic Code 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4-3 Ladder Instructions 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4-4 OUTPUT and OUTPUT NOT 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4-5 The END Instruction 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4-6 Logic Block Instructions 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4-7 Coding Multiple Right-hand Instructions 78 . . . . . . . . . . . . . . . . . . . . . .
4-5 The Programming Console 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of contents
4-5-1 The Keyboard 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-5-2 PC Modes 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-5-3 The Display Message Switch 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6 Preparation for Operation 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-1 Entering the Password 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-2 Buzzer 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-3 Clearing Memory 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-4 Registering the I/O Table 84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-5 Clearing Error Messages 85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-6 Verifying the I/O Table 86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-7 Reading the I/O Table 87 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-8 Clearing the I/O Table 89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-9 SYSMAC NET Link Table Transfer (CPU31/33-E Only) 90 . . . . . . . . .
4-7 Inputting, Modifying, and Checking the Program 92 . . . . . . . . . . . . . . . . . . . . . . . .
4-7-1 Setting and Reading from Program Memory Address 92 . . . . . . . . . . . .
4-7-2 Entering and Editing Programs 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7-3 Checking the Program 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7-4 Displaying the Cycle Time 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7-5 Program Searches 99 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7-6 Inserting and Deleting Instructions 100 . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7-7 Branching Instruction Lines 103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7-8 Jumps 107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-8 Controlling Bit Status 108 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-8-1 DIFFERENTIATE UP and DIFFERENTIATE DOWN 109 . . . . . . . . . . .
4-8-2 KEEP 109 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-8-3 Self-maintaining Bits (Seal) 109 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-9 Work Bits (Internal Relays) 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-10 Programming Precautions 112 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-11 Program Execution 114 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SECTION 5 – Instruction Set 115 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-1 Notation 118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-2 Instruction Format 118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-3 Data Areas, Definer Values, and Flags 118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-4 Differentiated Instructions 119 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-5 Expansion Instructions 120 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-6 Coding Right-hand Instructions 122 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-7 Instruction Set Lists 125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-7-1 Function Codes 125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-7-2 Alphabetic List by Mnemonic 125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-8 Ladder Diagram Instructions 129 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-8-1 LOAD, LOAD NOT, AND, AND NOT, OR, and OR NOT 129 . . . . . . . .
5-8-2 AND LOAD and OR LOAD 130 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-9 Bit Control Instructions 130 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-9-1 OUTPUT and OUTPUT NOT – OUT and OUT NOT 130 . . . . . . . . . . . .
5-9-2 DIFFERENTIATE UP and DOWN – DIFU(13) and DIFD(14) 131 . . . . .
5-9-3 SET and RESET – SET and RSET 133 . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-9-4 KEEP – KEEP(11) 133 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-10 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03) 135 . . . . . . . . . . . .
5-11 JUMP and JUMP END – JMP(04) and JME(05) 137 . . . . . . . . . . . . . . . . . . . . . . . . .
5-12 END – END(01) 138 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-13 NO OPERATION – NOP(00) 138 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-14 Timer and Counter Instructions 138 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-14-1 TIMER – TIM 139 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-14-2 HIGH-SPEED TIMER – TIMH(15) 143 . . . . . . . . . . . . . . . . . . . . . . . . . .
5-14-3 TOTALIZING TIMER – TTIM(87) 144 . . . . . . . . . . . . . . . . . . . . . . . . . .
5-14-4 COUNTER – CNT 145 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-14-5 REVERSIBLE COUNTER – CNTR(12) 148 . . . . . . . . . . . . . . . . . . . . . .
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5-15 Data Shifting 150 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15-1 SHIFT REGISTER – SFT(10) 150 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15-2 REVERSIBLE SHIFT REGISTER – SFTR(84) 152 . . . . . . . . . . . . . . . . .
5-15-3 ARITHMETIC SHIFT LEFT – ASL(25) 154 . . . . . . . . . . . . . . . . . . . . . .
5-15-4 ARITHMETIC SHIFT RIGHT – ASR(26) 154 . . . . . . . . . . . . . . . . . . . . .
5-15-5 ROTATE LEFT – ROL(27) 155 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15-6 ROTATE RIGHT – ROR(28) 155 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15-7 ONE DIGIT SHIFT LEFT – SLD(74) 156 . . . . . . . . . . . . . . . . . . . . . . . .
5-15-8 ONE DIGIT SHIFT RIGHT – SRD(75) 156 . . . . . . . . . . . . . . . . . . . . . . .
5-15-9 WORD SHIFT – WSFT(16) 157 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15-10 ASYNCHRONOUS SHIFT REGISTER – ASFT(17) 157 . . . . . . . . . . . .
5-16 Data Movement 158 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-1 MOVE – MOV(21) 159 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-2 MOVE NOT – MVN(22) 159 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-3 BLOCK SET – BSET(71) 160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-4 BLOCK TRANSFER – XFER(70) 161 . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-5 DATA EXCHANGE – XCHG(73) 162 . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-6 SINGLE WORD DISTRIBUTE – DIST(80) 162 . . . . . . . . . . . . . . . . . . .
5-16-7 DATA COLLECT – COLL(81) 164 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-8 MOVE BIT – MOVB(82) 166 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-9 MOVE DIGIT – MOVD(83) 167 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-10 TRANSFER BITS – XFRB(62) 168 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-17 Data Comparison 169 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-17-1 MULTI-WORD COMPARE – MCMP(19) 169 . . . . . . . . . . . . . . . . . . . . .
5-17-2 COMPARE – CMP(20) 170 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-17-3 DOUBLE COMPARE – CMPL(60) 172 . . . . . . . . . . . . . . . . . . . . . . . . . .
5-17-4 BLOCK COMPARE – BCMP(68) 174 . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-17-5 TABLE COMPARE – TCMP(85) 175 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-17-6 AREA RANGE COMPARE – ZCP(88) 176 . . . . . . . . . . . . . . . . . . . . . . .
5-17-7 DOUBLE AREA RANGE COMPARE – ZCPL(––) 177 . . . . . . . . . . . . .
5-17-8 SIGNED BINARY COMPARE – CPS(––) 178 . . . . . . . . . . . . . . . . . . . . .
5-17-9 DOUBLE SIGNED BINARY COMPARE – CPSL(––) 179 . . . . . . . . . . .
5-18 Data Conversion 180 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-1 BCD-TO-BINARY – BIN(23) 180 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-2 DOUBLE BCD-TO-DOUBLE BINARY – BINL(58) 181 . . . . . . . . . . . .
5-18-3 BINARY-TO-BCD – BCD(24) 181 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-4 DOUBLE BINARY-TO-DOUBLE BCD – BCDL(59) 182 . . . . . . . . . . . .
5-18-5 HOURS-TO-SECONDS – SEC(65) 183 . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-6 SECONDS-TO-HOURS – HMS(66) 184 . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-7 4-TO-16 DECODER – MLPX(76) 185 . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-8 16-TO-4 ENCODER – DMPX(77) 188 . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-9 7-SEGMENT DECODER – SDEC(78) 191 . . . . . . . . . . . . . . . . . . . . . . . .
5-18-10 ASCII CONVERT – ASC(86) 194 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-11 ASCII-TO-HEXADECIMAL – HEX(––) 195 . . . . . . . . . . . . . . . . . . . . . .
5-18-12 SCALING – SCL(––) 198 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-13 COLUMN TO LINE – LINE(63) 200 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-14 LINE TO COLUMN – COLM(64) 201 . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-15 2’S COMPLEMENT – NEG(––) 202 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-16 DOUBLE 2’S COMPLEMENT – NEGL(––) 203 . . . . . . . . . . . . . . . . . . .
5-19 BCD Calculations 204 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-1 INCREMENT – INC(38) 204 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-2 DECREMENT – DEC(39) 204 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-3 SET CARRY – STC(40) 205 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-4 CLEAR CARRY – CLC(41) 205 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-5 BCD ADD – ADD(30) 205 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-6 DOUBLE BCD ADD – ADDL(54) 206 . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-7 BCD SUBTRACT – SUB(31) 207 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-8 DOUBLE BCD SUBTRACT – SUBL(55) 209 . . . . . . . . . . . . . . . . . . . . .
5-19-9 BCD MULTIPLY – MUL(32) 211 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-10 DOUBLE BCD MULTIPLY – MULL(56) 212 . . . . . . . . . . . . . . . . . . . . .
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5-19-11 BCD DIVIDE – DIV(33) 212 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-12 DOUBLE BCD DIVIDE – DIVL(57) 213 . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-13 FLOATING POINT DIVIDE – FDIV(79) 214 . . . . . . . . . . . . . . . . . . . . . .
5-19-14 SQUARE ROOT – ROOT(72) 217 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-20 Binary Calculations 219 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-20-1 BINARY ADD – ADB(50) 219 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-20-2 BINARY SUBTRACT – SBB(51) 221 . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-20-3 BINARY MULTIPLY – MLB(52) 224 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-20-4 BINARY DIVIDE – DVB(53) 224 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-20-5 DOUBLE BINARY ADD – ADBL(––) 225 . . . . . . . . . . . . . . . . . . . . . . .
5-20-6 DOUBLE BINARY SUBTRACT – SBBL(––) 227 . . . . . . . . . . . . . . . . . .
5-20-7 SIGNED BINARY MULTIPLY – MBS(––) 229 . . . . . . . . . . . . . . . . . . . .
5-20-8 DOUBLE SIGNED BINARY MULTIPLY – MBSL(––) 230 . . . . . . . . . .
5-20-9 SIGNED BINARY DIVIDE – DBS(––) 231 . . . . . . . . . . . . . . . . . . . . . . .
5-20-10 DOUBLE SIGNED BINARY DIVIDE – DBSL(––) 232 . . . . . . . . . . . . .
5-21 Special Math Instructions 233 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-21-1 FIND MAXIMUM – MAX(––) 233 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-21-2 FIND MINIMUM – MIN(––) 234 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-21-3 AVERAGE VALUE – AVG(––) 235 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-21-4 SUM – SUM(––) 237 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-21-5 ARITHMETIC PROCESS – APR(69) 239 . . . . . . . . . . . . . . . . . . . . . . . .
5-21-6 PID CONTROL – PID(––) 242 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-22 Logic Instructions 249 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-22-1 COMPLEMENT – COM(29) 249 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-22-2 LOGICAL AND – ANDW(34) 250 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-22-3 LOGICAL OR – ORW(35) 251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-22-4 EXCLUSIVE OR – XORW(36) 252 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-22-5 EXCLUSIVE NOR – XNRW(37) 253 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-23 Subroutines and Interrupt Control 253 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-23-1 Subroutines 253 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-23-2 Interrupts 254 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-23-3 SUBROUTINE ENTER – SBS(91) 257 . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-23-4 SUBROUTINE DEFINE and RETURN – SBN(92)/RET(93) 259 . . . . . .
5-23-5 MACRO – MCRO(99) 260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-23-6 INTERRUPT CONTROL – INT(89) 262 . . . . . . . . . . . . . . . . . . . . . . . . .
5-24 Step Instructions 266 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-24-1 STEP DEFINE and STEP START–STEP(08)/SNXT(09) 266 . . . . . . . . .
5-25 Special Instructions 275 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-25-1 FAILURE ALARM – FAL(06) and
5-25-2 CYCLE TIME – SCAN(18) 276 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-25-3 TRACE MEMORY SAMPLING – TRSM(45) 277 . . . . . . . . . . . . . . . . . .
5-25-4 MESSAGE DISPLAY – MSG(46) 278 . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-25-5 LONG MESSAGE – LMSG(47) 279 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-25-6 TERMINAL MODE – TERM(48) 280 . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-25-7 WATCHDOG TIMER REFRESH – WDT(94) 281 . . . . . . . . . . . . . . . . . .
5-25-8 I/O REFRESH – IORF(97) 281 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-25-9 GROUP-2 HIGH-DENSITY I/O REFRESH – MPRF(61) 282 . . . . . . . . .
5-25-10 BIT COUNTER – BCNT(67) 283 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-25-11 FRAME CHECKSUM – FCS(––) 283 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-25-12 FAILURE POINT DETECTION – FPD(––) 285 . . . . . . . . . . . . . . . . . . . .
5-25-13 DATA SEARCH – SRCH(––) 289 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-25-14 EXPANSION DM READ – XDMR(––) 290 . . . . . . . . . . . . . . . . . . . . . . .
5-26 Network Instructions 291 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-26-1 NETWORK SEND – SEND(90) 291 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-26-2 NETWORK RECEIVE – RECV(98) 293 . . . . . . . . . . . . . . . . . . . . . . . . .
5-26-3 About Network Communications 295 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-27 Serial Communications Instructions 297 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-27-1 RECEIVE – RXD(––) 297 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-27-2 TRANSMIT – TXD(––) 299 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SEVERE FAILURE ALARM – FALS(07) 275 . . . . . . . . . . . . . . . . . . . . .
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5-28 Advanced I/O Instructions 301 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-28-1 7-SEGMENT DISPLAY OUTPUT – 7SEG(––) 301 . . . . . . . . . . . . . . . . .
5-28-2 DIGITAL SWITCH INPUT – DSW(––) 304 . . . . . . . . . . . . . . . . . . . . . . .
5-28-3 HEXADECIMAL KEY INPUT – HKY(––) 308 . . . . . . . . . . . . . . . . . . . .
5-28-4 TEN KEY INPUT – TKY(––) 311 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-28-5 MATRIX INPUT – MTR(––) 313 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SECTION 6 – Program Execution Timing 317 . . . . . . . . . . . . . . . . . . . . . . . . . .
6-1 Cycle Time 318 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-2 Calculating Cycle Time 322 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-2-1 PC with I/O Units Only 322 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-2-2 PC with Link Units 323 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-3 Instruction Execution Times 324 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-4 I/O Response Time 333 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-4-1 Basic Systems 333 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-4-2 Remote I/O Systems 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-4-3 Host Link Systems 336 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-4-4 PC Link Systems 337 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-4-5 One-to-one Link I/O Response Time 339 . . . . . . . . . . . . . . . . . . . . . . . . .
6-4-6 Interrupt Response Times 341 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SECTION 7 – Program Monitoring and Execution 345 . . . . . . . . . . . . . . . . . .
7-1 Monitoring Operation and Modifying Data 346 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-1-1 Bit/Word Monitor 346 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-1-2 Forced Set/Reset 349 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-1-3 Forced Set/Reset Cancel 351 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-1-4 Hexadecimal/BCD Data Modification 352 . . . . . . . . . . . . . . . . . . . . . . . .
7-1-5 Hex/ASCII Display Change 354 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-1-6 4-digit Hex/Decimal Display Change 355 . . . . . . . . . . . . . . . . . . . . . . . . .
7-1-7 8-digit Hex/Decimal Display Change 356 . . . . . . . . . . . . . . . . . . . . . . . . .
7-1-8 Differentiation Monitor 357 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-1-9 3-word Monitor 358 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-1-10 3-word Data Modification 358 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-1-11 Binary Monitor 359 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-1-12 Binary Data Modification 361 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-1-13 Changing Timer/Counter SV 362 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-1-14 Expansion Instruction Function Code Assignments 365 . . . . . . . . . . . . . .
7-1-15 UM Area Allocation 366 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-1-16 Reading and Setting the Clock 367 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-1-17 Expansion Keyboard Mapping 367 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-1-18 Keyboard Mapping 368 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SECTION 8 – Communications 373 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-1 Introduction 374 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-2 Parameters for Host Link and RS-232C Communications 374 . . . . . . . . . . . . . . . . .
8-2-1 Standard Communications Parameters 375 . . . . . . . . . . . . . . . . . . . . . . . .
8-2-2 Specific Communications Parameters 376 . . . . . . . . . . . . . . . . . . . . . . . . .
8-2-3 Wiring Ports 377 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-2-4 Host Link Communications 377 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-2-5 RS-232C Communications 379 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-2-6 One-to-one Link Communications 382 . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-2-7 NT Links 384 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SECTION 9 – Memory Cassette Operations 385 . . . . . . . . . . . . . . . . . . . . . . . .
9-1 Memory Cassettes 386 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-2 Memory Cassette Settings and Flags 386 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-3 UM Area Data 387 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-4 IOM Area Data 388 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
x
Table of contents
SECTION 10 – Troubleshooting 391 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-1 Alarm Indicators 392 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-2 Programmed Alarms and Error Messages 392 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3 Reading and Clearing Errors and Messages 392 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-4 Error Messages 392 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-5 Error Flags 397 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-6 Host Link Errors 399 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SECTION 11 – Host Link Commands 401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-1 Communications Procedure 402 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-2 Command and Response Formats 404 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-2-1 Commands from the Host Computer 404 . . . . . . . . . . . . . . . . . . . . . . . . . .
11-2-2 Commands from the PC 406 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3 Host Link Commands 407 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-1 IR/SR AREA READ –– RR 407 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-2 LR AREA READ –– RL 407 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-3 HR AREA READ –– RH 408 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-4 PV READ –– RC 408 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-5 TC STATUS READ –– RG 409 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-6 DM AREA READ –– RD 409 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-7 AR AREA READ –– RJ 410 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-8 IR/SR AREA WRITE –– WR 410 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-9 LR AREA WRITE –– WL 411 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-10 HR AREA WRITE –– WH 411 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-11 PV WRITE –– WC 412 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-12 TC STATUS WRITE –– WG 412 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-13 DM AREA WRITE –– WD 413 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-14 AR AREA WRITE –– WJ 413 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-15 SV READ 1 –– R# 414 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-16 SV READ 2 –– R$ 415 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-17 SV READ 3 –– R% 416 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-18 SV CHANGE 1 –– W# 417 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-19 SV CHANGE 2 –– W$ 417 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-20 SV CHANGE 3 –– W% 418 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-21 STATUS READ –– MS 419 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-22 STATUS WRITE –– SC 420 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-23 ERROR READ –– MF 421 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-24 FORCED SET –– KS 422 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-25 FORCED RESET –– KR 423 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-26 MULTIPLE FORCED SET/RESET –– FK 424 . . . . . . . . . . . . . . . . . . . . .
11-3-27 FORCED SET/RESET CANCEL –– KC 425 . . . . . . . . . . . . . . . . . . . . . .
11-3-28 PC MODEL READ –– MM 425 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-29 TEST–– TS 426 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-30 PROGRAM READ –– RP 426 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-31 PROGRAM WRITE –– WP 427 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-32 I/O TABLE GENERATE –– MI 427 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-33 COMPOUND COMMAND –– QQ 427 . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-34 ABORT –– XZ 429 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-35 INITIALIZE –– :: 430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-3-36 Undefined Command –– IC 430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-4 Host Link Errors 431 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xi
Table of contents
Appendix 433 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A – Standard Models 433 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B – Programming Instructions 443 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C – Error and Arithmetic Flag Operation 449 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D – Memory Areas 453 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E – PC Setup 461 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F – Word Assignment Recording Sheets 465 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
G – Program Coding Sheet 471 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
H – Data Conversion Tables 473 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I – Extended ASCII 475 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Glossary 477 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision History 493 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Index 497 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xii
PRECAUTIONS
This section provides general precautions for using the Programmable Controller (PC) and related devices.
The information contained in this section is important for the safe and reliable application of the PC. You must read
this section and understand the information contained before attempting to set up or operate a PC system.
1 Intended Audience xiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 General Precautions xiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Safety Precautions xiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Operating Environment Precautions xiv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Application Precautions xv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Conformance to EC Directives xvi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xiii
Operating Environment Precautions
1 Intended Audience
This manual is intended for the following personnel, who must also have knowledge of electrical systems (an electrical engineer or the equivalent).
• Personnel in charge of installing FA systems.
• Personnel in charge of designing FA systems.
• Personnel in charge of managing FA systems and facilities.
2 General Precautions
The user must operate the product according to the performance specifications
described in the operation manuals.
Before using the product under conditions which are not described in the manual
or applying the product to nuclear control systems, railroad systems, aviation
systems, vehicles, combustion systems, medical equipment, amusement
machines, safety equipment, and other systems, machines, and equipment that
may have a serious influence on lives and property if used improperly, consult
your OMRON representative.
Make sure that the ratings and performance characteristics of the product are
sufficient for the systems, machines, and equipment, and be sure to provide the
systems, machines, and equipment with double safety mechanisms.
This manual provides information for programming and operating OMRON PCs.
Be sure to read this manual before attempting to use the software and keep this
manual close at hand for reference during operation.
4
WARNING It is extremely important that a PC and all PC Units be used for the specified
!
purpose and under the specified conditions, especially in applications that can
directly or indirectly affect human life. You must consult with your OMRON
representative before applying a PC System to the abovementioned
applications.
3 Safety Precautions
WARNING Never attempt to disassemble any Units while power is being supplied. Doing so
!
may result in serious electrical shock or electrocution.
WARNING Never touch any of the terminals while power is being supplied. Doing so may
!
result in serious electrical shock or electrocution.
4 Operating Environment Precautions
Do not operate the control system in the following places.
• Where the PC is exposed to direct sunlight.
• Where the ambient temperature is below 0°C or over 55°C.
• Where the PC may be affected by condensation due to radical temperature
changes.
• Where the ambient humidity is below 10% or over 90%.
• Where there is any corrosive or inflammable gas.
• Where there is excessive dust, saline air, or metal powder.
• Where the PC is affected by vibration or shock.
• Where any water, oil, or chemical may splash on the PC.
xiv
Application Precautions
Caution The operating environment of the PC System can have a large ef fect on the lon-
!
gevity and reliability of the system. Improper operating environments can lead to
malfunction, failure, and other unforeseeable problems with the PC System. Be
sure that the operating environment is within the specified conditions at installation and remains within the specified conditions during the life of the system.
5 Application Precautions
Observe the following precautions when using the PC.
WARNING Failure to abide by the following precautions could lead to serious or possibly
!
fatal injury. Always heed these precautions.
• Always ground the system to 100 Ω or less when installing the system to pro-
tect against electrical shock.
• Always turn off the power supply to the PC before attempting any of the following. Performing any of the following with the power supply turned on may lead
to electrical shock:
• Mounting or dismounting Power Supply Units, I/O Units, CPU Units,
Memory Units, or any other Units.
• Assembling any devices or racks.
• Connecting or disconnecting any cables or wiring.
5
Caution Failure to abide by the following precautions could lead to faulty operation or the
!
PC or the system or could damage the PC or PC Units. Always heed these precautions.
• Use the Units only with the power supplies and voltages specified in the operation manuals. Other power supplies and voltages may damage the Units.
• Take measures to stabilize the power supply to conform to the rated supply if it
is not stable.
• Provide circuit breakers and other safety measures to provide protection
against shorts in external wiring.
• Do not apply voltages exceeding the rated input voltage to Input Units. The
Input Units may be destroyed.
• Do not apply voltages exceeding the maximum switching capacity to Output
Units. The Output Units may be destroyed.
• Always disconnect the LG terminal when performing withstand voltage tests.
• Install all Units according to instructions in the operation manuals. Improper
installation may cause faulty operation.
• Provide proper shielding when installing in the following locations:
• Locations subject to static electricity or other sources of noise.
• Locations subject to strong electromagnetic fields.
• Locations subject to possible exposure to radiation.
• Locations near to power supply lines.
• Be sure to tighten Backplane screws, terminal screws, and cable connector
screws securely.
• Do not attempt to take any Units apart, to repair any Units, or to modify any
Units in any way.
Caution The following precautions are necessary to ensure the general safety of the sys-
!
tem. Always heed these precautions.
• Provide double safety mechanisms to handle incorrect signals that can be
generated by broken signal lines or momentary power interruptions.
• Provide external interlock circuits, limit circuits, and other safety circuits in
addition to any provided within the PC to ensure safety.
xv
Conformance to EC Directives
6 Conformance to EC Directives
Observe the following precautions when installing the C200HS-CPU01-EC and
C200HS-CPU21-EC that conform to the EC Directives.
Provide reinforced insulation or double insulation for the DC power source connected to the DC I/O Unit and for the Power Supply Unit.
Use a separate power source for the DC I/O Unit from the external power supply
for the Relay Output Unit.
Section 6
xvi
SECTION 1
Introduction
This section gives a brief overview of the history of Programmable Controllers and explains terms commonly used in ladderdiagram programming. It also provides an overview of the process of programming and operating a PC and explains basic
terminology used with OMRON PCs. Descriptions of peripheral devices used with the C200HS, a table of other manuals
available to use with this manual for special PC applications, and a description of the new features of the C200HS are also
provided.
1-1 Overview 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-2 The Origins of PC Logic 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-3 PC Terminology 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-4 OMRON Product Terminology 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-5 Overview of PC Operation 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-6 Peripheral Devices 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-7 Available Manuals 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-8 New C200HS Features 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-8-1 Improved Memory Capabilities 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-8-2 Faster Execution Times 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-8-3 Larger Instruction Set 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-8-4 Wide Selection of Special I/O Units 9 . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-8-5 Improved Interrupt Functions 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-8-6 SYSMAC NET Link and SYSMAC LINK Capabilities 9 . . . . . . . . . . .
1-8-7 Built-in RS-232C Connector 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-8-8 More Flexible PC Settings 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-8-9 Debugging and Maintenance 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-8-10 New Programming Console Operations 10 . . . . . . . . . . . . . . . . . . . . . . . .
1-8-11 Peripheral Devices 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-8-12 Using C200H Programs 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
The Origins of PC Logic Section 1-2
1-1 Overview
A PC (Programmable Controller) is basically a CPU (Central Processing Unit)
containing a program and connected to input and output (I/O) devices. The program controls the PC so that when an input signal from an input device turns ON,
the appropriate response is made. The response normally involves turning ON
an output signal to some sort of output device. The input devices could be photoelectric sensors, pushbuttons on control panels, limit switches, or any other device that can produce a signal that can be input into the PC. The output devices
could be solenoids, switches activating indicator lamps, relays turning on motors, or any other devices that can be activated by signals output from the PC.
For example, a sensor detecting a passing product turns ON an input to the PC.
The PC responds by turning ON an output that activates a pusher that pushes
the product onto another conveyor for further processing. Another sensor, positioned higher than the first, turns ON a different input to indicate that the product
is too tall. The PC responds by turning on another pusher positioned before the
pusher mentioned above to push the too-tall product into a rejection box.
Although this example involves only two inputs and two outputs, it is typical of the
type of control operation that PCs can achieve. Actually even this example is
much more complex than it may at first appear because of the timing that would
be required, i.e., “How does the PC know when to activate each pusher?” Much
more complicated operations, however, are also possible. The problem is how
to get the desired control signals from available inputs at appropriate times.
To achieve proper control, the C200HS uses a form of PC logic called ladder-diagram programming. This manual is written to explain ladder-diagram programming and to prepare the reader to program and operate the C200HS.
1-2 The Origins of PC Logic
PCs historically originate in relay-based control systems. And although the integrated circuits and internal logic of the PC have taken the place of the discrete
relays, timers, counters, and other such devices, actual PC operation proceeds
as if those discrete devices were still in place. PC control, however, also provides computer capabilities and accuracy to achieve a great deal more flexibility
and reliability than is possible with relays.
The symbols and other control concepts used to describe PC operation also
come from relay-based control and form the basis of the ladder-diagram programming method. Most of the terms used to describe these symbols and concepts, however, have come in from computer terminology.
Relay vs. PC Terminology The terminology used throughout this manual is somewhat different from relay
terminology, but the concepts are the same.
The following table shows the relationship between relay terms and the PC
terms used for OMRON PCs.
Relay term PC equivalent
contact input or condition
coil output or work bit
NO relay normally open condition
NC relay normally closed condition
Actually there is not a total equivalence between these terms. The term condition is only used to describe ladder diagram programs in general and is specifically equivalent to one of certain set of basic instructions. The terms input and
output are not used in programming per se, except in reference to I/O bits that
are assigned to input and output signals coming into and leaving the PC. Normally open conditions and normally closed conditions are explained in
Ladder Diagrams
.
4-4 Basic
2
OMRON Product Terminology Section 1-4
1-3 PC Terminology
Although also provided in the
terms are crucial to understanding PC operation and are thus explained here.
PC Because the C200HS is a Rack PC, there is no one product that is a C200HS
PC. That is why we talk about the configuration of the PC, because a PC is a
configuration of smaller Units.
To have a functional PC, you would need to have a CPU Rack with at least one
Unit mounted to it that provides I/O points. When we refer to the PC, however , we
are generally talking about the CPU and all of the Units directly controlled by it
through the program. This does not include the I/O devices connected to P C i n puts and outputs.
If you are not familiar with the terms used above to describe a PC, refer to
tion 2 Hardware Considerations
Inputs and Outputs A device connected to the PC that sends a signal to the PC is called an input
device; the signal it sends is called an input signal. A signal enters the PC
through terminals or through pins on a connector on a Unit. The place where a
signal enters the PC is called an input point. This input point is allocated a location in memory that reflects its status, i.e., either ON or OFF. This memory location is called an input bit. The CPU, in its normal processing cycle, monitors the
status of all input points and turns ON or OFF corresponding input bits accordingly.
There are also output bits in memory that are allocated to output points on
Units through which output signals are sent to output devices, i.e., an output
bit is turned ON to send a signal to an output device through an output point. The
CPU periodically turns output points ON or OFF according to the status of the
output bits.
These terms are used when describing different aspects of PC operation. When
programming, one is concerned with what information is held in memory , and so
I/O bits are referred to. When talking about the Units that connect the PC to the
controlled system and the places on these Units where signals enter and leave
the PC, I/O points are referred to. When wiring these I/O points, the physical
counterparts of the I/O points, either terminals or connector pins, are referred to.
When talking about the signals that enter or leave the PC, one refers to input
signals and output signals, or sometimes just inputs and outputs. It all depends
on what aspect of PC operation is being talked about.
Glossary
at the back of this manual, the following
for explanations.
Sec-
Controlled System and
Control System
The Control System includes the PC and all I/O devices it uses to control an external system. A sensor that provides information to achieve control is an input
device that is clearly part of the Control System. The controlled system is the
external system that is being controlled by the PC program through these I/O
devices. I/O devices can sometimes be considered part of the controlled system, e.g., a motor used to drive a conveyor belt.
1-4 OMRON Product Terminology
OMRON products are divided into several functional groups that have generic
names.
The term Unit is used to refer to all of the OMRON PC products. Although a Unit
is any one of the building blocks that goes together to form a C200HS PC, its
meaning is generally, but not always, limited in context to refer to the Units that
are mounted to a Rack. Most, but not all, of these products have names that end
with the word Unit.
The largest group of OMRON products is the I/O Units. These include all of the
Rack-mounting Units that provide non-dedicated input or output points for general use. I/O Units come with a variety of point connections and specifications.
Appendix A Standard Models
list products according to these groups.
3
Overview of PC Operation Section 1-5
High-density I/O Units are designed to provide high-density I/O capability and
include Group 2 High-density I/O Units and Special I/O High-density I/O Units.
Special I/O Units are dedicated Units that are designed to meet specific needs.
These include some of the High-density I/O Units, Position Control Units, Highspeed Counter Units, and Analog I/O Units.
Link Units are used to create Link Systems that link more than one PC or link a
single PC to remote I/O points. Link Units include Remote I/O Units, PC Link
Units, Host Link Units, SYSMAC NET Link Units, and SYSMAC LINK Units.
SYSMAC NET Link and SYSMAC LINK Units can be used with the CPU11 only.
Other product groups include Programming Devices, Peripheral Devices,
and DIN Rail Products.
1-5 Overview of PC Operation
The following are the basic steps involved in programming and operating a
C200HS. Assuming you have already purchased one or more of these PCs, you
must have a reasonable idea of the required information for steps one and two,
which are discussed briefly below. This manual is written t o explain steps three
through six, eight, and nine. The relevant sections of this manual that provide
more information are listed with each of these steps.
1, 2, 3...
Control System Design Designing the Control System is the first step in automating any process. A PC
1. Determine what the controlled system must do, in what order, and at what
times.
2. Determine what Racks and what Units will be required. Refer to the
Installation Guide
tem Manual
3. On paper, assign all input and output devices to I/O points on Units and determine which I/O bits will be allocated to each. If the PC includes Special I/O
Units or Link Systems, refer to the individual
Manuals
4. Using relay ladder symbols, write a program that represents the sequence
of required operations and their inter-relationships. Be sure to also program
appropriate responses for all possible emergency situations. (
for details on I/O bit allocation. (
. If a Link System is required, refer to the appropriate
.
Operation Manuals
Section 3 Memory Areas)
C200HS
Sys-
or
System
Section 4
Writing and Inputting the Program, Section 5 Instruction Set, Section 6 Program Execution Timing)
5. Input the program and all required operating parameters into the PC. (
tion 4-7 Inputting, Modifying, and Checking the Program.
6. Debug the program, first to eliminate any syntax errors, and then to find execution errors. (
Section 4-7 Inputting, Modifying, and Checking the Program, Section 7 Program Monitoring and Execution,
Troubleshooting
7. Wire the PC to the controlled system. This step can actually be started as
soon as step 3 has been completed. Refer t o the
and to
Units.
8. Test the program in an actual control situation and carry out fine tuning as
required. (
Operation Manuals
Troubleshooting
9. Record two copies of the finished program on masters and store them safely
in different locations. (
Program
can be programmed and operated only after the overall Control System is fully
understood. Designing the Control System requires, first of all, a thorough understanding of the system that is to be controlled. The first step in designing a
Control System is thus determining the requirements of the controlled system.
)
)
C200HS Installation Guide
and
System Manuals
for details on individual
Section 7 Program Monitoring and Execution
)
Section 4-7 Inputting, Modifying, and Checking the
)
and
and
Sec-
Section 10
Section 10
4
Available Manuals Section 1-7
Input/Output Requirements The first thing that must be assessed is the number of input and output points
that the controlled system will require. This is done by identifying each device
that is to send an input signal to the PC or which is to receive an output signal
from the PC. Keep in mind that the number of I/O points available depends on
the configuration of the PC. Refer to
the allocation of I/O bits to I/O points.
Sequence, Timing, and
Relationships
Unit Requirements The actual Units that will be mounted or connected to PC Racks must be deter-
Next, determine the sequence in which control operations are to occur and the
relative timing of the operations. Identify the physical relationships between the
I/O devices as well as the kinds of responses that should occur between them.
For instance, a photoelectric switch might be functionally tied to a motor by way
of a counter within the PC. When the PC receives an input from a start switch, it
could start the motor. The PC could then stop the motor when the counter has
received a specified number of input signals from the photoelectric switch.
Each of the related tasks must be similarly determined, from the beginning of the
control operation to the end.
mined according to the requirements of the I/O devices. Actual hardware specifications, such as voltage and current levels, as well as functional considerations,
such as those that require Special I/O Units or Link Systems will need to be considered. In many cases, Special I/O Units, Intelligent I/O Units, or Link Systems
can greatly reduce the programming burden. Details on these Units and Link
Systems are available in appropriate
Once the entire Control System has been designed, the task of programming,
debugging, and operation as described in the remaining sections of this manual
can begin.
3-3 IR Area
Operation Manuals
for details on I/O capacity and
and
System Manuals.
1-6 Peripheral Devices
The following peripheral devices can be used in programming, either to input/
debug/monitor the PC program or to interface the PC to external devices to output the program or memory area data. Model numbers for all devices listed below are provided in
been placed in bold when introduced in the following descriptions.
Programming Console A Programming Console is the simplest form of programming device for OM-
RON PCs. All Programming Consoles are connected directly to the CPU without
requiring a separate interface.
Ladder Support Software:
LSS
LSS is designed to run on IBM AT/XT compatibles and allows you to perform all
the operations of the Programming Console as well as many additional ones. PC
programs can be written on-screen in ladder-diagram form as well as in mnemonic form. As the program is written, it is displayed on a display, making confirmation and modification quick and easy . Syntax checks may also be performed
on the programs before they are downloaded to the PC.
The LSS is available on either 5” or 3.5” disks.
A computer running the LSS is connected to the C200HS via the Peripheral Port
on the CPU using the CQM1-CIF02 cable.
Appendix A Standard Models
. OMRON product names have
1-7 Available Manuals
The following table lists other manuals that may be required to program and/or
operate the C200HS.
vided with individual Units and are required for wiring and other specifications.
Name Cat. No. Contents
GPC Operation Manual W84 Programming procedures for the GPC
FIT Operation Manual W150 Programming procedures for using the FIT
Operation Manuals
(Graphics Programming Console)
(Factory Intelligent Terminal
and/or
Operation Guides
are also pro-
5
New C200HS Features Section 1-8
Name ContentsCat. No.
SYSMAC Support Software Operation Manuals W247/W248 Programming procedures for using the SSS
Data Access Console Operation Guide W173 Data area monitoring and data modification
procedures for the Data Access Console
Printer Interface Unit Operation Guide W107 Procedures for interfacing a PC to a printer
PROM Writer Operation Guide W155 Procedures for writing programs to EPROM chips
Floppy Disk Interface Unit Operation Guide W119 Procedures for interfacing PCs to floppy disk drives
Wired Remote I/O System Manual
(SYSMAC BUS)
Optical Remote I/O System Manual
(SYSMAC BUS)
PC Link System Manual W135 Information on building a PC Link System to
Host Link System Manual
(SYSMAC WAY)
SYSMAC NET Link Unit Operation Manual W114 Information on building a SYSMAC NET Link
SYSMAC LINK System Manual W174 Information on building a SYSMAC LINK System to
High-speed Counter Unit Operation Manual W141 Information on High-speed Counter Unit
Position Control Unit Operation Manuals NC111: W137
Analog I/O Units Operation Guide W127 Information on the C200H-AD001, C200H-DA001
Analog Input Unit Operation Manual W229 Information on the C200H-AD002 Analog Input Unit
Temperature Sensor Unit Operation Guide W124 Information on Temperature Sensor Unit
ASCII Unit Operation Manual W165 Information on ASCII Unit
ID Sensor Unit Operation Guide W153 Information on ID Sensor Unit
Voice Unit Operation Manual W172 Information on Voice Unit
Fuzzy Logic Unit Operation Manual W208 Information on Fuzzy Logic Unit
Fuzzy Support Software Operation Manual W210 Information on the Fuzzy Support Software which
Temperature Control Unit Operation Manual W225 Information on Temperature Control Unit
Heat/Cool Temperature Control Unit Operation
Manual
PID Control Unit Operation Manual W241 Information on PID Control Unit
Cam Positioner Unit Operation Manual W224 Information on Cam Positioner Unit
W120 Information on building a Wired Remote I/O System
to enable remote I/O capability
W136 Information on building an Optical Remote I/O
System to enable remote I/O capability
automatically transfer data between PCs
W143 Information on building a Host Link System to
manage PCs from a ‘host’ computer
System and thus create an optical LAN integrating
PCs with computers and other peripheral devices
enable automatic data transfer, programming, and
programmed data transfer between the PCs in the
System
Information on Position Control Unit
NC112: W128
NC211: W166
Analog I/O Units
supports the Fuzzy Logic Units
W240 Information on Heating and Cooling Temperature
Control Unit
1-8 New C200HS Features
The C200HS CPUs (C200HS-CPU01-E, C200HS-CPU03-E, C200HSCPU21-E, C200HS-CPU23-E, C200HS-CPU31-E, and C200HS-CPU33-E)
have a number of new features that the C200H CPUs lacked. The new C200HS
features are described briefly in this section. The C200HS-CPU01-E, C200HSCPU21-E, C200HS-CPU31-E use an AC power supply and the C200HSCPU03-E, C200HS-CPU23-E, and C200HS-CPU33-E use DC.
In addition, the C200HS-CPU21-E, C200HS-CPU23-E, C200HS-CPU31-E,
and C200HS-CPU33-E CPUs have an RS-232C connector. The C200HSCPU31-E and C200HS-CPU33-E CPUs support the SYSMAC NET Link Unit
and SYSMAC LINK Unit.
6
New C200HS Features Section 1-8
1-8-1 Improved Memory Capabilities
Internal Memory (UM) The C200HS CPUs come equipped with 16 KW of RAM in the PC itself, so a very
large memory capacity is available without purchasing a separate Memory Unit.
Furthermore, the Ladder Program Area has been increased to 15.2 KW.
Memory Cassettes Two types of Memory Cassettes are available for storage of data such as the
program. The PC can be set to transfer data from the Memory Cassette to UM
automatically when the PC is turned on.
Model Specifications
C200HS-ME16K 16-K Word EEPROM
C200HS-MP16K 16-K Word EPROM
Note C200H Memory Cassettes cannot be used in the C200HS.
Clock Function The C200HS CPUs have a built-in clock. It is not necessary to purchase a
Memory Unit equipped with a clock, as it was with the C200H-CPU21-E.
Increased SR Area In addition to the conventional areas of the C200H, the following areas have
been added for the internal auxiliary relays and special auxiliary relays of the
C200H. The SR area has been increased substantially to provide more work
words and words dedicated to new instructions. The SR area now ranges from
SR 236 to SR 299. (The SR area ends at SR 255 in C200H CPUs.) By using
additional areas, the user can use Special I/O Units and Remote I/O Units without worrying the empty areas.
Conventional areas IR Area 1 (without I/O area): IR 030 to 235
SR Area 1: SR 236 to 255
Additional areas IR Area 2: IR 300 to 511
SR Area 2: SR 256 to 299
The number of operands and instruction execution time will be increased when
SR 256 to SR 511 are used in basic instructions.
Increased DM Area The Read/Write DM area has been increased substantially, too. It now ranges
from DM 0000 to DM 6143, compared to DM 0000 to DM 0999 in C200H CPUs.
The 6000 words from DM 0000 to DM 5999 are available for use in the program.
(DM 6000 to DM 6143 are used for the History Log and other functions.)
Fixed DM and Expansion
DM Areas
The Fixed DM Area, used to store initializing data for Special I/O Units, has been
decreased in size. It now contains the 512 words from DM 6144 to DM 6655,
compared to 1000 words (DM 1000 to DM 1999) in C200H CPUs.
On the other hand, up to 3000 words of UM can be allocated as expansion DM.
Expansion DM is allocated in 1000-word units in DM 7000 to DM 9999.
C200H data s t o re d i n w o r d s D M 1 0 0 0 t o D M 1999 can be used in C200HS PCs
by converting these 1000 words to ROM in the C200HS’s DM area (DM 7000 to
DM 7999) and then automatically transferring them to DM 1000 to DM 1999
when the C200HS is turned on.
1-8-2 Faster Execution Times
Instruction Execution Time Basic instructions in the C200HS are executed in !@2 of the time required in the
C200H. Other instructions are executed in just !@4 of the time.
END Processing Time The time required for the cycle’s overhead processes depend on the system
configuration, but these processes are executed in about !@4 of the time required
in the C200H.
7
New C200HS Features Section 1-8
I/O Refreshing Time The I/O refreshing time has been reduced for all units, as shown in the following
table.
I/O Unit Time Required for Refreshing
Standard I/O Units !@3 of the C200H I/O refreshing time
Group-2 High-density I/O Units !@3 of the C200H I/O refreshing time
Special I/O Units $@5 of the C200H I/O refreshing time
1-8-3 Larger Instruction Set
Advanced programming is facilitated by the 225 application instructions available with the C200HS-CPU01-E, C200HS-CPU03-E, C200HS-CPU21-E, and
C200HS-CPU23-E, or the 229 application instructions available with the
C200HS-CPU31-E and C200HS-CPU33-E. In addition, programming has been
simplified by the addition of convenient instructions and macro functions. The
new instructions and functions are covered in detail in
Improved Instructions Additional functions have been added to the 7 instructions in the following table.
Instruction Additional Function(s)
DIST(80) Stack operation. The stack can contain up to 999 words.
COLL(81) FIFO/LIFO stack operation. The stack can contain up to 999 words.
MLPX(76) 4-to-256 decoder capability.
DMPX(77) 256-to-8 encoder capability .
ADB(50) Signed binary data can be added.
SBB(51) Signed binary data can be subtracted.
INT(89) Can be used to set scheduled interrupts in 1 ms units and control
input interrupts.
Section 5 Instruction Set
.
Expansion Instructions A group of 47 instructions have been designated as expansion instructions. An
expansion instruction does not have a fixed function code; one of the 18 expansion instruction function codes must be assigned to it before it can be used in a
program. An instructions tables, which allocates functions codes to expansion
instructions, must be transferred to the C200HS before the expansion instructions can be used.
New Instructions A total of 36 new instructions have been added to the C200HS. These instruc-
tions are listed below. (Instructions with (--) for function codes are expansion
instructions, which do not have fixed function codes. Some expansion instruction do have default function codes. The SET and RESET instructions are basic
instructions, MACRO and TRACE MEMORY SAMPLE instructions are applied
instructions, and the other instructions are expansion applied instructions. A default function number is assigned to the TOTALIZING TIMER, TRANSFER
BITS, AREA RANGE COMPARE, MACRO, AND TRACE MEMORY SAMPLE
instructions.
8
New C200HS Features Section 1-8
TRSM(45) TRACE MEMORY SAMPLE
MCRO(99) MACRO
MAX(--) FIND MAXIMUM
MIN(--) FIND MINIMUM
SUM(--) SUM
SRCH(--) DATA SEARCH
FPD(--) FAILURE POINT DETECTION
PID(--) PID CONTROL
HEX(--) ASCII TO HEX
XDMR(--) EXPANSION DM READ
DSW(--) DIGITAL SWITCH INPUT
TKY(--) TEN-KEY INPUT
MTR(--) MATRIX INPUT
HKY(--) 16-KEY INPUT
ADBL(--) DOUBLE BINARY ADD
SBBL(--) DOUBLE BINARY SUBTRACT
MBSL(--) DOUBLE SIGNED BINARY MULTIPLY
DBSL(--) DOUBLE SIGNED BINARY DIVIDE
MBS(--) SIGNED BINARY MULTIPLY
DBS(--) SIGNED BINARY DIVIDE
FCS(--) FRAME CHECKSUM
7SEG(--) 7-SEGMENT DISPLAY OUTPUT
RXD(--) RECEIVE
TXD(--) TRANSMIT
CPS(--) SIGNED BINARY COMPARE
CPSL(--) SIGNED DOUBLE BINARY COMPARE
NEG(--) 2’S COMPLEMENT
NEGL(--) DOUBLE 2’S COMPLEMENT
ZCPL(--) DOUBLE AREA RANGE COMPARE
AVG(--) AVERAGE VALUE
SCL(--) SCALE
SET SET
RSET RESET
TTIM(87) TOTALIZING TIMER
XFRB(62) TRANSFER BITS
ZCP(88) AREA RANGE COMPARE
1-8-4 Wide Selection of Special I/O Units
C200HS Systems can be configured in a variety of ways, using High-density I/O
Units, High-speed Counters, Position Control Units, Analog I/O Units, Temperature Sensor Units, ASCII Units, Voice Units, ID Sensor Units, Fuzzy Logic Units,
Cam Positioner Units, and so on.
1-8-5 Improved Interrupt Functions
Scheduled Interrupts The C200HS’s scheduled interrupt function has been improved so that the inter-
rupt interval can be set in 1 ms units rather than the 10 ms units in the C200H.
When the interrupt mode is set to C200HS mode, the interrupt response time is
only 1 ms max. (excluding the input ON/OFF delays). When a Communications
Unit is used with the C200HS-CPU31-E/CPU33-E CPU, the interrupt response
time is 10 ms max.
Input Interrupts Up to 8 interrupt subroutines can be executed by inputs to a C200HS-INT01 In-
terrupt Input Unit mounted to the C200HS. When the interrupt mode is set to
C200HS mode, the interrupt response time is only 1 ms max. (excluding the input ON/OFF delays). When a Communications Unit is used with the C200HSCPU31-E/CPU33-E CPU, the interrupt response time is 10 ms max.
1-8-6 SYSMAC NET Link and SYSMAC LINK Capabilities
The SYSMAC NET Link and SYSMAC LINK Systems are high-speed FA networks which can be used with the C200HS-CPU31-E and C200HS-CPU33-E
CPUs and the following Units:
SYSMAC NET Link Unit: C200HS-SNT32
SYSMAC LINK Units: C200HS-SLK12 (optical fiber cable)
C200HS-SLK22 (coaxial cable)
Data can be exchanged with the PCs in a SYSMAC NET Link or SYSMAC LINK
System using the SEND and RECV instructions.
9
New C200HS Features Section 1-8
1-8-7 Built-in RS-232C Connector
Host link communications are possible using the RS-232C connector built into
the C200HS-CPU21-E/CPU23-E/CPU31-E/CPU33-E CPU. By using the TXD
and RXD instructions, RS-232C communications is possible without using timeconsuming procedures. A 1-to-1 link using the LR Area or an NT link with the
Programmable Terminal (PT) allows high-speed communications.
1-8-8 More Flexible PC Settings
With its default settings, the C200HS can be used like a C200H PC, but the
C200HS’s new settings provide more flexibility and allow it to be adjusted to fit
particular applications. These new settings are described below.
DIP Switch Settings The 6 pins on the C200HS’s DIP switch are used to write-protect part of UM, set
the CPU to automatically transfer Memory Card data to UM, and other functions.
UM Area Allocation Portions of the UM area can be allocated for use as the Expansion DM Area and
I/O Comment Area. (Most of the UM area is used to store the ladder program.)
PC Setup DM 6600 to DM 6655 is set aside for PC Setup data. The PC Setup determines
many operating parameters, including the startup mode and initial Special I/O
Unit area.
1-8-9 Debugging and Maintenance
Data Trace A data trace function has been added, allowing bit status or word content to be
traced in real time.
Differential Monitor The C200HS supports differential monitoring from either the Programming Con-
sole or LSS. The operator can detect OFF-to-ON or ON-to-OFF transition in a
specified bit.
Error Log Area The C200HS supports all of the C200H-CPU31-E error history area functions
and also records the time and date of power interruptions. The C200HS’s error
log area is DM 6000 to DM 6030 (not DM 0969 to DM 0999 as in the C200HCPU31-E).
1-8-10New Programming Console Operations
The following Programming Console operations are supported by the C200HS
in addition to those supported by the C200H.
• Constants can be input in decimal form.
• Monitor displays can be switched between hexadecimal and normal or long
decimal form.
• OFF to ON and ON to OFF transitions in bit status can be monitored (differential monitoring).
• Function codes can be allocated to expansion instructions and current function code allocations can be read.
• UM area allocations can be set.
• The clock in the C200HS can be read and set.
• In addition to the TERMINAL mode supported in the C200H, the C200HS has
an EXTENDED TERMINAL mode in which all of the Programming Console’s
keys can be used to the status of Key Bits.
• The memory clear operation has been separated into an operation to clear the
user program excluding I/O comments and UM area allocation information,
and one to clear the user program, I/O comments , and UM area allocation information.
1-8-11 Peripheral Devices
Peripheral Device
Connection
With the C200H a Peripheral Device had to be connected through a Peripheral
Interface Unit or Host Link Unit, but with the C200HS Peripheral Devices can be
connected to the PC through a CQM1-CIF02 Connecting Cable.
10
New C200HS Features Section 1-8
I/O Comments Stored in PC By allocating a part of UM as the I/O Comment area, it is no longer necessary to
read I/O Comments from a Peripheral Device’s floppy disk. If the Peripheral Device is connected to the C200HS online, the ladder diagram can be viewed with
I/O comments.
Online Editing A “CYCLE TIME OVER” error will no longer be generated when the program in
the PC itself is being edited online.
1-8-12Using C200H Programs
Programs developed for the C200H can be very easily transferred for use in the
C200HS. This section provides the steps necessary to achieve this. Two procedures are provided: one for transferring using only internal CPU memory and
one for transferring via Memory Cassettes.
Detailed procedures for the individual steps involved in transferring programs
can be found in the Version-3 LSS Operation Manuals. You will also require a
CQM1-CIF02 Connecting Cable to connect the computer running LSS to the
C200HS.
Precautions Observe the following precautions when transferring C200H programs to the
C200HS.
• If a C200H program including the SET SYSTEM instruction (SYS(49)) is transferred to the C200HS, the operating parameters set by this instruction will be
transferred to the C200HS’s PC Setup area (DM 6600, DM 6601, and
DM 6655) and overwrite any current settings. Be sure to confirm that the settings in these words are correct before using the C200HS after program transfer.
• If the C200H program accesses the C200H’s error log in DM 0969 to DM 0999,
the addresses of the words being accessed must be changed to DM 6000 to
DM 6030, which is the error log area for the C200HS.
• Any programs that rely on the execution cycle time (i.e., on the time require to
execute any one part of all of the program) must be adjusted when used on the
C200HS, which provides a much faster cycle time.
Using Internal Memory The following procedure outlines the steps to transfer C200H programs to the
user memory inside the C200HS.
1, 2, 3...
1. Transfer the program and any other required data to the LSS work area. This
data can be transferred from a C200H CPU, from floppy disk, or from a
C200HS Memory Unit.
To transfer from a C200H CPU, set the PC for the LSS to the C200H, connect the LSS to the C200H, go online, and transfer the program and any other require data to the LSS work area. Y ou will probably want to transfer DM
data and the I/O table, if you have created an I/O table for the C200H.
or To transfer from floppy disk, set the PC for the LSS to the C200H in the of fline
mode and load the program and any other require data to the LSS work
area. You will probably want to load DM data and the I/O table, if you have
created an I/O table for the C200H.
or To transfer from a C200H-MP831, set the PC for the LSS to the C200H in the
offline mode and read data from the Memory Unit into the LSS work area.
2. Go offline if the LSS is not already offline.
3. Change the PC setting for the LSS to the C200HS.
4. If you want to transfer I/O comments together with the program to the
C200HS, allocate UM area for I/O comments.
5. Connect the LSS to the C200HS and go online.
6. Make sure that pin 1 on the C200HS’s CPU is OFF to enable writing to the
UM area.
11
New C200HS Features Section 1-8
7. Transfer the program and and any other require data to the C200HS. You
will probably want to transfer DM data and the I/O table, if you have created
an I/O table for the C200H.
8. Turn the C200HS off and then back on to reset it.
9. Test program execution before attempting actual operation.
Using Memory Cassettes The following procedure outlines the steps to transfer C200H programs to the
C200HS via EEPROM or EPROM Memory Cassettes. This will allow you to read
the program data from the Memory Cassette automatically at C200HS startup.
The first four steps of this procedure is the same as those used for transferring
directly to the C200HS’s internal memory (UM area).
1, 2, 3...
1. Transfer the program and any other required data to the LSS work area. This
data can be transferred from a C200H CPU, from floppy disk, or from a
C200HS Memory Unit.
To transfer from a C200H CPU, set the PC for the LSS to the C200H, connect the LSS to the C200H, go online, and transfer the program and any other require data to the LSS work area. Y ou will probably want to transfer DM
data and the I/O table, if you have created an I/O table for the C200H.
or To transfer from floppy disk, set the PC for the LSS to the C200H in the of fline
mode and load the program and any other require data to the LSS work
area. You will probably want to load DM data and the I/O table, if you have
created an I/O table for the C200H.
or To transfer from a C200H-MP831, set the PC for the LSS to the C200H in the
offline mode and read data from the Memory Unit into the LSS work area.
2. Go offline if the LSS is not already offline.
3. Change the PC setting for the LSS to the C200HS.
4. If you want to transfer I/O comments together with the program to the
C200HS, allocate UM area for I/O comments.
5. Allocate expansion DM words DM 7000 to DM 7999 in the UM area using the
UM allocation operation from the LSS.
6. Copy DM 1000 through DM 1999 to DM 7000 through DM 7999.
7. Write “0100” to DM 6602 to automatically transfer the contents of DM 7000
through DM 7999 to DM 1000 through DM 1999 at startup.
8. To transfer to an EEPROM Memory Cassette, use the following procedure.
a) Connect the LSS to the C200HS and go online.
b) Make sure that pin 1 on the C200HS’s CPU is OFF to enable writing to
the UM area.
c) Transfer the program and any other require data to the C200HS. You will
probably want to transfer DM data and the I/O table, if you have created
an I/O table for the C200H. Make sure you specify transfer of the Expansion DM Area and, if desired, the I/O Comment Area.
d) Turn ON SR 27000 from the LSS to transfer UM data to the Memory Cas-
sette and continue from step 9.
or To transfer to an EPROM Memory Cassette, use the following procedure.
a) Connect an PROM Writer to the LSS and write the data to the EPROM
chip using the LSS EPROM writing operation.
e) Set the ROM type selector on the Memory Cassette to the correct capac-
ity.
f) Mount the ROM chip to the Memory Cassette.
g) Mount a EPROM Memory Cassette to the C200HS.
9. Turn ON pin 2 on the C200HS’s DIP switch to enable automatic transfer of
Memory Cassette data to the CPU at startup.
12
New C200HS Features Section 1-8
10. Turn the C200HS off and then back on to reset it and transfer data from the
Memory Cassette to the CPU.
11. Test program execution before attempting actual operation.
13
SECTION 2
Hardware Considerations
This section provides information on hardware aspects of the C200HS that are relevant to programming and software operation. These include CPU Components, basic PC configuration, CPU capabilities, and Memory Cassettes. This information is
covered in detail in the C200HS Installation Guide.
2-1 CPU Components 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1-1 CPU Indicators 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1-2 Peripheral Device Connection 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-2 PC Configuration 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-3 CPU Capabilities 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-4 Memory Cassettes 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-5 Installing Memory Cassettes 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-6 CPU DIP Switch 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
CPU Components Section 2-1
2-1 CPU Components
There are two groups of CPUs available, one that uses an AC power supply, and
one that uses a DC power supply. Select one of the models shown below according to requirements of your control system.
CPU model Power supply voltage
C200HS-CPU01-E/CPU21-E/CPU31-E 100 to 120 VAC or 200 to 240 VAC
C200HS-CPU03-E/CPU23-E/CPU33-E 24 VDC
The CPU21-E, CPU23-E, CPU31-E, and CPU33-E CPUs have an RS-232C
connector. The CPU31-E and CPU33-E CPUs support the SYSMAC NET Link
Unit and SYSMAC LINK Unit.
Caution Be sure to check the power supply used by the CPU. Absolutely do not provide an AC power sup-
!
ply to a DC-type CPU.
The following diagram shows the main CPU components.
Power fuse (MF51NR, 5.2 dia. x 20 mm)
Indicators
C200HS-CPU01-E: 2 A, 250 V
C200HS-CPU03-E: 5 A, 125 V
(voltage selector)
Battery/switch compartment
The backup lithium battery (C200H-BAT09)
and the DIP switch for setting C200HS operations are contained. An optional Memory Cassette can also be mounted.
Removable terminal block
Cable connector for Peripheral Devices
(Peripheral port)
16
CPU Components Section 2-1
C200HS-CPU21-E/CPU23-E/CPU31-E/CPU33-E
Power fuse (MF51NR, 5.2 dia. x 20 mm):
Indicators
Memory Casette compartment
Bus connector:
Available only with the CPU31-E
and CPU33-E. Use this connector
when SYSMAC NET Link Unit or
SYSMAC LINK Unit is used.
C200HS-CPU21-E/CPU31-E: 2 A, 250 V
C200HS-CPU23-E/CPU33-E: 5 A, 125 V
Removable terminal block
RS-232C
connector
Battery/Switch compartment
Cable connector for
peripheral devices
2-1-1 CPU Indicators
CPU indicators provide visual information on the general operation of the PC.
Although not substitutes for proper error programming using the flags and other
error indicators provided in the data areas of memory , these indicators provide
ready confirmation of proper operation.
CPU Indicators CPU indicators are shown and described below. (CPU01-E/03-E shown below.)
COMM/COMM1 (orange):
Lights when a peripheral device is in operation.
COMM2 (orange):
RUN indicator (green)
Lights when the PC is
operating normally.
COMM
Available only with the CPU21-E, CPU23-E, CPU31-E,
and CPU33-E. Lights when the CPU is communicating
via the RS-232C connector.
POWER (green)
Lights when power is
supplied to the CPU.
ALM (blinking red)
Blinks if an error occurs that
does not stop the CPU.
ERR (solid red)
Lights if an error occurs that stops the
CPU, at which time the RUN indicator
turns OFF and the outputs are turned
OFF.
OUT INHIBIT (red)
Lights when the Load OFF
flag (SR bit 25215) turns ON,
at which time all the outputs
are turned OFF.
17
PC Configuration Section 2-2
2-1-2 Peripheral Device Connection
A Programming Console or IBM PC/AT running LSS can be used to program
and monitor the C200HS PCs.
Programming Console A C200H-PR027-E or CQM1-PRO01-E Programming Console can be con-
nected as shown in the following diagram. The C200H-PR027-E is connected
via the C200H-CN222 or C200H-CN422 Programming Console Connecting
Cable, which must be purchased separately. A Connecting Cable is provided
with the CQM1-PRO01-E.
Connecting Cable
Programming Console
IBM PC/AT with LSS An IBM PC/AT or compatible computer can be connected as shown in the follow-
ing diagram. The LSS is available on either 3.5” disks (C500-SF312-EV3) or
5.25” disks (C500-SF711-EV3). Only version 3 or later of the LSS supports
C200HS functionality.
Connecting Cable
(CQM1-CIF02)
IBM PC/AT
2-2 PC Configuration
The basic PC configuration consists of two types of Rack: a CPU Rack and Expansion I/O Racks. The Expansion I/O Racks are not a required part of the basic
system. They are used to increase the number of I/O points. An illustration of
these Racks is provided in
can be used when the PC is provided with a Remote I/O System.
CPU Racks A C200HS CPU Rack consists of three components: (1) The CPU Backplane, to
which the CPU and other Units are mounted. (2) The CPU, which executes the
program and controls the PC. (3) Other Units, such as I/O Units, Special I/O
Units, and Link Units, which provide the physical I/O terminals corresponding to
I/O points.
A C200HS CPU Rack can be used alone or it can be connected to other Racks to
provide additional I/O points. The CPU Rack provides three, five, eight, or ten
slots to which these other Units can be mounted depending on the backplane
used.
3-3 IR Area.
A third type of Rack, called a Slave Rack,
18
CPU Capabilities Section 2-3
Expansion I/O Racks An Expansion I/O Rack can be thought of as an extension of the PC because it
provides additional slots to which other Units can be mounted. It is built onto an
Expansion I/O Backplane to which a Power Supply and up to ten other Units are
mounted.
An Expansion I/O Rack is always connected to the CPU via the connectors on
the Backplanes, allowing communication between the two Racks. Up to two Expansion I/O Racks can be connected in series to the CPU Rack.
Unit Mounting Position Only I/O Units and Special I/O Units can be mounted to Slave Racks. All I/O
Units, Special I/O Units, Group-2 High-density I/O Units, Remote I/O Master
Units, PC and Host Link Units, can be mounted to any slot on all other Racks.
Interrupt Input Units must be mounted to C200H-BCjj1-V2 Backplanes.
Refer to the
C200HS Installation Guide
for details about which slots can be used
for which Units and other details about PC configuration. The way in which I/O
points on Units are allocated in memory is described in
3-3 IR Area
.
2-3 CPU Capabilities
The following tables compare the capabilities of C200H and C200HS CPUs.
C200H
Function C200H
CPU21-E CPU23-E CPU31-E
Built-in clock/calendar No (see note) No (see note) Yes
Error log No No Yes
Data Trace No No No
Differential Monitor No No No
Expansion DM No No No
General-use DM 1000 words 970 words
Ladder Program capacity 6974 words (in Memory Unit)
SR Area SR 236 to SR 255
New instructions:
(See
1-8-3 Larger Instruction Set
36 new instructions.)
Network Instructions:
NETWORK SEND - SEND(90)
NETWORK RECEIVE - RECV(98)
Power Supply AC DC AC
for a list of the
No No No
No No Yes
Note The C200H-CPU21-E/CPU23-E can use the C200H-MR433/MR833/
ME432/ME832 Memory Units’ clock.
19
Memory Cassettes Section 2-4
C200HS
Function C200HS
CPU01-E CPU21-E CPU31-E CPU03-E CPU23-E CPU33-E
Built-in clock/calendar Yes
Error log Yes
Data Trace Yes
Differential Monitor Yes
Expansion DM 3K words max.
General-use DM 6K words
Ladder Program capacity 15.2K words max
SR Area SR 236 to SR 255 and SR 256 to SR 299
New instructions:
1-8-3 Larger Instruction Set
(See
36 new instructions.)
Network Instructions:
NETWORK SEND - SEND(90)
NETWORK RECEIVE - RECV(98)
Power Supply AC DC
for a list of the
Note 1. The C200HS CPUs record the time and date of power interruptions.
2. Part of the 16K-word UM can be allocated to Expansion DM and I/O comments.
1
2
2
Yes
No No Yes No No Yes
2-4 Memory Cassettes
The C200HS comes equipped with a built-in RAM for the user’s program, so a
normal program be created even without installing a Memory Cassette. An optional Memory Cassette, however, can be used. There are two types of Memory
Cassette available, each with a capacity of 16K words. For instructions on installing Memory Cassettes, refer to
The following table shows the Memory Cassettes which can be used with the
C200HS PCs. These Memory Cassettes cannot be used in C200H PCs.
Memory Capacity Model number Comments
EEPROM 16K words C200HS-ME16K --EPROM 16K words C200HS-MP16K The EPROM chip is not included
Note Memory Cassettes for the C200HS cannot be used with the C200H, and
Memory Units for the C200H cannot be used with the C200HS.
C200HS-MEj16K
(EEPROM)
When a Memory Cassette is installed in the CPU, reading and writing of the
user memory (UM) and I/O data is made possible. There is no need for a
backup power supply. The Memory Cassette can be removed from the CPU
and used for storing data.
2-5 Installing Memory Cassettes
with the Memory Cassette; it must
be purchased separately.
.
20
Installing Memory Cassettes Section 2-5
C200HS-MPj16K (EPROM) The program is written using a PROM Writer. The ROM is mounted to the
Memory Casette and then installed in the CPU. I/O data cannot be stored.
Notch
2-5 Installing Memory Cassettes
An optional Memory Cassette can be installed in the C200HS. (The C200H
Memory Unit cannot be used with the C200HS.) The two types of Memory Cassettes are described in
follow the procedure outlined below.
2-4 Memory Cassettes
. To install a Memory Cassette,
Caution Be careful to always turn the power off before inserting or removing a Memory Cassette. If a
!
Memory Cassette is inserted into or removed from the CPU with the power on, it may cause the
CPU to malfunction or cause damage to the memory.
1, 2, 3...
Note *Only 16K words accessible.
1. Set the DIP switch. For an EEPROM Memory Cassette, set pin no. 1 (write
protect) to either ON or OFF. Setting it to ON will protect the program in the
memory from being overwritten. Setting it to OFF will allow the program to
be overwritten. (The factory setting is OFF.)
For an EPROM Memory Cassette, set pin no. 1 (ROM Type Selector) according to the type of ROM that is to be mounted.
Pin no. 1 ROM type Model Capacity Access speed
OFF 27256 ROM-JD-B 16K words 150 ns
ON 27512 ROM-KD-B 32K words* 150 ns
2. Write to EPROM (if using an EPROM Memory Cassette). Using a PROM
Writer, write the program to EPROM. Then mount the EPROM chip to the
Memory Cassette, with the notched end facing upwards as shown in the illustration below.
Notch
21
Installing Memory Cassettes Section 2-5
3. Remove the bracket from the Memory Cassette, as shown in the illustration
below.
Metal bracket
4. Check that the connector side goes in first and that the Cassette’s circuit
components face right and then insert the Cassette into the CPU. The Cassette slides in along a track in the CPU.
5. Replace the Memory Cassette bracket over the Cassette and tighten the
screw that holds the bracket.
22
ggg
CPU DIP Switch Section 2-6
2-6 CPU DIP Switch
The DIP switch on C200HS CPUs is located between the Memory Cassette
compartment and battery.
The 6 pins on the DIP switch control 6 of the CPU’s operating parameters.
Pin no. Item Setting Function
1 Memory protect
2 Automatic transfer of Memory
Cassette contents
3 Message language
4 Expansion instruction setting
5 Communications parameters
6 Expansion TERMINAL mode
setting when AR 0709 is ON
ON Program Memory and read-only DM (DM 6144 to DM 6655)
data cannot be overwritten from a Peripheral Device.
OFF Program Memory and read-only DM (DM 6144 to DM 6655)
data can be overwritten from a Peripheral Device.
ON The contents of the Memory Cassette will be automatically
transferred to the internal RAM at start-up.
OFF The contents will not be automatically transferred.
ON Programming Console messages will be displayed in English.
OFF Programming Console messages will be displayed in the
language stored in system ROM. (Messages will be displayed
in Japanese with the Japanese version of system ROM.)
ON Expansion instructions set by user. Normally ON when using a
host computer for programming/monitoring.
OFF Expansion instructions set to defaults.
ON Standard communications parameters (see note) will be set for
the following serial communications ports.
• Built-in RS-232C port
• Peripheral port (only when a CQM1-CIF01/-CIF02 Cable is
connected. Does not apply to Programming Console.)
Note 1. Standard communications parameters are as fol-
lows:
Serial communications mode: Host Link or peripheral bus; start bits: 1; data length: 7 bits; parity: even;
stop bits: 2; baud rate: 9,600 bps
2. The CX-Programmer running on a personal computer can be connected to the peripheral port via the peripheral bus using the above standard communications parameters.
OFF The communications parameters for the following serial
communications ports will be set in PC Setup as follows:
• Built-in RS-232C port: DM 6645 and DM 6646
• Peripheral port: DM 6650 and DM 6651
Note When the CX-Programmer is connected to the peripheral
port with the peripheral bus, either set bits 00 to 0 3 of DM
6650 to 0 Hex (for standard parameters), or set bits 12 to
15 of DM 6650 to 0 Hex and bits 00 to 03 of DM 6650 to 1
Hex (for Host Link or peripheral bus) separately.
ON Expansion TERMINAL mode; AR 0712 ON.
OFF Normal mode; AR 0712: OFF
Note The above settings apply to CPUs manufactured from July 1995 (lot number **75 for July 1995). For CPUs
manufactured before July 1995 (lot number **65 for June 1995), only 1 stop bit will be set and the baud rate
will be 2,400 bps.
23
SECTION 3
Memory Areas
Various types of data are required to achieve effective and correct control. To facilitate managing this data, the PC is provided
with various memory areas for data, each of which performs a different function. The areas generally accessible by the user
for use in programming are classified as data areas. The other memory area is the UM Area, where the user’s program is
actually stored. This section describes these areas individually and provides information that will be necessary to use them. A s
a matter of convention, the TR area is described in this section, even though it is not strictly a memory area.
3-1 Introduction 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-2 Data Area Structure 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3 IR (Internal Relay) Area 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4 SR (Special Relay) Area 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-1 SYSMAC NET/SYSMAC LINK System 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-2 Remote I/O Systems 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-3 Link System Flags and Control Bits 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-4 Forced Status Hold Bit 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-5 I/O Status Hold Bit 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-6 Output OFF Bit 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-7 FAL (Failure Alarm) Area 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-8 Low Battery Flag 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-9 Cycle Time Error Flag 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-10 I/O Verification Error Flag 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-11 First Cycle Flag 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-12 Clock Pulse Bits 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-13 Step Flag 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-14 Group-2 Error Flag 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-15 Special Unit Error Flag 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-16 Instruction Execution Error Flag, ER 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-17 Arithmetic Flags 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-18 Interrupt Subroutine Areas 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-19 RS-232C Port Communications Areas 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-20 Peripheral Port Communications Areas 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-21 Memory Cassette Areas 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-22 Data Transfer Error Bits 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-23 Ladder Diagram Memory Areas 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-24 Memory Error Flags 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-25 Data Save Flags 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-26 Transfer Error Flags 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-27 PC Setup Error Flags 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5 AR (Auxiliary Relay) Area 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-1 Restarting Special I/O Units 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-2 Slave Rack Error Flags 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-3 Group-2 Error Flags 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-4 Optical I/O Unit and I/O Terminal Error Flags 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-5 SYSMAC LINK System Data Link Settings 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-6 Error History Bits 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-7 Active Node Flags 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-8 SYSMAC LINK/SYSMAC NET Link System Service Time 52 . . . . . . . . . . . . . . . . . . . . .
3-5-9 Calendar/Clock Area and Bits 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-10 TERMINAL Mode Key Bits 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-11 Power OFF Counter 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-12 Cycle Time Flag 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-13 Link Unit Mounted Flags 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-14 CPU-mounting Device Mounted Flag 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-15 FPD Trigger Bit 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-16 Data Tracing Flags and Control Bits 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-17 Cycle Time Indicators 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-6 DM (Data Memory) Area 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-6-1 Expansion DM Area 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-6-2 Special I/O Unit Data 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-6-3 Error History Area 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-6-4 PC Setup 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-7 HR (Holding Relay) Area 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-8 TC (Timer/Counter) Area 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-9 LR (Link Relay) Area 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-10 UM Area 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-11 TR (Temporary Relay) Area 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
y
Introduction Section 3-1
3-1 Introduction
Details, including the name, size, and range of each area are summarized in the
following table. Data and memory areas are normally referred to by their acronyms, e.g., the IR Area, the SR Area, etc.
Area Size Range Comments
I/O Area 480 bits IR 000 to IR 029 I/O words are allocated to the CPU Rack and
Expansion I/O Racks by slot position.
Group-2 High-density
I/O Unit and B7A
Interface Unit Area
SYSMAC BUS Area 800 bits IR 050 to IR 099 Allocated to Remote I/O Slave Racks 0 to 4.
Special I/O Unit Area 1,600 bits IR 100 to IR 199 Allocated to Special I/O Units 0 to 9.
Optical I/O Unit and I/O
Terminal Area
Work Area 1 64 bits IR 232 to IR 235 For use as work bits in the program.
Special Relay Area 1 312 bits SR 23600 to SR
Special Relay Area 2 704 bits SR 256 to SR 299
Macro Area
Work Area 2 3,392 bits IR 300 to IR 511 For use as work bits in the program.
Temporary Relay Area 8 bits TR 00 to TR 07 Used to temporarily store and retrieve execution
Holding Relay Area 1,600 bits HR 00 to HR 99 Used to store data and to retain the data values
Auxiliary Relay Area 448 buts AR 00 to AR 27 Contains flags and bits for special functions. Re-
Link Relay Area 1,024 bits LR 00 to LR 63 Used for data links in the PC Link System.
Timer/Counter Area 512 counters/
Data Memory Area
Fixed DM Area
Expansion DM Area 3,000 words max. DM 7000 to DM 9999 Read only
320 bits IR 030 to IR 049 Allocated to Group-2 High-density I/O Units and
to Group-2 B7A Interface Units 0 to 9
512 bits IR 200 to IR 231 Allocated to Optical I/O Units and I/O
Terminals.
Contains system clocks, flags, control bits, and
25507
(298 to 299 reserved
by system)
64 bits SR 290 to SR 293 Inputs
64 bits SR 294 to SR 297 Outputs
TC 000 to TC 51 1 Used to define timers and counters, and to
timers
6,144 words DM 0000 to DM 6143 Read/Write
1,000 words DM 0000 to DM 0999 Normal DM.
1,000 words DM 1000 to DM 1999 Special I/O Unit Area
4,000 words DM 2000 to DM 5999 Normal DM.
31 words DM 6000 to DM 6030 History Log
(44 words) DM 6100 to DM 6143 Link test area (reserved)
512 words DM 6144 to DM 6599 Fixed DM Area (read only)
56 words DM 6600 to DM 6655 PC Setup
status information.
Contains flags, control bits, and status informa-
tion.
conditions when programming certain types of
branching ladder diagrams.
when the power to the PC is turned off.
tains status during power failure.
access completion flags, PV, and SV.
Interval timers 0 through 2 and high-speed
counters 0 through 2 provided in separate area.
TIM 000 through TIM 015 can be refreshed via
interrupt processing as high-speed timers.
1
2
1
1
1
1
1
Note 1. These can be used as work words and bits when not used for their allocated
purposes.
2. The PC Setup can be set to use DM 7000 through DM 7999 as the Special
I/O Area.
26
Data Area Structure Section 3-2
Work Bits and Words When some bits and words in certain data areas are not being used for their in-
tended purpose, they can be used in programming as required to control other
bits. Words and bits available for use in this fashion are called work words and
work bits. Most, but not all, unused bits can be used as work bits. Those that can
be used are described area-by-area in the remainder of this section. Actual application of work bits and work words is described in
ting the Program
Flags and Control Bits Some data areas contain flags and/or control bits. Flags are bits that are auto-
matically turned ON and OFF to indicate particular operation status. Although
some flags can be turned ON and OFF by the user, most flags are read only; they
cannot be controlled directly.
Control bits are bits turned ON and OFF by the user to control specific aspects of
operation. Any bit given a name using the word bit rather than the word flag is a
control bit, e.g., Restart bits are control bits.
.
Section 4 Writing and Input-
3-2 Data Area Structure
When designating a data area, the acronym for the area is always required for
any but the IR and SR areas. Although the acronyms for the IR and SR areas are
often given for clarity in text explanations, they are not required, and not entered,
when programming. Any data area designation without an acronym is assumed
to be in either the IR or SR area. Because IR and SR addresses run consecutively, the word or bit addresses are sufficient to differentiate these two areas.
An actual data location within any data area but the TC area is designated by its
address. The address designates the bit or word within the area where the desired data is located.
for a specific timer or counter defined in the program. Refer to
more details on TC numbers and to
formation on their application.
The rest of the data areas (i.e., the IR, SR, HR, DM, AR, and LR areas) consist of
words, each of which consists of 16 bits numbered 00 through 15 from right to
left. IR words 000 and 001 are shown below with bit numbers. Here, the content
of each word is shown as all zeros. Bit 00 is called the rightmost bit; bit 15, the
leftmost bit.
The term least significant bit is often used for rightmost bit; the term most significant bit, for leftmost bit. These terms are not used in this manual because a
single data word is often split into two or more parts, with each part used for different parameters or operands. When this is done, the rightmost bits of a word
may actually become the most significant bits, i.e., the leftmost bits in another
word,when combined with other bits to form a new word.
The TC area consists of TC numbers, each of which is used
3-8 TC Area
5-14 Timer and Counter Instructions
for
for in-
Bit number
IR word 000 0000000000000000
IR word 001 0000000000000000
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
The DM area is accessible by word only; you cannot designate an individual bit
within a DM word. Data in the IR, SR, HR, AR, and LR areas is accessible either
by word or by bit, depending on the instruction in which the data is being used.
To designate one of these areas by word, all that is necessary is the acronym (if
required) and the two-, three-, or four-digit word address. To designate an area
by bit, the word address is combined with the bit number as a single four- or fivedigit address. The following table show examples of this. The two rightmost digits of a bit designation must indicate a bit between 00 and 15, i.e., the rightmost
digit must be 5 or less the next digit to the left, either 0 or 1.
27
Data Area Structure Section 3-2
The same TC number can be used to designate either the present value (PV) of
the timer or counter, or a bit that functions as the Completion Flag for the timer or
counter. This is explained in more detail in
Area Word designation Bit designation
IR 000 00015 (leftmost bit in word 000)
SR 252 25200 (rightmost bit in word 252)
DM DM 1250 Not possible
TC TC 215 (designates PV) TC 215 (designates completion flag)
LR LR 12 LR 1200
3-8 TC Area
Data Structure Word data input as decimal values is stored in binary-coded decimal (BCD);
word data entered as hexadecimal is stored in binary form. Each four bits of a
word represents one digit, either a hexadecimal or decimal digit, numerically
equivalent to the value of the binary bits. One word of data thus contains four
digits, which are numbered from right to left. These digit numbers and the corresponding bit numbers for one word are shown below.
Digit number 3210
.
Bit number
Contents 0000000000000000
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Converting Different Forms
of Data
When referring to the entire word, the digit numbered 0 is called the rightmost
digit; the one numbered 3, the leftmost digit.
When inputting data into data areas, it must be input in the proper form for the
intended purpose. This is no problem when designating individual bits, which
are merely turned ON (equivalent to a binary value of 1) or OFF (a binary value of
0). When inputting word data, however, it is important to input it either as decimal
or as hexadecimal, depending on what is called for by the instruction it is to be
used for.
Section 5 Instruction Set
specifies when a particular form of data is re-
quired for an instruction.
Binary and hexadecimal can be easily converted back and forth because each
four bits of a binary number is numerically equivalent to one digit of a hexadecimal number. The binary number 0101111101011111 is converted to hexadecimal by considering each set of four bits in order from the right. Binary 1111 is
hexadecimal F; binary 0101 is hexadecimal 5. The hexadecimal equivalent
3
would thus be 5F5F, or 24,415 in decimal (16
x 5 + 162 x 15 + 16 x 5 + 15).
Decimal and BCD are easily converted back and forth. In this case, each BCD
digit (i.e., each group of four BCD bits) is numerically equivalent of the corresponding decimal digit. The BCD bits 0101011101010111 are converted to decimal by considering each four bits from the right. Binary 0101 is decimal 5; binary
0111 is decimal 7. The decimal equivalent would thus be 5,757. Note that this is
not the same numeric value as the hexadecimal equivalent of
0101011101010111, which would be 5,757 hexadecimal, or 22,359 in decimal
3
x 5 + 162 x 7 + 16 x 5 + 7).
(16
Because the numeric equivalent of each four BCD binary bits must be numeri-
cally equivalent to a decimal value, any four bit combination numerically greater
then 9 cannot be used, e.g., 1011 is not allowed because it is numerically equivalent to 11, which cannot be expressed as a single digit in decimal notation. The
binary bits 1011 are of course allowed in hexadecimal are a equivalent to the
hexadecimal digit C.
There are instructions provided to convert data either direction between BCD
and hexadecimal. Refer to
5-18 Data Conversion
for details. Tables of binary
equivalents to hexadecimal and BCD digits are provided in the appendices for
reference.
28
Data Area Structure Section 3-2
Decimal Points Decimal points are used in timers only. The least significant digit represents
tenths of a second. All arithmetic instructions operate on integers only.
Signed and Unsigned Binary Data
This section explains signed and unsigned binary data formats. Many instructions can use either signed or unsigned data and a few (CPS(––), CPSL(––),
DBS(––), DBSL(––), MBS(––), and MBSL(––)) use signed data exclusively.
Unsigned binary Unsigned binary is the standard format used in OMRON PCs. Data in this manu-
al are unsigned unless otherwise stated. Unsigned binary values are always
positive and range from 0 ($0000) to 65,535 ($FFFF). Eight-digit values range
from 0 ($0000 0000) to 4,294,967,295 ($FFFF FFFF).
Digit value 16
3
16
2
16
1
16
0
Bit number
Contents 0000000000000000
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Signed Binary Signed binary data can have either a positive and negative value. The sign is
indicated by the status of bit 15. If bit 15 is OFF, the number is positive and if bit 15
is ON, the number is negative. Positive signed binary values range from 0
($0000) to 32,767 ($7FFF), and negative signed binary values range from
–32,768 ($8000) to –1 ($FFFF).
Sign indicator
Digit value 16
Bit number
Contents 0000000000000000
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
3
16
2
16
1
16
0
Eight-digit positive values range from 0 ($0000 0000) to 2,147,483,647 ($7FFF
FFFF), and eight-digit negative values range from –2,147,483,648 ($8000
0000) to –1 ($FFFF FFFF).
29
Data Area Structure Section 3-2
The following table shows the corresponding decimal, 16-bit hexadecimal, and
32-bit hexadecimal values.
Decimal 16-bit Hex 32-bit Hex
2147483647
2147483646
.
.
.
32768
32767
32766
.
.
.
2
1
0
–1
–2
.
.
.
–32767
–32768
–32769
.
.
.
–2147483647
–2147483648
–––
–––
–––
7FFF
7FFE
0002
0001
0000
FFFF
FFFE
8001
8000
–––
–––
–––
.
.
.
.
.
.
.
.
.
.
.
.
7FFFFFFF
7FFFFFFE
.
.
.
00008000
00007FFF
00007FFE
.
.
.
00000002
00000001
00000000
FFFFFFFF
FFFFFFFE
.
.
.
FFFF8001
FFFF8000
FFFF7FFF
.
.
.
80000001
80000000
Converting Decimal to
Signed Binary
Positive signed binary data is identical to unsigned binary data (up to 32,767)
and can be converted using BIN(100). The following procedure converts negative decimal values between –32,768 and –1 to signed binary. In this example
–12345 is converted to CFC7.
1. First take the absolute value (12345) and convert to unsigned binary:
Bit number
Contents 0011000000111001
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
2. Next take the complement:
Bit number
Contents 1100111111000110
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
3. Finally add one:
Bit number
Contents 1100111111000111
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
30
Reverse the procedure to convert negative signed binary data to decimal.
IR Area Section 3-3
3-3 IR (Internal Relay) Area
The IR area is used both as data to control I/O points, and as work bits to manipulate and store data internally. It is accessible both by bit and by word. In the
C200HS PC, the IR area is comprised of words 000 to 235 and 298 to 511.
Words in the IR area that are used to control I/O points are called I/O words. Bits
in I/O words are called I/O bits. Bits in the IR area which are not assigned as I/O
bits can be used as work bits. IR area work bits are reset when power is interrupted or PC operation is stopped.
I/O Words If a Unit brings inputs into the PC, the bit assigned to it is an input bit; if the Unit
sends an output from the PC, the bit is an output bit. To turn on an output, the
output bit assigned to it must be turned ON. When an input turns on, the input bit
assigned to it also turns ON. These facts can be used in the program to access
input status and control output status through I/O bits.
Input Bit Usage Input bits can be used to directly input external signals to the PC and can be used
in any order in programming. Each input bit can also be used in as many instructions as required to achieve effective and proper control. They cannot be used in
instructions that control bit status, e.g., the OUTPUT, DIFFERENTIATION UP,
and KEEP instructions.
Output Bit Usage Output bits are used to output program execution results and can be used in any
order in programming. Because outputs are refreshed only once during each
cycle (i.e., once each time the program is executed), any output bit can be used
in only one instruction that controls its status, including OUT, KEEP(11),
DIFU(13), DIFD(14) and SFT(10). If an output bit is used in more than one such
instruction, only the status determined by the last instruction will actually be output from the PC.
5-15-1 Shift Register – SFT(10)
See
‘bit-control’ instructions.
Word Allocation for Racks I/O words are allocated to the CPU Rack and Expansion I/O Racks by slot posi-
tion. One I/O word is allocated to each slot, as shown in the following table. Since
each slot is allocated only one I/O word, a 3-slot rack uses only the first 3 words,
a 5-slot rack uses only the first 5 words, and an 8-slot rack uses only the first 8
words. Words that are allocated to unused or nonexistent slots are available as
work words.
Left side of rack Right side of a 10-slot rack →
←
Rack Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8 Slot 9 Slot 10
CPU IR 000 IR 001 IR 002 IR 003 IR 004 IR 005 IR 006 IR 007 IR 008 IR 009
1st Expansion IR 010 IR 011 IR 012 IR 013 IR 014 IR 015 IR 016 IR 017 IR 018 IR 019
2nd Expansion IR 020 IR 021 IR 022 IR 023 IR 024 IR 025 IR 026 IR 027 IR 028 IR 029
for an example that uses an output bit in two
Unused Words Any words allocated to a Unit that does not use them can be used in program-
ming as work words and bits. Units that do not used the words assigned to the
slot they are mounted to include Link Units (e.g., Host Link Units, PC Link Units,
SYSMAC NET Link Units, etc.), Remote I/O Master Units, Special I/O Units,
Group-2 High-density I/O Units, Group-2 B7A Interface Units, and Auxiliary
Power Supply Units.
31
IR Area Section 3-3
Allocation for Special I/O
Units and Slave Racks
Up to ten Special I/O Units may be mounted in any slot of the CPU Rack or Expansion I/O Racks. Up to five Slave Racks may be used, whether one or two
Masters are used. IR area words are allocated to Special I/O Units and Slave
Racks by the unit number on the Unit, as shown in the following tables.
Special I/O Units Slave Racks
Unit number IR address Unit number IR address
0 100 to 109 0 050 to 059
1 110 to 119 1 060 to 069
2 120 to 129 2 070 to 079
3 130 to 139 3 080 to 089
4 140 to 149 4 090 to 099
5 150 to 159
6 160 to 169
7 170 to 179
8 180 to 189
9 190 to 199
The C500-RT001/002-(P)V1 Remote I/O Slave Rack may be used, but it requires 20 I/O words, not 10, and therefore occupies the I/O words allocated to 2
C200H Slave Racks, both the words allocated to the unit number set on the rack
and the words allocated to the following unit number. When using a C200HS
CPU, do not set the unit number on a C500 Slave Rack to 4, because there is no
unit number 5. I/O words are allocated only to installed Units, from left to right,
and not to slots as in the C200HS system.
Allocation for Optical I/O
Units and I/O Terminals
I/O words between IR 200 and IR 231 are allocated to Optical I/O Units and I/O
Terminals by unit number. The I/O word allocated to each Unit is IR 200+n,
where n is the unit number set on the Unit.
Allocation for Remote I/O
Master and Link Units
Remote Master I/O Units and Host Link Units do not use I/O words, and the PC
Link Units use the LR area, so words allocated to the slots in which these Units
are mounted are available as work words.
Bit Allocation for I/O Units An I/O Unit may require anywhere from 8 to 16 bits, depending on the model.
With most I/O Units, any bits not used for input or output are available as work
bits. T ransistor Output Units C200H-OD213 and C200H-OD411, as well as Triac
Output Unit C200H-OA221, however , uses bit 08 for the Blown Fuse Flag. Transistor Output Unit C200H-OD214 uses bits 08 to 1 1 for the Alarm Flag. Bits 08 to
15 of any word allocated to these Units, therefore, cannot be used as work bits.
Bit Allocation for Interrupt
Input Units
The Interrupt Input Unit uses the 8 bits of the first I/O word allocated to its slot in
the CPU Rack. (An Interrupt Input Unit will operate as a normal Input Unit when
installed in an Expansion I/O Rack.) The other 24 bits allocated to its slot in the
CPU Rack can be used as work bits.
32
SR Area Section 3-4
Allocation for Group-2
High-density I/O Units and
B7 Interface Units
Group-2 High-density I/O Units and B7A Interface Units are allocated words between IR 030 and IR 049 according to I/O number settings made on them and do
not use the words allocated to the slots in which they are mounted. For 32-point
Units, each Unit is allocated two words; for 64-point Units, each Unit is allocated
four words. The words allocated for each I/O number are in the following tables.
Any words or part of words not used for I/O can be used as work words or bits in
programming.
32-point Units 64-point Units
I/O number
0 IR 30 to IR 31 0 IR 30 to IR 33
1 IR 32 to IR 33 1 IR 32 to IR 35
2 IR 34 to IR 35 2 IR 34 to IR 37
3 IR 36 to IR 37 3 IR 36 to IR 39
4 IR 38 to IR 39 4 IR 38 to IR 41
5 IR 40 to IR 41 5 IR 40 to IR 43
6 IR 42 to IR 43 6 IR 42 to IR 45
7 IR 44 to IR 45 7 IR 44 to IR 47
8 IR 46 to IR 47 8 IR 46 to IR 49
9 IR 48 to IR 49 9 Cannot be used.
Words I/O number Words
When setting I/O numbers on the High-density I/O Units and B7A Interface
Units, be sure that the settings will not cause the same words to be allocated to
more than one Unit. For example, if I/O number 0 is allocated to a 64-point Unit,
I/O number 1 cannot be used for any Unit in the system.
Group-2 High-density I/O Units and B7A Interface Units are not considered Special I/O Units and do not affect the limit to the number of Special I/O Units allowed
in the System, regardless of the number used.
The words allocated to Group-2 High-density I/O Units correspond to the connectors on the Units as shown in the following table.
Unit Word Connector/row
32-point Units
64-point Units
Note Group-2 High-density I/O Units and B7A Interface Units cannot be mounted to
Slave Racks.
3-4 SR (Special Relay) Area
The SR area contains flags and control bits used for monitoring PC operation,
accessing clock pulses, and signalling errors. SR area word addresses range
from 236 through 511; bit addresses, from 23600 through 51115.
The following table lists the functions of SR area flags and control bits. Most of
these bits are described in more detail following the table. Descriptions are in
order by bit number except that Link System bits are grouped together.
Unless otherwise stated, flags are OFF until the specified condition arises, when
they are turned ON. Restart bits are usually OFF, but when the user turns one
ON then OFF , the specified Link Unit will be restarted. Other control bits are OFF
until set by the user.
First Row A
Second Row B
First CN1, row A
Second CN1, row B
Third CN2, row A
Fourth CN2, row B
33
Writeable
SR Area Section 3-4
Note all SR words and bits are writeable by the user . Be sure to check the function of a bit or word before attempting to use it in programming.
Word(s) Bit(s) Function
236 00 to 07 Node loop status output area for operating level 0 of SYSMAC NET Link System
08 to 15 Node loop status output area for operating level 1 of SYSMAC NET Link System
237 00 to 07 Completion code output area for operating level 0 following execution of
SEND(90)/RECV(98) SYSMAC LINK/SYSMAC NET Link System
08 to 15 Completion code output area for operating level 1 following execution of
SEND(90)/RECV(98) SYSMAC LINK/SYSMAC NET Link System
238 and 241 00 to 15 Data link status output area for operating level 0 of SYSMAC LINK or SYSMAC NET Link
System
242 and 245 00 to 15 Data link status output area for operating level 1 of SYSMAC LINK or SYSMAC NET Link
System
246 00 to 15 Reserved by system
247 and 248 00 to 07 PC Link Unit Run Flags for Units 16 through 31 or data link status for operating level 1
08 to 15 PC Link Unit Error Flags for Units 16 through 31 or data link status for operating level 1
249 and 250 00 to 07 PC Link Unit Run Flags for Units 00 through 15 or data link status for operating level 0
08 to 15 PC Link Unit Error Flags for Units 00 through 15 or data link status for operating level 0
251
Writeable
252 00 SEND(90)/RECV(98) Error Flag for operating level 0 of SYSMAC LINK or SYSMAC NET
253 00 to 07 FAL number output area (see error information provided elsewhere)
00 Remote I/O Error Read Bit
01 and 02 Not used
03 Remote I/O Error Flag
04 to 06 Unit number of Remote I/O Unit, Optical I/O Unit, or I/O Terminal with error
07 Not used
08 to 15 Word allocated to Remote I/O Unit, Optical I/O Unit, or I/O Terminal with error (BCD)
Link System
01 SEND(90)/RECV(98) Enable Flag for operating level 0 of SYSMAC LINK or SYSMAC NET
Link System
02 Operating Level 0 Data Link Operating Flag
03 SEND(90)/RECV(98) Error Flag for operating level 1 of SYSMAC LINK or SYSMAC NET
Link System
04 SEND(90)/RECV(98) Enable Flag for operating level 1 of SYSMAC LINK or SYSMAC NET
Link System
05 Operating Level 1 Data Link Operating Flag
06 Rack-mounting Host Link Unit Level 1 Communications Error Flag
07 Rack-mounting Host Link Unit Level 1 Restart Bit
08 Peripheral Port Restart Bit
09 RS-232C Port Restart Bit
10 PC Setup Clear Bit
11 Forced Status Hold Bit
12 Data Retention Control Bit
13 Rack-mounting Host Link Unit Level 0 Restart Bit
14 Not used.
15 Output OFF Bit
08 Low Battery Flag
09 Cycle Time Error Flag
10 I/O Verification Error Flag
11 Rack-mounting Host Link Unit Level 0 Communications Error Flag
12 Remote I/O Error Flag
13 Always ON Flag
14 Always OFF Flag
15 First Cycle Flag
34
SR Area Section 3-4
Word(s) FunctionBit(s)
254 00 1-minute clock pulse bit
01 0.02-second clock pulse bit
02 and 03 Reserved for function expansion. Do not use.
04 Overflow Flag (for signed binary calculations)
05 Underflow Flag (for signed binary calculations)
06 Differential Monitor End Flag
07 Step Flag
08 MTR Execution Flag
09 7SEG Execution Flag
10 DSW Execution Flag
11 Interrupt Input Unit Error Flag
12 Reserved by system
13 Interrupt Programming Error Flag
14 Group-2 Error Flag
15 Special Unit Error Flag (includes Special I/O, PC Link, Host Link, Remote I/O Master Units)
255 00 0.1-second clock pulse bit
01 0.2-second clock pulse bit
02 1.0-second clock pulse bit
03 Instruction Execution Error (ER) Flag
04 Carry (CY) Flag
05 Greater Than (GR) Flag
06 Equals (EQ) Flag
07 Less Than (LE) Flag
08 to 15 Reserved by system (used for TR bits)
256 to 261 00 to 15 Reserved by system
262 00 to 15 Longest interrupt subroutine (action) execution time (0.1 ms)
263 00 to 15 Number of interrupt subroutine (action) with longest execution time.
(8000 to 8512) 8000 to 8007, 8099
Bit 15: Interrupt Flag
264
265 00 to 15 RS-232C Port Reception Counter in General I/O Mode
266 00 to 15 Peripheral Reception Counter in General I/O Mode (BCD)
00 to 03 RS-232C Port Error Code
0: No error
2: Framing error
04 RS-232C Port Communications Error
05 RS-232C Port Send Ready Flag
06 RS-232C Port Reception Completed Flag
07 RS-232C Port Reception Overflow Flag
08 to 11 Peripheral Port Error Code in General I/O Mode
0: No error
2: Framing error
F: When in Peripheral Bus Mode
12 Peripheral Port Communications Error in General I/O Mode
13 Peripheral Port Send Ready Flag in General I/O Mode
14 Peripheral Port Reception Completed Flag in General I/O Mode
15 Peripheral Port Reception Overflow Flag in General I/O Mode
1: Parity error
3: Overrun error
1: Parity error
3: Overrun error
35
y
An error will be produced if turned ON in any other
occu g e e o y Casse e o beou u o
SR Area Section 3-4
Word(s) FunctionBit(s)
267
268 00 to 15 Reserved by system (not accessible by user)
269
270
271
272
00 to 04 Reserved by system (not accessible by user)
05 Host Link Level 0 Send Ready Flag
06 to 12 Reserved by system (not accessible by user)
13 Host Link Level 1 Send Ready Flag
14 and 15 Reserved by system (not accessible by user)
00 to 07 Memory Cassette Contents 00: Nothing; 01: UM; 02: IOM (03: HIS)
08 to 10 Memory Cassette Capacity
0: 0 KW (no cassette); 3: 16 KW
11 to 13 Reserved by system (not accessible by user)
14 EEPROM Memory Cassette Protected or EPROM Memory Cassette Mounted Flag
15 Memory Cassette Flag
00 Save UM to Cassette Bit
01 Load UM from Cassette Bit
02 Compare UM to Cassette Bit
03 Comparison Results
0: Contents identical; 1: Contents differ or comparison not possible
04 to 10 Reserved by system (not accessible by user)
11 Transfer Error Flag:
Transferring SYSMAC NET
data link table on UM during
active data link.
12 Transfer Error Flag: Not
PROGRAM mode
13 Transfer Error Flag: Read Only
14 Transfer Error Flag: Insufficient
Capacity or No UM
15 Transfer Error Flag: Board
Checksum Error
00 to 07 Ladder program size stored in Memory Cassette
Ladder-only File: 04: 4 KW; 08: 8 KW; 12: 12 KW; ... (64: 64 KW)
00: No ladder program or no file
Data updated at data transfer from CPU at startup. The file must begin in segment 0.
08 to 15 Ladder program size and type in CPU (Specifications are the same as for bits 00 to 07.)
Data updated when indexes generated. Default value (after clearing memory) is 16.
00 to 10 Reserved by system (not accessible by user)
11 Memory Error Flag: PC Setup Checksum Error
12 Memory Error Flag: Ladder Checksum Error
13 Memory Error Flag: Instruction Change Vector Area Checksum Error
14 Memory Error Flag: Memory Cassette Online Disconnection
15 Memory Error Flag: Autoboot Error
Data transferred to Memory Cassette when Bit is turned
ON in PROGRAM mode. Bit will automatically turn OFF.
p
mode.
Data will not be transferred from UM to the Memory
Cassette if an error occurs (except for Board Checksum
Error). Detailed information on checksum errors
occurring in the Memory Cassette will not be output to
SR 272 because the information is not needed. Repeat
the transmission if SR 27015 is ON.
36
y
ON in PROGRAM mode. Bit will automatically turn OFF
(y)
ggg
SR Area Section 3-4
Word(s) FunctionBit(s)
273
274 00 Special I/O Unit #0 Restart Flag
275
276
277 to 279 00 to 15 Used for keyboard mapping. See page 368.
280 to 289 00 to 15 Reserved by system (not accessible by user)
290 to 293 00 to 15 Macro Area inputs.
294 to 297 00 to 15 Macro Area outputs.
298 to 299 00 to 15 Reserved by system (not accessible by user)
00 Save IOM to Cassette Bit
01 Load IOM from Cassette Bit
02 to 11 Reserved by system (not accessible by user)
12 Transfer Error Flag: Not
PROGRAM mode
13 Transfer Error Flag: Read Only
14 Transfer Error Flag: Insufficient
Capacity or No IOM
15 Transfer Error Flag: Checksum
Error
01 Special I/O Unit #1 Restart Flag
02 Special I/O Unit #2 Restart Flag
03 Special I/O Unit #3 Restart Flag
04 Special I/O Unit #4 Restart Flag
05 Special I/O Unit #5 Restart Flag
06 Special I/O Unit #6 Restart Flag
07 Special I/O Unit #7 Restart Flag
08 Special I/O Unit #8 Restart Flag
09 Special I/O Unit #9 Restart Flag
10 to 15 Reserved by system (not accessible by user)
00 PC Setup Startup Error (DM 6600 to DM 6614)
01 PC Setup RUN Error (DM 6615 to DM 6644)
02 PC Setup Communications/Error Setting/Misc. Error (DM 6645 to DM 6655)
03 to 15 Reserved by system (not accessible by user)
00 to 07 Minutes (00 to 59)
08 to 15 Hours (00 to 23)
Data transferred to Memory Cassette when Bit is turned
ON in PROGRAM mode. Bit will automaticall
An error will be produced if turned ON in any other
mode.
Data will not be transferred from IOM to the Memory
Cassette if an error occurs (except for Read Only Error).
These flags will turn ON during restart processing.
These flags will not turn ON for Units on Slave Racks.
Used for time increments.
turn OFF.
.
3-4-1 SYSMAC NET/SYSMAC LINK System
Loop Status SR 236 provides the local node loop status for SYSMAC NET Systems, as
shown below.
––– Bit in SR 236
Level 0 07 06 05 04 03 02 01 00
Level 1 15 14 13 12 11 10 09 08
Status/
Meaning
Completion Codes SR 23700 to SR23707 provide the SEND/RECV completion code for operating
1 1 Central Power Supply
0: Connected
1: Not connected
level 0 and SR 23708 to SR 23215 provide the SEND/RECV completion code for
operating level 1. The completion codes are as given in the following tables.
1 Loop Status
11: Normal loop
10: Downstream backloop
01: Upstream backloop
00: Loop error
Reception Status
0: Reception enabled
1: Reception disabled
1
37
pg
pg
SR Area Section 3-4
SYSMAC LINK
Code Item Meaning
00 Normal end Processing ended normally.
01 Parameter error Parameters for network communication instruction is
not within acceptable ranges.
02 Unable to send Unit reset during command processing or local node
in not in network.
03 Destination not in
network
04 Busy error The destination node is processing data and cannot
05 Response timeout The response monitoring time was exceeded.
06 Response error There was an error in the response received from
07 Communications
controller error
08 Setting error There is an error in the node address settings.
09 PC error An error occurred in the CPU of the destination
Destination node is not in network.
receive the command.
the destination node.
An error occurred in the communications controller.
node.
SYSMAC NET
Code Item Meaning
00 Normal end Processing ended normally.
01 Parameter error Parameters for network communication instruction is
not within acceptable ranges.
02 Routing error There is a mistake in the routing tables for
connection to a remote network.
03 Busy error The destination node is processing data and cannot
receive the command.
04 Send error (token
lost)
05 Loop error An error occurred in the communications loop.
06 No response The destination node does not exist or the response
07 Response error There is an error in the response format.
The token was not received from the Line Server.
monitoring time was exceeded.
Data Link Status SR 238 to SR 245 contain the data link status for SYSMAC LINK/SYSMAC NET
Systems. The data structure depends on the system used to create the data link.
SYSMAC LINK
Operating
level 0
SR 238 SR 242 Node 4 Node 3 Node 2 Node 1
SR 239 SR 243 Node 8 Node 7 Node 6 Node 5
SR 240 SR 244 Node 12 Node 11 Node 10 Node 9
SR 241 SR 245 Node 16 Node 15 Node 14 Node 13
Operating
level 1
12 to 15 11 to 08 04 to 07 00 to 03
Bit
38
Leftmost bit Rightmost bit
1: PC RUN status
1: PC CPU error 1: Communica-
tions error
1: Data link
operating
pg
pg
SR Area Section 3-4
SYSMAC NET
Operating
level 0
SR 238 SR 242 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1
SR 239 SR 243 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9
SR 240 SR 244 24 23 22 21 20 19 18 17 24 23 22 21 20 19 18 17
SR 241 SR 245 32 31 30 29 28 27 26 25 32 31 30 29 28 27 26 25
Operating
level 1
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
1: PC CPU error 1: PC RUN status
Bit (Node numbers below)
3-4-2 Remote I/O Systems
SR 25312 turns ON to indicate an error has occurred in Remote I/O Systems.
The ALM/ERR indicator will flash, but PC operation will continue. SR 251, as
well as AR 0014 and AR 0015, contain information on the source and type of
error. The function of each bit is described below. Refer to
mote I/O System Manuals
for details.
Optical
Bit 00 – Error Check Bit If there are errors in more than one Remote I/O Unit, word 251 will contain error
information for only the first one. Data for the remaining Units will be stored in
memory and can be accessed by turning the Error Check bit ON and OFF. Be
sure to record data for the first error, which will be cleared when data for the next
error is displayed.
and
Wired Re-
Bits 01 and 02 Not used.
Bit 03 Remote I/O Error Flag: Bit 03 turns ON when an error has occurred in a Remote
I/O Unit.
0
Bits 04 to 15 The content of bits 04 to 06 is a 3-digit binary number (04: 2
the content of bits 08 to 15 is a 2-digit BCD number (08 to 11: 10
, 05: 21, 06: 22) and
0
, 12 to 15: 101).
If the content of bits 12 through 15 is B, an error has occurred in a Remote I/O
Master or Slave Unit, and the content of bits 08 through 11 will indicate the unit
number, either 0 or 1, of the Master involved. In this case, bits 04 to 06 contain
the unit number of the Slave Rack involved.
If the content of bits 12 through 15 is a number from 0 to 31, an error has occurred in a n Optical I/O Unit or I/O Terminal. The number is the unit number of the
Optical I/O Unit or I/O Terminal involved, and bit 04 will be ON if the Unit is assigned leftmost word bits (08 through 15), and OFF if it is assigned rightmost
word bits (00 through 07).
3-4-3 Link System Flags and Control Bits
Use of the following SR bits depends on the configuration of any Link Systems to
which your PC belongs. These flags and control bits are used when Link Units,
such as PC Link Units, Remote I/O Units, or Host Link Units, are mounted to the
PC Racks or to the CPU. For additional information, consult the System Manual
for the particular Units involved.
The following bits can be employed as work bits when the PC does not belong to
the Link System associated with them.
39
SR Area Section 3-4
Host Link Systems
Both Error flags and Restart bits are provided for Host Link Systems. Error flags
turn ON to indicate errors in Host Link Units. Restart bits are turned ON and then
OFF to restart a Host Link Unit. SR bits used with Host Link Systems are summarized in the following table. Rack-mounting Host Link Unit Restart bits are
not effective for the Multilevel Rack-mounting Host Link Units. Refer to the
Host Link System Manual
Bit Flag
25206 Rack-mounting Host Link Unit Level 1 Error Flag
25207 Rack-mounting Host Link Unit Level 1 Restart Bit
25213 Rack-mounting Host Link Unit Level 0 Restart Bit
25311 Rack-mounting Host Link Unit Level 0 Error Flag
for details.
PC Link Systems
PC Link Unit Error and Run
Flags
Single-level PC Link
Systems
When the PC belongs to a PC Link System, words 247 through 250 are used to
monitor the operating status of all PC Link Units connected to the PC Link System. This includes a maximum of 32 PC Link Units. If the PC is in a Multilevel PC
Link System, half of the PC Link Units will be in a PC Link Subsystem in operating
level 0; the other half, in a Subsystem in operating level 1. The actual bit assignments depend on whether the PC is in a Single-level PC Link System or a Multilevel PC Link System. Refer to the
PC Link System Manual
for details. Error and
Run Flag bit assignments are described below.
Bits 00 through 07 of each word are the Run flags, which are ON when the PC
Link Unit is in RUN mode. Bits 08 through 15 are the Error flags, which are ON
when an error has occurred in the PC Link Unit. The following table shows bit
assignments for Single-level and Multi-level PC Link Systems.
Flag type Bit no. SR 247 SR 248 SR 249 SR 250
Run flags 00 Unit #24 Unit #16 Unit #8 Unit #0
01 Unit #25 Unit #17 Unit #9 Unit #1
02 Unit #26 Unit #18 Unit #10 Unit #2
03 Unit #27 Unit #19 Unit #11 Unit #3
04 Unit #28 Unit #20 Unit #12 Unit #4
05 Unit #29 Unit #21 Unit #13 Unit #5
06 Unit #30 Unit #22 Unit #14 Unit #6
07 Unit #31 Unit #23 Unit #15 Unit #7
Error flags 08 Unit #24 Unit #16 Unit #8 Unit #0
09 Unit #25 Unit #17 Unit #9 Unit #1
10 Unit #26 Unit #18 Unit #10 Unit #2
11 Unit #27 Unit #19 Unit #11 Unit #3
12 Unit #28 Unit #20 Unit #12 Unit #4
13 Unit #29 Unit #21 Unit #13 Unit #5
14 Unit #30 Unit #22 Unit #14 Unit #6
15 Unit #31 Unit #23 Unit #15 Unit #7
40
SR Area Section 3-4
Multilevel PC Link Systems
Flag type Bit no. SR 247 SR 248 SR 249 SR 250
Run flags 00 Unit #8,
level 1
01 Unit #9,
level 1
02 Unit #10,
level 1
03 Unit #11,
level 1
04 Unit #12,
level 1
05 Unit #13,
level 1
06 Unit #14,
level 1
07 Unit #15,
level 1
Error flags 08 Unit #8,
level 1
09 Unit #9,
level 1
10 Unit #10,
level 1
11 Unit #11,
level 1
12 Unit #12,
level 1
13 Unit #13,
level 1
14 Unit #14,
level 1
15 Unit #15,
level 1
Unit #0,
level 1
Unit #1,
level 1
Unit #2,
level 1
Unit #3,
level 1
Unit #4,
level 1
Unit #5,
level 1
Unit #6,
level 1
Unit #7,
level 1
Unit #0,
level 1
Unit #1,
level 1
Unit #2,
level 1
Unit #3,
level 1
Unit #4,
level 1
Unit #5,
level 1
Unit #6,
level 1
Unit #7,
level 1
Unit #8,
level 0
Unit #9,
level 0
Unit #10,
level 0
Unit #1 1,
level 0
Unit #12,
level 0
Unit #13,
level 0
Unit #14,
level 0
Unit #15,
level 0
Unit #8,
level 0
Unit #9,
level 0
Unit #10,
level 0
Unit #1 1,
level 0
Unit #12,
level 0
Unit #13,
level 0
Unit #14,
level 0
Unit #15,
level 0
Unit #0,
level 0
Unit #1,
level 0
Unit #2,
level 0
Unit #3,
level 0
Unit #4,
level 0
Unit #5,
level 0
Unit #6,
level 0
Unit #7,
level 0
Unit #0,
level 0
Unit #1,
level 0
Unit #2,
level 0
Unit #3,
level 0
Unit #4,
level 0
Unit #5,
level 0
Unit #6,
level 0
Unit #7,
level 0
Application Example If the PC is in a Multilevel PC Link System and the content of word 248 is 02FF,
then PC Link Units #0 through #7 of in the PC Link Subsystem assigned operating level 1 would be in RUN mode, and PC Link Unit #1 in the same Subsystem
would have an error. The hexadecimal digits and corresponding binary bits of
word 248 would be as shown below.
Bit no. 15 00. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Binary 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1
Hex 0 2 F F
3-4-4 Forced Status Hold Bit
SR 25211 determines whether or not the status of bits that have been force-set
or force-reset is maintained when switching between PROGRAM and MONITOR mode to start or stop operation. If SR 25211 is ON, bit status will be maintained; if SR 25211 is OFF, all bits will return to default status when operation is
started or stopped. The Forced Status Hold Bit is only effective when enabled in
the PC Setup.
The status of SR 25211 in not affected by a power interruption unless the I/O
table is registered; in that case, SR 25211 will go OFF.
SR 25211 is not effective when switching to RUN mode.
SR 25211 should be manipulated from a Peripheral Device, e.g., a Program-
ming Console or LSS.
41
SR Area Section 3-4
Maintaining Status during
Startup
The status of SR 25211 and thus the status of force-set and force-reset bits can
be maintained when power is turned off and on by enabling the Forced Status
Hold Bit in the PC Setup. If the Forced Status Hold Bit is enabled, the status of
SR 25211 will be preserved when power is turned of f and on. If this is done and
SR 25211 is ON, then the status of force-set and force-reset bits will also be preserved, as shown in the following table.
ON ON Status maintained
OFF OFF Reset
Note Refer to
3-4-5 I/O Status Hold Bit
SR 25212 determines whether or not the status of IR and LR area bits is maintained when operation is started or stopped, when operation begins by switching
from PROGRAM mode to MONITOR or RUN modes. If SR 25212 is ON, bit status will be maintained; if SR 25212 is OFF, all IR and LR area bits will be reset.
The I/O Status Hold Bit is effective only if enabled in the PC Setup.
The status of SR 25212 in not affected by a power interruption unless the I/O
table is registered; in that case, SR 25212 will go OFF.
SR 25212 should be manipulated from a Peripheral Device, e.g., a Programming Console or LSS.
Maintaining Status during
Startup
The status of SR 25212 and thus the status of IR and LR area bits can be maintained when power is turned off and on by enabling the I/O Status Hold Bit in the
PC Setup. If the I/O Status Hold Bit is enabled, the status of SR 25212 will be
preserved when power is turned off and on. If this is done and SR 25212 is ON,
then the status of IR and LR area bits will also be preserved, as shown in the
following table.
ON ON Status maintained
OFF OFF Reset
Status before shutdown Status at next startup
SR 25211 SR 25211 Force-set/reset bits
3-6-4 PC Setup
Status before shutdown Status at next startup
SR 25212 SR 25212 IR and LR bits
for details on enabling the Forced Status Hold Bit.
Note Refer to
3-6-4 PC Setup
3-4-6 Output OFF Bit
SR bit 25215 is turned ON to turn OFF all outputs from the PC. The OUT INHIBIT
indicator on the front panel of the CPU will light. When the Output OFF Bit is OFF,
all output bits will be refreshed in the usual way.
The status of the Output OFF Bit is maintained for power interruptions or when
PC operation is stopped, unless the I/O table has been registered, or the I/O
table has been registered and either the Forced Status Hold Bit or the I/O Status
Hold Bit has not been enabled in the PC Setup.
3-4-7 FAL (Failure Alarm) Area
A 2-digit BCD FAL code is output to bits 25300 to 25307 when the FAL or FALS
instruction is executed. These codes are user defined for use in error diagnosis,
although the PC also outputs FAL codes to these bits, such as one caused by
battery voltage drop.
This area can be reset by executing the F AL instruction with an operand of 00 or
by performing a Failure Read Operation from the Programming Console.
3-4-8 Low Battery Flag
SR bit 25308 turns ON if the voltage of the CPU’s backup battery drops. The
ALM/ERR indicator on the front of the CPU will also flash.
42
for details on enabling the I/O Status Hold Bit.
SR Area Section 3-4
This bit can be programmed to activate an external warning for a low battery voltage.
The operation of the battery alarm can be disabled in the PC Setup if desired.
Refer to
3-6-4 PC Setup
for details.
3-4-9 Cycle Time Error Flag
SR bit 25309 turns ON if the cycle time exceeds 100 ms. The ALM/ERR indicator
on the front of the CPU will also flash. Program execution will not stop, however,
unless the maximum time limit set for the watchdog timer is exceeded. Timing
may become inaccurate after the cycle time exceeds 100 ms.
3-4-10I/O Verification Error Flag
SR bit 25310 turns ON when the Units mounted in the system disagree with the
I/O table registered in the CPU. The ALM/ERR indicator on the front of the CPU
will also flash, but PC operation will continue.
To ensure proper operation, PC operation should be stopped, Units checked,
and the I/O table corrected whenever this flag goes ON.
3-4-11 First Cycle Flag
SR bit 25315 turns ON when PC operation begins and then turns OFF after one
cycle of the program. The First Cycle Flag is useful in initializing counter values
and other operations. An example of this is provided in
Instructions
.
5-14 Timer and Counter
3-4-12Clock Pulse Bits
Five clock pulses are available to control program timing. Each clock pulse bit is
ON for the first half of the rated pulse time, then OFF for the second half. In other
words, each clock pulse has a duty factor of 50%.
These clock pulse bits are often used with counter instructions to create timers.
Refer to
5-14 Timer and Counter Instructions
Pulse width 1 min 0.02 s 0.1 s 0.2 s 1.0 s
Bit 25400 25401 25500 25501 25502
Bit 25400
1-min clock pulse
30 s 30 s
1 min.
Bit 25500
0.1-s clock pulse
.05 s .05 s
0.1 s
for an example of this.
Bit 25401
0.02-s clock pulse
.01 s .01 s
.02 s
Bit 25501
0.2-s clock pulse
0.1 s 0.1 s
0.2 s
Bit 25502
1.0-s clock pulse
0.5 s 0.5 s
1.0 s
Caution:
Because the 0.1-second and
0.02-second clock pulse bits have
ON times of 50 and 10 ms, respectively, the CPU may not be able to
accurately read the pulses if program execution time is too long.
43
SR Area Section 3-4
3-4-13Step Flag
SR bit 25407 turns ON for one cycle when step execution is started with the
STEP(08) instruction.
3-4-14Group-2 Error Flag
SR bit 25414 turns ON for any of the following errors for Group-2 High-density
I/O Units and B7A Interface Units: the same I/O number set twice, the same
words allocated to more than one Unit, refresh errors. If one of these errors occurs, the Unit will stop operation and the ALARM indicator will flash, but the overall PC will continue operation.
When the Group-2 Error Flag is ON, the number of the Unit with the error will be
provided in AR 0205 to AR 0214. If the Unit cannot be started properly even
though the I/O number is set correctly and the Unit is installed properly, a fuse
may be blown or the Unit may contain a hardware failure. If this should occur,
replace the Unit with a spare and try to start the system again.
There is also an error flag for High-density I/O Units and B7A Interface Units in
the AR area, AR 0215.
3-4-15Special Unit Error Flag
SR bit 25415 turns ON to indicate errors in the following Units: Special I/O, PC
Link, Host Link, and Remote I/O Master Units. SR bit 25415 will turn ON for any
of the following errors.
• When more than one Special I/O Unit is set to the same unit number.
• When an error occurs in refreshing data between a Special I/O Unit and the
PC’s CPU.
• When an error occurs between a Host Link Unit and the PC’s CPU.
• When an error occurs in a Remote I/O Master Unit.
Although the PC will continue operation if SR 25415 turns ON, the Units causing
the error will stop operation and the ALM indicator will flash. Check the status of
AR 0000 to AR 0015 to obtain the unit numbers of the Units for which the error
occurred and investigate the cause of the error.
Unit operation can be restarted by using the Restart Bits (AR 0100 to AR 0115,
SR 25207, and SR 25213), but will not be effective if the same unit number is set
for more than one Special I/O Unit. Turn off the power supply, correct the unit
number settings, and turn of the power supply again to restart.
SR 25415 will not turn OFF even if AR 0100 to AR 0115 (Restart Bits) are turned
ON. It can be turned OFF by reading errors from a Programming Device or by
executing FAL(06) 00 from the ladder program.
3-4-16Instruction Execution Error Flag, ER
SR bit 25503 turns ON if an attempt is made to execute an instruction with incorrect operand data. Common causes of an instruction error are non-BCD operand data when BCD data is required, or an indirectly addressed DM word that is
non-existent. When the ER Flag is ON, the current instruction will not be
executed.
3-4-17Arithmetic Flags
The following flags are used in data shifting, arithmetic calculation, and comparison instructions. They are generally referred to only by their two-letter abbreviations.
!
Caution These flags are all reset when the END(01) instruction is executed, and therefore cannot be moni-
tored from a programming device.
Refer to
5-20 Binary Calculations
44
5-15 Data Shifting, 5-17 Data Comparison, 5-19 BCD Calculations
for details.
, and
SR Area Section 3-4
Overflow Flag, OF SR bit 25404 turns ON when the result of a binary addition or subtraction ex-
ceeds 7FFF or 7FFFFFFF.
Underflow Flag, UF SR bit 25405 turns ON when the result of a signed binary addition or subtraction
exceeds 8000 or 80000000.
Carry Flag, CY SR bit 25504 turns ON when there is a carry in the result of an arithmetic opera-
tion or when a rotate or shift instruction moves a “1” into CY. The content of CY is
also used in some arithmetic operations, e.g., it is added or subtracted along
with other operands. This flag can be set and cleared from the program using the
Set Carry and Clear Carry instructions.
Greater Than Flag, GR SR bit 25505 turns ON when the result of a comparison shows the first of two
operands to be greater than the second.
Equal Flag, EQ SR bit 25506 turns ON when the result of a comparison shows two operands to
be equal or when the result of an arithmetic operation is zero.
Less Than Flag, LE SR bit 25507 turns ON when the result of a comparison shows the first of two
operands to be less than the second.
Note The four arithmetic flags are turned OFF when END(01) is executed.
3-4-18Interrupt Subroutine Areas
The following areas are used in subroutine interrupt processing.
Interrupt Subroutine
Maximum Processing Time
Area
Maximum Processing Time
Interrupt Subroutine
Number Area
SR bits 26200 to 26215 are used to set the maximum processing time of the interrupt subroutine. Processing times are determined to within 0.1 ms increments.
SR bits 26300 to 26315 contain the maximum processing time interrupt subroutine number. Bit 15 will be ON if there is an interruption.
3-4-19RS-232C Port Communications Areas
RS-232C Port Error Code SR bits 26400 to 26403 set when there is a RS-232C port error.
Setting Error type
0 No error
1 Parity error
2 Framing error
3 Overrun error
RS-232C Port
Communication Error Bit
RS-232C Port Send Ready
Flag
RS-232C Port Reception
Completed Flag
SR bit 26404 turns ON when there is a RS-232C port communication error.
SR bit 26405 turns ON when the C200HS is ready to transmit data.
SR bit 26406 turns ON when the C200HS has completed reading data from a
RS-232C device.
RS-232C Port Reception
Overflow Flag
RS-232C Reception Counter
Host Link Level 0 Send
Ready Flag
Host Link Level 1 Send
Ready Flag
SR bit 26407 turns ON when data overflow occurs following the reception of
data.
SR areas 26500 to 26515 contains the number of RS-232C port receptions in
General I/O Mode.
SR bit 26705 turns ON when the C200HS is ready to transmit to the Host Link
Unit.
SR bit 26713 turns ON when the C200HS is ready to transmit to the Host Link.
45
SR Area Section 3-4
3-4-20Peripheral Port Communications Areas
Peripheral Port Error Code SR bits 26408 to 26411 are set when there is a peripheral port error in the Gener-
al I/O Mode.
Setting Error type
0 No error
1 Parity error
2 Framing error
3 Overrun error
F Connected in Peripheral Mode
Peripheral Port
Communication Error Bit
Peripheral Port Send Ready
Flag
Peripheral Port Reception
Completed Flag
Peripheral Port Reception
Overflow Flag
Peripheral Reception
Counter
Host Link Level 0 Send
Ready Flag
Host Link Level 1 Receive
Ready Flag
SR bit 26412 turns ON when there is a peripheral port communication error (effective in General I/O Mode).
SR bit 26413 turns ON when the C200HS is ready to transmit data in General I/O
Mode.
SR bit 26414 turns ON when the C200HS has completed reading data from a
peripheral device. Effective in General I/O Mode.
SR bit 26415 turns ON when data overflow occurs following the reception of
data. Effective in General I/O Mode.
SR areas 26600 to 26615 contains the number of peripheral port receptions in
General I/O Mode (BCD).
SR bit 26705 turns ON when the C200HS is ready to transmit to the Host Link
Unit.
SR bit 26713 turns ON when the C200HS is ready to receive data from the Host
Link.
3-4-21Memory Cassette Areas
Memory Cassette Contents SR areas 26900 to 26907 indicate memory type contained on the Memory Cas-
sette.
Memory Type Code
Nothing 00
UM 01
IOM 02
Memory Cassette Capacity SR areas 26908 to 26910 indicate memory capacity of the Memory Cassette.
Capacity Code
0 KW (no board mounted) 0
16 KW 3
EEPROM/EPROM Memory
Cassette Mounted Flag
SR bit 26914 turns ON when EEPROM Memory Cassette is protected or
EPROM Memory Cassette is mounted.
Memory Cassette Flag SR bit 26915 turns ON when a Memory Cassette is mounted.
Save UM to Cassette Flag SR bit 27000 turns ON when UM data is read to a Memory Cassette in Program
Mode. Bit will automatically turn OFF. An error will be produced if turned ON in
any other mode.
Load UM from Cassette
Flag
SR bit 27001 turns ON when data is loaded into UM from a Memory Cassette in
Program Mode. Bit will automatically turn OFF. An error will be produced if
turned ON in any other mode.
46
SR Area Section 3-4
Collation (Between DM and
Memory Cassette)
SR bit 27002 turns ON when data is verified between DM and a Memory Cassette. SR bit 27003 turns OFF when the contents of the verification coincide and
turns ON when the contents of the verification do not coincide.
3-4-22Data Transfer Error Bits
Data will not be transferred from UM to the Memory Cassette if an error occurs
(except for Board Checksum Error). Detailed information on checksum errors
occurring in the Memory Cassette will not be output to SR 272 because the information is not needed. Repeat the transmission if SR 27015 is ON
Transfer Error Flag: Not
PROGRAM Mode
Transfer Error Flag: Read
Only
Transfer Error Flag:
Insufficient Capacity or No
UM
Transfer Error Flag: Board
Checksum Error
SR bit 27012 turns ON when the C200HS is not in Program Mode and data
transfer is attempted.
SR bit 27013 turns ON when the C200HS is in Read-only Mode and data transfer is attempted.
SR bit 27014 turns ON when data transfer is attempted and available UM is insufficient.
SR bit 27015 turns ON when data transfer is attempted and a Board Checksum
error occurs.
3-4-23Ladder Diagram Memory Areas
Memory Cassette Ladder
Diagram Size Area
SR areas 27100 to 27107 indicate the amount of ladder program stored in a
Memory Cassette.
Ladder-only File: 04: 4 KW; 08: 8 KW; 12: 12 KW; ... (64: 64 KW)
(Ladder File (Bit 07 will be ON): 84: 4 KW; 88: 8 KW; 92: 12 KW;
... (E4: 64 KW))
00: No ladder program or no file
Data updated at data transfer from CPU at startup. The file must begin in
segment 0.
CPU Ladder Diagram Size
and Type
SR areas 27108 to 27115 indicate the CPU’s ladder program size and type.
Specifications are the same as for bits 00 to 07.
3-4-24Memory Error Flags
Memory Error Flag: PC
Setup Error
Memory Error Flag: Ladder
Checksum Error
Memory Error Flag:
Instruction Change Error
Memory Error Flag: Memory
Cassette Disconnect Error
Memory Error Flag:
Autoboot Error
SR bit 27211 turns ON when a PC Setup Checksum error occurs.
SR bit 27212 turns ON when a Ladder Checksum error occurs.
SR bit 27213 turns ON when an instruction change vector area error occurs.
SR bit 27214 turns ON when a Memory Cassette is connected or disconnected
during operations.
SR bit 27215 turns ON when an autoboot error occurs.
3-4-25Data Save Flags
Data transferred to Memory Cassette when Bit is turned ON in PROGRAM
mode. Bit will automatically turn OFF. An error will be produced if turned ON in
any other mode.
47
AR Area Section 3-5
Save IOM to Cassette Bit SR bit 27300 turns ON when IOM is saved to a Memory Cassette.
Load IOM from Cassette Bit SR bit 27301 turns ON when loading to IOM from a Memory Cassette.
3-4-26Transfer Error Flags
Data will not be transferred from IOM to the Memory Cassette if an error occurs
(except for Read Only Error).
Transfer Error Flag: Not
PROGRAM mode
Transfer Error Flag SR bit 27313 turns ON when attempting to transfer data in Read-only Mode.
Transfer Error Flag SR bit 27314 turns ON when attempting to transfer data and IOM capacity is in-
SR bit 27312 turns ON when attempting to transfer data in other than Program
Mode.
sufficient.
3-4-27PC Setup Error Flags
PC Setup Startup Error SR bit 27500 turns ON when a PC Setup Startup error occurs (DM6600 to
DM6614).
PC Setup RUN Error SR bit 27501 turns ON when a PC Setup Run error occurs (DM6615 to
DM6644).
PC Setup
Communications/Error
Setting/Misc. Error
Minutes (00 to 59) SR bits 27600 to 27607 set the PC Clock to minutes (00 to 59).
Hours (00 to 23) SR bits 27608 to 27615 set the PC Clock to hours (0 to 23).
Keyboard Map Used for keyboard mapping.
SR bit 27501 turns ON when a PC Setup Communications, Error setting or Miscellaneous error occurs (DM6645 to DM6655).
3-5 AR (Auxiliary Relay) Area
AR word addresses extend from AR 00 to AR 27; AR bit addresses extend from
AR 0000 to AR 2715. Most AR area words and bits are dedicated to specific
uses, such as transmission counters, flags, and control bits, and words AR 00
through AR 07 and AR 23 through AR 27 cannot be used for any other purpose.
Words and bits from AR 08 to AR 22 are available as work words and work bits if
not used for the following assigned purposes.
Word Use
AR 0713 to AR 0715 Error History Area
AR 07 to 15 SYSMAC LINK Units
AR 16, AR 17 SYSMAC LINK and SYSMAC NET Link Units
AR 18 to AR 21 Calendar/clock Area
AR 0708, AR 0709,
and AR 22
The AR area retains status during power interruptions, when switching from
MONITOR or RUN mode to PROGRAM mode, or when PC operation is
stopped. Bit allocations are shown in the following table and described in the following pages in order of bit number.
AR Area Flags and Control Bits
Word(s) Bit(s) Function
00 00 to 09 Error Flags for Special I/O Units 0 to 9 (also function as Error Flags for PC Link Units)
10 Error Flag for operating level 1 of SYSMAC LINK or SYSMAC NET Link System
11 Error Flag for operating level 0 of SYSMAC LINK or SYSMAC NET Link System
12 Host Computer to Rack-mounting Host Link Unit Level 1 Error Flag
13 Host Computer to Rack-mounting Host Link Unit Level 0 Error Flag
14 Remote I/O Master Unit 1 Error Flag
15 Remote I/O Master Unit 0 Error Flag
TERMINAL Mode Key Bits
48
eable
Writeable
AR Area Section 3-5
Word(s) FunctionBit(s)
01 00 to 09 Restart Bits for Special I/O Units 0 to 9 (also function as Restart Bits for PC Link Units)
10 Restart Bit for operating level 1 of SYSMAC LINK or SYSMAC NET Link System
11 Restart Bit for operating level 0 of SYSMAC LINK or SYSMAC NET Link System
12, 13 Not used.
14 Remote I/O Master Unit 1 Restart Flag.
15 Remote I/O Master Unit 0 Restart Flag.
02 00 to 04 Slave Rack Error Flags (#0 to #4)
05 to 14 Group-2 Error Flags
15 Group-2 Error Flag
03 00 to 15 Error Flags for Optical I/O Units and I/O Terminals 0 to 7
04 00 to 15 Error Flags for Optical I/O Units and I/O Terminals 8 to 15
05 00 to 15 Error Flags for Optical I/O Units and I/O Terminals 16 to 23
06 00 to 15 Error Flags for Optical I/O Units and I/O Terminals 24 to 31
07 00 to 03 Data Link setting for operating level 0 of SYSMAC LINK System
04 to 07 Data Link setting for operating level 1 of SYSMAC LINK System
08 Normal TERMINAL Mode/Expansion TERMINAL Mode Input Cancel Bit
09 Expansion TERMINAL Mode Changeover Flag
10 and 11 Reserved by system.
12 Terminal Mode Flag
ON: Expansion; OFF: Normal (Same as status of pin 6 on CPU’s DIP switch)
13 Error History Overwrite Bit
14 Error History Reset Bit
15 Error History Enable Bit
08 to 11 00 to 15 Active Node Flags for SYSMAC LINK System nodes of operating level 0
12 to 15 00 to 15 Active Node Flags for SYSMAC LINK System nodes of operating level 1
16 00 to 15 SYSMAC LINK/SYSMAC NET Link System operating level 0 service time per cycle
17 00 to 15 SYSMAC LINK/SYSMAC NET Link System operating level 1 service time per cycle
18
Writeable
19
Writeable
20
Writeable
21
Writ
22 00 to 15 Keyboard Mapping
23 00 to 15 Power Off Counter (BCD)
00 to 07 Seconds: 00 to 99
08 to 15 Minutes: 00 to 59
00 to 07 Hours: 00 to 23 (24-hour system)
08 to 15 Day of Month: 01 to 31 (adjusted by month and for leap year)
00 to 07 Month: 1 to 12
08 to 15 Year: 00 to 99 (Rightmost two digits of year)
00 to 07 Day of Week: 00 to 06 (00: Sunday; 01: Monday; 02: Tuesday; 03: Wednesday; 04:
Thursday; 05: Friday; 06: Saturday)
08 to 12 Not used.
13 30-second Compensation Bit
14 Clock Stop Bit
15 Clock Set Bit
49
AR Area Section 3-5
Word(s) FunctionBit(s)
24 00 to 04 Reserved by system.
05 Cycle Time Flag
06 SYSMAC LINK System Network Parameter Flag for operating level 1
07 SYSMAC LINK System Network Parameter Flag for operating level 0
08 SYSMAC/SYSMAC NET Link Unit Level 1 Mounted Flag
09 SYSMAC/SYSMAC NET Link Unit Level 0 Mounted Flag
10 Reserved by system.
11 and 12 PC Link Level
13 Rack-mounting Host Link Unit Level 1 Mounted Flag
14 Rack-mounting Host Link Unit Level 0 Mounted Flag
15 CPU-mounting Device Mounted Flag
25 00 to 11 Reserved by system.
12 Trace End Flag
13 Tracing Flag
14 Trace Trigger Bit (writeable)
15 Trace Start Bit (writeable)
26 00 to 15 Maximum Cycle Time (0.1 ms)
27 00 to 15 Present Cycle Time (0.1 ms)
3-5-1 Restarting Special I/O Units
To restart Special I/O Units (including PC Link Units) turn the corresponding bit
ON and OFF (or turn power ON and OFF). Do not access data refreshed for Special I/O Units during restart processing (see SR 27400 to SR 27409 on page 37).
3-5-2 Slave Rack Error Flags
AR bits 0200 to AR 0204 correspond to the unit numbers of Remote I/O Slave
Units #0 to #4 and AR bits 0710 to AR 0712 correspond to the unit numbers of
Remote I/O Slave Units #5 to #7. These flags will turn ON if the same number is
allocated to more then one Slave or if a transmission error occurs when starting
the System. Refer to SR 251 for errors that occur after the System has started
normally.
3-5-3 Group-2 Error Flags
AR bits 0205 to AR 0215 correspond to Group-2 High-density I/O Units and B7A
Interface Units 0 to 9 (I/O numbers) and will turn ON when the same number is
set for more than one Unit, when the same word is allocated to more than one
Unit, when I/O number 9 is set for a 64-point Unit, or when the fuse burns out in a
Transistor High-density I/O Unit. AR bit 0215 will turn ON when a Unit is not recognized as a Group-2 High-density I/O Unit.
3-5-4 Optical I/O Unit and I/O Terminal Error Flags
AR 03 through AR 06 contain the Error Flags for Optical I/O Units and I/O Terminals. An error indicates a duplication of a unit number. Up to 64 Optical I/O Units
and I/O Terminals can be connected to the PC. Units are distinguished by unit
50
AR Area Section 3-5
number, 0 through 31, and a letter, L or H. Bits are allocated as shown in the following table.
Optical I/O Unit and I/O
Terminal Error Flags
Bits AR03
allocation
00 0 L 8 L 16 L 24 L
01 0 H 8 H 16 H 24 H
02 1 L 9 L 17 L 25 L
03 1 H 9 H 17 H 25 H
04 2 L 10 L 18 L 26 L
05 2 H 10 H 18 H 26 H
06 3 L 11 L 19 L 27 L
07 3 H 11 H 19 H 27 H
08 4 L 12 L 20 L 28 L
09 4 H 12 H 20 H 28 H
10 5 L 13 L 21 L 29 L
11 5 H 13 H 21 H 29 H
12 6 L 14 L 22 L 30 L
13 6 H 14 H 22 H 30 H
14 7 L 15 L 23 L 31 L
15 7 H 15 H 23 H 31 H
AR04
allocation
AR05
allocation
AR06
allocation
3-5-5 SYSMAC LINK System Data Link Settings
AR 0700 to AR 0703 and AR 0704 to AR 0707 are used to designate word allocations for operating levels 0 and 1 of the SYSMAC LINK System. Allocation can
be set to occur either according to settings from an FIT or automatically in the LR
and/or DM areas. If automatic allocation is designated, the number of words to
be allocated to each node is also designated. These settings are shown below.
External/Automatic
Allocation
Words per Node The following setting is necessary if automatic allocation is designated above.
Operating level 0 Operating level 1 Setting
AR 0700 AR 0701 AR 0704 AR 0705
0 0 0 0 Words set externally (FIT)
1 0 1 0 Automatic LR area only
0 1 0 1 allocation DM area only
1 1 1 1 LR and DM
areas
Operating level 0 Operating level 1 Words per node Max. no.
AR 0702 AR 0703 AR 0706 AR 0707 LR area DM area
0 0 0 0 4 8 16
1 0 1 0 8 16 8
0 1 0 1 16 32 4
1 1 1 1 32 64 2
of nodes
The above settings are read every cycle while the SYSMAC LINK System is in
operation.
3-5-6 Error History Bits
AR 0713 (Error History Overwrite Bit) is turned ON or OFF by the user to control
overwriting of r ecords in the Error History Area in the DM area. Turn AR 0713 ON
to overwrite the oldest error record each time an error occurs after 10 have been
recorded. Turn OFF AR 0713 to store only the first 10 records that occur each
time after the history area is cleared.
51
AR Area Section 3-5
AR 0714 (Error History Reset Bit) is turned ON and then OFF by the user to reset
the Error Record Pointer (DM 0969) and thus restart recording error records at
the beginning of the history area.
AR 0715 (Error History Enable Bit) is turned ON by the user to enable error history storage and turned OFF to disable error history storage.
Refer to
3-6 DM Area
for details on the Error History Area.
Error history bits are refreshed each cycle.
3-5-7 Active Node Flags
AR 08 through AR 1 1 and AR 12 through AR 15 provide flags that indicate which
nodes are active in the SYSMAC LINK System at the current time. These flags
are refreshed every cycle while the SYSMAC LINK System is operating.
The body of the following table show the node number assigned to each bit. If the
bit is ON, the node is currently active.
Level 0 Level 1 Bit (body of table shows node numbers)
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15
AR 08 AR 12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
AR 09 AR 13 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AR 10 AR 14 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
AR 11 AR 15 49 50 51 52 53 54 55 56 57 58 59 60 61 62 * **
*Communication Controller Error Flag
**EEPROM Error Flag
3-5-8 SYSMAC LINK/SYSMAC NET Link System Service Time
AR 16 provides the time allocated to servicing operating level 0 of the SYSMAC
LINK System and/or SYSMAC NET Link System during each cycle when a SYSMAC LINK Unit and/or SYSMAC NET Link Unit is mounted to a Rack.
AR 17 provides the time allocated to servicing operating level 1 of the SYSMAC
LINK System and/or SYSMAC NET Link System during each cycle when a SYSMAC LINK Unit and/or SYSMAC NET Link Unit is mounted to a Rack.
These times are recorded in 4-digit BCD to tenths of a millisecond (000.0 ms to
999.9 ms) and are refreshed every cycle.
Bits
15 to 12 11 to 08 07 to 04 03 to 00
10
2
10
1
10
0
10
–1
3-5-9 Calendar/Clock Area and Bits
Calendar/Clock Area A clock is built into the C200HS CPUs. If AR 2114 (Clock Stop Bit) is OFF, then
the date, day, and time will be available in BCD in AR 18 to AR 20 and AR 2100 to
AR 2108 as shown below. This area can also be controlled with AR 2113 (30-second Compensation Bit) and AR 2115 (Clock Set Bit).
Calendar/Clock Bits
Bits Contents Possible values
AR 1800 to AR 1807 Seconds 00 to 59
AR 1808 to AR 1815 Minutes 00 to 59
AR 1900 to AR 1907 Hours 00 to 23 (24-hour system)
AR 1908 to AR 1915 Day of month 01 to 31 (adjusted by month and for leap year)
AR 2000 to AR 2007 Month 1 to 12
AR 2008 to AR 2015 Year 00 to 99 (Rightmost two digits of year)
AR 2100 to AR 2107 Day of week 00 to 06 (00: Sunday; 01: Monday; 02: Tuesday; 03: Wednesday; 04:
Thursday; 05: Friday; 06: Saturday)
52
AR Area Section 3-5
30-second Compensation Bit AR 2113 is turned ON to round the seconds of the Calendar/clock Area to zero,
i.e., if the seconds is 29 or less, it is merely set to 00; if the seconds is 30 or greater, the minutes is incremented by 1 and the seconds is set to 00.
Clock Stop Bit AR 2114 is turned OFF to enable the operation of the Calendar/clock Area and
ON to stop the operation.
Clock Set Bit AR 2115 is used to set the Calendar/clock Area as described below. This data
must be in BCD and must be set within the limits for the Calendar/clock Area
given above.
1, 2, 3...
1. Turn ON AR 2114 (Stop Bit).
2. Set the desired date, day , and time, being careful not to turn OFF AR 2114
(Clock Stop Bit) when setting the day of the week (they’re in the same word).
(On the Programming Console, the Bit/Digit Monitor and Force Set/Reset
Operations are the easiest ways to set this data.)
3. Turn ON A R 2115 (Clock Set Bit). The Calendar/clock will automatically start
operating with the designated settings and AR 2114 and AR 2115 will both
be turned OFF.
The Calendar/clock Area and Bits are refreshed each cycle while operational.
Clock Accuracy Clock accuracy is affected by the ambient temperature as shown in the following
table.
Ambient
temperature
55°C –3 to 0 minutes
25°C ±1 minute
0°C –2 to 0 minutes
Accuracy (loss or
gain per month)
3-5-10TERMINAL Mode Key Bits
If the Programming Console is mounted to the PC and is in TERMINAL mode,
any inputs on keys 0 through 9 (including characters A through F, i.e, keys 0
through 5 with SHIFT) will turn on a corresponding bit in AR 22. TERMINAL
mode is entered by a Programming Console operation.
The bits in AR 22 correspond to Programming Console inputs as follows:
Bit Programming Console input
AR 2200 0
AR 2201 1
AR 2202 2
AR 2203 3
AR 2204 4
AR 2205 5
AR 2206 6
AR 2207 7
AR 2208 8
AR 2209 9
AR 2210 A
AR 2211 B
AR 2212 C
AR 2213 D
AR 2214 E
AR 2215 F
Refer to
Section 7 Program Monitoring and Execution
NAL mode.
for details on the TERMI-
53
AR Area Section 3-5
3-5-11 Power OFF Counter
AR 23 provides in 4-digit BCD the number of times that the PC power has been
turned off. This counter can be reset as necessary using the PV Change 1 operation from the Programming Console. (Refer to
Modification
is turned on.
for details.) The Power OFF Counter is refreshed every time power
7-1-4 Hexadecimal/BCD Data
3-5-12Cycle Time Flag
AR 2405 turns ON when the cycle time set with SCAN(18) is shorter than the
actual cycle time.
AR 2405 is refreshed every cycle while the PC is in RUN or MONITOR mode.
3-5-13Link Unit Mounted Flags
The following flags indicate when the specified Link Units are mounted to the
Racks. (Re f er to
Host Link Units.) These flags are refreshed every cycle.
Name Bit Link Unit
PC Link Unit Level 1 AR 2411 PC Link Unit in operating level 1
PC Link Unit Level 0 AR 2412 PC Link Unit in operating level 0
Rack-mounting Host Link Unit Level 1 AR 2413 Rack-mounting Host Link Unit in operating level 1
Rack-mounting Host Link Unit Level 0 AR 2414 Rack-mounting Host Link Unit in operating level 0
3-5-14 CPU-mounting Device Mounted Flag
for CPU-mounting
3-5-14CPU-mounting Device Mounted Flag
AR 2415 turns ON when any device is mounted directly to the CPU. This includes CPU-mounting Host Link Units, Programming Consoles, and Interface
Units. This flag is refreshed every cycle.
3-5-15FPD Trigger Bit
AR 2508 is used to adjust the monitoring time of FPD(––) automatically. Refer to
5-25-12 FAILURE POINT DETECT – FPD(––)
3-5-16Data Tracing Flags and Control Bits
The following control bits and flags are used during data tracing with TRSM(45).
The Tracing Flag will be ON during tracing operations. The Trace Completed
Flag will turn ON when enough data has been traced to fill Trace Memory.
Bit Name
AR 2512 Trace Completed Flag
AR 2513 Tracing Flag
AR 2514 Trace Trigger Bit (writeable)
AR 2515 Sampling Start Bit (writeable)
Note Refer to
5-25-3 TRACE MEMORY SAMPLING – TRSM(45)
for details.
for details.
3-5-17Cycle Time Indicators
AR 26 contains the maximum cycle time that has occurred since program execution was begun. AR 27 contains the present cycle time.
Both times are to tenths of a millisecond in 4-digit BCD (000.0 ms to 999.9 ms),
and are refreshed every cycle.
54
DM Area Section 3-6
3-6 DM (Data Memory) Area
The DM area is divided into various parts as described in the following table. A
portion of UM (up to 3,000 words in 1,000-word increments) can be allocated as
Expansion DM.
Addresses User
read/write
DM 0000 to DM 0999 Read/Write Normal DM.
DM 1000 to DM 1999 Special I/O Unit Area
DM 2000 to DM 5999 Normal DM.
DM 6000 to DM 6030 History Log
DM 6100 to DM 6143 Link test area (reserved)
DM 6144 to DM 6599 Read only System Settings
DM 6600 to DM 6655 PC Setup
DM 7000 to DM 9999 Expansion DM
Usage
1
2
Note 1. The PC Setup can be set to use DM 7000 through DM 7999 as the Special
I/O Area instead of DM 1000 to DM 1999. Refer to
3-6-4 PC Setup
for de-
tails.
2. The UM ALLOCATION Programming Console operation can be used to allocate up to 3000 words of UM as Expansion DM.
Although composed of 16-bit words like any other data area, data in the DM area
cannot be specified by bit for use in instructions with bit operands. DM 0000 to
DM 6143 can be written to by the program, but DM 6144 to DM 6655 can be overwritten only from a Peripheral Device, such as a Programming Console or host
computer with LSS.
The DM area retains status during power interruptions.
Indirect Addressing Normally, when the content of a data area word is specified for an instruction, the
instruction is performed directly on the content of that word. For example, suppose MOV(21) is performed with DM 0100 as the first operand and LR 20 as the
second operand. When this instruction is executed, the content of DM 0100 is
moved to LR 20.
Note Expansion DM cannot be used for indirect addressing.
It is possible, however, to use indirect DM addresses as the operands for many
instructions. To indicate an indirect DM address, :DM is input with the address
of the operand. With an indirect address, with content of this operand does not
contain the actual data to be used. Instead, it’s contents is assumed to hold the
address of another DM word, the content of which will actually be used in the
instruction. If :DM 0100 was used in our example above and the content of DM
0100 is 0324, then :DM 0100 actually means that the content of DM 0324 is to
be used as the operand in the instruction, and the content of DM 0324 will be
moved to LR 20.
MOV(21)
:DM 0100
LR 00
Indirect
address
Word Content
DM 0099 4C59
DM 0100 0324
DM 0101 F35A
DM 0324 5555
DM 0325 2506
DM 0326 D541
Indicates
DM 0324
5555 moved
to LR 00.
55
DM Area Section 3-6
3-6-1 Expansion DM Area
The expansion DM area is designed to provide memory space for storing operating parameters and other operating data for Link Units and Special I/O Units.
Up to 3,000 words of UM can be allocated as Expansion DM (in 1K-word increments) using the UM ALLOCATION operation in the Programming Console or
LSS. Expansion DM area addresses run from DM 7000 to DM 9999.
The data in the expansion DM area can be transferred to the Special I/O Unit
Default Area (DM 1000 to DM 1999) when starting the PC or via programming
instruction to easily change operating parameters, enabling rapid switching between control processes. The expansion DM area can also be used to store parameters for other devices connected in the PC system, e.g., Programmable
Terminal character string or numeral tables.
The expansion DM area is used to store operating parameters and cannot be
used in programming like the normal DM area. Expansion DM can only be overwritten from a Peripheral Device, retains status during power interruptions, and
cannot be used for indirect addressing.
The UM area can be allocated as expansion DM area in increments of 1K words.
Once expansion DM area has been created, it is saved and transferred as part of
the program, i.e., no special procedures are required when saving or transferring the program.
UM ALLOCATION Operation The procedure for the Programming Console’s UM ALLOCATION operation is
shown below. Refer to
1-8-10 New Programming Console Operations
for details
on the DATA CLEAR and UM ALLOCATION instructions.
1, 2, 3...
1. Clear memory.
CLR
NOT
RESETSET
EXT MONTR
Note UM allocation is not possible unless memory is cleared first.
2. The expansion DM area can be set to 0, 1, 2, or 3 K words. The following key
sequence creates a 2-KW expansion DM area (DM 7000 to DM 8999).
WRITECLR FUN VER CHG 2 SET 9 7 1 3
Press the 0 Key to eliminate the expansion DM area (0 KW).
or Press the 1 Key to allocate DM 7000 to DM 7999 (1 KW).
or Press the 2 Key to allocate DM 7000 to DM 8999 (2 KW).
or Press the 3 Key to allocate DM 7000 to DM 9999 (3 KW).
3-6-2 Special I/O Unit Data
Special I/O Units are allocated 1000 words in the DM Area as shown in the following table. The value set in the PC Setup (DM 6602 bits 08 to 15) determines
56
DM Area Section 3-6
whether DM 1000 to DM 1999 or DM 7000 to 7999 will be used. Refer to
PC Setup
Unit Addresses
0 DM 1000 to DM 1099 or DM 7000 to DM 7099
1 DM 1100 to DM 1199 or DM 7100 to DM 7199
2 DM 1200 to DM 1299 or DM 7200 to DM 7299
3 DM 1300 to DM 1399 or DM 7300 to DM 7399
4 DM 1400 to DM 1499 or DM 7400 to DM 7499
5 DM 1500 to DM 1599 or DM 7500 to DM 7599
6 DM 1600 to DM 1699 or DM 7600 to DM 7699
7 DM 1700 to DM 1799 or DM 7700 to DM 7799
8 DM 1800 to DM 1899 or DM 7800 to DM 7899
9 DM 1900 to DM 1999 or DM 7900 to DM 7999
for details.
3-6-4
Note These DM words can be used for other purposes when not allocated to Special
I/O Units.
3-6-3 Error History Area
DM 6000 to DM 6030 are used to store up to 10 records that show the nature,
time, and date of errors that have occurred in the PC.
The Error History Area will store system-generated or FAL(06)/FALS(07)-generated error codes whenever AR 0715 (Error History Enable Bit) is ON. Refer to
Section 10 Troubleshooting
Area Structure Error records occupy three words each stored between DM 6001 and DM 6030.
The last record that was stored can be obtained via the content of DM 6000 (Error Record Pointer). The record number, DM words, and pointer value for each of
the ten records are as follows:
for details on error codes.
Record Addresses Pointer value
None N.A. 0000
1 DM 6001 to DM 6003 0001
2 DM 6004 to DM 6006 0002
3 DM 6007 to DM 6009 0003
4 DM 6010 to DM 6012 0004
5 DM 6013 to DM 6015 0005
6 DM 6016 to DM 6018 0006
7 DM 6019 to DM 6021 0007
8 DM 6022 to DM 6024 0008
9 DM 6025 to DM 6027 0009
10 DM 6028 to DM 6030 000A
Although each of them contains a different record, the structure of each record is
the same: the first word contains the error code; the second and third words, the
day and time. The error code will be either one generated by the system or by
FAL(06)/FALS(07); the time and date will be the date and time from AR 18 and
AR 19 (Calender/date Area). Also recorded with the error code is an indication of
whether the error is fatal (08) or non-fatal (00). This structure is shown below.
Word Bit Content
First 00 to 07 Error code
08 to 15 00 (non-fatal) or 80 (fatal)
Second 00 to 07 Seconds
08 to 15 Minutes
Third 00 to 07 Hours
08 to 15 Day of month
57
DM Area Section 3-6
The following table lists the possible error codes and corresponding errors.
Error severity Error code Error
Fatal errors 00 Power Interruption
01 to 99 System error (FALS)
9F Cycle time error
C0 to C2 I/O bus error
E0 Input-output I/O table error
E1 Too many Units
F0 No END(01) instruction
F1 Memory error
Non-fatal errors 01 to 99 System error (FAL)
8A Interrupt Input error
8B Interrupt program error
9A Group 2 High-density I/O error
9B PC Setup error
9D UM Memory Cassette transfer error
B0 to B1 Remote I/O error
D0 Special I/O error
E7 I/O table verification error
F7 Battery error
F8 Cycle time overrun
Operation When the first error code is generated with AR 0715 (Error History Enable Bit)
turned ON, the relevant data will be placed in the error record after the one indicated by the History Record Pointer (initially this will be record 1) and the Pointer
will be incremented. Any other error codes generated thereafter will be placed in
consecutive records until the last one is used. Processing of further error records
is based on the status of AR 0713 (Error History Overwrite Bit).
If AR 0713 is ON and the Pointer contains 000A, the next error will be written into
record 10, the contents of record 10 will be moved to record 9, and so on until the
contents of record 1 is moved off the end and lost, i.e., the area functions like a
shift register. The Record Pointer will remain set to 000A.
If AR 0713 is OFF and the Pointer reaches 000A, the contents of the Error History Error will remain as it is and any error codes generate thereafter will not be
recorded until AR 0713 is turned OFF or until the Error History Area is reset.
The Error History Area can be reset by turning ON and then OFF
AR 0714 (Error History Reset Bit). When this is done, the Record Pointer will be
reset to 0000, the Error History Area will be reset (i.e., cleared), and any further
error codes will be recorded from the beginning of the Error History Area.
AR 0715 (Error History Enable Bit) must be ON to reset the Error History Area.
3-6-4 PC Setup
The PC Setup contains settings that determine C200HS operation. Data in the
PC Setup can be changed with a Programming Console or LSS if UM is not
write-protected by pin 1 of the CPU’s DIP switch. Refer to page 23 for details on
changing DIP switch pin settings.
58
The PC can be operated with the default PC Setup, which requires changing
only when customizing the PC’s operating environment to application needs.
The PC Setup parameters are described in the following table. Refer to
dix E PC Setup
for more details on these parameters.
Appen-
communications system (e.g
Host Link System). All
other settings must match those of the device being
DM Area Section 3-6
The PC Setup is allocated to DM 6600 through DM 6655.
Parameter Default Settings Remarks
STARTUP MODE
STARTUP
MODE
FORCED
STATUS
IOM HOLD BIT
STATUS
CYCLE TIME Variable Variable or minimum
Programming
Console
mode selector
Don’t hold Hold or don’t hold Determines whether or not the status of the Forced
Don’t hold Hold or don’t hold Determines whether or not the status of the IOM Hold
Programming Console
mode selector, previous
mode (i.e., the mode in
use last time power was
interrupted), PROGRAM,
MONITOR, or RUN
Minimum setting: 1 to
9,999 ms
Determines the operating mode the PC will start in
when power is turned ON.
This setting is required for restart continuation.
Setting is effective from next time power is turned on
to the PC.
Status Hold Bit is maintained after power interruptions.
If the status of the Forced Status Hold Bit is not set to
be held, it will be turned OFF the next time the PC is
started and forced status will be cleared.
Setting is effective from next time power is turned on
to the PC.
Bit is maintained after power interruptions. If the status
of the IOM Hold Bit is not set to be held, it will be
turned OFF the next time the PC is started and I/O
status will be cleared.
This setting is required for restart continuation.
Setting is effective from next time power is turned on
to the PC.
Determines whether or not a minimum cycle time is to
be used for user program execution. If a minimum time
is set, the PC will wait until the minimum time has
expired before starting program execution again. The
entire program will be executed even if the minimum
time is exceeded.
This setting can be used to reduce variations in I/O
response times.
An error of approximately 3 to 4 ms, plus the execution
time required for any interrupt programs, can occur.
Setting is effective immediately.
Detect Long
Cycles
RS-232C SETUP
METHOD Host link Host Link, RS-232C with
NODE NO 0 00 to 31
DELAY 0 0 to 9,999 ms
START CODE None 00 to FF
END CODE None 00 to FF or CR, LF
DATA LINK
AREAS
BAUD RATE 9,600 bps 1200, 2400, 4800, 9600,
STOP BITS 2 bits 1 or 2 bits
PARITY Even parity Even, odd, or none
DATA LENGTH 7 bits 7 or 8 bits
PC SETUP, HEX
INPUT
120 ms 0 to 99,000 ms If the set time is exceeded, the Cycle Time Exceeded
no protocol, 1:1 link
master, or 1:1 link slave
None LR 00 to LR 63, LR 00 to
LR 31, or LR 00 to LR 15
or 19200
Used to set the above parameters on a binary display.
Flag will turn ON and a fatal error will occur.
An error of approximately 3 to 4 ms can occur.
Setting is effective immediately.
Determines the settings used when a device, such as
a Programmable Terminal or bar code reader is
connected to the RS-232C port.
Do not set the node number to a number already used
by another Unit connected in the same
.,
other settings must match those of the device being
communicated with.
Settings are effective immediately.
59
TC Area Section 3-8
3-7 HR (Holding Relay) Area
The HR area is used to store/manipulate various kinds of data and can be accessed either by word or by bit. Word addresses range from HR 00 through HR
99; bit addresses, from HR 0000 through HR 9915. HR bits can be used in any
order required and can be programmed as often as required.
The HR area retains status when the system operating mode is changed, when
power is interrupted, or when PC operation is stopped.
HR area bits and words can be used to preserve data whenever PC operation is
stopped. HR bits also have various special applications, such as creating latching relays with the Keep instruction and forming self-holding outputs. These are
discussed in
tion Set
Note The required number of words is allocated between HR 00 and HR 42 for routing
tables and to monitor timers when using SYSMAC NET Systems.
Section 4 Writing and Inputting the Program
.
and
Section 5 Instruc-
3-8 TC (Timer/Counter) Area
The TC area is used to create and program timers and counters and holds the
Completion flags, set values (SV), and present values (PV) for all timers and
counters. All of these are accessed through TC numbers ranging from TC 000
through TC 511. Each TC number is defined as either a timer or counter using
one of the following instructions: TIM, TIMH, CNT , CNTR(12), and TTIM(87). No
prefix is required when using a TC number in a timer or counter instruction.
Once a TC number has been defined using one of these instructions, it cannot
be redefined elsewhere in the program either using the same or a different instruction. If the same TC number is defined in more than one of these instructions or in the same instruction twice, an error will be generated during the program check. There are no restrictions on the order in which TC numbers can be
used.
Once defined, a TC number can be designated as an operand in one or more of
certain set of instructions other than those listed above. When defined as a timer ,
a TC number designated as an operand takes a TIM prefix. The TIM prefix is
used regardless of the timer instruction that was used to define the timer. Once
defined as a counter, the TC number designated as an operand takes a CNT
prefix. The CNT is also used regardless of the counter instruction that was used
to define the counter.
TC numbers can be designated for operands that require bit data or for operands
that require word data. When designated as an operand that requires bit data,
the TC number accesses the completion flag of the timer or counter. When designated as a n operand that requires word data, the TC number accesses a memory location that holds the PV of the timer or counter.
TC numbers are also used to access the SV of timers and counters from a Programming Device. The procedures for doing so using the Programming Console
are provided in
The TC area retains the SVs of both timers and counters during power interruptions. The PVs of timers are reset when PC operation is begun and when reset in
interlocked program sections. Refer to
CLEAR – IL(02) and ILC(03)
locked program sections. The PVs of counters are not reset at these times.
Note that in programming “TIM 000” is used to designate three things: the T imer
instruction defined with TC number 000, the completion flag for this timer, and
the PV of this timer. The meaning in context should be clear, i.e., the first is always an instruction, the second is always a bit, and the third is always a word.
The same is true of all other TC numbers prefixed with TIM or CNT.
7-1 Monitoring Operation and Modifying Data.
5-10 INTERLOCK and INTERLOCK
for details on timer and counter operation in inter-
60
TR Area Section 3-11
3-9 LR (Link Relay) Area
The LR area is used as a common data area to transfer information between
PCs. This data transfer is achieved through a PC Link System.
Certain words will be allocated as the write words of each PC. These words are
written by the PC and automatically transferred to the same LR words in the
other PCs in the System. The write words of the other PCs are transferred in as
read words so that each PC can access the data written by the other PCs in the
PC Link System. Only the write words allocated to the particular PC will be available for writing; all other words may be read only. Refer to the
Manual
for details.
The LR area is accessible either by bit or by word. LR area word addresses
range from LR 00 to LR 63; LR area bit addresses, from LR 0000 to LR 6315. Any
part of the LR area that is not used by the PC Link System can be used as work
words or work bits.
LR area data is not retained when the power is interrupted, when the PC is
changed to PROGRAM mode, or when it is reset in an interlocked program section. Refer to
5-10 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03)
for details on interlocks.
PC Link System
3-10 UM Area
With the C200HS, the UM area is defined as the part of memory that can be converted and transferred to ROM. The UM area is 16 KW of RAM which is backed
up by the CPU’s battery. Some of the UM area is reserved to system use, so
15,488 words can be used by the operator . The structure of the C200HS DM and
UM areas is shown in the following illustration.
DM 0000 DM 6144 DM 6600 DM 6655 DM 7000 DM 9999
PC Setup Reserved
Special I/O Unit Default Area
DM 1000 to DM 1999
Note Allocating UM area for an expansion DM and/or I/O Comment Area will reduce
program capacity. Check program capacity requirements before allocating the
UM area.
Expansion
DM Area
Variable size
Ladder Program Area (15.1 KW)Fixed DM Area
UM Area (16.0 KW)Normal DM Area
I/O Comment
Area
Ladder program
3-11 TR (Temporary Relay) Area
The TR area provides eight bits that are used only with the LD and OUT instructions to enable certain types of branching ladder diagram programming. The use
of TR bits is described in
TR addresses range from TR 0 though TR 7. Each of these bits can be used as
many times as required and in any order required as long as the same LR bit is
not used twice in the same instruction block.
Section 4 Writing and Inputting the Program
.
61
SECTION 4
Writing and Inputting the Program
This section explains the basic steps and concepts involved in writing a basic ladder diagram program, inputting the program
into memory , and executing it. It introduces the instructions that are used to build the basic structure of the ladder diagram and
control its execution. The entire set of instructions used in programming is described in Section 5 Instruction Set.
4-1 Basic Procedure 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-2 Instruction Terminology 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3 Program Capacity 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4 Basic Ladder Diagrams 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4-1 Basic Terms 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4-2 Mnemonic Code 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4-3 Ladder Instructions 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4-4 OUTPUT and OUTPUT NOT 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4-5 The END Instruction 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4-6 Logic Block Instructions 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4-7 Coding Multiple Right-hand Instructions 78 . . . . . . . . . . . . . . . . . . . . . . .
4-5 The Programming Console 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-5-1 The Keyboard 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-5-2 PC Modes 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-5-3 The Display Message Switch 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6 Preparation for Operation 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-1 Entering the Password 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-2 Buzzer 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-3 Clearing Memory 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-4 Registering the I/O Table 84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-5 Clearing Error Messages 85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-6 Verifying the I/O Table 86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-7 Reading the I/O Table 87 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-8 Clearing the I/O Table 89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-9 SYSMAC NET Link Table Transfer (CPU31/33-E Only) 90 . . . . . . . . . .
4-7 Inputting, Modifying, and Checking the Program 92 . . . . . . . . . . . . . . . . . . . . . . . . .
4-7-1 Setting and Reading from Program Memory Address 92 . . . . . . . . . . . . .
4-7-2 Entering and Editing Programs 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7-3 Checking the Program 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7-4 Displaying the Cycle Time 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7-5 Program Searches 99 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7-6 Inserting and Deleting Instructions 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7-7 Branching Instruction Lines 103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7-8 Jumps 107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-8 Controlling Bit Status 108 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-8-1 DIFFERENTIATE UP and DIFFERENTIATE DOWN 109 . . . . . . . . . . . .
4-8-2 KEEP 109 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-8-3 Self-maintaining Bits (Seal) 109 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-9 Work Bits (Internal Relays) 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-10 Programming Precautions 112 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-11 Program Execution 114 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
63
Instruction Terminology Section 4-2
4-1 Basic Procedure
There are several basic steps involved in writing a program. Sheets that can be
Appendix F Word Assignment Re-
.
5-14 Timer and Counter
. Preparing for and inputting the pro-
4-5 The Programming
. The rest
Sec-
Section 7 Program Monitoring
also provides information required
1, 2, 3...
copied to aid in programming are provided in
and
cording Sheets
1. Obtain a list of all I/O devices and the I/O points that have been assigned to
them and prepare a table that shows the I/O bit allocated to each I/O device.
2. If the PC has any Units that are allocated words in data areas other than the
IR area or are allocated IR words in which the function of each bit is specified
by the Unit, prepare similar tables to show what words are used for which
Units and what function is served by each bit within the words. These Units
include Special I/O Units and Link Units.
3. Determine what words are available for work bits and prepare a table in
which you can allocate these as you use them.
4. Also prepare tables of TC numbers and jump numbers so that you can allocate these as you use them. Remember, the function of a TC number can be
defined only once within the program; jump numbers 01 through 99 can be
used only once each. (TC number are described in
Instructions
5. Draw the ladder diagram.
6. Input the program into the CPU. When using the Programming Console, this
will involve converting the program to mnemonic form.
7. Check the program for syntax errors and correct these.
8. Execute the program to check for execution errors and correct these.
9. After the entire Control System has been installed and is ready for use, execute the program and fine tune it if required.
10. Make a backup copy of the program.
The basics of ladder-diagram programming and conversion to mnemonic code
are described in
gram via the Programming Console are described in
Console
of Section 4 covers more advanced programming, programming precautions,
and program execution. All special application instructions are covered in
tion 5 Instruction Set
and Execution
for debugging.
through
Appendix G Program Coding Sheet
; jump numbers are described later in this section.)
4-4 Basic Ladder Diagrams
4-7 Inputting, Modifying, and Checking the Program
. Debugging is described in
.
Section 10 Troubleshooting
4-2 Instruction Terminology
There are basically two types of instructions used in ladder-diagram programming: instructions that correspond to the conditions on the ladder diagram and
are used in instruction form only when converting a program to mnemonic code
and instructions that are used on the right side of the ladder diagram and are
executed according to the conditions on the instruction lines leading to them.
Most instructions have at least one or more operands associated with them. Operands indicate or provide the data on which an instruction is to be performed.
These are sometimes input as the actual numeric values, but are usually the addresses of data area words or bits that contain the data to be used. For instance,
a MOVE instruction that has IR 000 designated as the source operand will move
the contents of IR 000 to some other location. The other location is also designated as an operand. A bit whose address is designated as an operand is called
an operand bit; a word whose address is designated as an operand is called an
operand word. If the actual value is entered as a constant, it is preceded by # to
indicate that it is not an address.
Other terms used in describing instructions are introduced in
tion Set
64
.
Section 5 Instruc-
Basic Ladder Diagrams Section 4-4
4-3 Program Capacity
The maximum user program size varies with the amount of UM allocated to expansion DM and the I/O Comment Area. Approximately 10.1 KW are available
for the ladder program when 3 KW are allocated to expansion DM and 2 KW are
allocated to I/O comments as shown below. Refer to the
information on UM allocation.
3-10 UM Area
for further
DM
6144
DM
6600DM6655
PC
Setup
4-4 Basic Ladder Diagrams
A ladder diagram consists of one line running down the left side with lines
branching off to the right. The line on the left is called the bus bar; the branching
lines, instruction lines or rungs. Along the instruction lines are placed conditions
that lead to other instructions on the right side. The logical combinations of these
conditions determine when and how the instructions at the right are executed. A
ladder diagram is shown below.
00000 06315
00001
DM
7000
Reserved
Expansion
DM Area
HR 0109 LR 250325208 24400
00501 00502 00503 00504
Variable size
Ladder Program Area (15.1 KW)Fixed DM Area
DM
9999
I/O Comment
Area
Ladder program
24401
Instruction
00100 00002
00010
00011
00003 HR 0050 00007 TIM 001 LR 0515
21001 21002
21005 21007
00403
00405
Instruction
As shown in the diagram above, instruction lines can branch apart and they can
join back together. The vertical pairs of lines are called conditions. Conditions
without diagonal lines through them are called normally open conditions and
correspond to a LOAD, AND, or OR instruction. The conditions with diagonal
lines through them are called normally closed conditions and correspond to a
LOAD NOT, AND NOT, or OR NOT instruction. The number above each condition indicates the operand bit for the instruction. It is the status of the bit associated with each condition that determines the execution condition for following
instructions. The way the operation of each of the instructions corresponds to a
condition is described below. Before we consider these, however, there are
some basic terms that must be explained.
Note When displaying ladder diagrams with LSS, a second bus bar will be shown on
the right side of the ladder diagram and will be connected to all instructions on
the right side. This does not change the ladder-diagram program in any functional sense. No conditions can be placed between the instructions on the right
side and the right bus bar, i.e., all instructions on the right must be connected
directly to the right bus bar. Refer to the
LSS Operation Manual
for details.
65
Basic Ladder Diagrams Section 4-4
4-4-1 Basic Terms
Normally Open and
Normally Closed
Conditions
Each condition in a ladder diagram is either ON or OFF depending on the status
of the operand bit that has been assigned to it. A normally open condition is ON if
the operand bit is ON; OFF if the operand bit is OFF. A normally closed condition
is ON if the operand bit is OFF; OFF if the operand bit is ON. Generally speaking,
you use a normally open condition when you want something to happen when a
bit is ON, and a normally closed condition when you want something to happen
when a bit is OFF.
00000
Instruction
Normally open
condition
00000
Instruction
Normally closed
condition
Instruction is executed
when IR bit 00000 is ON.
Instruction is executed
when IR bit 00000 is OFF.
Execution Conditions In ladder diagram programming, the logical combination of ON and OFF condi-
tions before an instruction determines the compound condition under which the
instruction is executed. This condition, which is either ON or OFF, is called the
execution condition for the instruction. All instructions other than LOAD instructions have execution conditions.
Operand Bits The operands designated for any of the ladder instructions can be any bit in the
IR, SR, HR, AR, LR, or TC areas. This means that the conditions in a ladder diagram can be determined by I/O bits, flags, work bits, timers/counters, etc. LOAD
and OUTPUT instructions can also use TR area bits, but they do so only in special applications. Refer to
4-7-7 Branching Instruction Lines
for details.
Logic Blocks The way that conditions correspond to what instructions is determined by the
relationship between the conditions within the instruction lines that connect
them. Any group of conditions that go together to create a logic result is called a
logic block. Although ladder diagrams can be written without actually analyzing
individual logic blocks, understanding logic blocks is necessary for efficient programming and is essential when programs are to be input in mnemonic code.
4-4-2 Mnemonic Code
The ladder diagram cannot be directly input into the PC via a Programming Console; LSS is required. To input from a Programming Console, it is necessary to
convert the ladder diagram to mnemonic code. The mnemonic code provides
exactly the same information as the ladder diagram, but in a form that can be
typed directly into the PC. Actually you can program directly in mnemonic code,
although it in not recommended for beginners or for complex programs. Also,
regardless of the Programming Device used, the program is stored in memory in
mnemonic form, making it important to understand mnemonic code.
Because of the importance of the Programming Console as a peripheral device
and because of the importance of mnemonic code in complete understanding of
a program, we will introduce and describe the mnemonic code along with the
ladder diagram. Remember, you will not need to use the mnemonic code if you
are inputting via LSS (although you can use it with LSS too, if you prefer).
Program Memory Structure The program is input into addresses in Program Memory. Addresses in Program
Memory are slightly different to those in other memory areas because each address does not necessarily hold the same amount of data. Rather , each address
holds one instruction and all of the definers and operands (described in more
detail later) required for that instruction. Because some instructions require no
operands, while others require up to three operands, Program Memory addresses can be from one to four words long.
66
Basic Ladder Diagrams Section 4-4
Program Memory addresses start at 00000 and run until the capacity of Program
Memory has been exhausted. The first word at each address defines the instruction. Any definers used by the instruction are also contained in the first word.
Also, if an instruction requires only a single bit operand (with no definer), the bit
operand is also programmed on the same line as the instruction. The rest of the
words required by an instruction contain the operands that specify what data is
to be used. When converting to mnemonic code, all but ladder diagram instructions are written in the same form, one word to a line, just as they appear in the
ladder diagram symbols. An example of mnemonic code is shown below. The
instructions used in it are described later in the manual.
Address Instruction Operands
00000 LD HR 0001
00001 AND 00001
00002 OR 00002
00003 LD NOT 00100
00004 AND 00101
00005 AND LD 00102
00006 MOV(21)
000
DM 0000
00007 CMP(20)
DM 0000
HR 00
00008 LD 25505
00009 OUT 00501
00010 MOV(21)
DM 0000
DM 0500
0001 1 DIFU(13) 00502
00012 AND 00005
00013 OUT 00503
The address and instruction columns of the mnemonic code table are filled in for
the instruction word only. For all other lines, the left two columns are left blank. If
the instruction requires no definer or bit operand, the operand column is left
blank for first line. It is a good idea to cross through any blank data column
spaces (for all instruction words that do not require data) so that the data column
can be quickly scanned to see if any addresses have been left out.
When programming, addresses are automatically displayed and do not have to
be input unless for some reason a different location is desired for the instruction.
When converting to mnemonic code, it is best to start at Program Memory address 00000 unless there is a specific reason for starting elsewhere.
4-4-3 Ladder Instructions
The ladder instructions are those instructions that correspond to the conditions
on the ladder diagram. Ladder instructions, either independently or in combination with the logic block instructions described next, form the execution conditions upon which the execution of all other instructions are based.
67
Basic Ladder Diagrams Section 4-4
LOAD and LOAD NOT The first condition that starts any logic block within a ladder diagram corre-
sponds to a LOAD or LOAD NOT instruction. Each of these instruction requires
one line of mnemonic code. “Instruction” is used as a dummy instruction in the
following examples and could be any of the right-hand instructions described later in this manual.
00000
A LOAD instruction.
00000
A LOAD NOT instruction.
When this is the only condition on the instruction line, the execution condition for
the instruction at the right is ON when the condition is ON. For the LOAD instruction (i.e., a normally open condition), the execution condition will be ON when IR
00000 is ON; for the LOAD NOT instruction (i.e., a normally closed condition), it
will be ON when 00000 is OFF.
Address Instruction Operands
00000 LD 00000
00001 Instruction
00002 LD NOT 00000
00003 Instruction
AND and AND NOT When two or more conditions lie in series on the same instruction line, the first
one corresponds to a LOAD or LOAD NOT instruction; and the rest of the conditions correspond to AND or AND NOT instructions. The following example
shows three conditions which correspond in order from the left to a LOAD, an
AND NOT, and an AND instruction. Again, each of these instructions requires
one line of mnemonic code.
00000 00100 LR 0000
Address Instruction Operands
00000 LD 00000
00001 AND NOT 00100
00002 AND LR 0000
00003 Instruction
Instruction
The instruction will have an ON execution condition only when all three conditions are ON, i.e., when IR 00000 is ON, IR 00100 is OFF, and LR 0000 is ON.
68
AND instructions in series can be considered individually, with each taking the
logical AND of the execution condition (i.e., the total of all conditions up to that
point) and t h e status o f t h e AND instruction’ s operand bit. If both of these are ON,
an ON execution condition will be produced for the next instruction. If either is
OFF, the result will also be OFF. The execution condition for the first AND instruction in a series is the first condition on the instruction line.
Each AND NOT instruction in series takes the logical AND of its execution condition and the inverse of its operand bit.
Basic Ladder Diagrams Section 4-4
OR and OR NOT When two or more conditions lie on separate instruction lines which run in paral-
lel and then join together, the first condition corresponds to a LOAD or LOAD
NOT instruction; the other conditions correspond to OR or OR NOT instructions.
The following example shows three conditions which correspond (in order from
the top) to a LOAD NOT, an OR NOT, and an OR instruction. Again, each of
these instructions requires one line of mnemonic code.
Combining AND and OR
Instructions
00000
Instruction
00100
LR 0000
Address Instruction Operands
00000 LD 00000
00001 OR NOT 00100
00002 OR LR 0000
00003 Instruction
The instruction will have an ON execution condition when any one of the three
conditions is ON, i.e., when IR 00000 is OFF, when IR 00100 is OFF, or when LR
0000 is ON.
OR and OR NOT instructions can be considered individually, each taking the
logical OR between its execution condition and the status of the OR instruction’s
operand bit. If either one of these were ON, an ON execution condition will be
produced for the next instruction.
When AND and OR instructions are combined in more complicated diagrams,
they can sometimes be considered individually, with each instruction performing
a logic operation on the execution condition and the status of the operand bit.
The following is one example. Study this example until you are convinced that
the mnemonic code follows the same logic flow as the ladder diagram.
00002 0000300000 00001
00200
Address Instruction Operands
00000 LD 00000
00001 AND 00001
00002 OR 00200
00003 AND 00002
00004 AND NOT 00003
00005 Instruction
Instruction
Here, an AND is taken between the status of IR 00000 and that of IR 00001 to
determine the execution condition for an OR with the status of IR 00200. The
result of this operation determines the execution condition for an AND with the
status of IR 00002, which in turn determines the execution condition for an AND
with the inverse (i.e., and AND NOT) of the status of IR 00003.
In more complicated diagrams, however, it is necessary to consider logic blocks
before an execution condition can be determined for the final instruction, and
that’s where AND LOAD and OR LOAD instructions are used. Before we consider more complicated diagrams, however, we’ll look at the instructions required to
complete a simple “input-output” program.
69
Basic Ladder Diagrams Section 4-4
4-4-4 OUTPUT and OUTPUT NOT
The simplest way to output the results of combining execution conditions is to
output it directly with the OUTPUT and OUTPUT NOT. These instructions are
used to control the status of the designated operand bit according to the execution condition. With the OUTPUT instruction, the operand bit will be turned ON
as long as the execution condition is ON and will be turned OFF as long as the
execution condition is OFF. With the OUTPUT NOT instruction, the operand bit
will be turned ON as long as the execution condition is OFF and turned OFF as
long as the execution condition is ON. These appear as shown below. In mnemonic code, each of these instructions requires one line.
00000
00001
In the above examples, IR 00200 will be ON as long as IR 00000 is ON and IR
00201 will be OFF as long as IR 00001 is ON. Here, IR 00000 and IR 00001 will
be input bits and IR 00200 and IR 00201 output bits assigned to the Units controlled by the PC, i.e., the signals coming in through the input points assigned IR
00000 and IR 00001 are controlling the output points assigned IR 00200 and IR
00201, respectively.
The length of time that a bit is ON or OFF can be controlled by combining the
OUTPUT or OUTPUT NOT instruction with TIMER instructions. Refer to Examples under
4-4-5 The END Instruction
The last instruction required to complete a simple program is the END instruction. When the CPU cycles the program, it executes all instruction up to the first
END instruction before returning to the beginning of the program and beginning
execution again. Although an END instruction can be placed at any point in a
program, which is sometimes done when debugging, no instructions past the
first END instruction will be executed until it is removed. The number following
the END instruction in the mnemonic code is its function code, which is used
when inputted most instruction into the PC. These are described later. The END
instruction requires no operands and no conditions can be placed on the same
instruction line with it.
00200
00201
5-14-1 TIMER – TIM
Address Instruction Operands
00000 LD 00000
00001 OUT 00200
Address Instruction Operands
00000 LD 00001
00001 OUT NOT 00201
for details.
70
00000 00001
Address Instruction Operands
00000 LD 00000
00001 AND NOT 00001
00002 Instruction
00003 END(01) ---
Instruction
END(01)
Program execution
ends here.
If there is no END instruction anywhere in the program, the program will not be
executed at all.
Basic Ladder Diagrams Section 4-4
Now you have all of the instructions required to write simple input-output programs. Before we finish with ladder diagram basic and go onto inputting the program into the PC, let’s look at logic block instruction (AND LOAD and OR LOAD),
which are sometimes necessary even with simple diagrams.
4-4-6 Logic Block Instructions
Logic block instructions do not correspond to specific conditions on the ladder
diagram; rather, they describe relationships between logic blocks. The AND
LOAD instruction logically ANDs the execution conditions produced by two logic
blocks. The OR LOAD instruction logically ORs the execution conditions produced by two logic blocks.
AND LOAD Although simple in appearance, the diagram below requires an AND LOAD in-
struction.
00000
00001
Address Instruction Operands
00000 LD 00000
00001 OR 00001
00002 LD 00002
00003 OR NOT 00003
00004 AND LD ---
00002
Instruction
00003
The two logic blocks are indicated by dotted lines. Studying this example shows
that an ON execution condition will be produced when: either of the conditions in
the left logic block is ON (i.e., when either IR 00000 or IR 00001 is ON), and
when either of the conditions in the right logic block is ON (i.e., when either IR
00002 is ON or IR 00003 is OFF).
The above ladder diagram cannot, however, be converted to mnemonic code
using AND and OR instructions alone. If an AND between IR 00002 and the results of an OR between IR 00000 and IR 00001 is attempted, the OR NOT between IR 00002 and IR 00003 is lost and the OR NOT ends up being an OR NOT
between just IR 00003 and the result of an AND between IR 00002 and the first
OR. What we need is a way to do the OR (NOT)’s independently and then combine the results.
To do this, we can use the LOAD or LOAD NOT instruction in the middle of an
instruction line. When LOAD or LOAD NOT is executed in this way, the current
execution condition is saved in a special buffer and the logic process is restarted. To combine the results of the current execution condition with that of a
previous “unused” execution condition, an AND LOAD or an OR LOAD instruction is used. Here “LOAD” refers to loading the last unused execution condition.
An unused execution condition is produced by using the LOAD or LOAD NOT
instruction for any but the first condition on an instruction line.
71
Basic Ladder Diagrams Section 4-4
Analyzing the above ladder diagram in terms of mnemonic instructions, the condition for IR 00000 is a LOAD instruction and the condition below it is an OR instruction between the status of IR 00000 and that of IR 00001. The condition at
IR 00002 is another LOAD instruction and the condition below is an OR NOT
instruction, i.e., an OR between the status of IR 00002 and the inverse of the
status of IR 00003. To arrive at the execution condition for the instruction at the
right, the logical AND of the execution conditions resulting from these two blocks
will have to be taken. AND LOAD does this. The mnemonic code for the ladder
diagram is shown below. The AND LOAD instruction requires no operands of its
own, because it operates on previously determined execution conditions. Here
too, dashes are used to indicate that no operands needs designated or input.
OR LOAD The following diagram requires an OR LOAD instruction between the top logic
block and the bottom logic block. An ON execution condition will be produced for
the instruction at the right either when IR 00000 is ON and IR 00001 is OFF, or
when IR 00002 and IR 00003 are both ON. The operation of the OR LOAD instruction and its mnemonic code is exactly the same as that for an AND LOAD
instruction, except that the current execution condition is ORed with the last unused execution condition.
Logic Block Instructions in
Series
00000 00001
Instruction
00002 00003
Address Instruction Operands
00000 LD 00000
00001 AND NOT 00001
00002 LD 00002
00003 AND 00003
00004 OR LD ---
Naturally, some diagrams will require both AND LOAD and OR LOAD instructions.
To code diagrams with logic block instructions in series, the diagram must be
divided into logic blocks. Each block is coded using a LOAD instruction to code
the first condition, and then AND LOAD or OR LOAD is used to logically combine
the blocks. With both AND LOAD and OR LOAD there are two ways to achieve
this. One is to code the logic block instruction after the first two blocks and then
after each additional block. The other is to code all of the blocks to be combined,
starting each block with LOAD or LOAD NOT, and then to code the logic block
instructions which combine them. In this case, the instructions for the last pair of
blocks should be combined first, and then each preceding block should be combined, working progressively back to the first block. Although either of these
methods will produce exactly the same result, the second method, that of coding
all logic block instructions together, can be used only if eight or fewer blocks are
being combined, i.e., if seven or fewer logic block instructions are required.
72
Basic Ladder Diagrams Section 4-4
The following diagram requires AND LOAD to be converted to mnemonic code
because three pairs of parallel conditions lie in series. The two options for coding
the programs are also shown.
00000 00002 00004
00001 00003 00005
Address Instruction Operands Address Instruction Operands
00000 LD 00000
00001 OR NOT 00001
00002 LD NOT 00002
00003 OR 00003
00004 AND LD —
00005 LD 00004
00006 OR 00005
00007 AND LD —
00008 OUT 00500
00000 LD 00000
00001 OR NOT 00001
00002 LD NOT 00002
00003 OR 00003
00004 LD 00004
00005 OR 00005
00006 AND LD —
00007 AND LD —
00008 OUT 00500
00500
Again, with the method on the right, a maximum of eight blocks can be combined. There is no limit to the number of blocks that can be combined with the
first method.
The following diagram requires OR LOAD instructions to be converted to mnemonic code because three pairs of series conditions lie in parallel to each other .
00000 00001
00501
00002 00003
00040 00005
The first of each pair of conditions is converted to LOAD with the assigned bit
operand and then ANDed with the other condition. The first two blocks can be
coded first, followed by OR LOAD, the last block, and another OR LOAD; or the
three blocks can be coded first followed by two OR LOADs. The mnemonic
codes for both methods are shown below.
Address Instruction Operands Address Instruction Operands
00000 LD 00000
00001 AND NOT 00001
00002 LD NOT 00002
00003 AND NOT 00003
00004 OR LD —
00005 LD 00004
00006 AND 00005
00007 OR LD —
00008 OUT 00501
00000 LD 00000
00001 AND NOT 00001
00002 LD NOT 00002
00003 AND NOT 00003
00004 LD 00004
00005 AND 00005
00006 OR LD —
00007 OR LD —
00008 OUT 00501
Again, with the method on the right, a maximum of eight blocks can be combined. There is no limit to the number of blocks that can be combined with the
first method.
Combining AND LOAD and
OR LOAD
Both of the coding methods described above can also be used when using AND
LOAD and OR LOAD, as long as the number of blocks being combined does not
exceed eight.
73
Basic Ladder Diagrams Section 4-4
The following diagram contains only two logic blocks as shown. It is not necessary to further separate block b components, because it can be coded directly
using only AND and OR.
00000 00001 00002 00003
00201
00004
Block
a
Address Instruction Operands
00000 LD 00000
00001 AND NOT 00001
00002 LD 00002
00003 AND 00003
00004 OR 00201
00005 OR 00004
00006 AND LD —
00007 OUT 00501
Block
b
00501
Although the following diagram is similar to the one above, block b in the diagram
below cannot be coded without separating it into two blocks combined with OR
LOAD. In this example, the three blocks have been coded first and then OR
LOAD has been used to combine the last two blocks, followed by AND LOAD to
combine the execution condition produced by the OR LOAD with the execution
condition of block a.
When coding the logic block instructions together at the end of the logic blocks
they are combining, they must, as shown below , be coded in reverse order, i.e.,
the logic block instruction for the last two blocks is coded first, followed by the
one to combine the execution condition resulting from the first logic block instruction and the execution condition of the logic block third from the end, and on
back to the first logic block that is being combined.
Block
b1
00000 00001 00002 00003
00004 00202
Block
b2
Block
a
Block
b
00502
Address Instruction Operands
00000 LD NOT 00000
00001 AND 00001
00002 LD 00002
00003 AND NOT 00003
00004 LD NOT 00004
00005 AND 00202
00006 OR LD —
00007 AND LD —
00008 OUT 00502
Complicated Diagrams When determining what logic block instructions will be required to code a dia-
gram, it is sometimes necessary to break the diagram into large blocks and then
continue breaking the large blocks down until logic blocks that can be coded
without logic block instructions have been formed. These blocks are then coded,
combining the small blocks first, and then combining the larger blocks. Either
AND LOAD or OR LOAD is used to combine the blocks, i.e., AND LOAD or OR
LOAD always combines the last two execution conditions that existed, regardless of whether the execution conditions resulted from a single condition, from
logic blocks, or from previous logic block instructions.
74
Basic Ladder Diagrams Section 4-4
When working with complicated diagrams, blocks will ultimately be coded starting at the top left and moving down before moving across. This will generally
mean that, when there might be a choice, OR LOAD will be coded before AND
LOAD.
The following diagram must be broken down into two blocks and each of these
then broken into two blocks before it can be coded. As shown below, blocks a
and b require an AND LOAD. Before AND LOAD can be used, however, OR
LOAD must be used to combine the top and bottom blocks on both sides, i.e., to
combine a1 and a2; b1 and b2.
Block
a1
00000 00001 00004 00005
00002 00003
Block
a2
Block
a
Block
b1
00006 00007
Block
b2
Block
b
Address Instruction Operands
00000 LD 00000
00503
00001 AND NOT 00001
00002 LD NOT 00002
00003 AND 00003
Blocks a1 and a2
00004 OR LD —
00005 LD 00004
00006 AND 00005
00007 LD 00006
00008 AND 00007
Blocks b1 and b2
Blocks a and b
00009 OR LD —
00010 AND LD —
00011 OUT 00503
The following type of diagram can be coded easily if each block is coded in order:
first top to bottom and then left to right. In the following diagram, blocks a and b
would be combined using AND LOAD as shown above, and then block c would be
coded and a second AND LOAD would be used to combined it with the execution
condition from the first AND LOAD. Then block d would be coded, a third AND
LOAD would be used to combine the execution condition from block d with the
execution condition from the second AND LOAD, and so on through to block n.
00500
Block
a
Block
b
Block
c
Block
n
75
Basic Ladder Diagrams Section 4-4
The following diagram requires an OR LOAD followed by an AND LOAD to code
the top of the three blocks, and then two more OR LOADs to complete the mnemonic code.
00000
00004 00005
00006 00007
00002 00003
00001
00004 00005
00006 00007
00001
00002 00003
00000
LR 0000
Address Instruction Operands
00000 LD 00000
00001 LD 00001
00002 LD 00002
00003 AND NOT 00003
00004 OR LD ––
00005 AND LD ––
00006 LD NOT 00004
00007 AND 00005
00008 OR LD ––
00009 LD NOT 00006
00010 AND 00007
00011 OR LD ––
00012 OUT LR 0000
Although the program will execute as written, this diagram could be drawn as
shown below to eliminate the need for the first OR LOAD and the AND LOAD,
simplifying the program and saving memory space.
Address Instruction Operands
LR 0000
00000 LD 00002
00001 AND NOT 00003
00002 OR 00001
00003 AND 00000
00004 LD NOT 00004
00005 AND 00005
00006 OR LD ––
00007 LD NOT 00006
00008 AND 00007
00009 OR LD ––
00010 OUT LR 0000
76
00000
Block a
00001 00002
Block b
00003
00004
The following diagram requires five blocks, which here are coded in order before
using OR LOAD and AND LOAD to combine them starting from the last two
blocks and working backward. The OR LOAD at program address 00008 combines blocks blocks d and e, the following AND LOAD combines the resulting
execution condition with that of block c, etc.
Address Instruction Operands
Block dBlock c
00005
00006 00007
Block e
LR 0000
Blocks d and e
Block c with result of above
Block b with result of above
Block a with result of above
00000 LD 00000
00001 LD 00001
00002 AND 00002
00003 LD 00003
00004 AND 00004
00005 LD 00005
00006 LD 00006
00007 AND 00007
00008 OR LD ––
00009 AND LD ––
00010 OR LD ––
00011 AND LD ––
00012 OUT LR 0000
Basic Ladder Diagrams Section 4-4
Again, this diagram can be redrawn as follows to simplify program structure and
coding and to save memory space.
00006 00007
00005
00001 00002
00003 00004 00000
The next and final example may at first appear very complicated but can be
coded using only two logic block instructions. The diagram appears as follows:
00000 00001
01000 01001
00500
The first logic block instruction is used to combine the execution conditions resulting from blocks a and b, and the second one is to combine the execution condition of block c with the execution condition resulting from the normally closed
condition assigned IR 00003. The rest of the diagram can be coded with OR,
AND, and AND NOT instructions. The logical flow for this and the resulting code
are shown below.
LR 0000
Block a
00002 00003
Address Instruction Operands
00000 LD 00006
00001 AND 00007
00002 OR 00005
00003 AND 00003
00004 AND 00004
00005 LD 00001
00006 AND 00002
00007 OR LD ––
00008 AND 00000
00009 OUT LR 0000
00004 00005
00500
00006
Block cBlock b
00000 00001
LD 00000
AND 00001
OR LD
00500
OR 00500
00002 00003
AND 00002
AND NOT 00003
Block bBlock a
01000 01001
LD 01000
AND 01001
AND LD
00500
Block c
00004 00005
LD 00004
AND 00005
00006
LD 00006
Address Instruction Operands
00000 LD 00000
00001 AND 00001
00002 LD 01000
00003 AND 01001
00004 OR LD ––
00005 OR 00500
00006 AND 00002
00007 AND NOT 00003
00008 LD 00004
00009 AND 00005
00010 OR 00006
00011 AND LD ––
00012 OUT 00500
77
The Programming Console Section 4-5
4-4-7 Coding Multiple Right-hand Instructions
If there is more than one right-hand instruction executed with the same execution condition, they are coded consecutively following the last condition on the
instruction line. In the following example, the last instruction line contains one
more condition that corresponds to an AND with IR 00004.
00000 00003
00001
0000400002
HR 0000
4-5 The Programming Console
This and the next section describe the Programming Console and the operations necessary to prepare for program input.
Checking the Program
into memory.
Although the Programming Console can be used to write ladder programs, it is
primarily used to support LSS operations and is very useful for on-site editing
and maintenance. The main Programming Console functions are listed below.
1, 2, 3...
Note The Programming Console does not support all of the LSS operations, only
1. Displaying operating messages and the results of diagnostic checks.
2. Writing and reading ladder programs, inserting and deleting instructions,
searching for data or instructions, and monitoring I/O bit status.
3. Monitoring I/O status, force-setting/resetting bits.
4. The Programming Console can be connected to or disconnected from the
PC with the power on.
5. The Programming Console can be used with C-series PCs.
6. Supports TERMINAL mode, which allows the display of a 32-character
message, as well as operation of the keyboard mapping function. Refer to
5-25-6 TERMINAL MODE – TERM(––)
those required for on-site editing and maintenance.
HR
0001
00500
00506
Address Instruction Operands
00000 LD 00000
00001 OR 00001
00002 OR 00002
00003 OR HR 0000
00004 AND 00003
00005 OUT HR 0001
00006 OUT 00500
00007 AND 00004
00008 OUT 00506
4-7 Inputting, Modifying, and
describes actual procedures for inputting the program
for details.
4-5-1 The Keyboard
The keyboard of the Programming Console is functionally divided by key color
into the following four areas:
White: Numeric Keys The ten white keys are used to input numeric program data such as program
addresses, data area addresses, and operand values. The numeric keys are
also used in combination with the function key (FUN) to enter instructions with
function codes.
Red: CLR Key The CLR key clears the display and cancels current Programming Console op-
erations. It is also used when you key in the password at the beginning of programming operations. Any Programming Console operation can be cancelled
by pressing the CLR key, although the CLR key may have to be pressed two o r
three times to cancel the operation and clear the display.
Yellow: Operation Keys The yellow keys are used for writing and correcting programs. Detailed explana-
tions of their functions are given later in this section.
78
The Programming Console Section 4-5
Gray: Instruction and Data
Area Keys
Except for the SHIFT key on the upper right, the gray keys are used to input instructions and designate data area prefixes when inputting or changing a program. The SHIFT key is similar to the shift key of a typewriter , and is used to alter
the function of the next key pressed. (It is not necessary to hold the SHIFT key
down; just press it once and then press the key to be used with it.)
The gray keys other than the SHIFT key have either the mnemonic name of the
instruction or the abbreviation of the data area written on them. The functions of
these keys are described below.
Pressed before the function code when inputting an instruction
via its function code.
Pressed to enter SFT (the Shift Register instruction).
Input either after a function code to designate the differentiated
form of an instruction or after a ladder instruction to designate
an inverse condition.
Pressed to enter AND (the AND instruction) or used with NOT
to enter AND NOT.
Pressed to enter OR (the OR instruction) or used with NOT to
enter OR NOT.
Pressed to enter CNT (the Counter instruction) or to designate
a TC number that has already been defined as a counter.
Pressed to enter LD (the Load instruction) or used with NOT to
enter LD NOT. Also pressed to indicate an input bit.
Pressed to enter OUT (the Output instruction) or used with
NOT to enter OUT NOT. Also pressed to indicate an output bit.
Pressed to enter TIM (the Timer instruction) or to designate a
TC number that has already been defined as a timer.
Pressed before designating an address in the TR area.
Pressed before designating an address in the LR area.
Pressed before designating an address in the HR area.
Pressed before designating an address in the AR area.
Pressed before designating an address in the DM area.
Pressed before designating an indirect DM address.
Pressed before designating a word address.
Pressed before designating an operand as a constant.
Pressed before designating a bit address.
Pressed before function codes for block programming instructions, i.e., those placed between pointed parentheses <>.
79
Preparation for Operation Section 4-6
4-5-2 PC Modes
The Programming Console is equipped with a switch to control the PC mode. To
select one of the three operating modes—RUN, MONITOR, or PROGRAM—
use the mode switch. The mode that you select will determine PC operation as
well as the procedures that are possible from the Programming Console.
RUN mode is the mode used for normal program execution. When the switch is
set to RUN and the START input on the CPU Power Supply Unit is ON, the CPU
will begin executing the program according to the program written in its Program
Memory. Although monitoring PC operation from the Programming Console is
possible in RUN mode, no data in any of the memory areas can be input or
changed.
MONITOR mode allows you to visually monitor in-progress program execution
while controlling I/O status, changing PV (present values) or SV (set values),
etc. In MONITOR mode, I/O processing is handled in the same way as in RUN
mode. MONITOR mode is generally used for trial system operation and final program adjustments.
In PROGRAM mode, the PC does not execute the program. PROGRAM mode
is for creating and changing programs, clearing memory areas, and registering
and changing the I/O table. A special Debug operation is also available within
PROGRAM mode that enables checking a program for correct execution before
trial operation of the system.
DANGER Do not leave the Programming Console connected to the PC by an extension cable when in
!
RUN mode. Noise picked up by the extension cable can enter the PC, affecting the program
and thus the controlled system.
4-5-3 The Display Message Switch
Pin 3 of the CPU’s DIP switch determines whether Japanese or English language messages will be displayed on the Programming Console. It is factory set
to ON, which causes English language messages to be displayed.
4-6 Preparation for Operation
This section describes the procedures required to begin Programming Console
operation. These include password entry, clearing memory, error message
clearing, and I/O table operations. I/O table operations are also necessary at
other times, e.g., when changes are to be made in Units used in the PC configuration.
DANGER Always confirm that the Programming Console is in PROGRAM mode when turning on the
!
PC with a Programming Console connected unless another mode is desired for a specific
purpose. If the Programming Console is in RUN mode when PC power is turned on, any
program in Program Memory will be executed, possibly causing a PC-controlled system to
begin operation.
80
1, 2, 3...
The following sequence of operations must be performed before beginning initial program input.
1. Insert the mode key into the Programming Console.
2. Set the mode switch to PROGRAM mode. (The mode key cannot be removed while set to PROGRAM mode.)
3. Turn on PC power.
Note When I/O Units are installed, turn on those Units also. The Program-
ming Console will not operate if these Units are not turned on.
Preparation for Operation Section 4-6
4. Confirm that the CPU’s POWER LED is lit and the following display appears
on the Programming Console screen. (If the ALM/ERR LED is lit or flashing
or an error message is displayed, clear the error that has occurred.)
<PROGRAM>
PASSWORD!
5. Enter the password. See
6. Clear memory. Skip this step if the program does not need to be cleared.
4-6-3 Clearing Memory
See
4-6-1 Entering the Password
To gain access to the PC’ s programming functions, you must first enter the password. The password prevents unauthorized access to the program.
The PC prompts you for a password when PC power is turned on or, if PC power
is already on, after the Programming Console has been connected to the PC. To
gain access to the system when the “Password!” message appears, press CLR
and then MONTR. Then press CLR to clear the display.
If the Programming Console is connected to the PC when PC power is already
on, the first display below will indicate the mode the PC was in before the Programming Console was connected. Ensure that the PC is in PROGRAM mode
before you enter the password. When the password is entered, the PC will
shift to the mode set on the mode switch, causing PC operation to begin if the
mode is set to RUN or MONITOR. The mode can be changed to RUN or MONITOR with the mode switch after entering the password.
4-6-1 Entering the Password
for details.
for details.
4-6-2 Buzzer
<PROGRAM>
PASSWORD!
<PROGRAM> BZ
Indicates the mode set by the mode selector switch.
Immediately after the password is input or anytime immediately after the mode
has been changed, SHIFT and then the 1 key can be pressed to turn on and off
the buzzer that sounds when Programming Console keys are pressed. If BZ is
displayed in the upper right corner, the buzzer is operative. If BZ is not displayed,
the buzzer is not operative.
This buzzer also will also sound whenever an error occurs during PC operation.
Buzzer operation for errors is not affected by the above setting.
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Preparation for Operation Section 4-6
4-6-3 Clearing Memory
Using the Memory Clear operation it is possible to clear all or part of the UM area
(RAM or EEPROM), and the IR, HR, AR, DM and TC areas. Unless otherwise
specified, the clear operation will clear all of the above memory areas. The UM
area will not be cleared if the write-protect switch (pin 1 of the CPU’s DIP switch)
is set to ON.
Before beginning to programming for the first time or when installing a new program, all areas should normally be cleared. Before clearing memory, check to
see if a program is already loaded that you need. If you need the program, clear
only the memory areas that you do not need, and be sure to check the existing
program with the program check key sequence before using it. The check sequence is provided later in this section. Further debugging methods are provided in
press CLR until all zeros are displayed, and then input the keystrokes given in
the top line of the following key sequence. The branch lines shown in the sequence are used only when performing a partial memory clear, which is described below.
Memory can be cleared in PROGRAM mode only. The following table shows
which memory areas will be cleared for the 3 memory clearing operations (all
clear, partial clear, memory clear).
I/O words Cleared Cleared Cleared
Work words Cleared --- Cleared
HR, AR, TC, DM, fixed DM Cleared Cleared Cleared
Expansion DM Cleared --- Cleared
I/O comments Cleared --- --Ladder program Cleared Cleared Cleared
UM Allocation information Cleared --- ---
Section 7 Program Monitoring and Execution
Memory Area All clear Partial clear Memory clear
. To clear all memory areas
Note 1. The error history area (DM 6000 to DM 6030) will not be cleared when the
DM area is cleared.
2. When the PC Setup area (DM 6600 to DM 6655 in fixed DM) is cleared, the
settings will be returned to their factory-set defaults.
3. When the All Clear operation is executed, the ladder program area will be
allocated entirely to the ladder program. (The expansion DM and I/O comment areas will be set to 0 KW.)
All Clear The key sequence for all clear is shown below.
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Preparation for Operation Section 4-6
The following procedure is used to clear memory completely.
MEMORY ERR
I/O VER ERR
Continue pressing
the CLR key once for
each error message
until “00000” appears
on the display
00000
00000
00000MEMORY CLR?
HR CNT DM
00000MEM ALLCLR?
All clear
00000MEM ALLCLR
END
Partial Clear It is possible to retain the data in specified areas or part of the ladder program. To
retain the data in the HR and AR, TC, and/or DM areas, press the appropriate
key after entering REC/RESET. HR is pressed to designate both the HR and AR
areas. In other words, specifying that HR is to be retained will ensure that AR is
retained also. If not specified for retention, both areas will be cleared. CNT is
used for the entire TC area. The display will show those areas that will be
cleared.
It is also possible to retain a portion of the ladder program from the beginning to a
specified address. After designating the data areas to be retained, specify the
first program address to be cleared. For example, to leave addresses 00000 to
00122 untouched, but to clear addresses from 00123 to the end of Program
Memory, input 00123.
The key sequence for a partial memory clear is shown below.
Program Memory cleared
from designated address.
Both AR and HR areas
TC area
DM area
Retained if pressed
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Preparation for Operation Section 4-6
To leave the TC area uncleared and retain Program Memory addresses 00000
through 00122, input as follows:
00000
00000
00000
00000MEMORY CLR?
HR CNT DM
00000MEMORY CLR?
HR DM
00123MEMORY CLR?
HR DM
00000MEMORY CLR
END HR DM
Memory Clear The memory clear operation clears all memory areas except the I/O comments
and UM Allocation information.
The key sequence for a partial memory clear is shown below.
The Programming Console will display the following screens:
00000
00000
00000
00000MEMORY CLR?
HR CNT DM
00000MEMORY CLR
END HR CNT DM
Note When the write-protect switch (pin 1 of the CPU’s DIP switch) is set to ON the UM
area (from DM 6144 through the ladder program) will not be cleared. Other data
areas, such as HR, AR, CNT, and DM from DM 0000 to DM 6143 will be cleared.
4-6-4 Registering the I/O Table
The I/O Table Registration operation records the types of I/O Units controlled by
the PC and the Rack locations of the I/O Units. It also clears all I/O bits.
It is not absolutely necessary to register the I/O table with the C200HS. When the
I/O table has not been registered, the PC will operate according to the I/O Units
mounted when power is applied. The I/O verification/setting error will not occur.
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Preparation for Operation Section 4-6
It is necessary to register the I/O table if I/O Units are changed, otherwise an I/O
verification error message, “I/O VER ERR” or “I/O SET ERROR”, will appear
when starting programming operations.
I/O Table Registration can be performed only in PROGRAM mode with the writeprotection switch (pin 1 of the CPU’s DIP switch) set to OFF (OFF=“WRITE”).
Group-2 HIgh-density I/O Units will not be displayed in the I/O table when it is
displayed using a host computer. Four asterisks (∗∗∗∗), indicating no Unit, will be
displayed instead.
Key Sequence
Initial I/O Table Registration
00000
00000
FUN (??)
00000IOTBL ?
?-?U=
00000IOTBL WRIT
????
00000IOTBL WRIT
9713
00000IOTBL WRIT
OK
4-6-5 Clearing Error Messages
After the I/O table has been registered, any error messages recorded in memory
should be cleared. It is assumed here that the causes of any of the errors for
which error messages appear have already been taken care of. If the beeper
sounds when an attempt is made to clear an error message, eliminate the cause
of the error, and then clear the error message (refer to
).
ing
To display any recorded error messages, press CLR, FUN, and then MONTR.
The first message will appear. Pressing MONTR again will clear the present
message and display the next error message. Continue pressing MONTR until
all messages have been cleared.
Although error messages can be accessed in any mode, they can be cleared
only in PROGRAM mode.
Register I/O table
Section 10 Troubleshoot-
Key Sequence
85
Preparation for Operation Section 4-6
4-6-6 Verifying the I/O Table
The I/O Table Verification operation is used to check the I/O table registered in
memory to see if it matches the actual sequence of I/O Units mounted. The first
inconsistency discovered will be displayed as shown below. Every subsequent
pressing of VER displays the next inconsistency.
Note This operation can be executed only when the I/O table has been registered.
Key Sequence
Example
00000
00000
FUN (??)
00000IOTBL ?
?-?U=
00000IOTBL CHK
(No errors)
OK
00000IOTBL CHK
0-1U=O*** I***
(An error occurred)
Actual I/O words
Registered I/O table words
I/O slot number
Rack number
Meaning of Displays The following display indicates a C500, C1000H, or C2000H and C200H or
C200HS have the same unit number on a Remote I/O Slave Rack.
00000I/OTBL CHK
*-*U=----
86
The following display indicates a duplication in Optical I/O Unit unit numbers.
00000I/OTBL CHK
2**HU=R*-I R*-W
Indicates duplication
Preparation for Operation Section 4-6
4-6-7 Reading the I/O Table
The I/O Table Read operation is used to access the I/O table that is currently
registered in the CPU memory. This operation can be performed in any PC
mode.
Key Sequence
[0 to 2] [0 to 9]
Rack
number
Press the EXT key to select Remote
I/O Slave Racks or Optical I/O Units.
Unit
number
Example
00000
00000
FUN (??)
00000IOTBL ?
?-?U=
(Slave Rack Units)
00000IOTBL ?
R??-?U=
(Optical I/O Unit)
00000IOTBL ?
2??LU=
00000IOTBL ?
?-?U=
00000IOTBL ?
0-?U=
00000IOTBL ?
0-5U=
(Main Rack)
(Main Rack)
00000IOTBL READ
0-5U=i*** 005
00000IOTBL READ
0-4U=o*** 004
00000IOTBL READ
0-5U=i*** 005
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