OKI MSM83C154S-xxxTS-K, MSM83C154S-xxxJS, MSM80C154STS-K, MSM80C154SJS, MSM83C154S-xxxRS Datasheet

E2E1023-27-Y3

This version: Jan. 1998

MSM80C154S/83C154S¡ Semiconductor

¡ Semiconductor

Previous version: Nov. 1996

MSM80C154S/83C154S

CMOS 8-bit Microcontroller

GENERAL DESCRIPTION

The MSM80C154S/MSM83C154S, designed for the high speed version of the existing
MSM80C154/MSM83C154, is a higher performance 8-bit microcontroller providing low-power
consumption.
The MSM80C154S/MSM83C154S covers the functions and operating range of the existing
MSM80C154/83C154/80C51F/80C31F.
The MSM80C154S is identical to the MSM83C154S except it does not contain the internal
program memory (ROM).

FEATURES

• Operating range
Operating frequency : 0 to 3 MHz (Vcc=2.2 to 6.0 V)

0 to 12 MHz (Vcc=3.0 to 6.0 V)
0 to 24 MHz (Vcc=4.5 to 6.0 V)

Operating voltage : 2.2 to 6.0 V

Operating temperature : –40 to +85°C (Operation at +125°C conforms to

the other specification.)

• Fully static circuit

• Upward compatible with the MSM80C51F/80C31F

• On-chip program memory : 16K words x 8 bits ROM (MSM83C154S only)

• On-chip data memory : 256 words x 8 bits RAM

• External program memory address space : 64K bytes ROM (Max)

• External data memory address space : 64K bytes RAM

• I/O ports : 4 ports x 8 bits

(Port 1, 2, 3, impedance programmable) : 32

• 16-bit timer/counters : 3

• Multifunctional serial port : I/O Expansion mode

: UART mode (featuring error detection)

• 6-source 2-priority level

Interrupt and multi-level
Interrupt available by programming IP and IE registers

• Memory-mapped special function registers

• Bit addressable data memory and SFRs

• Minimum instruction cycle : 500 ns @ 24 MHz operation

• Standby functions : Power-down mode (oscillator stop)

Activated by software or hardware; providing
ports with floating or active status
The software power-down stet mode is termi­nated by interrupt signal enabling execution from
the interrupted address.

1/40

MSM80C154S/83C154S¡ Semiconductor

• Package options

40-pin plastic DIP (DIP40-P-600-2.54) :

44-pin plastic QFP (QFP44-P-910-0.80-2K) :

44-pin QFJ (QFJ44-P-S650-1.27) : (Product name: MSM80C154SJS/

44-pin TQFP (TQFP44-P-1010-0.80-K) : (Product name: MSM80C154STS-K/

(Product name: MSM80C154SRS/

MSM83C154S-xxxRS)

(Product name: MSM80C154SGS-2K/

MSM83C154S-xxxGS-2K)

MSM83C154S

MSM83C154S-xxxTS-K)

xxx: indicates the code number

-xxx

JS)

2/40

3/40

MSM80C154S/83C154S¡ Semiconductor

T2CON

PCH

CONTROL SIGNAL

SPECIAL
FUNCTION
REGISTER

ADDRESS
DECODER

PLA

IR AIR

C-ROM

TR1

TR2ACC

ALU

BR

PSW

RAMDP

R/W AMP

RAM

256 WORDS

x 8BITS

TH2

RCAP2H

RCAP2L

DPH

PCL

SP

ROM

16K WORDS x 8BITS

SENSE AMP

DPL

PCLL

PORT 2PORT 0

PCONIOCON

OSC and TIMING

PORT 1PORT 3

P2.0

P2.7

P0.0

P0.7

P1.0

P1.7

P3.0

P3.7

XTAL1

XTAL2

ALE

RESET

PSEN

EA

TH1 TL1 TH0 TL0 TMOD TCON IE IP SBUF(T) SBUF(R)

INTERRUPT

TIMER/COUNTER 0 & 1

SERIAL IO

SCON

SIGNALR/W

TIMER/

COUNTER 2

PCHL

ADDRESS DECODER

TL2

BLOCK DIAGRAM (MSM83C154S)

PIN CONFIGURATION (TOP VIEW)

MSM80C154S/83C154S¡ Semiconductor

P1.0/T2

P1.1/T2EX

P1.2
P1.3
P1.4

P1.5
P1.6
P1.7

RESET

P3.0/RXD

P3.1/TXD
P3.2/INT0
P3.3/INT1

P3.4/T0

P3.5/T1/HPDI

P3.6/WR

P3.7/RD

XTAL2
XTAL1

V

SS

10
11
12
13
14
15
16
17
18

19
20

1
2
3
4
5

6
7
8
9

40
39
38
37
36

35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

V

CC

P0.0
P0.1
P0.2
P0.3

P0.4
P0.5
P0.6
P0.7

EA

ALE

PSEN

P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0

40-Pin Plastic DIP

4/40

PIN CONFIGURATION (Continued)

P1.4

P1.3

44

43

P1.2
42

P1.1
41

P1.0NCV
40

39

CC

38

P0.0

37

P0.1
36

P0.2
35

MSM80C154S/83C154S¡ Semiconductor

P0.3
34

P1.5
P1.6
P1.7

RESET

P3.0/RXD

NC

P3.1/TXD
P3.2/INT0
P3.3/INT1

P3.4/T0

P3.5/T1/HPDI

10
11

1
2
3
4
5
6
7
8
9

12

13

14

15

16

17

18

19

20

21

22

SSVSS

P3.7/RD

P3.6/WR

XTAL2

XTAL1

V

P2.0

P2.1

P2.2

P2.3

P2.4

33
32
31
30
29
28
27
26
25
24
23

P0.4
P0.5
P0.6
P0.7
EA
NC
ALE
PSEN
P2.7
P2.6
P2.5

NC : No-connection pin

44-Pin Plastic QFP

5/40

P1.4
44

P1.3
43

P1.2
42

P1.1
41

P1.0NCV
40

39

CC

38

P0.0
37

P0.1
36

P0.2
35

MSM80C154S/83C154S¡ Semiconductor

P0.3
34

P1.5
P1.6
P1.7

RESET

P3.0/RXD

NC

P3.1/TXD
P3.2/INT0
P3.3/INT1

P3.4/T0

P3.5/T1/HPDI

10
11

1
2
3
4
5
6
7
8
9

12

13

14

15

16

17

18

19

20

21

22

SSVSS

P3.7/RD

P3.6/WR

XTAL2

XTAL1

V

P2.0

P2.1

P2.2

P2.3

P2.4

33
32
31
30
29
28
27
26
25
24
23

P0.4
P0.5
P0.6
P0.7
EA
NC
ALE
PSEN
P2.7
P2.6
P2.5

NC : No-connection pin

44-Pin Plastic TQFP

6/40

PIN CONFIGURATION (Continued)

P0.5
38

P0.6
37

P0.4
39

P0.7EANC
36

35

34

ALE

33

PSEN

32

P2.7

31

P2.6

30

MSM80C154S/83C154S¡ Semiconductor

P2.5
29

P0.3
P0.2
P0.1
P0.0

V

CC

NC

P1.0/T2

P1.1/T2EX

P1.2
P1.3
P1.4

40
41
42
43
44

P2.4

28
27

P2.3

26

P2.2

25

P2.1

24

P2.0
1
2
3
4
5
6

7

8

9

10

11

12

13

14

15

16

17

P1.5

P1.6

P1.7

RESET

NC

P3.0/RXD

P3.1/TXD

P3.2/INT0

P3.4/T0

P3.3/INT1

P3.5/T1/HPDI

23
22
21
20
19
18

NC

V

SS

XTAL1

XTAL2

P3.7/RD

P3.6/WR

NC : No-connection pin

44-Pin Plastic QFJ

7/40

PIN DESCRIPTIONS

Symbol Descriptipn

P0.0 to P0.7

Bidirectional I/O ports. They are also the data/address bus (input/output of data and output of
lower 8-bit address when external memory is accessed).
They are open-drain outputs when used as I/O ports, but 3-state outputs when used as data/address
bus.

MSM80C154S/83C154S¡ Semiconductor

P1.0 to P1.7

P2.0 to P2.7

P3.0 to P3.7

P1.0 to P1.7 are quasi-bidirectional I/O ports. They are pulled up internally when used as input
ports. Two of them have the following secondary functions:

•P1.0 (T2)

•P1.1 (T2EX)

P2.0 to P2.7 are quasi-bidirectional I/O ports. They also output the higher 8-bit address when
an external memory is accessed. They are pulled up internally when used as input ports.

P3.0 to P3.7 are quasi-bidirectional I/O ports. They are pulled up internally when used as input
ports. They also have the following secondary functions:

•P3.0 (RXD)
Serial data input/output in the I/O expansion mode and serial data input in the UART mode when

the serial port is used.

•3.1 (TXD)
Synchronous clock output in the I/O expansion mode and serial data output in the UART mode
when the serial port is used.

•3.2 (INT0)
Used as input pin for the external interrupt 0, and as count-up control pin for the timer/counter 0.

•3.3 (INT1)
Used as input pin for the external interrupt 1, and as count-up control pin for the timer/counter 1.

•3.4 (T0)
Used as external clock input pin for the timer/counter 0.

•3.5 (T1)
Used as external clock input pin for the timer/counter 1 and power-down-mode control input pin.

•3.6 (WR)
Output of the write-strobe signal when data is written into external data memory.

•3.7 (RD)
Output of the read-strobe signal when data is read from external data memory.

: used as external clock input pins for the timer/counter 2.
: used as trigger input for the timer/counter 2 to be reloaded or captured;
causing the timer/counter 2 interrupt.

ALE

PSEN

EA

Address latch enable output for latching the lower 8-bit address during external memory access.
Two ALE pulses are activated per machine cycle except during external data memory access at
which time one ALE pulse is skipped.

Program store enable output which enables the external memory output to the bus during external
program memory access. Two PSEN pulses are activated per machine cycle except during
external data memory access at which two PSEN pulses are skipped.

When EA is held at "H" level, the MSM 83C154S executes instructions from internal program
memory at address 0000H to 3FFFH, and executes instructions from external program memory
above address 3FFFH.
When EA is held at "L" level, the MSM80C154S/MSM83C154S executes instructions from external
program memory for all addresses.

8/40

PIN Descriptions (Continued)

Symbol Descriptipn

RESET

If this pin remains "H" for at least one machine cycle, the MSM80C154S/MSM83C154S is reset.
Since this pin is pulled down internally, a power-on reset is achieved by simply connecting a
capacitor between V

and this pin.

CC

MSM80C154S/83C154S¡ Semiconductor

XTAL1
XTAL2
V

CC

V

SS

Oscillator inverter input pin. External clock is input through XTAL1 pin.
Oscillator inverter output pin.
Power supply pin during both normal operation and standby operations.
GND pin.

9/40

REGISTERS

Diagram of Special Function Registers

MSM80C154S/83C154S¡ Semiconductor

REGISTER

NAME

IOCON

B

ACC

PSW

TH2

TL2

RCAP2H

RCAP2L

T2CON

IP

P3

IE

P2

SBUF

SCON

P1
TH1
TH0

TL1
TL0

TMOD

TCON
PCON

DPH

DPL

SP

P0

b7 b5 b4 b3 b2 b1 b0b6
FF

F7
E7
D7

CF
BF
B7
AF
A7

9F
97

8F

87

FE
F6
E6

D6

CE
BE
B6
AE
A6

9E
96

8E

86

BIT ADDRESS

FD
F5
E5
D5

CD
BD
B5
AD
A5

9D
95

8D

85

FC
F4
E4
D4

CC
BC
B4
AC
A4

9C
94

8C

84

FB
F3
E3
D3

CB
BB
B3
AB
A3

9B
93

8B

83

FA
F2
E2
D2

CA
BA
B2
AA
A2

9A
92

8A

82

F9
F1
E1

D1

C9
B9
B1
A9
A1

99
91

89

81

F8
F0
E0

D0

C8
B8
B0
A8
A0

98
90

88

80

DIRECT

ADDRESS

0F8H (248)
0F0H (240)
0E0H (224)

0D0H (208)

0CDH (205)

0CCH (204)
0CBH (203)
0CAH (202)
0C8H (200)
0B8H (184)
0B0H (176)
0A8H (168)
0A0H (160)

99H (153)
98H (152)
90H (144)
8DH (141)
8CH (140)
8BH (139)
8AH (138)
89H (137)
88H (136)
87H (135)
83H (131)
82H (130)
81H (129)
80H (128)

10/40

Special Function Registers

Timer mode register (TMOD)

MSM80C154S/83C154S¡ Semiconductor

NAME

TMOD 89H GATE C/T M1 M0 GATE C/T M1 M0

BIT LOCATION FLAG FUNCTION

TMOD.0 M0 M1 M0

TMOD.2 C/T

TMOD.3 GATE

TMOD.4 M0 M1 M0

TMOD.5 M1

TMOD.6 C/T

TMOD.7 GATE

ADDRESS

MSB LSB

76543210

Timer/counter 0 mode setting
00
01
10
11TMOD.1 M1

Timer/counter 0 count clock designation control bit.
XTAL1•2 divided by 12 clocks is the input applied to timer/counter 0 when
C/T = "0".
The external clock applied to the T0 pin is the input applied to timer/counter 0
when C/T = "1".

When this bit is "0", the TR0 bit of TCON (timer control register) is used to
control the start and stop of timer/counter 0 counting.
If this bit is "1", timer/counter 0 starts counting when both the TR0 bit of TCON
and INT0 pin input signal are "1", and stops counting when either is changed
to "0".

00
01
10
11

Timer/counter 1 count clock designation control bit.
XTAL1•2 divided by 12 clocks is the input applied to timer/counter 1 when
C/T = "0".
The external clock applied to the T1 pin is the input applied to timer/counter 1
when C/T = "1".

When this bit is "0", the TR1 bit of TCON is used to control the start and stop of
timer/counter 1 counting.
If this bit is "1", timer/counter 1 starts counting when both the TR1 bit of TCON
and INT1 pin input signal are "1", and stops counting when either is changed
to "0".

8-bit timer/counter with 5-bit prescalar.

16-bit timer/counter.

8-bit timer/counter with 8-bit auto reloading.

Timer/counter 0 separated into TLO (8-bit) timer/counter

and TH0 (8-bit) timer/counter. TF0 is set by TL0 carry, and

TF1 is set by TH0 carry.

Timer/counter 1 mode setting

8-bit timer/counter with 5-bit prescalar.

16-bit timer/counter

8-bit timer/counter with 8-bit auto reloading.

Timer/counter 1 operation stopped.

11/40

Power control register (PCON)

MSM80C154S/83C154S¡ Semiconductor

NAME

PCON 87H SMOD HPD RPD — GF1 GF0 PD IDL

BIT LOCATION FLAG FUNCTION

PCON.0 IDL

PCON.1 PD

PCON.5 RPD

ADDRESS

MSB LSB

76543210

IDLE mode is set when this bit is set to "1". CPU operations are stopped when
IDLE mode is set, but XTAL1•2, timer/counters 0, 1 and 2, the interrupt circuits,
and the serial port remain active. IDLE mode is cancelled when the CPU is reset
or when an interrupt is generated.

PD mode is set when this bit is set to "1". CPU operations and XTAL1•2 are
stopped when PD mode is set. PD mode is cancelled when the CPU is reset or
when an interrupt is generated.

General purpose bit.PCON.2 GF0
General purpose bit.PCON.3 GF1
Reserved bit. The output data is "1", if the bit is read.PCON.4 —
This bit is used to specify cancellation of CPU power down mode (IDLE or PD) by an

interrupt signal.
Power-down mode cannot be cancelled by an interrupt signal if the interrupt is not
enabled by IE (interrupt enable register) when this bit is "0".
If the interrupt flag is set to "1" by an interrupt request signal when this bit is
"1" (even if interrupt is disabled), the program is executed from the next address
of the power-down-mode setting instruction.
The flag is reset to "0" by software.

PCON.6 HPD

PCON.7 SMOD

The hard power-down setting mode in enabled when this bit is set to "1".
If the level of the power failure detect signal applied to the HPDI pin (pin 3.5)
is changed from "1" to "0" when this bit is "1", XTAL1•2 oscillation is stopped and
the system is put into hard power down mode. HPD mode is cancelled when the
CPU is reset.

When the timer/counter 1 carry signal is used as a clock in mode 1, 2 or 3 of
the serial port, this bit has the following functions.
The serial port operation clock is reduced by 1/2 when the bit is "0" for delayed
processing. When the bit is "1", the serial port operation clock is normal
for faster processing.

12/40