OKI MSM6882-5GS-K, MSM6882-3GS-K, MSM6882-5RS, MSM6882-3RS Datasheet

E2A0035-16-X0

¡ Semiconductor MSM6882-3/6882-5

¡ Semiconductor

This version: Jan. 1998

Previous version: Nov. 1996

MSM6882-3/6882-5

2400/1200 bps Single Chip MSK Modem

GENERAL DESCRIPTION

The MSM6882-3/6882-5 is a single chip MSK (Minimum Shift Keying) modem which is fabricated
by Oki’s low power consumption CMOS silicon gate technology.
The demodulator receives the data to be transmitted (SD) synchronized with the transmit timing
clock (ST) generated by the on-chip clock generator. The signal, which is modulated by MSK method,
is output.
The demodulator converts the received MSK signal to the received data (RD) by means of a delay
detection technique after limiting the band of the received MSK signal. This signal is input to the
digital PLL and the re-generated timing clock (RT) is output from the demodulator, synchronized
with the RD.

FEATURES

• Signal power supply:+3.6 V (MSM6882-3)
+5 V (MSM6882-5)

• On-chip SCF (Switched Capacitor Filter)

• The transmit filter can be also used as voice splatter filter.

• The receive timing re-generator has two different lock-in time performance options to be chosen

from.

• Bit rate 2400/1200 bps

• CCIR Rec. 623

• The modulation method can be selected from COS-FFSK and SIN-FFSK.

• Built-in crystal oscillation circuit.

• Package options:

22-pin plastic DIP (DIP22-P-400-2.54) (Product name: MSM6882-3RS)

(Product name: MSM6882-5RS)

24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name: MSM6882-3GS-K)

(Product name: MSM6882-5GS-K)

1/15

¡ Semiconductor MSM6882-3/6882-5

BLOCK DIAGRAM

ST

SD

PRE

SIN

Modu-

lator

1

0

RC

LPF

Transmit

LPF

1

0

RC

LPF

FT

AO

ME

BR

TI

CF

RT

RD

CT

MCS

X1

Timing

Re-generator

Mixer

PDF

*

Clock

Generator

PRE

LPF

LIM

Delay

Detector

Receive

RC

LPF

Signal

Ground

BPF

SH

0

1

AI

V

DD

GND

X2

* Post Detection Filter

SG

2/15

¡ Semiconductor MSM6882-3/6882-5

PIN CONFIGURATION (TOP VIEW)

1

X1

2 21X2 FT

3

4

5

6

7

8

9

10

22

V

DD

20MCS CT

19ME CF

18SD RT

17ST RD

16SIN CDO

15PRE CDT

14BR AI

13SG AO

1

X1

2

X2

3

MCS

4

ME

5

SD

6

ST

7

SIN

8

PRE

9

BR

10 15SG AI

11

12

24

V

23

FT

22

CT

21

CF

20

RT

19

(NC)

18

RD

17

CDO

16

CDT

14GND AO

13GND TI

DD

11

GND

22-Pin Plastic DIP

NC : No connect pin

12

TI

24-Pin Plastic SOP

3/15

¡ Semiconductor MSM6882-3/6882-5

PIN DESCRIPTION

Name Description

X1

X2

Crystal connection pins.
A 3.6864 MHz or 7.3728 MHz crystal shall be connected.
When an external clock is applied for MSM6882's oscillation source, it has to be input to X2.
In this case, X2 has to be AC-coupled by the capacitor of 200 pF. X1 shall be left open.

Master clock selection.

MCS

ME

SD

ST

MCS

Modulator enable.
When a "high" is input on this pin, MSK modulator output is connected to the input of transmit
LPF.
When a "low" is input on this pin, TI is connected to the input of transmit LPF.

Send data input.
The data on this pin is synchronized with the rising edge of ST and input to MSK modulator
as an actual transmit data.

This timing signal is used to latch serial input data on the SD pin.
The frequency of ST coincides with the transmission bit rate.

Modulation method selection.
Data put on this pin selects either SINE FAST FSK or COSINE FAST FSK.

Crystal or External Clock
0 3.6864 MHz
1 7.3728 MHz

SD

ST

MSK Modulated Data

SIN

PRE

Data (2400 bps)

Sine Fast FSK

Cosine Fast FSK

Preamble or data transmission selection.
When a "low" is input on this pin, the data put on the SD pin is output on the AO pin.
When a "high" is input on this pin, the data put on the SD pin is neglected and preamble data
is output.
Data put on PRE is latched on the rising edge of ST.
Preamble means to modulate as 010101...pattern.

010011

4/15

¡ Semiconductor MSM6882-3/6882-5

Name Description

Baud rate selection.

BR

SG

TI

Master Clock

(MHz)

7.3728

3.6864

3.6864

MCS BR

11
10
00
11
10

Bit Rate

(bps)

2400
1200
1200
1200

600

Carrier Freq. (Hz)
Mark Space
1200
1200
1200

600
600

2400
1800
1800
1200

900

Built-in analog signal ground.
The DC voltage is approximately half of V

, so the analog interfaces signals of AI, AO, and TI

DD

with peripheral circuits which must be implemented by AC-coupling. To make this voltage
source impedance lower and ensure the device performance of this device, more than 0.1 mF
bypass capacitors should be connected from SG to GND and from SG to V

DD

.

Ground. (0 V)GND

Voice signal input.
The signal input to this pin can be sent out to AO through the transmit LPF, the characteristics
of which, gives the splatter filter for voice band signal.
When this function is used, digital "0" must be input to ME.
TI is biased to SG through internal resistor.

Transmit analog signal output.
The data put on ME and FT can set the status of AO as follows.

AO

FT

"1" "1"

ME Transmit LPF State of AO

MSK Signal

Power On

"1" "0" Voice Signal
"0" "1" The Output of Receive BPF

Power Down

"0" "0" No-signal (SG level)

TI

Power down

Transmit LPF

+
–

AO

AI

SD

Modu-

lator

SG

Receive BPF

The state when FT and ME = "0" is shown above. When the input digital data on FT changes to
"1" from "0", AO remains to be connected to SG during about 2 ms and after that, and AO is
switched to transmit LPF.
This delay time prevents AO from outputting meaningless signal during transient time from
power down to on of LPF.

5/15