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MSM5117805B-50TS-L
Datasheet
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OKI MSM5117805B-70TS-L, MSM5117805B-70JS, MSM5117805B-50TS-L, MSM5117805B-50JS, MSM5117805B-70TS-K Datasheet

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263
¡ Semiconductor MSM5117805B
DESCRIPTION
The MSM5117805B is a 2,097,152-word ¥ 8-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM5117805B achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM5117805B is available in a 28-pin plastic SOJ or 28-pin plastic TSOP.
FEATURES
• 2,097,152-word ¥ 8-bit configuration
• Input : TTL compatible, low input capacitance
• Output : TTL compatible, 3-state
• Refresh : 2048 cycles/32 ms
• Fast page mode with EDO, read modify write capability
• CAS before RAS refresh, hidden refresh, RAS-only refresh capability
• Multi-bit test mode capability
• Package options: 28-pin 400 mil plastic SOJ (SOJ28-P-400-1.27) (Product : MSM5117805B-xxJS) 28-pin 400 mil plastic TSOP (TSOPII28-P-400-1.27-K) (Product : MSM5117805B-xxTS-K)
(TSOPII28-P-400-1.27-L) (Product : MSM5117805B-xxTS-L)
xx indicates speed rank.
PRODUCT FAMILY
¡ Semiconductor
MSM5117805B
2,097,152-Word ¥ 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
MSM5117805B-70
70 ns
130 ns
90 ns
605 mW
825 mW
Family
Access Time (Max.)
Cycle Time
(Min.)
Standby (Max.)
Power Dissipation
MSM5117805B-50
t
RAC
50 ns
35 ns
t
AA
25 ns
20 ns
t
CAC
13 ns
20 ns
t
OEA
13 ns
MSM5117805B-60
60 ns
110 ns 715 mW
30 ns 15 ns 15 ns
Operating (Max.)
5.5 mW
E2G0047-17-41
264
MSM5117805B ¡ Semiconductor
PIN CONFIGURATION (TOP VIEW)
3
4
5
9
10
11
12
13
DQ2
DQ3
DQ4
A10R
A0
A1
A2
A3
26
25
24
20
19
18
17
16
DQ7
DQ6
DQ5
A8
A7
A6
A5
A4
2
DQ1 27 DQ8
1
V
CC
28 V
SS
28-Pin Plastic SOJ
3
4
5
9
10
11
12
13
26
25
24
20
19
18
17
16
2
27
1
28
26
25
24
20
19
18
17
16
3
4
5
9
10
11
12
13
27
2
28
1
28-Pin Plastic TSOP
(K Type)
28-Pin Plastic TSOP
(L Type)
6WE 23 CAS 23 23 6
8NC 21 A9 21 21 8
6
8
7RAS 22 OE 22 22 77
14V
CC
15 V
SS
14 15 15 14
DQ2
DQ3
DQ4
A10R
A0
A1
A2
A3
DQ1
V
CC
WE
NC
RAS
V
CC
DQ7
DQ6
DQ5
A8
A7
A6
A5
A4
DQ8
V
SS
CAS
A9
OE
V
SS
DQ2
DQ3
DQ4
A10R
A0
A1
A2
A3
DQ1
V
CC
WE
NC
RAS
V
CC
DQ7
DQ6
DQ5
A8
A7
A6
A5
A4
DQ8
V
SS
CAS
A9
OE
V
SS
Pin Name Function
A0 - A9, A10R
Address Input
RAS Row Address Strobe CAS Column Address Strobe
DQ1 - DQ8 Data Input/Data Output
OE Output Enable
WE Write Enable
V
CC
Power Supply (5 V)
V
SS
Ground (0 V)
NC No Connection
Note : The same power supply voltage must be provided to every VCC pin, and the same GND
voltage level must be provided to every VSS pin.
265
¡ Semiconductor MSM5117805B
BLOCK DIAGRAM
Timing
Generator
Refresh
Control Clock
Column Address
Buffers
Internal Address Counter
Row
Address
Buffers
Row Deco­ders
Word
Drivers
Memory
Cells
Sense Amplifiers
Column Decoders
I/O
Controller
I/O
Selector
Output Buffers
Input
Buffers
On Chip
V
BB
Generator
V
CC
DQ1 - DQ8
CAS
WE
A0 - A9
10 10
8
8
8
8
88
11
10
OE
RAS
On Chip
IV
CC
Generator
V
SS
1
A10R
266
MSM5117805B ¡ Semiconductor
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Voltage on Any Pin Relative to V
SS
Short Circuit Output Current
Power Dissipation
Operating Temperature
Storage Temperature
V
IN
, V
OUT
Symbol
I
OS
P
D
*
T
opr
T
stg
–0.5 to VCC + 0.5
50
1
0 to 70
–55 to 150
Rating
mA
W
°C
°C
Parameter
V
Unit
Voltage on VCC Supply Relative to V
SS
V
CC
–0.5 to 7 V
Recommended Operating Conditions
*: Ta = 25°C
Power Supply Voltage
Input High Voltage
Input Low Voltage
V
CC
Symbol
V
SS
V
IH
V
IL
5.0
0
—
—
Typ.Parameter
4.5
0
2.4
–0.5
*2
Min.
5.5
0
V
CC
+ 0.5
*1
0.8
Max.
(Ta = 0°C to 70°C)
V
Unit
V
V
V
Notes : *1. The input voltage is VCC + 2.0 V when the pulse width is less than 20 ns (the pulse width
is with respect to the point at which VCC is applied).
*2. The input voltage is VSS – 2.0 V when the pulse width is less than 20 ns (the pulse width
is with respect to the point at which VSS is applied).
Capacitance
Input Capacitance (A0 - A9, A10R) Input Capacitance (RAS, CAS, WE, OE)
Output Capacitance (DQ1 - DQ8)
C
IN1
Symbol
C
IN2
C
I/O
5
7
7
Max.
pF
Unit
pF
pF
Parameter
(V
CC
= 5 V ±10%, Ta = 25°C, f = 1 MHz)
—
—
—
Typ.
267
¡ Semiconductor MSM5117805B
IOH = –5.0 mAOutput High Voltage
I
OL
= 4.2 mAOutput Low Voltage
0 V £ V
I
£ 6.5 V;
All other pins notInput Leakage Current
under test = 0 V
DQ disable
Output Leakage Current
0 V £ V
O
£ 5.5 V
RAS, CAS cycling,
Average Power
t
RC
= Min.
Supply Current
(Operating)
RAS, CAS = V
IH
Power Supply
RAS, CAS
Current (Standby)
RAS cycling,Average Power CAS = V
IH
,Supply Current
t
RC
= Min.(RAS-only Refresh)
RAS = V
IH
,
Power Supply
CAS = V
IL
,
Current (Standby)
DQ = enable
Average Power
CAS before RAS
Supply Current (CAS before RAS Refresh)
RAS = VIL,Average Power CAS cycling,Supply Current
t
HPC
= Min.(Fast Page Mode)
V
OH
V
OL
I
LI
I
LO
I
CC1
I
CC2
I
CC3
I
CC5
I
CC6
I
CC7
≥ VCC –0.2 V
RAS cycling,
Parameter Condition
MSM5117805
B-50
MSM5117805
B-60
MSM5117805
B-70
(VCC = 5 V ±10%, Ta = 0°C to 70°C)
Symbol
Min.
2.4 0
–10
–10
—
—
—
—
—
—
—
Max.
V
CC
0.4
10
10
150
2
1
150
150
150
5
Min.
2.4 0
–10
–10
—
—
—
—
—
—
—
Max.
V
CC
0.4
10
10
130
2
1
130
130
130
5
Min.
2.4 0
–10
–10
—
—
—
—
—
—
—
Max.
V
CC
0.4
10
10
110
2
1
110
110
110
5
Unit
V V
mA
mA
mA
mA
mA
mA
mA
mA
Note
1, 2
1, 2
1, 2
1, 3
1
1
DC Characteristics
Notes : 1. ICC Max. is specified as ICC for output open condition.
2. The address can be changed once or less while RAS = VIL.
3. The address can be changed once or less while CAS = VIH.
268
MSM5117805B ¡ Semiconductor
AC Characteristics (1/2)
Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write
Cycle Time Access Time from RAS Access Time from CAS
Access Time from Column Address Access Time from CAS Precharge
CAS to Data Output Buffer Turn-off Delay Time
Transition Time
RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode with EDO) RAS Hold Time
CAS Pulse Width CAS Hold Time
RAS to CAS Delay Time RAS to Column Address Delay Time
CAS to RAS Precharge Time
Row Address Set-up Time
Row Address Hold Time
Column Address Set-up Time
Column Address Hold Time
Column Address to RAS Lead Time
Access Time from OE
OE to Data Output Buffer Turn-off Delay Time
Refresh Period
RAS Hold Time referenced to OE
RAS Hold Time from CAS Precharge
t
RC
t
RWC
t
HPC
t
HPRWC
t
RAC
t
CAC
t
AA
t
CPA
t
CEZ
t
T
t
RP
t
RAS
t
RASP
t
RSH
t
CAS
t
CSH
t
RCD
t
RAD
t
CRP
t
ASR
t
RAH
t
ASC
t
CAH
t
RAL
t
OEA
t
OEZ
t
REF
t
ROH
t
RHCP
Output Low Impedance Time from CAS t
CLZ
CAS Precharge Time (Fast Page Mode with EDO)
t
CP
Parameter
MSM5117805
B-60
MSM5117805
B-70
MSM5117805
B-50
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 12, 13
Symbol
Note
4, 5, 6
4, 5 4, 6
4
7, 8
5 6
4
7
4
3
Max.
— — —
—
60
15 30
35
—
15
50
—
10,000
100,000
—
—
10,000
—
45 30
—
—
—
—
— —
15
15
32
—
Unit
ns ns ns
ns
ns
ns ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns ns
ns
ns
ns
ns
ns ns
ns
ns
ms
ns
ns
Min.
84
110
20
58
—
— —
—
0
0
1
30
50
50
7
7
7
35
11
9
5
0
7
0
7
25
—
0
—
7
30
Max.
— — —
—
50
13 25
30
—
13
50
—
10,000
100,000
—
—
10,000
—
37 25
—
—
—
—
—
—
13
13
32
—
—
Min.
124 160
30
78
—
— —
—
0
0
1
50
70
70
13
10
13
45
14 12
5
0
10
0
13
35
—
0
—
13
40
Max.
— — —
—
70
20 35
40
—
20
50
—
10,000
100,000
—
—
10,000
—
50 35
—
—
—
—
— —
20
20
32
—
—
Min.
104 135
25
68
—
— —
—
0
0
1
40
60
60
10
10
10
40
14 12
5
0
10
0
10
30
—
0
—
10
35 —
Data Output Hold After CAS Low
WE to Data Output Buffer Turn-off Delay Time
RAS to Data Output Buffer Turn-off Delay Time
t
DOH
t
WEZ
t
REZ
7, 8
7
—
15
15
ns
ns
ns
5
0
0
—
13
13
5
0
0
—
20
20
5
0
0
OE Hold Time from CAS (DQ Disable) t
CHO
ns5— 5—5—
269
¡ Semiconductor MSM5117805B
AC Characteristics (2/2)
Write Command Pulse Width
Write Command to CAS Lead Time
Write Command to RAS Lead Time
Data-in Set-up Time
CAS to WE Delay Time
RAS to WE Delay Time
Column Address to WE Delay Time
RAS to CAS Hold Time (CAS before RAS)
CAS Active Delay Time from RAS Precharge
Data-in Hold Time
Write Command Hold Time
OE Command Hold Time
OE to Data-in Delay Time
Write Command Set-up Time
RAS to CAS Set-up Time (CAS before RAS)
WE to RAS Precharge Time (CAS before RAS) WE Hold Time from RAS (CAS before RAS) RAS to WE Set-up Time (Test Mode)
CAS Precharge WE Delay Time
RAS to WE Hold Time (Test Mode)
t
WP
t
CWL
t
RWL
t
DS
t
CWD
t
RWD
t
AWD
t
CSR
t
CHR
t
RPC
t
DH
t
WCH
t
OEH
t
OED
t
WCS
t
WRP
t
WRH
t
WTS
t
CPWD
t
WTH
MSM5117805
B-60
MSM5117805
B-70
MSM5117805
B-50
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 12, 13
Parameter
Symbol
Max.
10 10 10
ns ns ns
10 10 10
10 10 10
Note
11
10
10
10
11
10
10
10 ns10 10
Min.
10
10
10
0
34
79
49
5
10
5
10
10
10
15
0
54
Max.
ns
ns
ns
ns
ns
ns
ns
ns ns
ns
ns
ns
ns
ns
ns
Unit
ns
Min.
7
7
7
0
30
67
42
5
10
5
7
7
7
13
0
47
Max. Min.
10
13
13
0
44
94
59
5
10
5
13
13
13
20
0
64
—
—
—
—
—
—
—
— —
—
—
—
—
—
—
— — — —
—
—
—
—
—
—
—
—
— —
—
—
—
—
—
—
— — — —
—
—
—
—
—
—
—
—
— —
—
—
—
—
—
—
— — — —
—
Read Command Set-up Time
Read Command Hold Time Read Command Hold Time referenced to RAS
t
RCS
t
RCH
t
RRH
9
9
—
—
—
ns
ns
ns
0
0
0
—
—
—
0
0
0
—
—
—
0
0
0
WE Pulse Width (DQ Disable) t
WPE
10 ns710———
OE Precharge Time t
OEP
10 ns710———
OE Command Hold Time t
OCH
10 ns710———
270
MSM5117805B ¡ Semiconductor
Notes: 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved.
2. The AC characteristics assume tT = 2 ns.
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL.
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the t
RCD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RCD
(Max.) is specified as a reference point only. If t
RCD
is greater than the specified
t
RCD
(Max.) limit, then the access time is controlled by t
CAC
.
6. Operation within the t
RAD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RAD
(Max.) is specified as a reference point only. If t
RAD
is greater than the specified
t
RAD
(Max.) limit, then the access time is controlled by tAA.
7. t
CEZ
(Max.), t
REZ
(Max.), t
WEZ
(Max.) and t
OEZ
(Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels.
8. t
CEZ
and t
REZ
must be satisfied for open circuit condition.
9. t
RCH
or t
RRH
must be satisfied for a read cycle.
10. t
WCS
, t
CWD
, t
RWD
, t
AWD
and t
CPWD
are not restrictive operating parameters. They are
included in the data sheet as electrical characteristics only. If t
WCS
≥ t
WCS
(Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If t
CWD
≥ t
CWD
(Min.) , t
RWD
≥ t
RWD
(Min.),
t
AWD
≥ t
AWD
(Min.) and t
CPWD
≥ t
CPWD
(Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate.
11. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle.
12. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet is a 2-bit parallel test function. CA9 is not used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle.
13. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet.
See ADDENDUM M for AC Timing Waveforms
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