OKI MS81V04160-25TB, MS81V04160-30TB Datasheet
OKI Semiconductor
MS81V04160
Dual FIFO (262,214-word x 8-Bits) x 2
GENERAL DESCRIPTION
The MS81V04160 is a single-chip 4Mb FIFO functionally composed of two OKI 2Mb FIFO
(First-In First-Out) memories which were designed for 256k x 8-bit high-speed
asynchronous read/write operation.
The read clocks and the write clocks of each of the 2Mb FIFO memories are connected in
common. The MS81V04160, functionally compatible with Oki's 2Mb FIFO memory
(MSM51V8222A), can be use d as a x16 configuration FIFO.
The MS81V04160 is a field memory for wide or low end use in genera l com mod ity TVs an d
VTRs exclusively and is not designed for high end use in professional graphics systems,
which require long term picture storage, data storage, medical use and other storage
systems.
The MS81V04160 provides independent control clocks to support asynchronous read and
write operations. Different clock rates are also supported, which allow alter nate data rates
between write and read data streams.
The MS81V04160 provides high speed FIFO (First-in First-out) operation without exter nal
refreshing: MS81V04160 refreshes its DRAM stor age cells automatically, so t hat it appears
fully static to the users.
REVISION1 1 999.4.15
Moreover, fully static type memory cells and decoders for serial access enable the refresh
free serial access operation, so that serial read and/or write control clock can be halted
high or low for any duration as long as the power is on. Internal conflicts of memory access
and refreshing operations are prevented by special arbitration logic.
The MS81V04160’s functio n is simple, and similar to a digital dela y d e vice whos e delay-bitlength is easily set by reset timing. The delay length and the number of read delay clocks
between write and read, is d etermined by e xternally controlled write and read reset t imings.
Additional SRAM serial registers, or line buffers for the initial access of 256 x 16-bit enable
high speed first-bit-access with no clock delay just after the write or read reset timings.
Additionally, the MS81V04160 has a write mask function or input enable function (IE), and
read- data skipping function or output enable function (OE). The differences between write
enable (WE) and input enable (IE), and between read enable (RE) and output enable (OE)
are that WE and RE can stop serial write/read address increments, but IE and OE cannot
stop the increment, when write/read clocking is continuously applied to MS81V04160. The
input enable (IE) function allows the user to write into selected locations of the memory
only, leaving the rest of the memory contents uncha nge d. This facilitates data processing to
display a “pict ure in picture” on a TV screen.
1
MS81V04160
OKI Semiconductor
FEATURES
512 Rows x 512 columns x 8 bits x2
Fast FIFO(First-In First-Out)Operation :25ns cycle time
Self refresh(No refresh control is required)
High speed asynchronous serial access
Read/Write Cycle Time 25ns/30ns
Access Time 22ns/25ns
Variable length delay bit (600 to 262215)
Write mask function (Output enable control)
Cascading capability by mode setting
p
Single power supply:3.3V
Package:
100-Pin plastic TQFP(TQFP 100-P-1414-0.50-k)(Product:MS81V04160-xxTB)
xx indicates speed rank.
10%
Paramete r Symbol
M S81V04160-xxTB
-25 -30
Access Time
Read/Write
Cycl e Time
Operation current
Standby current 3mA 3mA
tAC 23ns 30ns
tSWC
25ns 30ns
tSRC
I cc1 80mA 80mA
Icc2
(MODE2 ="L")
2
MS81V04160
PIN CONFIGURATION (TOP VIEW)
OKI Semiconductor
NC
DI 23
Vss
DI 24
DI 25
DI 26
DI 27
NC
Vss
Vss
Vcc
Vcc
SWCK
Vcc
Vcc
Vss
Vss
NC
DI 17
DI 16
DI 15
DI 14
Vss
DI 13
NC
NC
88
38
NC
Vss
87
39
Vss
NC
86
40
NC
MODE1
RSTR2
OE2
RE2
Vcc
NC
81
82
83
84
85
45
44
43
42
41
RE1
RSTR1
Vcc
MODE3
MODE2
Vss
Vss
NC
NC
76
77
78
79
80
75
Vcc
74
DO 20
73
DO 21
72
Vss
71
DO 22
70
DO 23
69
DO 24
68
DO 25
67
Vss
66
DO 26
65
DO 27
64
Vcc
63
SRCK
62
Vcc
61
DO 17
60
DO 16
59
Vss
58
DO 15
57
DO 14
56
DO 13
55
DO 12
54
Vss
53
DO 11
52
DO 10
51
Vcc
50
49
48
47
46
NC
Vss
Vss
NC
OE1
RSTW2
DI 20
DI 21
DI 22
NC
100
98
99
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
28
27
26
DI 11
DI 12
NC
WE2
Vss
IE2
93
94
95
96
97
Vcc
92
Vss
91
NC
90
Vcc
89
100 PIN TQFP
TOP VIEW
37
36
35
34
33
32
31
30
29
Vcc
NC
Vss
Vcc
Vss
WE1
IE1
RSTW1
DI 10
Pin Name Pin Name
SWCK SRCK
WE1 WE2
RE1 RE2
IE1 IE2
OE1 OE2
RSTW1 RSTW2
RSTR1 RSTR2
DI 10-17 DI 20-27
DO 10-17 DO 20-27
MODE1,2,3
Vcc Vss
Function
Serial Write Clock
Port1 Write Inable
Port1 Read Inable
Port1 Input Inable
Port1 Output Inabl e
Port1 Reset Write
Port1 Reset Read
Port1 Data Input
Port1 Data Output
Mode Input
Power Supply(3.3V)
NC
Function
Serial Read Clock
Port2 Write Inable
Port2 Read Inable
Port2 Input Inable
Port2 Output Inabl e
Port2 Reset Write
Port2 Reset Read
Port2 Data Input
Port2 Data Output
No Connection
Ground(0V)
Note: The same power supply voltage must be provided to every Vcc pin,and
the same GND voltage level must be provided to every Vss pin.
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MS81V04160
BLOCK DIAGRAM
OKI Semiconductor
8)
q
DO (
OE2
RE2
RSTR2
SRCK
Data-Out
Controller
Read
Serial
8)
q
Buffer (
8)
8)
q
q
Low-Half (
Read Line Buffer
8)
q
High-Half (
512 Word Serial Read Register (
Read Line Buffer
8)256 (
q
256 (
8)
q
8)
q
71 Word
Sub-Register (
8)
q
256k (
Read/Write
8)
q
71 Word
Sub-Register (
8)
q
Array
Memory
-
Decoder
Controller
and Refresh
256 (
8)
q
256 (
Clock
Oscillator
8)
8)
q
q
Low-Half (
Write Line Buffer
8)
q
High-Half (
Write Line Buffer
512 Word Serial Write Register (
8)
q
Data-In
Buffer (
ControllerSerial
Write
MODE1,2,3
8)
q
DI (
IE2
WE2RSTW2SWCK
VBB
Generator
RSTR1 SRCK
OE1
8)
q
DO (
Controller
Read/Write
and Refresh
8)
q
8)
8)
q
Controller
Read Line Buffer
Data-Out
Read
Serial
512 Word Serial Read Register (
Read Line Buffer
8)
q
Buffer (
RE1
256 (
q
8)
High-Half (
q
256 (
8)
q
Low-Half (
-
Decoder
8)
q
Array
Memory
256k (
8)
q
71 Word
Sub-Register (
71 Word
8)
q
8)
8)
q
q
Controller
8) 256 (
High-Half (
Write Line Buffer
q
256 (
8)
q
Low-Half (
512 Word Serial Write Register (
8)
q
Sub-Register (
Write Line Buffer
Write
Serial
8)
q
Data-In
Buffer (
SWCK
WE1 RSTW1
IE1
8)
q
DI (
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MS81V04160
OKI Semiconductor
PIN DESCRIPTION
Data Inputs: (DIN 10 - 17)
These pins are used for serial data inputs.
Write Reset: RSTW1
The first positive transition of SWCK after RSTW becomes high resets the write address
pointers to zero. RSTW1 setup and hold times are referenced to the rising edge of SWCK.
Because the write reset funct ion is so lely co ntrolled by the SWCK rising edge after the high
level of RSTW, the states of WE1 and IE1 are ignored in the write reset cycle. Before
RSTW1 may be brought high again for a further reset operation, it must be low for at least
two SWCK cycles.
Write Enable: WE1
WE1 is used for data write enable/disable control. WE1 high level enables the input, and
WE1 lowlevel disables the input and holds the internal write address pointer. There are no
WE1 disabletime (low) and WE1 enable time (high) restrictions, because the MS8104160
is in fully static operation as long as the power is on. Note that WE1 setup and hold times
are referenced to t he rising ed ge of SWCK.
Input Enable: IE1
IE1 is used to enable/disable writing into memory. IE1 high level enables writing. The
internal write address pointer is always incremented by cycling SWCK regardless of the
IE1 level. Note that IE1 setup and hold times are referenced to the rising edge of SWCK.
Data Out: (DOUT 0 - 11)
These pins are used for serial data outputs.
Read Reset: RSTR1
The first positive transition of SRCK after RSTR1 becomes high resets the read address
pointers to zero. RSTR1 setup and hold times are referenced to the rising edge of SRCK.
Because the read reset function is solely controlled by the SRCK rising edge after the high
lev el of RSTR, the states of RE1 and OE1 are ign ored in the read reset cyc le. Before RST R
may be brought high again for a further reset operation, it must be low for at least *two
SRCK cycles.
Read Enable: RE1
The function of RE1 is to gate of the SRCK clock for incrementing the read pointer. When
RE1 is high before the rising edge of SRCK, the read pointer is incremented. When RE1 is
low, the read pointer is not incremented. RE1 setup times (tRENS and tRDSS) and RE1
hold times (tRENH and tRDSH) are referenced to the rising edge of the SRCK clock.
Output Enabl e: OE1
OE1 is used to enable/disable the outputs. OE1 high level enables the outputs. The internal
read address pointer is always incremented by cycling SRCK regardless of the OE1 level.
Note that OE1 setup and ho ld t ime s are referenced to the rising edge of SRCK.
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MS81V04160
Serial Write Cl ock: SWCK
The SWCK latches the input data on chip when WE1, 2 is high, and also increments the
internal write address pointer. Data-in setup time tDS, and hold time tDH are referenced to
the rising edge of SWCK.
Serial Read Clock: SRCK
Data is shifted out of the data registers. It is triggered by the rising edge of SRCK when
RE1, 2 is highduring a read operation. The SRCK input increments the internal read
address pointer when RE1,2 is high.
The three-state output buffer provide s dire ct TTL compatib ilit y (no pullup resistor req uire d).
Data out is the same polarity as data in. The output becomes valid after the access time
interval tAC that begins with the rising edge of SRCK. *There are no output valid time
restriction on MS8104160.
Data Input: (DIN 20-27)
These pins are used for serial data inputs.
Write Reset: RSTW2
The first positive transition of SWCK after RSTW becomes high resets the write address
pointers to zero. RSTW2 setup and hold times are referenced to the rising edge of SWCK.
Because the write reset funct ion is sol ely controlled by the S WCK rising ed ge after the high
level of RSTW2, the states of WE2 and IE2 are ignored in the write reset cycle. Before
RSTW2 may be brought high again for a further reset operation, it must be low for at least
two SWCK cycles.
OKI Semiconductor
Write Enable: WE2
WE is used for data write enable/disable control. WE2 high level enables the input, and
WE2 lowlevel disables the input and holds the internal write address pointer. There are no
WE2 disabletime (low) and WE2 enable time (high) restrictions, because the MS8104160
is in fully static operation as long as the power is on. Note that WE2 setup and hold times
are referenced to the rising edge of SWCK.
Input Enable: IE2
IE2 is used to enable/disable writing into memory. IE2 high level enables writing. The
internal write address pointer is always incremented by cycling SWCK regardless of the
IE2 level. Note that IE2 setup and hold times are referenced to the rising edge of SWCK.
DOUT 20 – 27
Data Out :
These pins are used for serial data outputs.
Read Reset: RSTR2
The first positive transition of SRCK after RSTR2 becomes high resets the read address
pointers to zero. RSTR2 setup and hold times are referenced to the rising edge of SRCK.
Because the read reset functio n is solely controlled by the SRCK rising edge after the high
level of RSTR2, the states of RE2 and OE2 are ignored in the read reset cycle. Before
RSTR2 may be brought high again for a further reset operation, it must be low for at least
*two SRCK cycles.
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MS81V04160
Output Enabl e: OE2
OE2 is used to enable/disable the outputs. OE2 high level enables the outputs. The internal
read address pointer is always incremented by cycling SRCK regardless of the OE2 level.
Note that OE2 setup and ho ld t ime s are referenced to the rising edge of SRCK.
Mode Setting: MODE1
The Cascade/Non cascade select pin. Setting the MODE1 pin to the Vcc level configures
this memory device as cascade type and se tting the pin to the Vss level configures this
memory device as non cascade. During memor y operation, the pin must be per manentry
connected to Vcc or Vss. If a MODE1 level is changed during memory operation, memory
data is not guaranteed.
Note: Cascade/Non cascade
When MODE1 is set to the Vss level, memory accessing starts in the cycle in which the
control signals are input (Non cascad e t ype).
When MODE1 is set to the Vcc level, memory accessing starts in the cycle subsequent to
the cycle in which the control signals are input (Cascade type). This type is used for
consecutive memory accessing.
MODE2 Setting: MODE2
MODE2 selects whether the control input signals are enabled at a high level or a low level.
Setting MODE2 to the Vcc level enables the control input signals at a low level and setting
MODE2 to the Vss level enables the control input signals at a high level.
OKI Semiconductor
MODE Setting: MODE3
The boost control pin for data-out Buffer. For the MS8104160, the MODE3 pin should be
permanentry Connected to the Vss level.
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