OKI MR27V3266D Datasheet

1 Semiconductor

MR27V3266D

2M x16 / 1M x32 Synchronous OTP ROM

DESCRIPTION

The MR27V3266D is a 32Mbit One Time Programmable Synchronous Read Only Memory whose configuration can be electrically switched between 2,097,152 x16bit(word mode) and 1,048,576 x32bit(double word mode) by the state of the /WORD pin. The MR27V3266D supports high speed synchronous read operations using a single

3.3V power supply.

FEATURES ON READ

- 3.3V power supply

- LVTTL compatible with multiplexed address

- Dual, electrically switchable configurations 2M x16(word mode) / 1M x32(double word mode)

- All inputs are sampled at the rising edge of the system clock

- High speed read operation

66MHz : CAS Latency=5

tRCDmin=2 Burst Length (4, 8)

Data scramble (sequential, interleave)

50MHz : CAS Latency=4, 5

tRCDmin=1 Burst Length (4, 8)

Data scramble (sequential, interleave)

- DQM for data out masking

- No Precharge operation is required. No Refresh operation is required.

- No power on sequence is required.

Mode register is automatically initialized to the default state after power on. "Row Active" command to read data is applicable as the first command just after power on.

- Single Bank operation

- Package : TSOP II 86-P-400-0.50-K

FEATURES ON PROGRAMMING

- 9.75V programming Power supply

- Programming algorithm is compatible with conventional asynchronous 32M OTP. MR27V3266D can be programmed with conventional EPROM programmers.

Synchronous Burst read or Static Programming Operation are selected by the state of STO pin.

High STO level enables full static programming. (Program, Program Verify, asynchronous Read) Low STO level enables synchronous burst read.

Exclusive 86pin socket adapters are available from OKI to support programming requirements.

The socket adapter is used on a 48DIP socket on the programmer. The socket adapter is designed with the STO pin connected to V as conventional 32M OTP.

EPROM programmer must have the proper algorithm for 32M OTP.

*Device damage can occur if improper algorithm is used.

- High speed programming

10µs programming pulse per word allows high speed programming.

August , 1999 Revision 2.4

CC in order to program MR27V3266D

32M Synchronous OTP

1 Semiconductor

FUNCTION BLOCK DIAGRAM

A12

Address Buffer

Latch

Row Address

Latch

Row Decoder

MR27V3266D

Memory Cell Array

1Mx32 or 2Mx16

Row Select

Column Select

Sence Amplifier & Program Bias

RAS

CAS

WORD

Command

Controller

Mode

CLK Buffer

CKE CLK

Column Address

Burst Sequence

Controller

Program Mode

Controller

Column Decoder

STO DQ24-DQ31

CAP0-CAP7

Data Output

Latch

Data Outputs

Selector

Data Output/Input Buffer

& Data Output/Address Buffer

Data Input

Buffer

DQ0-DQ15

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AMPX

DQ16-DQ23

32M Synchronous OTP

1 Semiconductor

PIN CONFIGURATION

Programming in Static Operation (STO is high)

MR27V3266D

TOP VIEW

Synchronous Read (STO is VSS or open)

VCC

DQ0

VCCQ

DQ1

VSSQ

DQ2

VCCQ

DQ3

VSSQ

DC DC

VCC

NC /CAS /RAS

/WORD

A12 A11 A10

A0 A1 A2

VCC

DQ4

VSSQ

DQ5

VCCQ

DQ6

VSSQ

DQ7

VCCQ

VCC

DQ0 VCCQ DQ16

DQ1

VSSQ

DQ17

DQ2 VCCQ DQ18

DQ3

VSSQ

DQ19

/MR VCC

DQM

NC /CAS /RAS

/CS

/WORD

A12 A11 A10

A0 A1 A2

VCC

DQ4

VSSQ

DQ20

DQ5 VCCQ DQ21

DQ6

VSSQ

DQ22

DQ7 VCCQ DQ23

VCC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

86PIN

TSOP II

86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44

VSS DQ31 VSSQ DQ15 DQ30 VCCQ DQ14 DQ29 VSSQ DQ13 DQ28 VCCQ DQ12 NC VSS DC DC DC CLK CKE A9 A8 A7 A6 A5 A4 A3 DC VSS DC DQ27 VCCQ DQ11 DQ26 VSSQ DQ10 DQ25 VCCQ DQ9 DQ24 VSSQ DQ8 VSS

VSS CAP0 VSSQ DQ15 CAP1 VCCQ DQ14 CAP2 VSSQ DQ13 CAP3 VCCQ DQ12 NC VSS VPP /CE /OE DC DC A9 A8 A7 A6 A5 A4 A3 AMPX VSS STO CAP4 VCCQ DQ11 CAP5 VSSQ DQ10 CAP6 VCCQ DQ9 CAP7 VSSQ DQ8 VSS

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DC(Don't Care) : Logical input level is ignored, however the pin is connected to input buffer of OTP

32M Synchronous OTP

1 Semiconductor

MR27V3266D

PIN FUNCTION FOR SYNCHRONOUS READ OPERATION ( STO pin is low level or open )

PIN NAME

STO

CLK

/CS

CKE

A0-A12

/RAS

/CAS

/MR

FUNCTION

Static Operation

System Clock

Chip Select

Clock Enable

Address

Row Address Strobe

Column Address Strobe

Mode Register Set

DESCRIPTION

Must be low for synchronous operation. Internal resistance (around 10k ohms) pulls the input level down to V this pin is open. High level STO enables programming operation compatible with standard OTPs.

All inputs are sampled at the rising edge.

Enables command sampling by the CLK signal with a low level on the /CS input.

Masks internal system clock to freeze the CLK operation o subsequent CLK cycle. CKE must be enabled for command sampling cycles. CLK is disabled for two types of operations.

1)Clock Suspend

2)Power down.

Row and column addresses are multiplexed on the same pins. Row address:RA0-RA12 Column address:CA0-CA6(x32) / CA0-CA7(x16)

Functionality depends on the combination. See the function table.

SS when

DQ0-DQ31

DQM

/WORD

VCC

CCQ

SSQ

Data Output

Data Output Masking

x32/x16 Organization Selection

Power Supply

Ground

Data Output Power Supply

Data Output Ground

No Connection

Don't Care

Data outputs are valid at the rising edge of CLK for read cycles. Except for read cycles DQn is high-Z state.

Data outputs are masked after two cycles from when high level DQM is applied.

The /WORD pin defines the organization of each read command to be x16 (word mode) or x32 (double word mode). High=x32 Low=x16

3.3V Power supply

3.3V Power supply to DQ0-DQ31

Logical input level is ignored.

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PIN FUNCTION FOR PROGRAMMING OPERATION ( STO pin is high level )

MR27V3266D

PIN NAME

STO

AMPX

A0-A12

/RAS

/CAS

DQ0-DQ15

FUNCTION

Static Operation

Address Multiplex

Address

Row address strobe

Column address strobe

Data Input/Output

DESCRIPTION

Must be set high for programming operation. Internal resistance (around 10k ohms) pulls the input level down to V

SS for open state condition to be low level for synchronous

read operation.

When AMPX is low, the addresses are not multiplexed and all address bits must be supplied to A0-A12(Row Address) and CAP0-CAP7(Column Address) simultaneously. This pin should be set low on programming operation.

When AMPX is low, A0-A12 is row address input.

When AMPX is low, input is not used.

Input of data for programming and output for program verify and read data.

/WORD

CAP0-CAP7

/OE

/CE

CC/VSS

VCCQ/VSSQ Data Output Power/Ground

VPP

x32/x16 organization Selection

Address Input

Output Enable

Chip Enable

Power Supply/Ground

Program Power Supply

The /WORD pin defines the organization to be x16(word mode) or x32(double word mode). High= x32 Low = x16 Must be set low for programming operation.

When /WORD is low, High-Z state on CAP0-CAP7 is held to be input pins. When AMPX is low, CAP0 - CAP7 is column address input.

Control signal input for programming. /OE of conventional OTP.

Control signal input for programming. Function for programming is associated with conventional OTP.

Power and ground for the input buffers and the core logic.

Power and ground for output.

High voltage program power is supplied through V When V between V V

PP mode. To keep stable static read operation VPP pin must

be kept lower than V

PP is higher than a predetermined voltage level

CC+0.5V and VCC+2V, pin function alters to high

CC+0.5V.

PP pin.

The functionality of loose device programming must be studied with the specification of socket adapter that will be supplied by OKI. MR27V3266D on the socket adapter is the same programming functionality as conventional OTP.

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FUNCTION TABLE FOR SYNCHRONOUS READ

MR27V3266D

COMMAND NAME

Mode Register Set

Row Active

Read Word (x16)

Read Double Word (x32)

Burst Stop

Precharge

Clock Suspend (on Read)

Power Down (on Active

Standby)

Read Output

Mask Output

No Operation

( H=Logical high, L=Logical low, X=Don't Care, L of STO includes pin open due to internal pull down resistor )

Note

1. Refer to "Mode register Field Table" for Address Codes, and Mode Transition Chart for operational state. After power on any command can be sampled at any cycle in Active Standby state. After "Mode register Set" command is sampled, no new command can be accepted for 3 CLK cycles. The /CS input must be kept high for the 3 CLK cycles to prevent unexpected sampling of a command.

2. The "Row Active" command is effective till new "Row Active" command is implemented.

3. The /WORD input is sampled simultaneously with "Read" command to select data width. A Double Word Burst(x32 ) or a Word Burst(x16) is selected by the /WORD input for each "Read" command. On condition of constant voltage level on /Word pin, organization is fixed to either x16 or x32.

"Read" command ends it's implementation by itself at the finishing cycle of the burst read.

4. Since OTP technology uses static sense amplifiers, the "Precharge" command is not required however, due to customer request for the similarity of logical input code with SDRAM command, the name of "Precharge" is adopted. Function of "Precharge" command and "Burst Stop" command is only to stop the burst read cycles delayed by CAS Latency.

5. Sampled low level CKE disables CLK buffer to suspend internal clock signals at the next rising edge of CLK. Sampled high level CKE enables internal clock at the next rising edge of CLK. Low level CKE sampled in the period from the simultaneous cycle with a "Read" command till the end of the burst read cycle is distinguished with internal command controller from the low level CKE sampled in Active Standby state not to stop data sensing and burst read operation those consume power.

6. Low level CKE sampled in Active Standby state cuts power dissipation to be in Power Down state. High level CKE sampled in Power Down state enables internal CKE to be in Active Standby state with preserved row address.

FUNCTION

Mode Register Set

Row Address Latch

Column Address Latch Trigger Burst Read

Burst Stop

Entry

Exit

Entry

Exit

Output Enable

High-Z Output

Write on SDRAM

Self Refresh on SDRAM

Illegal on SDRAM

( CKEn expresses the logical level at the simultaneous cycle with a command. )

CKE

H H

H H H

H H H H H H H

n-1 NotesSTO/WORDAdd.DQM/MR/CAS/RAS/CSCKEn

X X

X X X

H X X

X X

L X X

X X

LL H

LL L

HHH

X X

X X X X

H X X X X X

Code

X X X X

X X X X X X X

X X

X X X X

X X X X X X X

L L L L L L L

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MODE REGISTER FIELD TABLE

Address A5 A0A1A2A3A4

CAS Latency Burst Type Burst LengthFunction

MR27V3266D

A3A4A5

Note A7 and A8 must be low during Mode Register Set cycle. During power on, mode register is initialized to the default state when V The default state of Mode Register is below. (less than 3.0V)

CAS Latency=5 Burst Type=Sequential Burst length=4

000

Length

Reserved

BURST SEQUENCE ( BURST LENGTH = 4 )

Initial address

A1 A0

Sequential Interleave

Type

Sequential

Interleave

CC reaches a specific voltage.

A0A1

Length

Reserved

BURST SEQUENCE ( BURST LENGTH = 8 )

Initial address

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A0A1A2

Sequential

001

Interleave

001

312

32M Synchronous OTP

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ADDRESSING MAP

(1) /WORD = "H" : x32 Organization

MR27V3266D

Pin Name

Row Address

Column Address

(2) /WORD = "L" : x16 Organization

Pin Name

Row Address

Column Address

(3) Programming

Address displayed on programmer : x16

Device Address : x16 STO = "H", AMPX = "L"

Address ( STO = "L" ) /WORD = "L" : x16

Address ( STO = "L" ) /WORD = "H" : x32

Address displayed on programmer : x16

Device Address : x16 STO = "H", AMPX = "L"

Note1

Note2 Note3

CA1

Ad13 Ad14

A5 A6

A5 A6A2 A3 A4A0 A1 A7 A8 A9 A10 A11 A12

RA5 RA6RA2 RA3 RA4RA0 RA1 RA7 RA8 RA9 RA10 RA11 RA12

CA5 CA6CA2 CA3 CA4CA0CA1 XXXXXX

A5 A6A2 A3 A4A0 A1 A7 A8 A9 A10 A11 A12

RA5 RA6RA2 RA3 RA4RA0 RA1 RA7 RA8 RA9 RA10 RA11 RA12

CA5 CA6CA2 CA3 CA4CA0 CA1 CA7 X X X X X

Ad5 Ad6Ad2 Ad3 Ad4Ad0 Ad1 Ad7 Ad8 Ad9 Ad10 Ad11 Ad12

CAP5 CAP6CAP2 CAP3 CAP4CAP0 CAP1 CAP7 A2 A3 A4A0 A1

CA3 CA4CA0

CA5 CA6

CA7

CA3 CA4CA0

CA2

Note4

Note5

CA2

CA1

Ad15 Ad16 Ad17 Ad18 Ad19 Ad20

A7 A8 A9 A10 A11 A12

( X = Don't Care )

RA2 RA3 RA4RA0 RA1

Address ( STO = "L" ) /WORD = "L" : x16

Address ( STO = "L" ) /WORD = "H" : x32

User of MR27V3266D is recommended to study the relation between "Address displayed on programmer" and "Address(STO="L")" ignoring "Device Address:x16, STO="H"". Order of data on Synchronous Read operation(STO="L") is checked on this table. "Device Address:x16, STO="H"" will be utilized to design socket adapter on programmer or to check boards designed to mount blank OTP and program OTP on board. OKI will supply socket adapter to program MR27V3266D as conventional x16 standard OTP. The users and the venders of programmer who use the socket adapter can ignore "Device Address:x16, STO="H"".

Note

1. A0 in programmer distinguishes upper word(x16) or lower word(x16) of Double word(x32). On word(x16) organization the address of device corresponds to the address of programmer. On double word(x32) organization the address numeral code of device is half of that in programmer, and output on DQ0-DQ15 is lower word(A0="0") and output on DQ16-DQ31 is upper word(A0="1").

2. CA1 is MSB of burst read on condition of /WORD="L" and BL=4

3. CA2 is MSB of burst read on condition of /WORD="L" and BL=8

4. CA1 is MSB of burst read on condition of /WORD="H" and BL=4

5. CA2 is MSB of burst read on condition of /WORD="H" and BL=8

RA5 RA6 RA7 RA8 RA9 RA10 RA11 RA12

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MR27V3266D

READ OPERATIONS

CLOCK ( CLK )

The clock input enables MR27V3266D to sample all the inputs, control internal circuitry, and turn on output drivers. All timings are referred to the rising edge of the clock. All inputs with high level CKE and low level /CS should be valid at the rising edge of CLK for proper functionality.

CLOCK ENABLE ( CKE )

The clock enable(CKE) turns on or switches off the admission of the clock input into the internal clock signal lines. All internal circuits are controlled by the internal clock signal to implement every command. High level CKE sampled at CKEn-1 clock cycle enables the admission of the rising edge of clock input into internal clock line at CKEn cycle. Low level CKE sampled at CKEn-1 cycle suspends the rising edge of CLK at CKEn cycle. The suspension of internal clock signal in all state ignores new input except CKE, and holds internal state and output state. Low level CKE in Active Standby state, defined as Power Down state, cuts power dissipation. In Power Down state the contents of mode register and Row Address are preserved. After recovering high level CKE to exit from Power Down state, MR27V3266D is in Active Standby state. Low level CKE just after the sampling of "Read" command till the completion of burst read, defined as Clock Suspend, makes read operation go on with power dissipation. Any command operation does not interrupted by arbitrary low level CKE. Sampling command with low level CKE preceded with high level CKE is illegal.

POWER ON

Apply power and start clock considering following issues.

1. During power on Mode Register is initialized into default state. (default state: CAS latency=5, Burst Type=Sequential, Burst length=4)

2. After power on MR27V3266D is in Active Standby state and ready for "Mode Register set" command or

"Row Active" command. MR27V3266D requires neither command nor waiting time as power on sequence after starting CLK input in order to start "Row Active" command to read data.

3. It is recommended in order to utilize default state of Mode Register that /MR and CKE inputs are maintained

to be pulled up during power on till the implementation of the first "Row Active" command. After above power on "Row Active" command and "Read" command can be started immediately on default Mode Register state.

4. It is recommended that DQM input is maintained to be pulled up to prevent unexpected operation of output

buffers.

ORGANIZATION CONTROL

Organization of data output(DQ0-DQ31) depends on the logical level on /WORD at the input timing of every "Read" command. High level sampling of /WORD derives double word mode(x32) output and low level sampling of /WORD derives word mode(x16) output. Constant /WORD level input brings consistent organization.

MODE REGISTER

Mode register stores the operating mode of MR27V3266D. Operating modes are consisted with CAS latency, Burst Type, and Burst Length. Registration of RAS latency is not required, because RAS to CAS delay(tRCD) is requested independently of system clock. When the contents of Mode register are required to be changed for the next operation, "Mode Register Set" command can be sampled at any cycle in Active Standby state. After "Mode Register Set" command is sampled, /CS must be fixed to logical high level to prevent sampling of new command input during succeeding three clock cycles. Refer to Mode Register Field Table for the relation between Operation modes and input pin assignment.

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MR27V3266D

READ OPERATIONS

CAS LATENCY

After sampling "Read" command MR27V3266D starts actual data read operation with sense amplifiers, and transmits the data from sense amplifiers to data out buffers to start burst read. This flow of sequential functionality takes time as clock cycles defined as CAS latency(CL). CAS latency is set in Mode Register as either four cycles or five cycles. In this sequence(from sampling "Read" command to start of driving data bus) sense amplifiers consume maximum current flow. The detailed sequence is below.

1. Fix column address of memory matrix driver. Row address is already fixed with "Row Active" command.

(at 1st cycle)

2. Read data of selected memory cells with sense amplifiers.

3. Deliver data detected with sense amplifiers to the register for data output latch.

4. Couple selectively the section of the register storing each (double)word to output buffers.

5. Turn off sense amplifiers to save power. (at CL-1 cycle)

6. Enable output buffers to drive data bus. (at CL-1 cycle)

7. Data output on data bus can be sampled at the rising edge of system clock at CL cycle.

New "Row Active" command or new "Read" command can be sampled to perform gapless burst read at CL-1 clock cycle of the last "Read" command. New command preceding CL-1 cycle interrupts sense amplifiers to read the data at the selected memory cells of the last "Read" command. Interrupted "Read" command perishes or outputs invalid data before the starting of the data burst of new "Read" command. Refer to the timing chart of "Burst Read/Interrupt I" and "Burst Read/Interrupt II".

BURST READ

Data outputs are consecutive during the cycle number defined as Burst Length(BL). The latest burst read is completed unless any interruption such as "Precharge" command stops the sequential data output. Burst Length is set in Mode Register as either four or eight. After sampling of "Read" command the first output can be read at the cycle delayed by CAS latency. Burst Type is also stored in Mode register as either sequential or interleave. The output buffers go into high impedance state after burst read sequence is finished, unless a new "Read" command has been sampled to perform gapless read or preemptive read. Burst read can be interrupted by "Burst Stop" command or "Precharge" command at the cycle delayed by CAS latency from the command. On condition that reading data with sense amplifiers of preceding "Read" command is not interrupted by new "Read" command or "Row active" command, burst read of preceding "Read" command is continued regularly until the burst data sequence of the new "Read" command starts. The new(latest) burst data sequence always starts regularly.

DQM

Input level on DQM is sampled at rising edge of system clock to mask data at two cycles later. Output of masked data is high-Z state.

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READ OPERATIONS

MODE TRANSITION CHART

Row Active Mode Register Set

Active Standby

MR27V3266D

CKE=H CKE=L

Power Down

Exit

Entry

Note

Entry

Clock Suspend

Read

Exit

DQM

Burst Stop

Precharge*

*All operation of "Precharge" command is to stop burst read.

: passing command

: state can be kept for any duration

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32M Synchronous OTP

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