OKI ML9211GA, ML9211GP Datasheet
E2C0045-19-83
Preliminary
¡ Semiconductor
This version: Aug. 1999
ML9211
¡ Semiconductor
ML9211
56-Bit Duplex/Triplex (1/2 duty / 1/3 duty) VF Controller/Driver with Digital Dimming
GENERAL DESCRIPTION
The ML9211 is a full CMOS controller/driver for Duplex or Triplex (1/2 duty or 1/3 duty)
vacuum fluorescent display tube. It consists of a 56-segment driver multiplexed to drive up to
168 segments, and 10-bit digital dimming circuit.
ML9211 features a selection of a master mode and a slave mode, and therefore it can be used to
expand segments for the VFD driver with keyscan and A/D converter function.
ML9211 provides an interface with a microcontroller only by three signal lines: DATA IN,
CLOCK and CS.
FEATURES
• Logic supply voltage (VDD) : 4.5 to 5.5V
• Driver supply voltage (V
• Duplex/Triplex (1/2 duty / 1/3 duty) selectable
DUP/TRI=1/2 duty selectable at "H" level
DUP/TRI=1/3 duty selectable at "L" level
• Number of display segments
Max. 112-segment display (during 1/2 duty mode)
Max. 168-segment display (during 1/3 duty mode)
• Master/Slave selectable
M/S=Master mode selectable at "H" level
M/S=Slave mode selectable at "L" level
• Interface with a microcontroller
Three lines: CS, CLOCK, and DATA IN
• 56-segment driver outputs : IOH=–5mA at VOH=V
(can be directly connected to VFD tube : IOH=–10mA at VOH=V
and require no external resistors) : IOL=500mA at VOL=2V (SEG1 to 56)
• 3-grid pre-driver outputs : IOH=–5.0mA at VOH=V
(require external drivers) IOL=10mA at VOL=2V
• Logic outputs : IOH=–200mA at VOH=VDD–0.8V
• Built-in digital dimming circuit (10-bit resolution)
• Built-in oscillation circuit (external R and C)
• Built-in Power-On-Reset circuit
• Package options:
80-pin plastic QFP (QFP80-P-1420-0.80-BK) Product name: ML9211GA
80-pin plastic QFP (QFP80-P-1414-0.65-K) Product name: ML9211GP
) : 8 to 18V
DISP
IOL=200mA at VOL=0.8V
–0.8V (SEG1 to 37)
DISP
–0.8V (SEG38 to 56)
DISP
–0.8V
DISP
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¡ Semiconductor
BLOCK DIAGRAM
V
DISP
D-GND
56 Segment Driver
ML9211
GRID2 GRID3GRID1SEG56SEG1
3 Grid pre Driver
V
DD
L-GND
CS
CLOCK
DATA IN
OSC0
DIM IN
SYNC IN1
SYNC IN2
M/S
DUP/TRI
POR
Power
On
Reset
0H 4H
Mode Select
in1-3
Control
OSC
POR
1H
0H
POR
Out1-56
Segment Latch
1
in1-56
Out1-3
3bit Shift Register
POR
Out1-56
168 to 56 Segment Control
in1-56 in1-56in1-56
2H
0H
POR
Out1-56
Segment Latch
2
in1-56
Out1-56
56bit Shift Register
POR
POR
POR
Timing Generator
3H
0H
POR
4H
Out1-56
Segment Latch
3
in1-56
in1-10
Dimming Latch
Out1-10
10bit Digital
Dimming
DIM OUT
SYNC OUT1
SYNC OUT2
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¡ Semiconductor
INPUT AND OUTPUT CONFIGURATION
Schematic Diagram of Driver Output Circuit
ML9211
V
D-GND
DISP
V
DISP
OUTPUT
D-GND
3/19
¡ Semiconductor
PIN CONFIGURATION (TOP VIEW)
ML9211
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
GRID1
GRID2
GRID3
NC
D-GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DISP
V
80
1
2
3
4
5
6
7
8
9
SEG36
SEG37
78
79
SEG34
SEG35
76
77
SEG33
75
SEG31
SEG32
73
74
SEG30
72
SEG28
SEG29
70
71
SEG26
SEG27
68
69
SEG25
67
DISP
V
SEG24
65
66
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
NC
25
V
DD
32
31
30
29
28
27
26
DIM IN
SYNC IN 1
CS
SYNC IN 2
CLOCK
DATA IN
NC
NC: No connection
80-pin Plastic QFP
(QFP80-P-1420-0.80-BK)
34
33
OSC0
L-GND
35
DUP/TRI
38
37
36
M/S
SYNC OUT 2
40
39
D-GND
DIM OUT
SYNC OUT 1
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¡ Semiconductor
ML9211
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
GRID1
GRID2
GRID3
10
11
12
13
14
15
16
17
18
19
20
DISP
SEG39
SEG38
V
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
80797877767574737271706968676665646362
1
2
3
4
5
6
7
8
9
SEG25
SEG24
DISP
V
SEG23
SEG22
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
21222324252627282930313233343536373839
NC
DD
V
D-GND
DIM IN
CS
SYNC IN 1
SYNC IN 2
CLOCK
DATA IN
NC
OSC0
L-GND
M/S
DUP/TRI
D-GND
DIM OUT
SYNC OUT 2
SYNC OUT 1
NC
NC: No connection
80-pin Plastic QFP
(QFP80-P-1414-0.65-K)
40
SEG1
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¡ Semiconductor
PIN DESCRIPTIONS
ML9211
Symbol
QFP-1*
V
DISP
V
DD
65, 80 —
D-GND 24, 40 —
QFP-2*
63 78
25 —
22, 38
L-GND 33 —
SEG1 to 37
42 to 64,
66 to 79
40 to 62,
64 to 77
Type Description
23
31
79, 80,
Pin
SEG38 to 56 1 to 19 O
GRID1
GRID2 21 O
GRID3
CS 29 I
CLOCK 30 I
DATA IN 31 I
DUP/TRI 35 I
1 to 17
20 18
19
22 20
27
28
29
33
Power supply pins for VFD driver circuit.
These should be connected externally.
Power supply pin for logic drive.
D-GND is ground pin for the VFD driver circuit. L-GND is ground pin for the
logic circuit. These should be connected externally.
Segment (anode) signal output pins for a VFD tube. These pins can be directly
O
connected to the VFD tube. External circuit is not required.
£–5 mA
I
OH
Segment (anode) signal output pins for a VFD tube.These pins can be directly
connected to the VFD tube. External circuit is not required.
£–10 mA
I
OH
Inverted Grid signal output pins. For pre-driver, the external circuit is required.
£10 mA
I
OL
Chip select input pin.
Data is not transferred when CS is set to a Low level.
Shift clock input pin.
Serial data shifts at the rising edge of the CLOCK.
Serial data input pin (positive logic).
Data is input to the shift register at the rising edge of the CLOCK signal.
Duplex/Triplex operation select input pin.
Duplex (1/2 duty) operation is selected when this pin is set to V
DD
.
Triplex (1/3 duty) operation is selected when this pin is set to L-GND.
M/S 36 I
DIM IN 26 I
34
24
SYNC IN 1 27 25
SYNC IN 2 28
DIM OUT 39 O
26
37
Master/Slave mode select input pin.
Master mode is selected when this pin is set to V
DD
.
Slave mode is selected when this pin is set to L-GND.
Dimming pulse input.
When the slave mode is selected, connect this pin to the master side DIM
OUT pin at the slave mode. The pulse width of the all segment output are
controlled by a input pulse width of DIM IN.
When the master mode is selected, the input level of this pin is ignored.
Connect this pin to V
or L-GND at the master mode. The pulse width of the
DD
all grids and segment outputs are controlled by a built-in 10-bit dimming circuit.
Synchronous signal input.
When the slave mode is selected, connect these pins to the master side SYNC
I
OUT 1 and 2 pins.
When the master mode is selected, the input level of these pins are ignored.
Connect these pins to V
or L-GND at the master mode.
DD
Dimming pulse output.
Connect this pin to the slave side DIM IN pin.
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