OKI ML9040-AxxGA, ML9040-BxxGA Datasheet

E2B0048-29-21

Prelim

This version: Feb. 1999

ML9040-Axx/-Bxx¡ Semiconductor

¡ Semiconductor

Previous version: Mar. 1996

ML9040-Axx/-Bxx

DOT MATRIX LCD CONTROLLER WITH 16-DOT COMMON DRIVER AND 40-DOT

SEGMENT DRIVER

GENERAL DESCRIPTION

The ML9040-Axx/-Bxx is a dot matrix LCD controller which is fabricated in low power CMOS
silicon gate technology. Character display on the dot matrix character type LCD can be
controlled in combination with a 4-bit or 8-bit microcontroller. This LSI consists of 16-dot
COMMON driver, 40-dot SEGMENT driver, display data RAM, character generator RAM,
character generator ROM and control circuit.

The ML9040-Axx/-Bxx has the character generator ROM that can be programmed by custom
mask. The ML9040-Axx/-Bxx is a standard version having 160 characters with lowercase (5 x
7 dots), and 32 characters with uppercase (5 x 10 dots) in this ROM.

inary

FEATURES

• Easy interface with an 8-bit or 4-bit microcontroller.

• Dot matrix LCD controller/driver for lowercase (5 x 7 dots) or uppercase (5 x 10 dots).

• Automatic power ON reset.

• COMMON signal drivers (16) and SEGMENT signal drivers (40).

• Can control up to 80 characters when used in combination with MSM5259.

• Character generator ROM for 160 characters with lowercase (5 x 7 dots) and 32 characters with
uppercase (5 x 10 dots).

• Character patterns are programmable by character generator RAM. (Lowercase: 5 x 8 dots,
8 patterns, uppercase: 5 x 11 dots, 4 patterns).

• Built-in oscillation circuit to connect with external resistor or ceralock.

• 1/8 duty (1 line; 5 x 7 dots + cursor), 1/11 duty (1 line; 5 x 10 dots + cursor), or 1/16 duty (2
lines; 5 x 7 dots + cursor), selectable.

• Clear display even at 1/5 bias, 3.0V LCD driving voltage.

• LCD driving waveform
ML9040-Axx: A mode
ML9040-Bxx: B mode

• Package options:

80-pin plastic QFP (QFP80-P-1420-0.80-BK)

(Product name: ML9040-Axx/-BxxGA)

xx indicates code number.

1

¡ SemiconductorML9040-Axx/-Bxx

2

BLOCK DIAGRAM

DO

SEG

1~40

40

COM

1~16

16

L
CP

DF

16

55

5

8

8

77

7

8

8

8

8

7

4

4

V

DD

GND

OSC

1

OSC

2

E
RS
R/W

DB

0

- DB

3

DB4 - DB

7

V

1

Common
signal
driver

16-bit
shift
register

Parallel/
serial
conver­sion

Cursor blink
control

Character
generator
ROM
(CG RAM)

Character
generator
RAM
(CG RAM)

Display data
RAM
(DD RAM)

Timing
generation
circuit

Input/
output
buffer

Instruction
register
(IR)

Instruction
decoder
(ID)

Data
register
(DR)

Busy flag
(BF)

Address
counter
(ADC)

4040

Seg­ment
signal
driver

40-bit
latch

40-bit
shift
register

V

2

V

3

V

4

V

5

INPUT AND OUTPUT CONFIGURATION

V

DD

ML9040-Axx/-Bxx¡ Semiconductor

V

DD

V

DD

P

N

Applicable to pin E.

V

DD

V

DD

P

N

V

Applicable to pins DB

DD

- DB7.

0

P

N

Applicable to pins R/W and RS.

P

V

DD

N

P

N

Applicable to pins DO, CP, L, and DF.

3

PIN CONFIGURATION (TOP VIEW)

ML9040-Axx/-Bxx GA

27

26

24

SEG

79

25

SEG

78

SEG

77

SEG

76

23

SEG

80

28

SEG

75

29

SEG

74

30

SEG

73

31

SEG

72

32

SEG

71

33

SEG

70

34

SEG

69

35

SEG

68

36

SEG

67

37

SEG

66

¡ SemiconductorML9040-Axx/-Bxx

38

SEG

65

SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG

SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG

GND

OSC

22
21
20
19
18
17
16
15
14
13
12
11
10

1
2
3
4
5
6
7
8

9
10
11
12
13
14

9

15

8

16

7

17

6

18

5

19

4

20

3

21

2

22

1

23
24

1

64
63
62
61
60
59
58
57
56
55
54

53
52
51
50
49
48
47
46
45
44
43
42
41

SEG
SEG
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
DB

7

DB

6

DB

5

DB

4

DB

3

DB

2

39
40

16
15
14
13

12
11
10
9
8
7
6
5
4
3
2
1

25

2

OSC

26

33

34

32

31

30

29

28

27

5

4

3

2

1

V

V

V

L

V

V

CP

V

DD

DF

35

DO

36

RS

37

R/W

38

40

39

1

0

E

DB

DB

80-Pin Plastic QFP

4

PIN DESCRIPTIONS

ML9040-Axx/-Bxx¡ Semiconductor

Symbol

Description

R/W Read/write selection input pin.

"H" : Read, and "L" : Write

RS Register selection input pin.

"H" : Data register, and "L" : Instruction register
E Input pin for data input/output with CPU and for instruction register activation.
DB0 - DB

7

OSC1, OSC

2

Input/output pins for data send/receive with CPU

Clock oscillating pins required for internal operation upon receipt of the LCD drive signal

and CPU instruction.
COM1 - COM

SEG1 - SEG

16

40

LCD COMMON signal output pins.

LCD SEGMENT signal output pins.
DO Output pin to be connected to MSM5259 to expand the number of characters to be

displayed.
CP Clock output pin used when DO pin data output shifts inside of MSM5259.

L Clock output pin for the serially transferred data to be latched to MSM5259.
DF The alternating current signal (Display Frequency) output pin.
V

DD

Power supply pin.
GND Ground pin.
V1, V2, V3, V4, V

Bias voltage input pins to drive the LCD.

5

5

ABSOLUTE MAXIMUM RATINGS

¡ SemiconductorML9040-Axx/-Bxx

Parameter

Supply Voltage

LCD Driving Voltage

Input Voltage V

Power Dissipation P
Storage Temperature T

Symbol Condition Rating Unit Applicable pin

Ta = 25°C –0.3 to + 7.0 V VDD, GND
Ta = 25°C

Ta = 25°C –0.3 to V

— 500 mW —
— –55 to + 150 °C—

V

1

V4, V

V

DD

, V2, V

5

I

D

STG

3

RECOMMENDED OPERATING CONDITIONS

Parameter

Supply Voltage
Data Holding Voltage

LCD Driving Voltage

*1

*2

Operating Temperature T

Symbol Condition Range Unit Applicable pin

V

V

DD

HOLD

— 4.5 to 5.5 V VDD, GND
— 3.0 to 5.5 V VDD, GND

1/4 bias, VDD–V

V

LCD

op

1/5 bias, VDD–V

— –20 to + 75 °C—

V

DD

V

DD

– 8.0 to

+ 0.3

V

V

1

V4, V

, V2, V

3

5

R/W, RS, E,

DB

+ 0.3 V

DD

*3

5

5

3.0 to 6.0 V

*4

3.0 to 6.0 V

0

OSC

V

DD

- DB

1

, V

7

5

*1 Voltage to assure Rf oscillation and register data retention.
*2 Voltage between VDD and V

5.

*3 Voltages applicable to V1, V2, V3 and V4 are as follows.

V1 = VDD – 1/4 (VDD – V5)
V2 = V3 = VDD – 1/2 (VDD - V5)
V4 = VDD – 3/4 (VDD – V5)

*4 V1 = VDD – 1/5 (VDD – V5)

V2 = VDD – 2/5 (VDD – V5)
V3 = VDD – 3/5 (VDD – V5)
V4 = VDD – 4/5 (VDD – V5)

6

ELECTRICAL CHARACTERISTICS

DC Characteristics

Parameter

"H" Input Voltage
"L" Input Voltage V
"H" Input Voltage V
"L" Input Voltage V
"H" Output Voltage V
"L" Output Voltage V
"H" Output Voltage V
"L" Output Voltage V
Driver ON Resistor
(COM pins)
Driver ON Resistor
(SEG pins)

Input Leakage Current

Input Current I

Symbol Condition Min. Typ. Max. Unit Applicable pin

— 2.2 — V
— –0.3 — 0.6 V
—V
— –0.3 — 1.0 V

IO = –0.205mA 2.4 — — V

IO = 1.2mA — — 0.4 V
IO = –40mA 0.9V

IO = 40mA — — 0.1V

VI = V

SS

= V

V

I

DD

R

V

R

IH1

IL1

IH2

IL2

OH1

OL1

OH2

OL2

COM

SEG

I

IL

IO = ±50mA, V

IO = ±50mA, V

VDD = 5.0V

= V

V

I

SS

VI = VDD, excluding current

IL2

flowing over pullup resistor

and output drive MOS

ML9040-Axx/-Bxx¡ Semiconductor

(V

= 4.5 to 5.5V, Ta = –20 to +75°C)

DD

DD

–1.0 — V

DD

DD

= 4V — — 20 kW COM1 - COM

LCD

= 4V — — 30 kW SEG1 - SEG

LCD

— — V DO, CP, L,

DD

——–1mA
——1mA

–50 –125 –250 mA

——2mA

V R/W, RS, E,

V

V

DD

DB

DB

DC, OSC

R/W, RS

DB

- DB

0

OSC

- DB

0

E

- DB

0

7

1

7

2

16

40

7

Supply Current (1) I

Supply Current (2) I

LCD Driving Bias
Input Voltage
Schmitt voltage
width
Built-in reset
detection voltage

V
V

V

V

DD1

DD2

LCD1

LCD2

SUM

RES

= 5.0V,

V

DD

resistor oscillation or
external clock input via

.

OSC

1

= 270kHz.

f

OSC

— 0.35 0.6 mA
E is in "L" level.
Other inputs are open.
Output pins are
all no load. *1

VDD = 5.0V,
ceramic oscillation,

= 250kHz.

f

OSC

E is in "L" level.

— 0.55 0.8 mA
Other pins are open.
Output pins are
all no load. *1

1/5 bias — 6.0

V

DD–V5

*6

1/4 bias — 6.0

——— TBD

3.0

3.0

V

V

3

TBD TBD V E

VDD, V1, V2,

——— — — 3.0 V V

V

DD

V

DD

, V4, V

DD

5

7

AC Characteristics

Parameter

R

Clock Oscillation

f

Frequency
Clock Input
Frequency

Symbol Condition Min. Typ. Max. Unit Applicable pin

f

OSC1

f

IN

Rf = 91kW ± 2%
*2
OSC2 is open.
Input from OSC

1

¡ SemiconductorML9040-Axx/-Bxx

= 4.5 to 5.5V, Ta = –20 to +75°C)

(V

DD

175 250 350 kHz

125 250 350 kHz OSC

OSC
OSC

1

2

1

Input Clock Duty f

DUTY

*3

45 50 55 % OSC

Input Clock Rise
Time

t

r

*4

— — 0.2 ms OSC

Input Clock Fall
Time

Ceramic Unit
Oscillation
Frequency

f

t

f

OSC

R

= 510kW,

f

= C2 = 200 pF,

C

1

= 30kW, and

R

d

Ceralock CSB250A.

*4

— — 0.2 ms OSC

245 250 255 kHz

*5

*1 Applicable to the current that flows in pin VDD when power is input as follows:

VDD = 5V, GND = 0V, V1 = 3.4V, V2 = 1.8V, V3 = 0.2V, V4 = -1.4V, and V5 = -3V.

*2

OSC

1

Rf=91kW±2%

Minimum wiring is required between
OSC

and Rf and between OSC2 and Rf.

1

OSC

R

f

2

OSC
OSC

1

1

1

1

2

8

ML9040-Axx/-Bxx¡ Semiconductor

*3 Applied to pulse input via OSC

0.5V

f

IN

waveform

*4 Applied to pulse input via OSC

VDD–1.0V

fIN
waveform

*5

OSC

.

1

DD

.(-Axx/-Bxx)

1

t

r

1

t

HW

0.5V

DD

f

= tHW/ (tHW + tLW) x 100(%)

DUTY

–1.0V

V

DD

1.0V1.0V

t

f

C

1

R

f

Ceralock

t

LW

0.5V

DD

OSC

2

R

d

C

2

Ceralock : CSB250A (mfd. by MURATA MFG.Co.)

R

: 510kW ±5%

f

: 30kW ±5%

R

d

: 200pF ±10%

C

1

: 200pF ±10%

C

2

Please contact us when using this circuit.

*6 Input the voltage listed in the table below to V1 - V5:

N (LCD lines)

1-line mode 2-line mode

Pin

V

V

1

V

2

V

3

V

4

V

DD

V

DD

V

DD

V

DD

LCD

–

4

V

LCD

–

2

V

LCD

–

2

3V

LCD

–

4

V

LCD

–

V

DD

V

DD

V

DD

V

DD

5

2V

LCD

–

5

3V

LCD

–

5

4V

LCD

–

5

V

5

V

is an LCD driving voltage. (For "N" (number of LCD lines),

LCD

– V

V

DD

LCD

refer to the initial set of the instruction code.)

– V

V

DD

LCD

9

¡ SemiconductorML9040-Axx/-Bxx

• Timing for output to the CPU

(V

= 4.5 to 4.5V, Ta = –20 to +75°C)

DD

Parameter

R/W and RS setup time
E "H" pulse width t
R/W and RS hold time t
E rise time t
E fall time t
E "L" pulse width t
E cycle time t

to DB7 data output delay time t

DB

0

to DB7 data output hold time t

DB

0

Symbol Min. Typ. Max. Unit

t

B

W

A

r

f

L

C

D

O

140 — — ns
280 — — ns

10 — — ns
— — 100 ns

— — 100 ns**
280 — — ns
667 — — ns

— — 220 ns

20 — — ns

* Values of tr and tf are design specification and are actually determined after sample

evaluation.

DB

0

R/W

-DB

RS

V

IH1

V

IH1

V

IL1

t

B

V

V

E

IL1

t

r

IH1

t

7

t

W

D

V

OH1

Output data

V

OL1

V

IH1

V

IH1

V

IL1

t

A

t

L

V

IH1

V

IL1

t

f

t

O

V

OH1

V

OL1

t

C

V

IL1

10

ML9040-Axx/-Bxx¡ Semiconductor

Switching Characteristics

• Timing for input from the CPU

(V

= 4.5 to 5.5V, Ta = –20 to +75°C)

DD

Parameter

R/W and RS setup time
E "H" pulse width t
R/W and RS hold time t
E rise time t
E fall time t
E "L" pulse width t
E cycle time t

to DB7 input data setup time t

DB

0

to DB7 input data hold time t

DB

0

* Values of tr and tf are design specification and are actually determined after sample

evaluation.

Symbol Min. Typ. Max. Unit

t

B

W

A

r

f

L

C

I

H

140 — — ns
280 — — ns

10—— ns
— — 100 ns

— — 100 ns
280 — — ns
667 — — ns
180 — — ns

10—— ns

*
*

DB

0

R/W

RS

E

- DB

V

IL1

V

IH1

V

IL1

V

V

IH1

IL1

t

W

t

I

Input data

t

B

V

IL1

IH1

V

t

r

7

V

IL1

V

IH1

V

IL1

t

A

t

L

V

IH1

V

IL1

t

f

t

H

V

IH1

V

IL1

t

C

V

IL1

11

• Timing for output to MSM5259

Parameter

CP "H" pulse width
CP "L" pulse width t
DO setup time t
DO holding time t
"L" clock set-up time t
"L" clock hold time t
"L" "H" pulse width t
DF delay time t

¡ SemiconductorML9040-Axx/-Bxx

= 4.5 to 5.5V, Ta = –20 to +75°C)

(V

DD

Symbol Min. Typ. Max. Unit

t

HW1

HW2

LW

S

DH

SU

HO

M

800 — — ns
800 — — ns
300 — — ns
300 — — ns
500 — — ns
100 — — ns
800 — — ns

–1000 — 1000 ns

DO

CP

DF

V

OH2

V

OL2

t

t

HW1

V

OH2VOH2

t

LW

V

OL2

s

V

OL2

OH2

V

OH2

V

L

V

OH2

V

OL2

t

DH

V

V

OL2

t

t

SU

HW2

V

OH2

t

HO

V

OL2

t

M

V

OH2

OH2

12

ML9040-Axx/-Bxx¡ Semiconductor

FUNCTIONAL DESCRIPTION

Instruction Register (IR) and Data Register (DR)

These two registers are selected by the REGISTER SELECTION (RS) pin.
The DR is selected when the "H" level is input to the RS pin and IR is selected when the "L"
level is input.
The IR is used to store the address of the display data RAM (DD RAM) or character
generator RAM (CG RAM) and instruction code.
The IR can be written, but not be read by the microcomputer (CPU).
The DR is used to write and read the data to and from the DD RAM or CG RAM.
The data written to DR by the CPU is automatically written to the DD RAM or CG RAM
as an internal operation.
When an address code is written to IR, the data (of the specified address) is automatically
transferred from the DD RAM or CG RAM to the DR. Next, when the CPU reads the DR,
it is possible to verify DD RAM or CG RAM data from the DR data.
After the writing of DR by the CPU, the next adress in the DD RAM or CG RAM is selected
to be ready for the next CPU writing.
Likewise, after the reading out of DR by the CPU, DD RAM or CG RAM data is read out
by the DR to be ready for the next CPU reading.
Write/read to and from both registers is carried out by the READ/WRITE (R/W) pin.

Table 1 RS and R/W pins functions

R/W

L

H L Read of busy flag (BF) and address counter (ADC)

L H DR write

H H DR read

RS Function

L IR write

Busy Flag (BF)

When the busy flag is at "H", it indicates that the ML9040-Axx/-Bxx is engaged in internal
operation.
When the busy flag is at "H", any new instruction is ignored.
When R/W = "H" and RS = "L", the busy flag is output from DB7.
New instruction should be input when busy flag is "L" level.
When the busy flag is at "H", the output code of the address counter (ADC) is undefined.

Address Counter (ADC)

The address counter (ADC) allocates the address for the DD RAM and CG RAM write/
read and also for the cursor display.
When the instruction code for a DD RAM address or CG RAM address setting is input to
IR, after deciding whether it is DD RAM or CG RAM, the address code is transferred from
IR to ADC. After writing (reading) the display data to (from) the DD RAM or CG RAM,
the ADC is incremented (decremented) by 1 internally.
The data of the ADC is output to DB0 - DB6 on the conditions that R/W = "H", RS = "L", and
BF = "L".

13

¡ SemiconductorML9040-Axx/-Bxx

Timing Generator Circuit

This circuit is used to generate timing signals to activate internal operations upon receipt
of CPU instruction and also from such internal circuits as the DD RAM, CG RAM, and CG
ROM.
It is designed so that the internal operation caused by accessing from the CPU will not
interfer e with the internal operation caused by LCD driving. Consequently, when data
is written from the CPU to DD RAM, flickering does not occur in a display area other than
the display area where the data is written.
In addition, this circuit generates the transfer signal to MSM5259 for display character
expansion.

Display Data RAM (DD RAM)

This RAM is used to store display data of 8-bit character codes (see Table 2).
DD RAM address corresponds to the display position of the LCD. The correspondence
between the two is described in the following.
DD RAM address (set to ADC) is expressed in hexadecimal notation as shown below:

ADC

(Example)
When DD RAM
address is 2A

DB

6

Hexadecimal notation Hexadecimal notation

HLHLH

2A

DB

LSBMSB

0

LL

(1) Corresponden ce between address and display position in the 1-line display mode

First
digit

MSB LSB

2023034045

01

00

794F80
4E

Display position
DD RAM address (hex.)

(2)When the ML9040-Axx/-Bxx alone is used, up to 8 characters can be displayed from the

first to eighth digit.

First
digit

00

2023034

01

04505606707

8

14

When the display is shifted by instruction, the correspondence between the LCD
display position and the DD RAM address changes as shown below:

First

(Display
shifted
to right)

(Display
shifted
to left)

digit

First
digit

2013024035046057068

00

4F

2033044055066077088

02

01

ML9040-Axx/-Bxx¡ Semiconductor

(3)When the ML9040-Axx/-Bxx is used with one MSM5259, up to 16 characters can be

displayed from the first to sixteenth digit as shown below:

First
digit

2023034045056067

00

01

07

8

100A110B120C130D140E150F169

08 09

MSM5259 displayML9040-Axx/-Bxx display

When the display is shifted by instruction, the correspondence between the LCD
display and the DD RAM address changes as shown below:

First
digit

(Display shifted to right)

2013024035046057068

4F

00

01

02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10(Display shifted to left)

07

1009110A120B130C140D150E169
08

MSM5259 displayML9040-Axx/-Bxx display

(4)Since the ML9040-Axx/-Bxx has a DD RAM capacity of up to 80 characters, up to 9

MSM5259 devices can be connected to ML9040-Axx/-Bxx so that 80 characters can be
displayed.

First
digit

2023034045056067078

01

00

08

100A110B120C130D140E150F169
09

1817

10 11

MSM5259 (1) displayML9040-Axx/-Bxx display

- (8) display

744A754B764C774D784E794F8073

48 49

MSM5259 (9) displayMSM5259 (2)

15