DOT MATRIX LCD CONTROLLER WITH 16-DOT COMMON DRIVER AND 40-DOT
SEGMENT DRIVER
GENERAL DESCRIPTION
The ML9040-Axx/-Bxx is a dot matrix LCD controller which is fabricated in low power CMOS
silicon gate technology. Character display on the dot matrix character type LCD can be
controlled in combination with a 4-bit or 8-bit microcontroller. This LSI consists of 16-dot
COMMON driver, 40-dot SEGMENT driver, display data RAM, character generator RAM,
character generator ROM and control circuit.
The ML9040-Axx/-Bxx has the character generator ROM that can be programmed by custom
mask. The ML9040-Axx/-Bxx is a standard version having 160 characters with lowercase (5 x
7 dots), and 32 characters with uppercase (5 x 10 dots) in this ROM.
FEATURES
inary
• Easy interface with an 8-bit or 4-bit microcontroller.
• Dot matrix LCD controller/driver for lowercase (5 x 7 dots) or uppercase (5 x 10 dots).
• Automatic power ON reset.
• COMMON signal drivers (16) and SEGMENT signal drivers (40).
• Can control up to 80 characters when used in combination with MSM5259.
• Character generator ROM for 160 characters with lowercase (5 x 7 dots) and 32 characters with
uppercase (5 x 10 dots).
• Character patterns are programmable by character generator RAM. (Lowercase: 5 x 8 dots,
8 patterns, uppercase: 5 x 11 dots, 4 patterns).
• Built-in oscillation circuit to connect with external resistor or ceralock.
• 1/8 duty (1 line; 5 x 7 dots + cursor), 1/11 duty (1 line; 5 x 10 dots + cursor), or 1/16 duty (2
lines; 5 x 7 dots + cursor), selectable.
• Clear display even at 1/5 bias, 3.0V LCD driving voltage.
• LCD driving waveform
ML9040-Axx: A mode
ML9040-Bxx: B mode
• Package options:
80-pin plastic QFP (QFP80-P-1420-0.80-BK)
(Product name: ML9040-Axx/-BxxGA)
xx indicates code number.
1
2
V
DD
GND
OSC
OSC
E
RS
R/W
DB
- DB
0
DB4 - DB
Input/
output
buffer
Timing
generation
circuit
8
8
Instruction
register
(IR)
Data
register
(DR)
Busy flag
(BF)
7
Instruction
8
decoder
(ID)
7
8
Address
counter
(ADC)
77
Cursor blink
control
Character
generator
RAM
(CG RAM)
8
Display data
RAM
(DD RAM)
16-bit
shift
register
Parallel/
serial
55
conversion
5
Character
generator
ROM
(CG RAM)
8
40-bit
shift
register
16
40-bit
latch
Common
signal
driver
4040
Segment
signal
driver
1
2
4
3
4
7
V
1
V
2
V
3
V
4
V
5
L
CP
DF
16
COM
1~16
40
SEG
1~40
DO
BLOCK DIAGRAM
¡ SemiconductorML9040-Axx/-Bxx
INPUT AND OUTPUT CONFIGURATION
V
DD
ML9040-Axx/-Bxx¡ Semiconductor
V
DD
V
DD
P
N
Applicable to pin E.
V
DD
V
DD
P
N
Applicable to pins DB
V
DD
- DB7.
0
P
N
Applicable to pins R/W and RS.
P
V
DD
N
P
N
Applicable to pins DO, CP, L, and DF.
3
PIN CONFIGURATION (TOP VIEW)
ML9040-Axx/-Bxx GA
27
26
25
23
24
SEG
SEG
SEG
SEG
SEG
80
79
76
77
78
28
SEG
75
29
SEG
74
30
SEG
73
31
SEG
72
32
SEG
71
33
SEG
70
34
SEG
69
35
SEG
68
36
SEG
67
37
SEG
66
¡ SemiconductorML9040-Axx/-Bxx
38
SEG
65
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
GND
OSC
1
22
2
21
3
20
4
19
5
18
6
17
7
16
8
15
9
14
10
13
11
12
12
11
13
10
14
9
15
8
16
7
17
6
18
5
19
4
20
3
21
2
22
1
23
24
1
64
SEG
39
63
SEG
40
62
COM
16
61
COM
15
60
COM
14
59
COM
13
58
COM
12
57
COM
11
56
COM
10
55
COM
9
54
COM
COM
COM
COM
COM
COM
COM
COM
DB
DB
DB
DB
DB
DB
8
7
6
5
4
3
2
1
7
6
5
4
3
2
53
52
51
50
49
48
47
46
45
44
43
42
41
25
2
OSC
26
2
1
V
V
5
4
3
V
V
V
CP
DD
V
33
32L31
30
29
28
27
37RS36DO35DF34
R/W
40
39
38
1
0
E
DB
DB
80-Pin Plastic QFP
4
PIN DESCRIPTIONS
ML9040-Axx/-Bxx¡ Semiconductor
Symbol
Description
R/WRead/write selection input pin.
"H" : Read, and "L" : Write
RSRegister selection input pin.
"H" : Data register, and "L" : Instruction register
EInput pin for data input/output with CPU and for instruction register activation.
DB0 - DB
OSC1, OSC
7
2
Input/output pins for data send/receive with CPU
Clock oscillating pins required for internal operation upon receipt of the LCD drive signal
and CPU instruction.
COM1 - COM
SEG1 - SEG
16
40
LCD COMMON signal output pins.
LCD SEGMENT signal output pins.
DOOutput pin to be connected to MSM5259 to expand the number of characters to be
displayed.
CPClock output pin used when DO pin data output shifts inside of MSM5259.
LClock output pin for the serially transferred data to be latched to MSM5259.
DFThe alternating current signal (Display Frequency) output pin.
V
DD
Power supply pin.
GNDGround pin.
V1, V2, V3, V4, V5Bias voltage input pins to drive the LCD.
5
ABSOLUTE MAXIMUM RATINGS
¡ SemiconductorML9040-Axx/-Bxx
Parameter
Supply Voltage
LCD Driving Voltage
Input VoltageV
Power DissipationP
Storage TemperatureT
SymbolConditionRatingUnitApplicable pin
Ta = 25°C–0.3 to + 7.0VVDD, GND
V
Ta = 25°C
DD
V
DD
Ta = 25°C–0.3 to V
—500mW—
—–55 to + 150°C—
V
1
V
DD
, V2, V
V4, V
I
D
STG
3
5
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Data Holding Voltage
LCD Driving Voltage
*1
*2
Operating TemperatureT
*1 Voltage to assure Rf oscillation and register data retention.
*2 Voltage between VDD and V
*3 Voltages applicable to V1, V2, V3 and V4 are as follows.
*6 Input the voltage listed in the table below to V1 - V5:
N (LCD lines)
1-line mode2-line mode
Pin
V
V
1
V
2
V
3
V
4
V
5
V
is an LCD driving voltage. (For "N" (number of LCD lines),
LCD
V
V
V
V
V
DD
DD
DD
DD
DD
–
–
–
–
– V
V
V
3V
LCD
LCD
4
LCD
2
LCD
2
LCD
4
refer to the initial set of the instruction code.)
V
LCD
–
V
DD
5
2V
LCD
–
V
DD
V
DD
V
DD
V
DD
–
–
– V
3V
4V
LCD
5
LCD
5
LCD
5
9
¡ SemiconductorML9040-Axx/-Bxx
• Timing for output to the CPU
(V
= 4.5 to 4.5V, Ta = –20 to +75°C)
DD
Parameter
R/W and RS setup time
E "H" pulse widtht
R/W and RS hold time t
E rise time t
E fall time t
E "L" pulse width t
E cycle time t
to DB7 data output delay time t
DB
0
to DB7 data output hold time t
DB
0
SymbolMin.Typ.Max.Unit
t
B
W
A
r
f
L
C
D
O
140 ——ns
280 ——ns
10 — —ns
——100 ns
——100 ns**
280 ——ns
667 ——ns
——220 ns
20 — —ns
*Values of tr and tf are design specification and are actually determined after sample
evaluation.
DB
0
R/W
-DB
RS
V
IH1
V
IH1
V
IL1
IH1
t
W
t
D
V
OH1
Output data
V
OL1
t
B
V
V
E
7
IL1
t
r
V
IH1
V
IH1
V
IL1
t
A
t
L
V
IH1
V
IL1
t
f
t
O
V
OH1
V
OL1
t
C
V
IL1
10
ML9040-Axx/-Bxx¡ Semiconductor
Switching Characteristics
• Timing for input from the CPU
(V
= 4.5 to 5.5V, Ta = –20 to +75°C)
DD
Parameter
R/W and RS setup time
E "H" pulse widtht
R/W and RS hold time t
E rise time t
E fall time t
E "L" pulse width t
E cycle time t
to DB7 input data setup time t
DB
0
to DB7 input data hold time t
DB
0
*Values of tr and tf are design specification and are actually determined after sample
evaluation.
SymbolMin.Typ.Max.Unit
t
B
W
A
r
f
L
C
I
H
140——ns
280——ns
10—— ns
——100ns
——100ns**
280——ns
667——ns
180——ns
10—— ns
DB
0
- DB
R/W
RS
E
V
IL1
V
IH1
V
IL1
V
V
IH1
IL1
t
W
Input data
t
I
t
B
V
V
t
r
7
IH1
IL1
V
IL1
V
IH1
V
IL1
t
A
t
L
V
IH1
V
IL1
t
f
t
H
V
IH1
V
IL1
t
C
V
IL1
11
• Timing for output to MSM5259
Parameter
CP "H" pulse width
CP "L" pulse widtht
DO setup timet
DO holding time t
"L" clock set-up time t
"L" clock hold timet
"L" "H" pulse widtht
DF delay time t
These two registers are selected by the REGISTER SELECTION (RS) pin.
The DR is selected when the "H" level is input to the RS pin and IR is selected when the "L"
level is input.
The IR is used to store the address of the display data RAM (DD RAM) or character
generator RAM (CG RAM) and instruction code.
The IR can be written, but not be read by the microcomputer (CPU).
The DR is used to write and read the data to and from the DD RAM or CG RAM.
The data written to DR by the CPU is automatically written to the DD RAM or CG RAM
as an internal operation.
When an address code is written to IR, the data (of the specified address) is automatically
transferred from the DD RAM or CG RAM to the DR. Next, when the CPU reads the DR,
it is possible to verify DD RAM or CG RAM data from the DR data.
After the writing of DR by the CPU, the next adress in the DD RAM or CG RAM is selected
to be ready for the next CPU writing.
Likewise, after the reading out of DR by the CPU, DD RAM or CG RAM data is read out
by the DR to be ready for the next CPU reading.
Write/read to and from both registers is carried out by the READ/WRITE (R/W) pin.
Table 1 RS and R/W pins functions
R/W
L
HLRead of busy flag (BF) and address counter (ADC)
LHDR write
HHDR read
RSFunction
LIR write
Busy Flag (BF)
When the busy flag is at "H", it indicates that the ML9040-Axx/-Bxx is engaged in internal
operation.
When the busy flag is at "H", any new instruction is ignored.
When R/W = "H" and RS = "L", the busy flag is output from DB7.
New instruction should be input when busy flag is "L" level.
When the busy flag is at "H", the output code of the address counter (ADC) is undefined.
Address Counter (ADC)
The address counter (ADC) allocates the address for the DD RAM and CG RAM write/
read and also for the cursor display.
When the instruction code for a DD RAM address or CG RAM address setting is input to
IR, after deciding whether it is DD RAM or CG RAM, the address code is transferred from
IR to ADC. After writing (reading) the display data to (from) the DD RAM or CG RAM,
the ADC is incremented (decremented) by 1 internally.
The data of the ADC is output to DB0 - DB6 on the conditions that R/W = "H", RS = "L", and
BF = "L".
13
¡ SemiconductorML9040-Axx/-Bxx
Timing Generator Circuit
This circuit is used to generate timing signals to activate internal operations upon receipt
of CPU instruction and also from such internal circuits as the DD RAM, CG RAM, and CG
ROM.
It is designed so that the internal operation caused by accessing from the CPU will not
interfer e with the internal operation caused by LCD driving. Consequently, when data
is written from the CPU to DD RAM, flickering does not occur in a display area other than
the display area where the data is written.
In addition, this circuit generates the transfer signal to MSM5259 for display character
expansion.
Display Data RAM (DD RAM)
This RAM is used to store display data of 8-bit character codes (see Table 2).
DD RAM address corresponds to the display position of the LCD. The correspondence
between the two is described in the following.
DD RAM address (set to ADC) is expressed in hexadecimal notation as shown below:
ADC
(Example)
When DD RAM
address is 2A
DB
6
Hexadecimal notationHexadecimal notation
HLHLH
2A
DB
LSBMSB
0
LL
(1) Corresponden ce between address and display position in the 1-line display mode
First
digit
2023034045
01
00
MSBLSB
794F80
4E
Display position
DD RAM address (hex.)
(2) When the ML9040-Axx/-Bxx alone is used, up to 8 characters can be displayed from the
first to eighth digit.
First
digit
2023034045056067078
00
01
When the display is shifted by instruction, the correspondence between the LCD
display position and the DD RAM address changes as shown below:
First
digit
(Display
shifted
to right)
(Display
shifted
to left)
2013024035046057068
00
4F
First
digit
2033044055066077088
02
01
14
ML9040-Axx/-Bxx¡ Semiconductor
(3)When the ML9040-Axx/-Bxx is used with one MSM5259, up to 16 characters can be
displayed from the first to sixteenth digit as shown below:
First
digit
2023034045056067078
00
01
100A110B120C130D140E150F169
0809
MSM5259 displayML9040-Axx/-Bxx display
When the display is shifted by instruction, the correspondence between the LCD
display and the DD RAM address changes as shown below: