OKI ML87V21071TB User Manual
OKI Semiconductor
PEDL87V21071-01
Issue Date: Nov. 15, 2005
ML87V21071
Video Signal Noise Reduction IC with a Built-in Frame Memory
Preliminary
GENERAL DESCRIPTION
The ML87V21071, which comprises a frame memory and signal processing and memory control logic circuits, has
achieved motion-adaptive 3D noise reduction.
To perform noise reduction with afterimage suppression, the ML87V210 71 also enables noise reduction using the
edge-adaptive 2D noise reduction filter.
Each noise reduction function allows setting an automatic mode. In automatic mode, noise of a vertical blanking
period and a valid data peri od is detected t o reduce noi se accordin g to the noise status fro m which t he noise reduct ion
setting value is detected.
The ML87V21071 also has a cross-color cancellation function that uses the motion-adaptive 3D comb filter method
that removes cross colors occurring at two-dimensional YC separation in the NTSC/PAL system.
Since the same format as the input can be selected for outpu t, n oise re ducti on can ea sil y be achie ved by i nsertin g t he
IC into the conventional system.
FEATURES
• Built-in memory:
Frame memory (78 × 608 × 16-bit) × 1 unit
• Maximum input and output operating frequencies (16-bit/8-bit, ITU-R BT.656):
14.75/29.5 MHz
* For 525p/625p, only 16-bit input mode is supported (Max.: 29.5 MHz).
• Power supply voltage:
3.3 V ± 0.3 V
• Input/ouput pin:
LVCMOS (3.3 V)
• Input/ouput data format:
YCbCr (8 bit (Y) + 8 bit (CbCr))(4:2:2): 16-bit mode
YCbCr (8 bit (YCbCr))(4:2:2): 8-bit mode
ITU-R656 (8 bit (YCbCr)): ITU-R BT.656 mode
* In 16-bit input mode, neither 8-bit mode nor ITU-R BT.656 mode can be selected for output.
• Serial bus:
2
C-bus interface: (400 kHz, 100 kHz)
I
• Memory controller:
Compatible with 625/50Hz 2:1(625i), 525/60Hz 2:1(525i), 625/50Hz 1:1(625p), and 525/60Hz 1:1(525p)
• Motion-adaptive 3D noise reduction:
Frame-field-line-correlation noise detection and noise subtraction method
Supports automatic noise reduction setting
• Edge-adaptive 2D noise reduction:
Edge-adaptive space filter used
• Chrominance signal cross color cancelling:
Motion-adaptive 3D comb filter used
Compatible with 525i (NTSC decode signal)/625i (PAL decode signal)
• Package:
100-pin TQFP (TQFP100-P-1414-0.50-K) (ML87V21071TB)
1/123
PEDL87V21071-01
OKI Semiconductor
BLOCK DIAGRAM
YI0-7
CI0-7
ICLK
IVS
IHS
x16
Input/Output
Process
Block
+
3D NR
+
2D NR
+
CC
x16
Frame
Memory
Memory
Controller
x16
ML87V21071
YO0-7
CO0-7
OVS
OHS
HREF
CLKO
SCL
SDA
SLA1
SLA2
MODE0-4
TEST0-5
RESET
I2C-bus
I/F
Register
Control
Signal
2/123
PEDL87V21071-01
OKI Semiconductor
PIN CONFIGURATION (TOP VIEW)
VDD
N.C.
V
MODE3
MODE4
N.C.
OE
N.C.
N.C.
N.C.
N.C.
TEST5
VDD
TEST4
TEST3
TEST2
TEST1
TEST0
N.C.
N.C.
TESTM
TSELF
VSS
N.C.
V
SS
TEST6
RESET
74
75
76
77
78
SS
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DD
YO7
TEST7
V
71
72
73
YO4
YO6
YO5
68
69
70
VDD
YO3
YO2
65
66
67
SS
N.C.
V
YO1
YO0
63
64
VDD
60
61
62
ML87V21071TB
(TQFP100-P-1414-0.5-K)
CO7
59
CO6
58
CO5
57
CO4
56
ML87V21071
VSS
CO3
CO2
CO1
CO0
51
52
53
54
55
50
VDD
49
N.C.
48
SS
V
47
HREF
46
OVS
45
OHS
44
N.C.
43
N.C.
42
N.C.
41
N.C.
40
V
DD
39
N.C.
38
N.C.
37
VSS
36
VDD
35
CLKO
34
MODE2
33
N.C.
32
MODE1
31
MODE0
30
IHS
29
IVS
28
VSS
27
N.C.
26
V
DD
1
YI7
YI6
VSS
N.C.
SCL
SDA
SLA1
SLA2
YI5
12
11
10
YI3
YI2
YI4
15
14
13
DD
YI1
YI0
V
16
ICLK
18
17
CI7
VSS
21
20
19
CI6
CI5
CI4
24
23
22
CI3
25
CI2
CI1
CI0
9
8
7
6
5
4
3
2
3/123
PEDL87V21071-01
OKI Semiconductor
PIN DESCRIPTIONS
No. Symbol I/O Pad Remarks Pin Description
1 N.C. —
2 VSS —
3 SDA I/O
4 SCL I Schmitt
5 SLA1 I
6 SLA2 I
7 YI7 I
8 YI6 I
9 YI5 I
10 YI4 I
11 YI3 I
12 YI2 I
13 YI1 I
14 YI0 I
15 VDD —
16 ICLK I
17 VSS —
18 CI7 I pull-down 50k
19 CI6 I pull-down 50k
20 CI5 I pull-down 50k
21 CI4 I pull-down 50k
22 CI3 I pull-down 50k
23 CI2 I pull-down 50k
24 CI1 I pull-down 50k
25 CI0 I pull-down 50k
26 VDD —
27 N.C. —
28 VSS —
29 IVS I
30 IHS I
31 MODE0 I
32 MODE1 I
33 N.C. —
Schmitt(IN)/
OpenDrain(OUT)
Schmitt
pull-down 50k
Schmitt
pull-down 50k
Schmitt
pull-down 50k
Schmitt
pull-down 50k
Schmitt
pull-down 50k
Schmitt
pull-down 50k
Unused pin
Ground
2
I
C-bus data pin
2
C-bus clock pin
I
Slave address setting pin bit 1
Slave address setting pin bit 2
Luminance signal input pin bit 7 (MSB)
Luminance signal input pin bit 6
Luminance signal input pin bit 5
Luminance signal input pin bit 4
Luminance signal input pin bit 3
Luminance signal input pin bit 2
Luminance signal input pin bit 1
Luminance signal input pin bit 0 (LSB)
3.3 V power supply
System clock Input pin
Ground
Chrominance signal input pin bit 7 (MSB)
Chrominance signal input pin bit 6
Chrominance signal input pin bit 5
Chrominance signal input pin bit 4
Chrominance signal input pin bit 3
Chrominance signal input pin bit 2
Chrominance signal input pin bit 1
Chrominance signal input pin bit 0 (LSB)
3.3 V power supply
Unused pin
Ground
Input system vertical Sync. signal input pin
Input system horizontal Sync. signal input pin
Mode setting pin bit 0
(Equivalent to internal register VMD[0])
Mode setting pin bit 1
(Equivalent to internal register HMD[0])
Unused pin
ML87V21071
Termination of
unused pin
Not used
X
X
X
Not used or
connected to GND
Not used or
connected to GND
X
X
X
X
X
X
X
X
X
X
X
Not used or
connected to GND
Not used or
connected to GND
Not used or
connected to GND
Not used or
connected to GND
Not used or
connected to GND
Not used or
connected to GND
Not used or
connected to GND
Not used or
connected to GND
X
Not used
X
Not used or
connected to GND
Not used or
connected to GND
Not used or
connected to GND
Not used or
connected to GND
Not used
4/123
PEDL87V21071-01
OKI Semiconductor
No. Symbol I/O Pad Remarks Pin Description
34 MODE2 I
35 CLKO O
36 VDD —
37 VSS —
38 N.C. —
39 N.C. —
40 VDD —
41 N.C. —
42 N.C. —
43 N.C. —
44 N.C. —
45 OHS O
46 OVS O
47 HREF O
48 VSS —
49 N.C. —
50 VDD —
51 CO0 O
52 CO1 O
53 CO2 O
54 CO3 O
55 VSS —
56 CO4 O
57 CO5 O
58 CO6 O
59 CO7 O
60 VDD —
61 N.C. —
62 VSS —
63 YO0 O
64 YO1 O
65 YO2 O
66 YO3 O
67 VDD —
68 YO4 O
69 YO5 O
70 YO6 O
71 YO7 O
72 VSS —
73 TEST7 I
74 TEST6 I
75
76 VDD —
RESET
I Schmitt
Schmitt
pull-down 50k
Schmitt
pull-down 50k
Schmitt
pull-down 50k
Mode setting pin bit 2
(Equivalent to internal register DISEL[0])
Clock output (I
3.3 V power supply
Ground
Unused pin
Unused pin
3.3 V power supply
Unused pin
Unused pin
Unused pin
Unused pin
Horizontal Sync. signal output pin
Vertical Sync. signal output pin
Data output horizontal reference signal output
pin
Ground
Unused pin
3.3 V power supply
Chrominance signal output pin bit 0 (LSB)
Chrominance signal output pin bit 1
Chrominance signal output pin bit 2
Chrominance signal output pin bit 3
Ground
Chrominance signal output pin bit 4
Chrominance signal output pin bit 5
Chrominance signal output pin bit 6
Chrominance signal output pin bit 7 (MSB)
3.3 V power supply
Unused pin
Ground
Luminance signal output pin bit 0 (LSB)
Luminance signal output pin bit 1
Luminance signal output pin bit 2
Luminance signal output pin bit 3
3.3 V power supply
Luminance signal output pin bit 4
Luminance signal output pin bit 5
Luminance signal output pin bit 6
Luminance signal output pin bit 7 (MSB)
Ground
Test input pin bit 7 (1: Test mode)
Test input pin bit 6 (1: Test mode)
System reset/input pin
0: System reset
1: Operation
3.3 V power supply
2
C-bus control possible)
ML87V21071
Termination of
unused pin
Not used or
connected to GND
Not used
X
X
Not used
Not used
X
Not used
Not used
Not used
Not used
Not used
Not used
Not used
X
Not used
X
Not used
Not used
Not used
Not used
X
Not used
Not used
Not used
Not used
X
Not used
X
X
X
X
X
X
X
X
X
X
X
Not used or
connected to GND
Not used or
connected to GND
X
X
5/123
PEDL87V21071-01
OKI Semiconductor
No. Symbol I/O Pad Remarks Pin Description
77 N.C. —
78 VSS —
79 MODE3 I
80 MODE4 I
81 N.C. —
82 OE —
83 N.C. —
84 N.C. —
85 N.C. —
86 N.C. —
87 TEST5 I
88 VDD —
89 TEST4 I
90 TEST3 I
91 TEST2 I
92 TEST1 I
93 TEST0 I
94 N.C. —
95 N.C. —
96 TESTM I
97 SELF I
98 VSS —
99 N.C. —
100 VDD —
Schmitt
pull-down 50k
Schmitt
pull-down 50k
Schmitt
pull-down 50k
Schmitt
pull-down 50k
Schmitt
pull-down 50k
Schmitt
pull-down 50k
Schmitt
pull-down 50k
Schmitt
pull-down 50k
Schmitt
pull-down 50k
Schmitt
pull-down 50k
Schmitt
pull-down 50k
Unused pin
Ground
Mode setting pin bit 3
(Equivalent to internal register R656I)
Mode setting pin bit 4
(Equivalent to internal register DOSEL)
Unused pin
Output enable input pin
Unused pin
Unused pin
Unused pin
Unused pin
Test input pin bit 5 (1: test mode)
3.3 V power supply
Test input pin bit 4 (1: test mode)
Test input pin bit 3 (1: test mode)
Test input pin bit 2 (1: test mode)
Test input pin bit 1 (1: test mode)
Test input pin bit 0 (1: test mode)
Unused pin
Unused pin
Memory test input pin (1: test mode)
Self refresh test input setting pin
Ground
Unused pin
3.3 V power supply
ML87V21071
Termination of
unused pin
Not used
X
Not used or
connected to GND
Not used or
connected to GND
Not used
Not used or
connected to GND
Not used
Not used
Not used
Not used
Not used or
connected to GND
X
Not used or
connected to GND
Not used or
connected to GND
Not used or
connected to GND
Not used or
connected to GND
Not used or
connected to GND
Not used
Not used
Not used or
connected to GND
Not used or
connected to GND
X
Not used
X
6/123
PEDL87V21071-01
OKI Semiconductor
ML87V21071
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Symbol Condition Rating Unit
Power supply voltage
Input pin voltage
Output pin short-circuit current
Power dissipation
Operating temperature
Storage temperature
Recommended Operating Conditions
Parameter Symbol Min. Typ. Max. Unit
Power supply voltage VDD 3.0 3.3 3.6 V
Power supply voltage VSS 0 0 0 V
Operating temperature
Pin Capacitance
Parameter Symbol Min. Max. Unit
Input capacitance Ci — 7 pF
Input/output capacitance (SDA) Cio — 7 pF
Output capacitance Co — 7 pF
V
DD
V
I
I
OS
P
D
T
— 0 to 70
opr
T
— –50 to +150
stg
Ta = 25°C
Ta = 25°C –0.5 to V
Ta = 25°C
Ta = 25°C
–0.5 to +4.6 V
+ 0.5 ≤ 4.6
DD
50 mA
1 W
Ta 0 — 70
(VCC = 3.3 V ± 0.3 V, f = 1 MHz, Ta = 25°C)
V
°C
°C
°C
7/123
PEDL87V21071-01
OKI Semiconductor
ML87V21071
DC Characteristics
(Ta = 0 to 70°C)
Parameter Symbol Condition Min. Max. Unit
V
“H” level input voltage V
“L” level input voltage V
“H” level input voltage
(TEST1–TEST7, TESTM, SELF)
“L” level input voltage
(TEST1–TEST7, TESTM, SELF)
“H” level input voltage
(SDA, SCL, IVS, IHS, RESET)
“L” level input voltage
(SDA, SCL, IVS, IHS, RESET)
—
IH1
—
IL1
V
IH2
V
IL2
V
Schmitt
IH3
Schmitt –0.3
V
IL3
—
—
V
V
V
DD
–0.3
DD
–0.3
DD
× 0.7
× 0.75
× 0.75
+0.3 V
DD
× 0.3
V
DD
+0.3 V
V
DD
V
× 0.25
DD
+0.3 V
V
DD
V
× 0.25
DD
V
V
V
“H” level input current (pull-down) IIH 50 kΩ pull down 20 200 µA
Input leakage current IIL — –10 +10 µA
“H” level output voltage (other than SDA) VOH I
“L” level output voltage (other than SDA) VOL I
“L” level output voltage (N-Ch. OD)
(SDA)
V
I
OOL
Output leakage current IOL
Supply current (during operation) I
Supply current (during standby) I
DD1
Input pin = 0 V — 5 mA
DD2
= –4 mA 2.4 VDD V
OH
= 4 mA 0 0.4 V
OL
= 4 mA 0 0.4 V
OL
0 ≤ V
≤ VDD
out
Output disabled
ICLK: 29.5MHz
Output disabled
–10 +10 µA
— 100 (TBD) mA
AC Characteristics
(Ta = 0 to 70°C)
Parameter Symbol Condition Min. Max. Unit
t
ICLK clock cycle time
ICLK clock duty ratio
ICLK input set-up time
ICLK input hold time
ICLK output delay time
CLKO delay time
Data through time
— 33 — ns
ICLK
dt
— 40 60 %
ICLK
t
— 5 — ns
IISU
t
— 3 — ns
IIH
t
C
IOD
t
CKD
t
DIDO
CL = 30 pF (IICLK output) 2 25
C
L
C
= 30pF 2 25 ns
L
= 30 pF (ICLK output) 2 17
= 30 pF 2 17 ns
L
ns
Note 1: Measurement conditions
Output comparison level: V
Input voltage level: V
IH
= VDD/2, VOL = VDD/2
OH
= VDD, VIL = 0.0 V
Note 2: Input/output data for the internal memory is guaranteed from the third input-system vertical synchronization
signal with RESET = 1 after V
reaches 3.0 V after the power is turned on. (Due to memory initialization,
DD
the first and second data for two fields is not guaranteed.)
8/123
PEDL87V21071-01
OKI Semiconductor
INPUT/OUTPUT TIMING
1. ICLK Input/Output Timing
ICLK
DATA &
CONTROL
INPUT (ICLK)
DATA &
CONTROL
OUTPUT (ICLK)
CLKO
(CKINV=0)
CLKO
(CKINV=1)
2. Data through Mode Input/Output Timing
t
IISU
t
CKD
t
CKD
t
IOD
ML87V21071
t
ICLK
50%
t
IIH
50%
50%
50%
50%
DATA &
CONTROL
INPUT
DATA &
CONTROL
OUTPUT
t
DIDO
50%
50%
9/123
PEDL87V21071-01
OKI Semiconductor
3. System Reset Timing
Power ON
1ms (Min.)
Power
supply
voltage
RESET
* When the power supply voltage reaches V
RESET pin for 1 ms or more to initialize the internal circuits.
* After the RESET pin goes to 1, the I
Don't care
(3.0 to 3.6 V) from 0 V after power is turned on, input 0 to the
DD
2
C-bus interface can be used while the input of ICLK is stable.
ML87V21071
V
DD
0 V
V
DD
0 V
10/123
PEDL87V21071-01
OKI Semiconductor
ML87V21071
FUNCTIONAL DESCRIPTION
1. Input/Output
1.1 Memory Control
The ML87V21071 accesses data to the input data frame memory by generating a line access type memory control
signal from Sync. signals of the IVS and IHS pin inputs or the Sync. signals separated from SAV and EAV, and
achieves noise reduction of frame/field/line adaptation recursive type.
1.1.1 Input Control Mode Settings
As shown in the table below, this IC offer s a choi ce of 12 i nput cont rol m odes includi ng the progressi ve m ode by
the INPR setting (SUB:44h-bit[7]), which can be selected by setting either the external setting pin mode (IRMON
= 0 (SUB: 40h–bit [7]) or internal register mode (IRMON = 1).
In ITU-R BT.656 input mode and i n the m ode of vali d 720 pixel s in the horizont al directi on (HM D[1:0] =0h), the
IC checks the mode by measuring the blanking period (between EAV and SAV) of the timing reference code of
the input data (YI[7:0]) and automatically sets VMD[0] by setting APN656 = 1 (SUB: 41h-bit[2]).
During APN656=1, do not set any value other than HMD[1:0]=1.
Table F1-1-1 (1) Input Control Mode Setting Allocation 1
IRMON
0 SUB:40h-bit[1]
1 SUB:40h-bit[1] SUB:40h-bit[0] SUB:40h-bit[3] SUB:40h-bit[2]
[1] [0] [1] [0]
VMD HMD
MODE 0
(External pin)
SUB:40h-bit[3]
MODE 1
(External pin)
Table F1-1-1 (2) Input Control Mode Setting Allocation 2
INPR Mode
0 Interlace (525i/625i)
1 Progressive (525p/625p)
* In progressive mode, neithe r 8-bit input m ode nor ITU-R BT.6 56 input mode can be
seected.
Table F1-1-1 (3) Input Control Mode Settings(INPR=0: Interlace)
VMD HMD
[1] [0] [1] [0]
0 0 0 0 625/50Hz 2:1 288 13.5/27 864 720
0 1 0 0 525/60Hz 2:1 243 13.5/27 858 720
0 0 0 1 625/50Hz 2:1 288 14.75/29.5 944 768
0 1 0 1 525/60Hz 2:1 243
0 0 1 0 625/50Hz 2:1 288 14.75/29.5 944 768
0 1 1 0 525/60Hz 2:1 243
Other than above Test modes
Vertical mode
The input system internal clock frequency f
16-bit input mode: f
IICLK
= f
ICLK
8-bit input mode/ITU-R BT.656 mode: f
Number of
valid lines
is as follows:
IICLK
= f
IICLK
Standard clock
frequency f
12.272727/
24.545454
14.31818/
28.63636
/2
ICLK
[MHz]
ICLK
Standard pixels
per line
780 640
910 768
Valid pixels
11/123
PEDL87V21071-01
OKI Semiconductor
ML87V21071
Table F1-1-1 (4) Input Control Mode Settings(INPR=1: Progressive)
VMD HMD
[1] [0] [1] [0]
Vertical mode
Number of
valid lines
0 0 0 0 625/50Hz 1:1 288 27 864 720
0 1 0 0 525/60Hz 1:1 243 27 858 720
0 0 0 1 625/50Hz 1:1 288 29.5 944 768
0 1 0 1 525/60Hz 1:1 243 24.545454 780 640
0 0 1 0 625/50Hz 1:1 288 29.5 944 768
0 1 1 0 525/60Hz 1:1 243 28.63636 910 768
Other than above Test modes
The input system internal clock frequency f
16-bit input mode: f
IICLK
= f
ICLK
is as follows:
IICLK
Standard clock
frequency f
ICLK
[MHz]
Standard pixels
per line
Valid pixels
12/123
PEDL87V21071-01
OKI Semiconductor
ML87V21071
1.1.2 Input System Field Detection
The IC detects the input data field from the phase of IVS and IHS and generates the input field pulse (IF) to
control the internal memory.
The field detection pulse can be selected from the IHS (IFLS = 0) or from 0.5H pulse IHALF (IFLS = 1) by setting
2
the I
C-bus setting register IFLS (SUB:42h-bit[3]).
In the rear edge of judgment area, since the field ju dgm ent uncert ainty are a cont ains 10 c locks o f IICL K (inter nal
input system clock), external phase adjustment will be necessary if the phase of IVS lies in this area. (However,
there is no problem if the change of IVS and IHS is in the same phase.)
When a single field Sync. signal is input (8 fields or more) while the output is in progressive mode, the inter-frame
movement compensation stops.
The device also has the function to automatical ly generate a field pulse by judging a si ngle field Sync . signal input
(continuous for more than 8 fields) with the setting of FCON (SUB:42h-bit[7]) = 1. For example, if there is only
field A input, the pulse toggled by IVS is regarded as the field pulse.
IVS
Field A detection
phase
IHS
Field A detection
0.5H
phase
pulse
#IF
Figure F1-1-2 (1) Input System Field A Detection Timing
IVS
Field B detection
phase
IHS
Field B detection
0.5H
phase
pulse
#IF
Figure F1-1-2 (2) Input System Field B Detection Timing
13/123
PEDL87V21071-01
OKI Semiconductor
IVS
#IF
Figure F1-1-2 (3) Field Detection during Continuous Same Field Input (FCON = 1)
IHS
or
0.5H pulse
Field A Field A Field A
Field A Field B Field A
Field A judgment area
Field judgment margin (10 clocks)
Field judgment uncertainty area
Field B judgment area
Field judgment margin (10 clocks)
Field judgment uncertainty area
Figure F1-1-2 (4) Field Judgment Uncertainty Area
ML87V21071
14/123
PEDL87V21071-01
OKI Semiconductor
ML87V21071
1.1.3 Setting Input System Write Enable and Read Enable
This IC generates the write enable signals (IWE) for writing data in the valid area made up of the valid vertical
lines and the valid horizontal pixels defined by the input control mode settings to the write port of the frame
memory.
With the write enable, it is possible to set the starting point in the vertical and horizontal directions. This setting
makes it possible to position the areas of valid lines and valid pixels with non-standard phase Sync. signals.
This IC also generates a Read Enable (IRE) signal for Read operation to establish recursive noise reduction.
By setting PAOS (SUB:72h-bit[4]) to 1, the valid start offset, which is 2 lines at the setting of INPR=0 and 4 lines
at the setting of INPR=1, is set and the number of valid lines is reduced by 2 lines or 4 lines from the normal
condition.
Table F1-1-3(1) Valid Input Data Area (INPR=0: Interlace)
VMD HMD
[1] [0] [1] [0]
0 0 0 0 288(286) 720
0 1 0 0 243(241) 720
0 0 0 1 288(286) 768
0 1 0 1 243(241) 640
0 0 1 0 288(286) 768
0 1 1 0 243(241) 768
Other than above Test modes (not settable)
Valid lines Valid pixels
Table F1-1-3(2) Valid Input Data Area (INPR=1: Progressive)
VMD HMD
[1] [0] [1] [0]
0 0 0 0 576(572) 720
0 1 0 0 486(482) 720
0 0 0 1 576(572) 768
0 1 0 1 486(482) 640
0 0 1 0 576(572) 768
0 1 1 0 486(482) 768
Other than above Test modes (not settable)
Valid lines Valid pixels
15/123
PEDL87V21071-01
OKI Semiconductor
IHS
IWE
IRE
YI
CI
IHS
IWE
IRE
YI
CI
243/288/486/576lines
: Valid data : Invalid data
Figure F1-1-3(1) Input Vertical Valid Lines
720/640/768pixels
: Valid data : Invalid data
Figure F1-1-3(2) Input Horizontal Valid Pixels
ML87V21071
16/123
PEDL87V21071-01
OKI Semiconductor
• Setting of Input System Vertical Valid Line Start Position
The input system vertical valid line start position (IVPS) is set in line unit with reference to the input system
vertical reset (IVR: internal signal ), generated from IVS, by setting N PVWE[4:0] (SUB :44h-bit[4:0]) . Data of
valid lines is written in the memory taking the input data subsequent to IVPS as valid data.
For this value, ±7 lines (15 stages) can be set for the reference position (NPVWE[3:0]=8h) in interlace mode
(INPR=0) and in progressive mode (INPR=1), ±15 lines (31 stages) can be set for the reference position
(NPVWE[4:0]=10h).
In interlace mode, NPVWE[4] is ignored.
Table F1-1-3 (3) Input System Vertical Valid Line Start Position (INPR=0: Interlace)
R656I
0 0 0 13 (–7 lines)
0 0 1 7 (–7 lines)
1 0 0 17 (–7 lines) (*1)
1 0 1 12 (–7 lines) (*1)
Other than above Test modes (not settable)
*1: In the case of field B, it is +1.
VMD IVPS position (number of IHS’s from IVR)
[1] [0] NPVWE=1h
……
……
……
……
……
NPVWE=8h
20 (default)
14 (default)
24 (default) (*1)
19 (default) (*1)
……
……
……
……
……
NPVWE=Fh
27 (+7 lines)
21 (+7 lines)
31 (+7 lines) (*1)
26 (+7 lines) (*1)
Table F1-1-3 (4) Input System Vertical Valid Line Start Position (INPR=1: Progressive)
R656I
0 0 0 24 (–15 lines)
0 0 1 12 (–15 lines)
VMD IVPS position (number of IHS’s from IVR)
[1] [0] NPVWE=1h
……
……
……
NPVWE=10h
49 (default)
27 (default)
……
……
……
NPVWE=1Fh
54 (+15 lines)
42 (+15 lines)
IVS
7 lines7 lines
ML87V21071
IHS
#IVR
#IWE/IRE
YI[7:0]
CI[8:0]
IVS
IHS
#IVR
#IWE/IRE
YI[7:0]
CI[8:0]
IVPS
288/243 lines
: Valid data #: Internal signal
Figure F1-1-3 (3) Input System Vertical Valid Line Start Timing (INPR=0)
15 lines15 lines
IVPS
576/486 lines
: Valid data #: Internal signal
Figure F1-1-3 (4) Input System Vertical Valid Line Start Timing (INPR=1)
17/123
PEDL87V21071-01
OKI Semiconductor
ML87V21071
• Setting of Input System Horizontal Valid Pixel Start Position
The input system horizontal valid pixel start position (IHPS) is set in pixel unit with reference to the input
system horizontal reset (IHR: internal signal), generated from IHS, by setting NPHWE[7:0]
(SUB:45h-bit[7:0]).
The data subsequent to IHPS is written in the data memory of valid pixels as the valid data.
This value can be set in 255 levels of ±127 pixels with regard to the initial value (NPHWE[7:0] = 80h).
In the ITU-R BT.656 mode, the value cann ot be set. Wri te enable with regard to valid data is generated on the
basis of detected SAV, EAV.
Table F1-1-3 (5) Input System Horizontal Valid Pixel Start Position
HMD IHPS position (Number of pixels from IHS)
[1] [0]
0 0 0 17 (–127 pixels)
0 0 1 11 (–127 pixels)
0 1 0 49 (–127 pixels)
0 1 1 13 (–127 pixels)
1 0 0 49 (–127 pixels)
1 0 1 15 (–127 pixels)
Other than above Test modes (Setting inhibited)
VMD
[0]
NPHWE=01h
……
……
……
……
……
……
……
NPHWE=80h
144 (default)
138 (default)
176 (default)
140 (default)
176 (default)
142 (default)
……
……
……
……
……
……
……
NHPWE=FFh
271 (+127 pixels)
265 (+127 pixels)
303 (+127 pixels)
267 (+127 pixels)
303 (+127 pixels)
269 (+127 pixels)
127 pixels127 pixels
IHS
IHPS
#IWE
1 pixel
YI[7:0]
CI[7:0]
640/720/768 pixels
1 pixel
Valid data
Figure F1-1-3 (5) Input System Horizontal Valid Pixel Start Timing
18/123
PEDL87V21071-01
[
]
[
]
OKI Semiconductor
ML87V21071
1.1.4 Input System Sync. Signal Polarity Inversion Setting
Negative polarity IVS can also be supported by setting the I
2
C-bus setting register IVSINV (SUB:42h-bit[0]).
Moreover, with regard to field detection, setting is possible even when setting the internal IVR generation edge.
Table F1-1-4 (1) IVINV Setting
IVSINV Recommended input IVS polarity IVR generation edge
0 Positive (default) Rising edge
1 Negative Falling edge
IVSINV=1IVSINV=0
IVS
IWE
Value set by
NPVWE[3:0]
IVS
IWE
Value set by
NPVWE[3:0]
Figure F1-1-4 (1) Support of Input System Vertical Sync. Signal Polarity Inversion
Negative polarity IHS can also be supported by setting the I
2
C-bus setting register IHSINV (SUB:42h-bit[1]).
Table F1-1-4 (2) IHSINV Setting
IHSINV Input IHS polarity
0 Positive (default)
1 Negative
IHSINV=1IHSINV=0
IHS
IWE
Value set by
NPHWE
7:0
IHS
IWE
Value set by
NPHWE
Figure F1-1-4 (2) Support of Input System Horizontal Sync. Signal Polarity Inversion
7:0
19/123
PEDL87V21071-01
OKI Semiconductor
ML87V21071
1.1.5 Input System Detection Field Inversion Setting
Inversion of input system internal field detection is possible by setting IFINV (SUB:42h-bit[2]) by I
interface. However, setting is not necessary if there is no problem in normal detection.
Table F1-1-5 IFIND Setting
IFINV
0 0 1
1 1 0
Field A Field B
Input field
* PAL : Field A = 1st, 3rd, 5th, 7th color field
Field B = 2nd, 4th, 6th, 8th color field
* NTSC : Field A = 2nd, 4th color field
Field B = 1st, 3rd color field
1.1.6 Input System Vertical Reset Compensation Mode Setting
In this IC, the rear edge (in the case of standard signal, 625 lines; A-3 line, 0.5H position, in between B-315 an d
B-316 lines, 525 lines; A-6 line, 0.5H position, in between B-6 and B-7 lines) of normally standard vertical Sync.
signal (IVS) is regarded as the reference position (IVR generating position) to perform field detection and
memory control.
If a Sync. signal with unspecified phase of the IVS rear edge and horizo n t al Sy nc. signal (IHS) is input, the front
edge can be used with the setting IVSINV = 1. But if the front edge is used in standard 626-line mod e, the
detection filed reverses in normal operation and field B gets written in the memory with one line earlier phase.
Therefore, by setting the I
2
C-bus setting register IVEM (SUB:42h-bit[4]), the detection field is inve rted (A→B,
B→A) and the vertical phase with regard to field B of the inverted result is delayed by 1H.
This allows compensation for field detection and IVR which is the typical front edge phase of IVS of 625-line
mode.
In practice, this allows compliance with the Sync. signal examples shown in Table F1-1-6 and Figure F1-1-6.
Note: Use it in case the phase of field-detecting IVS and IHS reverses in the IC standard setting.
Table F1-1-6 Input System Vertical Reset Compensation by IVEM Setting
Condition
Phase 1
Phase 2
Phase 3
Phase 4
Vertical
reference
Rear edge
IVSINV = 0
Rear edge
IVSINV = 0
Front edge
IVSINV = 1
Front edge
IVSINV = 1
Input
data field
A A n
B B
A B A n
B A
A A n
B B
A B A n
B A
Internal
decision field
IVEM
setting
0 No compensation
1
0 No compensation
1
Field after
compensation
B n + 1
B n + 1
Valid data start
position
n
n
2
C-bus
20/123
PEDL87V21071-01
OKI Semiconductor
Input sync signal phase 1
Field A input
IHS
IVS
#IVR
#IF
Field B input
IHS
IVS
#IVR
#IF
Input sync signal phase 2
Field A input
IHS
IVS
#IVR
#IF
0 1 2 nn-1
0 1 2 nn-1
ML87V21071
Input sync signal phase 3
nn-10 1 2
Input sync signal phase 4
IHS
IVS
#IVR
#IF
IHS
IVS
#IVR
#IF
IHS
IVS
#IVR
#IF
Field A input
0 1 2 nn-1
Field B input
Field A input
0 1 2 nn-1
3 4 5
3 4 5
3 4 5
nn-10 1 2
IHS
IVS
#IVR
#IF
Field B input
nn-10 1 2 n+1
IHS
IVS
#IVR
#IF
Field B input
3 4 5
nn-10 1 2 n+1
Figure F1-1-6 Input System Vertical Reset Compensation by IVEM Setting
21/123
PEDL87V21071-01
OKI Semiconductor
ML87V21071
1.1.7 Stop Memory Write Setting (Freeze Function)
By setting the I
2
C-bus settings register STL[2:0] (SUB:43h-bit[2:0]), you can stop writing data to the memory.
When you do this, the noise reduction feature stops.
Further, by setting STLM[1:0] (SUB:43h-bit[4:3]), field still image output, frame still image output, or frame still
median) image output can be selected.
The still image data output is achieved by rewriting only the signals read from the memory for the valid data
period selected by the IBLK signal, which indicates the valid data. Therefore, it is necessary to input the input
Sync. signals as normal.
The data output as a field or frame (median) still image is based on the most recent data written to the memory
(before the writing was stopped).
The timing of the writing stop and restoration can be set in one of the following three modes: selected field A/B
timing, field A timing, and field B timing.
In the mode of selected field A/B timing, writing is stopped after data for the next frame (field A + field B) after
writing stop is set is written. Writing is restored from the next frame after writing restoration is set. In this mode,
the field still image output depends on the writing stop setting timing.
In the mode of field A timing, after data for one frame (field B + field A) is written from the field B after writing
stop is set, writing is stopped from the next field B vertical Sync. signal. Writing is restored with the field B
vertical Sync. signal. In this mode, field A is always output for the field still image output.
In the mode of field B timing, after data for one frame (field A + field B) is written from the field A after writing
stop is set, writing is stopped from the next field A vertical Sync. signal. Writing is restored with the field A
vertical Sync. signal. In this mode, field B is always output for the field still image output.
When INPR is set to 1, the setting of field timing STL[2:1] is ignored and only STL[0] stop operation is
performed.
Table F1-1-7(1) Writing Stop Settings
STL
[2] [1] [0]
0 0 0 Possible (field A restoration)
0 1 0 Possible (field B restoration)
1 X 0 Possible (either field restoration)
0 0 1 Stopped (field A maintained)
0 1 1 Stopped (field B maintained)
1 X 1 Stopped (either field output maintained)
Input data writing
Table F1-1-7 (2) Still Image Output Mode Settings
STLM
[1] [0]
0 X Field image
1 0 Frame image
1 1 Frame image (median)
Output still image
22/123
PEDL87V21071-01
OKI Semiconductor
[Field A timing setting example 1]
IVS
Field
[Field A timing setting example 2]
IVS
Field
[Field B timing setting example 1]
IVS
Field
[Field B timing setting example 2]
IVS
Field
Writing stop set
A B
A B
A B A B A B A B A B A B
Writing stop processing
A B
A B A B A B A B A B A B
A B A B A B A B A B AB
Writing stop processing
start position
Writing stop processing
A B A B A B A B A B A B
Writing stop processing
start position
start position
Frame for pre-stop
write processing
start position
Frame for pre-stop
write processing
Frame for pre-stop
write processing
Frame for pre-stop
write processing
Stopping period
Stopping period
Writing restoration set
Stopping period
Writing stop processing
end position
Stopping period
Writing stop processing
end position
Writing stop processing
Writing stop processing
Figure F1-1-7 (1) Writing Stop/Restoration Timing
ML87V21071
end position
AB
end position
Input data
Memory data
Valid dataBLK data
Valid data
#IBLK
Output data
BLK data Valid data
Figure F1-1-7(2) Output Data in Still Image Mode
* When MEM411 is set to 1, output data from the memory is converted to 4:2:2 data (pseudo conversion) through
linear interpolation of c hrom inance data si nc e the o utput da t a is 4:1: 1 data . The refore , t he ban d o f t he da ta on t he
chrominance side deteriorates from that of the normal data.
23/123
PEDL87V21071-01
OKI Semiconductor
ML87V21071
1.2 Input/Output Format
1.2.1 Input Data Format
The input of this IC complies with 16-bit 4:2:2 (YI[7:0] = Y-8bit, CI[7:0] = CbCr-8bit 4:2:2) format (input in
16-bit mode), 8-bit 4:2:2 (YI[7:0] = YCbCr-8bit 4:2:2, without SAV, EVA) format (input in 8-bit mode) and
ITU-R BT.656 conforming (YI[7:0] = YCbCr-8bit 4:2:2, with SAV, EAV) format (ITU-R BT.656 mode).
However, when INPR is set to 1, neither 8-bit input mode nor ITU-R BT.656 input mode can be selected.
The input format mode is set by an exte rnal pin MODE 2 or I
R656 (SUB:41h-bit[1]).
Switching of an external pin and a register is accomplished by setting the I
2
C-bus setting register DISEL (SUB: 4 1h -bit[0]), or
2
C-bus setting register IRMON
(SUB:40h-bit[7]).
Table F1-2-1 (1) Input Data Format Mode
IRMON MODE2 DISEL R656I Mode
0 0 X 0
1 X 0 0
0 1 X 0
1 X 1 0
X X X 1 ITU-R BT.656 mode
Input in 16-bit mode
Input in 8-bit mode
Table F1-2-1(2) Input Data Format
Input pin Input in 16-bit mode
YI7 Y07 Y17 Cb07 Y07 Cr07 Y17
YI6 Y06 Y16 Cb06 Y06 Cr06 Y16
YI5 Y05 Y15 Cb05 Y05 Cr05 Y15
YI4 Y04 Y14 Cb04 Y04 Cr04 Y14
YI3 Y03 Y13 Cb03 Y03 Cr03 Y13
YI2 Y02 Y12 Cb02 Y02 Cr02 Y12
YI1 Y01 Y11 Cb01 Y01 Cr01 Y11
YI0 Y00 Y10 Cb00 Y00 Cr00 Y10
CI7 Cb07 Cr07 — — — —
CI6 Cb06 Cr06 — — — —
CI5 Cb05 Cr05 — — — —
CI4 Cb04 Cr04 — — — —
CI3 Cb03 Cr03 — — — —
CI2 Cb02 Cr02 — — — —
CI1 Cb01 Cr01 — — — —
CI0 Cb00 Cr00 — — — —
Y point 0 1 0 1
C point 0 0
Input in 8-bit mode
ITU-R BT.656 mode
24/123
PEDL87V21071-01
OKI Semiconductor
Input in 8-bit mode or ITU-R BT.656 modeInput in 16-bit mode
ICLK
#IICLK #IICLK
YI[7:0]
CI[7:0]
#: Internal signal
Yn Yn+1 Yn+2 Yn+3
Cn Cn+1 Cn+2 Cn+3
ICLK
YI[7:0]
CI[7:0]
Cbn Yn Crn Yn+1
Figure F1-2-1 (1) Input Data Timing
The data and control signal interfaces according to input system modes are as follows.
• Input in 16-bit mode
Vertical Sync. signal: IVS
Horizontal Sync. signal: IHS
Data input pin: YI[7:0], CI[7:0] (YCbCr-4:2:2)
Input system clock frequency: f
= 12.2727272/13.5/14.31818/14.75 MHz
ICLK
Clip level: None
• Input in 8-bit mode
Vertical Sync. signal: IVS
Horizontal Sync. signal: IHS
Data input pin: YI[7:0], (YCbCr-4:2:2)
Input system clock frequency: f
= 24.545454/27/28.63636/29.5 MHz
ICLK
Clip level: None
• ITU-R BT.656 mode
Vertical Sync. signal: SAV, EAV split
Horizontal Sync. signal: SAV, EAV split
Data input pin: YI[7:0] (YCbCr-4:2:2)
Input system clock frequency: f
= 27 MHz
ICLK
Clip level: 00h → 01h, FFh → Feh
* By setting POFF (SUB:41h-bit[6]) to 1, the parity bits of SAV and EAV can be disabled.
ML87V21071
don't care (no connect)
25/123
PEDL87V21071-01
OKI Semiconductor
• Internal Input System Clock (IICLK)
The IICLK is IICLK = ICLK in 16-bit 4:2: 2 mode whereas in 8-bi t 4:2:2 mode and IT U-R BT.656 mode
it is the clock pulse obtained by internally frequency-dividing ICLK to 1/2.
In 8-bit 4:2:2 mode, the position which is two ICLK clocks delayed from the rise of IHS is used for
resetting and IICLK is generated by frequency-dividing ICLK to 1/2.
Normally reset of IICLK presumes the rise position of positive polarity IHS (IHSINV = 0), but by setting
IHES (SUB:41h-bit[5]) and IHSINV, selection of compliance with negative polarity IHS and fall
position is also possible.
In ITU-R BT 656 mode, ICLK is frequency-divided to 1/2 based on SAV.
In 8-bit 4:2:2 mode, if the p hase of IHS for l umina nce and chrominance d ata reverses (n umber of ICL Ks
from IICLK reset to initial chrominance data is odd), it is possible to avoid the reversal by setting ICINV
(SUB:41h-bit[4]).
Table F1-2-1 (4) Compliance with Luminance-Chrominance Phase Reversal
ICINV Usage conditions (8-bit 4:2:2 mode)
8-bit 4:2:2 mode
ICLK
IHS
IICLK
Reset
IICLK
YI[7:0]
Table F1-2-1 (3) IICLK Reset Position
IHES IHSINV Reset position
0 0
1 0
0 1
1 1
0 Number of ICLKs from IICLK reset to initial chrominance data is even.
1 Number of ICLKs from IICLK reset to initial chrominance data is odd.
Positive polarity IHS rise (horizontal Sync. signal front
edge)
Positive polarity IHS fall (horizontal Sync. signal rear
edge)
Negative polarity IHS fall (horizontal Sync. signal front
edge)
Negative polarity IHS rise (horizontal Sync. signal rear
edge)
Crn Yn Cbn Yn+1
Figure F1-2-1 (2) IICLK Phase Timing Example
ML87V21071
26/123
PEDL87V21071-01
OKI Semiconductor
ML87V21071
1.2.2 Output Data Format
Since internal signal processing is performed independently for luminance and chrominance signals, the output
data format of basic output of this IC is YCbCr 16bit 4:2:2.
However, in YCbCr 8bit 4:2:2 mode and ITU-R BT.656 mode, selection of YCbCr 8bit 4:2:2 (same format as
input) is enabled by setting DOSEL (SUB:60h-bit[1]) to 1. In this case, unused CO[7:0] becomes Hi-Z.
Table F1-2-2(2) shows the delay amount from input to output and the same delay amount occurs for all the data
and Sync. signals.
Table F1-2-2 (1) Output Data Format
Output Normal mode 8-bit input – 8-bit output mode (DOSEL =1)
YO7 Y07 Y07 Cr07 Y17 Cb07 Y17
YO6 Y06 Y06 Cr06 Y16 Cb06 Y16
YO5 Y05 Y05 Cr05 Y15 Cb05 Y15
YO4 Y04 Y04 Cr04 Y14 Cb04 Y14
YO3 Y03 Y03 Cr03 Y13 Cb03 Y13
YO2 Y02 Y02 Cr02 Y12 Cb02 Y12
YD1 Y01 Y01 Cr01 Y11 Cb01 Y11
YD0 Y00 Y00 Cr00 Y10 Cb00 Y10
CO7 Cb07 Cr07 — — — —
CO6 Cb06 Cr06 — — — —
CO5 Cb05 Cr05 — — — —
CO4 Cb04 Cr04 — — — —
CO3 Cb03 Cr03 — — — —
CO2 Cb02 Cr02 — — — —
CO1 Cb01 Cr01 — — — —
CO0 Cb00 Cr00 — — — —
Table F1-2-2(2) Combinations for Input/Output Data Format
DISEL R656I DOSEL Input Output
0 0 X 16-bit + Sync (H, V) 16-bit + Sync (H, V) 32 (ICLK)
1 0 0 8-bit + Sync (H, V) 8-bit + Sync (H, V) 64 (ICLK)
1 0 1 8-bit + Sync (H, V) 8-bit + Sync (H, V) 66 (ICLK)
X 1 0 ITU-R BT.656 16-bit + Sync (H, V) 64 (ICLK)
X 1 1 ITU-R BT.656 ITU-R BT.656 + Sync (H, V) 66 (ICLK)
Input/output delay
amount
* When input is ITU-R BT.656, Sync (H, V) on the output side is output to OVS and OHS as the Sync. signal
separated from SAV and EAV.
27/123
PEDL87V21071-01
OKI Semiconductor
ICLK
YI[7:0]
CI[7:0]
YO[7:0]
CO[7:0]
ICLK
YI[7:0]
ML87V21071
Y0 Y1
Cb0 Cr0
32(ICLK)
Y0 Y1 Y2
Cb0 Cr0 Cb1
Figure F1-2-2(1) Input/Output Delay in 16-Bit Input Mode
Cb0 Y0 Cr0 Y1
[DOSEL=0]
YO[7:0]
CO[7:0]
[DOSEL=1]
YO[7:0]
ICLK
YI[7:0]
[DOSEL=0]
YO[7:0]
CO[7:0]
[DOSEL=1]
64(ICLK)
Y0 Y1 Y2
Cb0 Cr0 Cb0
66(ICLK)
Cb0 Y0 Cr0 Y1
Figure F1-2-2(2) Input/Output Delay in 8-Bit Input Mode
FF 00 00 SAV Cb0 Y0 Cr0 Y1
64(ICLK)
00 SAV Y0 Y1 Y2
FF 00 Cb0 Cr0 Cb0
66(ICLK)
YO[7:0]
FF 00 00 SAV Cb0 Y0 Cr0 Y1
Figure F1-2-2(3) Input/Output Delay in ITU-R BT.656 Mode
28/123
PEDL87V21071-01
OKI Semiconductor
ML87V21071
2. Video Signal Processing Functions
2.1 Motion-Adaptive 3D Noise Reduction
This IC performs noise reduction first by detecting noise and predicting motion using frame recursion, field
recursion, and line correlation, then by performing noise subtraction while performing motion compensation for
the detected noise. Moreover, it achieves adaptive noise reduction by synthesizing four NR data items based on
prediction of motion.
However, when INPR is set to 1, the field recursion stops and adaptive noise reduction is performed by the two
NR data items, frame recursion and line correlation.
• Principle of Noise Reduction
Difference between the current field data and the filed data preceding one frame, one field, or one line is
extracted as time motion and noise independently for luminance and chrominance signals.
The low gain portion of this data is judged to be noise and the high gain portion to be motion an d is extrac ted
as motion level detection noise.
The noise component extracted here is subjected to motion prediction by ad jacent motion level and adjacent
code, then further subjected to c om pensati on base d on m otion a nd i s regarde d as the fina l noi se component.
Finally, noise reduction is carried out by subtracting this final noise data from the current field data.
Luminance
input data
Luminance noise detection
+
-
-
LPF
MSB
Non-
linear filter
Motion
detection
Limiter
Motion
compen-
sation
+
-
-
Field
memory
NR recursive data
Luminance
output data
Chrominance
input data
+
-
-
Chrominance noise detection
+
-
-
LPF
Non-
linear filter
Motion
detection
Limiter
Chrominance
motion level
compen-
sation
Luminance
interlock
motion
compensation
Field
memory
Figure F2-1 (1) Noise Detection Type Noise Reduction Configuration
Chrominance
output data
NR recursive data
29/123
PEDL87V21071-01
Noi
OKI Semiconductor
Current field data
One preceding field data
–
–
se
–
–
detection
+
motion
compensation
Figure F2-1(2) Noise Reduction by Noise Detection
ML87V21071
Data after 3DNR
30/123
Loading...