OKI ML696500 User Manual

Preliminary

ML696500 Series

ML696500 and ML69Q6500

32-Bit ARM946E™ Based Microcontroller

Description

The Oki ML69Q6500 microcontroller is a system LSI for digi­tal audio players based on the ARM946E™ 32-bit CPU core .

The ML69Q6500 provides a 120-MHz ARM-9E CPU along
with:

• High speed USB 2.0 interface,

• Ultra DMA hard drive controller (ATA),

• NAND Flash controller

• 16-bit audio codec.
It is targeted for portable MP3 players. The ML69Q6500 also

contains 128KB of SRAM, 512KB of embedded Flash ROM as
well as an internal memory controller that can connect to
external ROM, SRAM and SDRAM.

Features

• ARM946E-S CPU

- 8-KB instruction Cache

- 8-KB Data Cache

- JTAG debug function

• Internal Memory

- 128-KB SRAM

- 16-KB Boot ROM

- 512-KB Flash ROM (ML69Q6500 only)

• USB 2.0 High Speed controller

• IDE (ATA) controller

- DMA / Ultra DMA support

• NAND Flash memory controller

- Smart Media 2000 Compliant

- Built in ECC circuit

• Audio DA/AD

- 2 stereo channels

- 16-bit resolution

- Built-in Headphone Amp

• Timers: 16-bit auto-reload x 4

• DMA Controller – 4-Channel

• PWM – 16-bit x 1-Channel

Tyical Applications

• Portable digital-audio players

• MP3 Juke Box

• Digital Audio Encoder/Decodeer

• 16-bit Watchdog T imer

- Interrupt or Reset control

• A/D Converter – Four, 10-bit Channels

2

S T ransceiver

•I

- 16-bit Data

- 32, 44.1 & 48-kHz sample rates

• Real-time Clock (RTC) Generation

• Serial Interfaces:

- SSIO

- UART

2

C

-I

• General Purpose I/O – 88 Programmable pins

• External Memory Controllers:

- ROM

- SRAM

- SDRAM

- Peripheral I/O Banks

• Advanced Power Management

- Clock Gears — 1/2 to 1/32

- Power-down and Halt modes

• Package – 272-pin LFBGA 0.65 mm pitch

January 2005, Rev 1.1b

Data Sheet

Product Selector

Part Number Clock Frequency Built-in Flash ROM Package

ML696500 120 MHz n/a 272-pin LFBGA 0.65 mm pitch

ML69Q6500 120 MHz 512 KB 272-pin LFBGA 0.65 mm pitch

ML696500 and ML69Q6500

Block Diagram

TDI

TDO

nTRST

TMS

TCK

RTCK

RESET_N

TXD
RXD

OSC48M0

OSC48M1B

OSC11M0

OSC11M1B

SIORXD[1:0]
SIOTXD[1:0]

ARM946ES

APB Bridge

PWMOUT

SIOCK[1:0]

*For ML69Q6500 Only

6

AMBA

AHB Bus

AMBA

APB Bus

System

TIMER

MCP

FLASH

JTAG

FLASH

µPLAT946

SIO

TIC

Default

Slave

BIC

IRC

System
Control

CGB

52

XA[23:1]
XD[15:0]
XOE_N
XWE_N
XROMCS_N
XRAMCS_N
XIOCS_N[1:0]
XBS_N[1:0]
XCAS_N
XRAS_N
XSDCLK
XSDCKE
XDQM[1:0]

DRAMC

Exp. IRC

APB Bridge

with wait

6

Default

Slave

WDT

UNIV

TIMER

16 bit x 3ch

PWM

16 bit x 1ch

SSIO

2ch

USB_DP
USB_DM
USB_RPU
USB_REXT
USB_ATEST1
USB_ATEST0
USB_VOREF

6

PHY

HS-USB

AHBROMAHBRAM

APB Bus

29

VDD_CORE
GND_CORE
VDD_PLL
GND_PLL
VDD_IO
GND_IO
VDD_RTC
GND_RTC
AVDD
AGND
AVDD_RX
AGND_RX
AVDD_TX
AGND_TX
AVDD_C
AGND_C

13

3

3 13

4

4

4

IDEA[2:0]
IDED[15:0]
IDERE_N
IDEWE_N
IDERDY
IDERDY_CLK
IDECS_N[1:0]
IDEDREQ
IDEDACK_N
IDEIRQ
IDEDIR_N

IDE

Controller

DMAC

NAND FLASH

Controller

NAND FLASH

Buffer

SSIO

1ch

I2S

Trans

I2S

Receive

A/D AIN[3:0]

DREQ
DREQCLR
TCOUT

FRD_N
FFWR_N
FCLE
FALE
FRB
FD[7:0]

Audio

AD/DA

Preliminary

LLINEOUT
RLINEOUT
LLINEIN
RLINEIN
MICIN
LRADIOIN
RRADIOIN
LOUT
MOUT
ROUT
REFP
REFN
COMM

CKOUTD
SDD
WSD
SCLD

CKOUTA
SDA
WSA
SCLA

SDAT

SCL

PIOA[15:0], PIOB[15:0]
PIOC[15:0], PIOD[15:0]

PIOE[15:0], PIOF[6:0]

2

• Oki Semiconductor January 2005, Rev 1.1b

2

88

I2C

GPIO

RTC

Backup Area

Test Mode

2

12

OSC32K_IN
OSC32K_OUT

Preliminary

Functional Description

• CPU

- 32-bit RISC CPU (ARM946E)

- Built-in 8-KB instruction cache and 8-KB data cache

- Little-endian format

- Maximum operating frequency of 120 MHz

- Instruction structure – Highly dense 32-bit ARM instructions and a subset
16-bit Thumb instructions with high object code efficiency

- 31 General-purpose registers x 32 bits

- Built-in barrel shifter – The oper ations of the ALU and barrel shift can be
executed by one instruction.

- Built-in multiplier (32 bits x 16 bits)

- Built-in debug function (JTAG)

• Internal memory

- Built-in 128-KB SRAM (32 KWords x 32 bits)

- AHB bus connection

- Built-in 16-KB ROM for boot up (4 KWords x 32 bits)

- 512-KB Flash ROM(ML69Q6500 only)

• External memory and I/O controller (16-bit devices)

- ROM (Flash) access function

- SRAM access function

- SDRAM access function – supports distributed CBR

- External I/O interface – two 16-bit banks

• Interrupt controller / extended-interrupt controller

- FIQ: Used for an internal interrupt (IFIQ_N) from the AUDIO module.

- 27 IRQ sources (23 internal sources and 4 external sources)

- Seven interrupt priority levels can be set for each interrupt source

• µPLAT system timer

- 16-bit auto reload timer x 1 channel

• µPLAT-SIO (UART)

- Full-duplex start-stop synchronization method

- Built-in baud-rate generator

• DMA controller

- Four channels

- Fixed mode or round-robin mode priority can be selected

- Cycle-steal mode or burst-mode bus access privilege can be selected

- Software requests and external requests are supported as DMA transfer
requests

- Maximum transfer count is 65,536 (64K)

- Data transfer sizes are 8, 16, or 32 bits

• High speed USB Port

- USB 2.0 standard compliant

- High-speed (480 Mbps)

- Interface to AMBA high-speed bus

• IDE Controller

- ATA66 compliant

- DMA and Ultra DMA are supported.

- Switchable to NAND Flash + GPIO using the IDEMODE pin

• PWM

- PWM x 1 channel (16-bit resolution)

ML696500 and ML69Q6500

• Watchdog timer

- 16-bit timer

- Interval-mode or watchdog-mode can be selected

- An interrupt or a reset can be generated

• Analog-to-digital converter

- 10-bit successive approximation type x 4 channels

- Sample / hold function

- Shortest conversion time is 6.7 µs

2

•I

C Bus Controller

2

-I

C bus standard compliant controller x 1 channel

- Operates only as I

- Communication speed is 100-400 kbps

- Supports 7-bit and 10-bit addressing

• Timer

- 16-bit auto reload timer x 3 channels

- A different clock can be set for each channel.

- One-shot mode or interval mode can be set for each channel.

• Synchronous Serial I/O (SSIO)

- 3 channels of 8-bit clock synchronous serial port

- One-of-3 channels is used to control built-in audio Codec

- Configurable Clock polarity

- Select LSB first or MSB first

- Select Master or Slave mode

• Universal Registers

- Four 8-bit general-purpose internal status/setup registers

• NAND Flash memory controller

- SmartMedia Standard 2000 compliant (512-Bytes/sector)

- Supports SmartMedia of 8 MB to 128 MB

- Built-in ECC circuit

- 512-Byte/2048-Byte auto write/read function

•RTC

- 1-second clock generation function from 32.768 kHz

- Built-in 32-bit 1-second clock counter

- 32-bit compare interrupt function

• GPIO

- Built-in GPIO of 16 pin x 5 channels (GPIOA, GPIOB, GPIOC, GPIOD,
GPIOE) and 8 pin x 1 channel (GPIOF)

- Each port configurable at bit level

- Interrupt inputs can be set at bit level

- GPIOA[15:00], GPIOB[15:00] and GPIOC[15:00] can be set to an exter­nal bus by setting the EXTBUS pin

- GPIOD[15:00] can be used to select a secondary function in units of bits.

- GPIOE[15:11] can be used as external interrupts.

- GPIOE[15] is 5-V tolerant input

- GPIOF[06:00] function as IDE data, when the IDE controller mode is set
using the IDEMODE pin.

- GPIOF[7] is used as a control input to the internal audio Codec

2

C bus master device

January 2005, Rev 1.1b

Oki Semiconductor • 3

ML696500 and ML69Q6500

2

•I

S transmission/reception

- Sampling frequencies of 32, 44.1, and 48 kHz, as well as 1/2 and 1/4 of
these frequencies are supported

- System clock is 256 times the sampling rate

- Channel data length is 16 bits

- With or without 1-bit delay, left/right reversible

•

Audio DA/AD circuit

- 16-bit DAC resolution

- Two stereo channels

- Built-in headphone amplifier

- S/N ratio is 90 db (preliminary)

- 16-bit ADC resolution

- Two stereo channels

- Built-in amplifier/ALC

- S/N ratio: 90 db (preliminary)

• Flash

- ML69Q6500: (256-K x 16-bit) Flash ROM is embedded in the MCP
(Multi-chip Package)

- ML696500: Version without Flash ROM

Preliminary

• Clocks

- Can connect a 48-MHz crystal oscillator and input an external clock
directly.

- The RTC section can connect a 32.768-kHz crystal oscillator.

- Can connect an 11.2896-MHz crystal oscillator for audio and input an
external clock directly.

• Power Management

- Power down mode – The power supply can be disabled to all sections,
except for the RTC section.

- Stop mode – Software disables clock supply to the main section including
the processor

- Halt mode – Partially disables clock supply

- Clock gear – Software can dynamically change clock to 1/1, 1/2, 1/4,
1/8, 1/16 or 1/32 of the clock input frequency

- Clock control – Software can stop clock supply for each function

• Package

- 272-pin LFBGA, 0.65 mm ball pitch

4

• Oki Semiconductor January 2005, Rev 1.1b

Preliminary

Pin Configuration

RLINEINREFPRRADIOIN

RLINE

VDD_HPLOUT

OUT

ADIN[3]ADIN[2]ROUT

OSC48M1BOSC48M0VDD_PLL

USB_

VOREF

ATEST[0]

OSC11M0VDD_PLLUSB_

MICINLLINEINVDD_ADCLRADIOIN

ADC

CORE

VDD_
CORE

ML696500 and ML69Q6500

2143567810 912 11131415161718192021

PIOD[12]/

PIOD[11]/

VDD_

CODEC

C

CODEC

SCLD

GND_IOVDD_CAPGND_IOGND_

GND_IORESET_NGND_IOCOMREFNVDD_DACLLINEOUT

GND_IOGND_IOGND_IOGND_DA

WSD

VDD_
CORE

VDD_
CORE

CORE

CKOUTD

PIOD[2]/

SDD

VDD_
CORE

SDA

SCLA/SCL

PIOD[5]/

WSA

VDD_IOVDD_IOVDD_

SSIOTXD

[0]

VDD_FLAPIOD[4]/

PIOD[7]/

CKOUTA/

CLKOUT

GND_
CORE

SSIOTXD

[1]

PIOD[9]/

SSIORXD

[0]

PIOD[10]/

SSIOCK[0]

CORE

SSIORXD

[1]

SSIOCK[1]

UP_RXD

UP_TXD

SCLPIOD[13]

SDATPIOD[15]/

VDD_IOVDD_IOGND_

RSV

BYPASS

CORE

PIOD[8]/

PIOD[6]/

PIOD[3]/

PIOD[1]/

PIOD[0]/

GND_

BOOT[1]TMODE[0]TMODE[2]PWMOUTPIOD[14]/

CORE

BOOT[0]EXTBUSTMODE[1]TEST_

CORE

CORE

CORE

VDD_
CORE

GND_IOGND_

nTRSTGND_IOVDD_IOVDD_IOVDD_

RTCKGND_IOAVDDADIN[1]GND_HPMOUT

TCKVDD_IOGND_

TMSVDD_IOVDD_IOVSSFLAAGNDADIN[0]

TDIVDD_

IDED[3]

IDEMODETMODE[3]PLL

IDED[0]

FD[2]/

IDED[2]

FD[6]/

IDED[6]

PIOF[0]/

IDED[8]

PIOF[3]/
IDED[11]

PIOF[5]/
IDED[13]

IDED[15]FD3/

GND_IOGND_IOGND_

TDOGND_IOGND_

VSSFLAFD[0]/

FD[1]/

IDED[1]

FD[4]/

IDED[4]

FD[7]/

IDED[7]

PIOF[2]/

IDED[10]

PIOF[4]/

IDED[12]

PIOF[6]/

IDED[14]

AA

Y

W

V

U

T

R

P

N

REXT

XWAIT

[1]

PIOC[2]/
XBS_N

[0]

PIOC[9]/

XROMCS

_N

XOE_N

GND_IO

AGND_CAVDDRX

XSDCS_NPIOC[1]/

PIOC[4]/

XIOCS_N

[0]

PIOC[10]/

XWE_N

GND_IOPIOC[11]/

PIOB[1]/

XD[1]

ATEST[1]

PIOC[0]/
XWAIT

[0]

PIOC[3]/
XBS_N

[1]

GND_IO

PIOB[0]/

XD[0]

PIOB[3]/

XD[3]

OSC11M1BGND_PLLAVDDCUSB_

XSYSCLKVDD_IOXRAS_NXCAS_N

XSDCLK

VDD_IO

GND_IOVDD_IOGND_IOGND_IO

PIOC[6]/

XIOCS_N

[10]

PIOB[2]/

XD[2]

PIOB[4]/

XD[4]

GND_
CORE

PIOC[5]/

XIOCS_N

[1]

PIOB[7]/

XD[7]

PIOB[6]/

XD[6]

GND_

CORE

PIOC[7]/

XIOCS_N

[11]

PIOB[10]/

XD[10]

PIOB[8]/

XD[8]

CORE

PIOC[8]/

XRAMCS_N

PIOB[12]/

XD[12]

PIOB[11]/

XD[11]

PIOB[5]/

XD[5]

PIOA[0]/

XA[1]

PIOB[14]/

XD[14]

PIOB[9]/

XD[9]

PIOB[15]/

XD[15]

PIOA[2]/

XA[3]

VDD_IOVDD_IOVDD_IOGND_

PIOB[13]/

XD[13]

PIOA[1]/

XA[2]

PIOA[4]/

XA[5]

272-Pin LFBGA

(TOP VIEW)

VDD_
CORE

PIOA[3]/

XA[4]

PIOA[5]/

XA[6]

PIOA[6]/

XA[7]

CORE

PIOA[7]/

XA[8]

PIOA[9]/

XA[10]

PIOA[8]/

XA[9]

PIOA[10]/

XA[11]

PIOA[12]/

XA[13]

PIOA[11]/

XA[12]

VDD_IOVDD_IOGND_

XA[17]

PIOA[15]/

XA[16]

PIOA[13]/

XA[14]

VDD_
CORE

XA[19]

PIOA[14]/

XA[15]

CORE

PIOC[13]/

XA[18]

XA[20]

VDD_IOGND_PLLUSB_

VDD_IOTCOUTDREQCLRAGND_TXUSB_DP

VDD_IOXDQM[1]XSDCKEAGND_RXAVDDTX

GND_
CORE

VDD_
CORE

CORE

GND_
CORE

IDED[5]

PIOF[1]/

IDED[9]

32K_

TESTMODE

VDDRTCVDD_IODREQXDQM[0]AGND_TXUSB_DM

FCLE/

IDECS_N

[0]

IDERST_

N

CORE

RTC_

TESTMODE

NPCBRID

_N

FRB/

IDERDY

FRD_N/

IDERE_N

PIOE[11]PIOE[14]XA[22]PIOC[15]/

2143567810 912 11131415161718192021

GND_RTCOSC32K1BFD[5]/

OSC32K

[0]

IDEIRQIDE

IDEDREQIDEDACK

FALE/

IDECS_N

[1]

FWR_N/

IDEWR_N

IDEA[0]IDEA[2]IDEA[1]VDD_

PIOE[0]PIOE[1]GND_

PIOE[2]PIOE[3]PIOE[5]GND_IOGND_IOVDD_

PIOE[7]PIOE[8]GND_IOPIOE[4]PIOE[6]PIOE[15]XA[21]PIOC[12]/

PIOE[9]GND_IOPIOE[10]PIOE[13]PIOE[12]XA[23]PIOC[14]/

GND_IO

M

L

K

J

H

G

F

E

D

C

B

A

Figure 1. 272-Pin LFBGA

Notes:

1. For pins that have multiple functions, the signals are noted by their pri­mary / secondary functions.

January 2005, Rev 1.1b

Oki Semiconductor • 5

B1

C1

D1

E1

F1

G1

H1

J1

K1

L1

M1

ML696500 and ML69Q6500

Pin Assignment Definitions and Functions

Pin Definitions

Pin Name/Function Description

A/B A = Primary Function / B = Secondary Function
A/- A = Primary Function /

-/B
_N Active-Low Input or Output

No Primary Function

List of Pins

BGA Pin Symbol BGA Pin Symbol BGA Pin Symbol BGA Pin Symbol

A1

A2 PIOE[11]/- B2 GND_IO C2 PIOE[8]/- D2 PIOE[3]/­A3 PIOE[14]/- B3 PIOE[10]/- C3 GND_IO D3 PIOE[5]/­A4 -/XA[22] B4 PIOE[13]/- C4 PIOE[4]/- D4 GND_IO
A5 PIOC[15]/XA[20] B5 PIOE[12]/- C5 PIOE[6]/- D5 GND_IO
A6 PIOC[13]/XA[18] B6 -/XA[23] C6 PIOE[15]/- D6 VDD_CORE
A7 PIOA[14]/XA[15] B7 PIOC[14]/XA[19] C7 -/XA[21] D7 VDD_CORE
A8 PIOA[13]/XA[14] B8 PIOA[15]/XA[16] C8 PIOC[12]/XA[17] D8 VDD_IO

A9 PIOA[11]/XA[12] B9 PIOA[12]/XA[13] C9 PIOA[10]/XA[11] D9 VDD_IO
A10 PIOA[8]/XA[9] B10 PIOA[9]/XA[10] C10 PIOA[7]/XA[8] D10 GND_CORE
A11 PIOA[6]/XA[7] B11 PIOA[5]/XA[6] C11 PIOA[3]/XA[4] D11 VDD_CORE
A12 PIOA[4]/XA[5] B12 PIOA[1]/XA[2] C12 PIOB[13]/XD[13] D12 VDD_IO
A13 PIOA[2]/XA[3] B13 PIOB[15]/XD[15] C13 PIOB[9]/XD[9] D13 VDD_IO
A14 PIOB[14]/XD[14] B14 PIOA[0]/XA[1] C14 PIOB[5]/XD[5] D14 VDD_IO
A15 PIOB[11]/XD[11] B15 PIOB[12]/XD[12] C15 PIOC[8]/XRAMCS_N D15 GND_CORE
A16 PIOB[8]/XD[8] B16 PIOB[10]/XD[10] C16 PIOC[7]/XIOCS_N[11] D16 GND_CORE
A17 PIOB[6]/XD[6] B17 PIOB[7]/XD[7] C17 PIOC[5]/XIOCS_N[1] D17 GND_CORE
A18 PIOB[4]/XD[4] B18 PIOB[2]/XD[2] C18 PIOC[6]/XIOCS_N[10] D18 GND_IO
A19 PIOB[3]/XD[3] B19 PIOB[0]/XD[0] C19 GND_IO D19 VDD_IO
A20 PIOB[1]/XD[1] B20 GND_IO C20 PIOC[10]/XWE_N D20 GND_IO
A21 GND_IO B21 PIOC[11]/XOE_N C21 PIOC[9]/XROMCS_N D21 GND_IO

GND_IO

No Secondary Function

/ B = Secondary Function

PIOE[09]/-

PIOE[7]/-

Preliminary

PIOE[2]/-

PIOE[0]/­E2 PIOE[1]/- F2 -/IDEA[2] G2 FRD_N/IDERE_N H2 FRB/IDERDY
E3 GND_CORE F3 -/IDEA[1] G3 -/IDERST_N H3 FCLE/IDECS_N[0]
E4 GND_CORE F4 VDD_CORE G4 VDD_CORE H4 VDD_IO

E18 VDD_IO F18 -/XSDCLK G18 -/XSYSCLK H18 -/XDQM[1]
E19 PIOC[3]/XBS_N[1] F19 PIOC[0]/XWAIT[0] G19 VDD_IO H19 -/XSDCKE
E20 PIOC[4]/XIOCS_N[0] F20 -/XSDCS_N G20 -/XRAS_N H20 AGND_RX/­E21 PIOC[]2/XBS_N[0] F21 PIOC01/XWAIT[1] G21 -/XCAS_N H21 AVDD_TX/-

-/IDEDREQ
J2 -/IDEDACK_N K2 -/IDENPCBRID L2 RTC_TESTMODE/- M2 OSC32K1B/­J3 VDD_RTC/- K3 32K_TESTMODE/- L3 PIOF[1]/IDED[9] M3 FD[5]/IDED[5]
J4 VDD_IO K4 VDD_IO L4 VDD_IO M4 GND_CORE

J18 -/DREQ K18 -/TCOUT L18 GND_PLL/- M18 OSC11M1B/­J19 -/XDQM[0] K19 -/DREQCLR L19 USB_ATEST1/- M19 GND_PLL/-

6

• Oki Semiconductor January 2005, Rev 1.1b

-/IDEA[0]

-/IDEIRQ

FWR_N/IDEWR_N

OSC32K0/-

FALE/IDECS_N[1]

GND_RTC/-