OKI ML67Q4061HA User Manual

ML67Q4050/Q4060 Series

32-Bit ARM®-Based General Purpose Microcontroller

DESCRIPTION

The Oki ML67Q4050/Q4060 Series of microcontrollers
have been added to Oki's growing family of ARM
based microcontrollers. These devices are the world's
smallest packaged ARM processors. They contain a

33.33-MHz, 32-bit ARM7TDMI

TM

core with either

Features

• ARM7TDMITM CPU

- JTAG debug function

• Internal Memory

- 64KB or 128KB 32-bit wide FLASH, zero wait state

- 16KBytes SRAM

- Boot loader

• External Memory Controller (ML67Q4050/51 only)

- ROM, RAM and I/O banks

- 8,16 or 32-bit wide accesses

• Power Supply

-2.5V V

DD_CORE

- Selectable 2.5V to 3.3V V

DD_IO

• Programmable Timers

- 16-bit System Timer

- Six 16-bit Flexible Timers

- Auto reload, input capture, compare output

• 16-bit Watchdog timer

- Selectable interrupt or reset

• Two DMAC Channels

• Four 10-bit A/D converter channels

• Two UART channels

- 16550A-compatible

- Independent 16-bit Tx and Rx FIFOs

- Supports 9-bit mode

•I2C

- Conforms to I2C bus specification

- Multi-master support

64KBytes or 128KBytes of 32-bit wide zero-wait state
FLASH memory and 16KBytes of SRAM. The devices
also contain multiple serial interfaces, like I

2

C, I2S,
SPI, and UARTs (supporting 9-bit communications),
along with many other peripheral functions.

•SIO

- Full duplex operation with built in baud rate generator

•I2S

- Conforms to the I2S (the Inter-IC Sound) specification
for DAC/ADC IF

- Supports master/slave modes

- Channel data length 16/18/20/24-bit (CPU interface is
16 bits)

- One 256 x 16 shared FIFO

- Master clock output

• Two SPI channels

- Selectable master/slave

- Bus Collision Detection

- Supports 8-bit and 16-bit transfers

•Clocks

- Main clock = 33.333 MHz (Max)

- RTC clock = 32.768 kHz

- Ring Oscillator

• Power Management

- Low-power mode

-Halt mode

- Stop Mode

- Clock divider can be dynamically changed during
operation

• Packages

- 64-pin WCSP (the world’s smallest package)

- 64-pin TQFP

- 84-pin LFBGA

- 144-pin LQFP (ML67Q4050/51 Only)

June 2006, Rev 1.2

Data Sheet

Typical Applications

• Consumer, medical, and communications applications where small package size is important.

Product Selector

Part Number Flash ROM Package Part Number Flash ROM Package

ML67Q4050TC 64KB

ML67Q4051TC 128KB ML67Q4061LA 128KB

ML67Q4060TB 64KB

ML67Q4061TB 128KB ML67Q4061HA 128KB

144-Pin LQFP

64-Pin TQFP

ML67Q4060LA 64KB

ML67Q4060HA 64KB

84-Pin LFBGA

64-Pin WCSP

ML67Q4050/Q4060 Series

Block Diagram

TDI

TDO

NTRST

TMS
TCK

JTAGE

RESET_N

SYSCLK_P
SYSCLK_N
RTCCLK_P
RTCCLK_N

TXD
RXD

EXINT[5:1]

EFIQ_N

2

6

VDD_CORE

VDD_IO

GND
VDD_PLL
GND_PLL
TEST[2:1]

Flash

6

JTAG IF

Internal RAM

16KB

-7B

ARM7TDMI

AHB IF

APB IF

System

Controller

CGB

Internal & External
Memory Controller

Processor Bus

AMBA

AHB Bus

AMBA

APB Bus

SIO

PBIC

IRC

System

Timer

MISO[1:0]
MOSI[1:0]

SSN[1:0]
SCK[1:0]

Internal FLASH RO M

ML67Q4050/ML67Q4060:64KB

ML67Q4051/ML67Q4061:128KB

The PBIC and Extended I/O

Signals are only for the

ML67Q4050TC/ML67Q4051TC

Boot ROM

8KB

Exp. IRC

2-Ch SPI

8

APB Bridge

APB Bus

RTC

DMAC

2-Channels

TIMER

16 bit x 6ch

WDT

I2S

GPIO

I2C

A/D

2-Ch UART

(16550)

6

3

39

2

4

16

XA[22:0]
XD[31:0]
OE_N
WR_N
ROMCS_N
RAMCS_N
IOCS[1:0]_N
BS[3:0]_N
DMAREQ
DMACLR
EXBUSE
EXIROME
BOOT[1:0]
BOOTCLK
PG[6:0]
PH[7:0]
PI[7:0]
PJ[7:0]
PK[7:0]
PL[7:0]
PM[7:0]
PN[7:0]
PO[1:0]

TIMER[5:0]

SD
WS
SCK

PA[6:0]
PB[5:0]
PC[7:0]
PD[5:0]
PE[6:0]
PF[5:0]

SDA
SCL

AIN[3:0]

TX[1:0]
RX[1:0]
CTS[1:0]
DSR[1:0]
DCD[1:0]
DTR[1:0]
RTS[1:0]
RI[1:0]

2

• Oki Semiconductor June 2006, Rev 1.2

FUNCTIONAL DESCRIPTION

•CPU

- 32-bit RISC CPU (ARM7TDMI)

- Little endian byte order

- Maximum operating frequency: 33.33 MHz

- Instruction set: Free switching between a highly efficient 32-bit instruc­tion set, and a 16-bit subset offering higher object code density

- General-purpose registers: 31 32-bit registers

- Barrel shifter: Simultaneous ALU and barrel shift operations in the
same instruction

- Multiplier (32-bit x 8-bit)

- JTAG interface for debugging

• Built-in Memory

- SRAM: 16KBytes (4K x 32 bits), 1-cycle access

- Built-in Flash ROM: 128KBytes (ML67Q4051, ML67Q4061) or
64KBytes (ML67Q4050, ML67Q4060), 1-cycle access, connected to
the processor bus Flash ROM programming cycle count: 100 (max.)

- Boot ROM: 8KBytes

• External Memory Controller (only for ML67Q4050/51)

- Programmable access timing setting for each space

- ROM (Flash) access function

- Supports 1 bank x 8KBytes ROM space.

- Supports 16-bit and 32-bit devices

- Supports flash memories

- Supports page accessing

- SRAM access function

- Supports 1 bank x 8MBytes SRAM space.

- Supports 16-bit and 32-bit devices.

- Supports asynchronous SRAM.

- External I/O access function

- Supports 2-bank I/O space.

- Supports 8-bit, 16-bit, and 32-bit devices.

- Supports asynchronous wait from external devices.

- Allows address setup in units of single cycles, RE/WE pulse, and
data-off timing setting.

• Interrupt Controller

- One fast interrupt (FIQ) source (external)

- 31 interrupt (IRQ) sources (40 interrupt sources for ML67Q4050/51)

- Independent masking for each FIQ and IRQ source

- Independent interrupt priority level settings for each IRQ source

- Priority control blocking IRQ requests with priority levels at or below
those for interrupt requests currently being processed

• System Timers

- One 16-bit system timer

• Flexible Timers

- Six 16-bit flexible timers

- Auto Reload Timer (ART) / Compare Out (CMO) / Pulse Width Mod­ulation (PWM) / Capture (CAP)

• Watchdog Timer

- One 16-bit timer

- Choice of interrupt or reset on overflow

- Maximum period: 8.94 sec. (at Peripheral clock = 30 MHz)

- Change watch dog period while running counting

- Setting of period asserting reset signal (RSTOUT_N)

•SIO

- Full duplex asynchronous operation

- Built-in baud-rate generator

ML67Q4050/Q4060 SeriesFUNCTIONAL DESCRIPTION

• DMA Controller

- Two channels

- Selectable DMA request source, source peripheral: I
(External DMA request is available only for ML67Q4050/51)

- Choice of fixed or round robin mode for channel priority order

- Choice of cycle-steal or burst mode for requesting bus access

- Choice of software or external DMA transfer requests

- Maximum transfer count: 65,535

- Data transfer sizes: 8-, 16-, and 32-bit

2

S, I2C, UART , SPI

•GPIO

- Three 20-mA sink pins

- Individual settings for pin I/O direction

- Individual settings for pin interrupt requests

- One 8-bit port, two 7-bit ports, three 6-bit ports

- For ML67Q4050/51 series:

- Eight 8-bit ports

- Three 7-bit ports

- Three 6-bit ports

- One 5-bit port

- For ML67Q4060/61 series:

- One 8-bit ports

- Two 7-bit ports

- Three 6-bit ports

• Analog-to-Digital Converter

- Four channels of 10-bit resolution, each using consecutive comparison

- Sample and hold function

- Choice of scan or select operation

- Conversion time: 20 μs (MAX 50k-sample/s)

- DNL (MAX) =

- INL (MAX) =

- Zero Scale Error (MAX) = ± 8.0 LSB

- Full Scale Error (MAX) = ± 8.0 LSB

± 6.0 LSB

± 6.0 LSB

•UART

- Two 16550A-compatible asynchronous communications

- Independent 16-byte FIFOs for transmit and receive operations

- Full duplex operation

- Built-in baud-rate generator

- Supports DMA transfers

•I2C

- Controller in conformity of I2C bus specification ver2.1

- Multi Master support

- Supports fast mode (400 kbps), standard mode (100 kbps)

- Supports 7-bit, 10-bit address

- Supports DMA transfers

•I2S Transmitter/Receiver

- Conforms to I2S (the Inter-IC Sound) specification for DAC/ADC I/F

- Three-line communication, bit clock (SCK), word clock (WS), serial
data (SD)

- Supports Master/Slave

- Word Clock: 32fs / 64fs

- Channel data length: 16/18/20/24-bit (16-bit CPU I/F)

- Support 1-bit delay, reverse L-Ch and R-Ch

- Supports DMA

- One 256 x 16-bit FIFO shared Transmitter/Receiver

- Master clock output

June 2006, Rev 1.2 Oki Semiconductor • 3

ML67Q4050/Q4060 Series FUNCTIONAL DESCRIPTION

• SPI

- Two channels of full duplex serial-parallel Interface.

- Selectable Master/Slave

- Independent 16 entry x 16-bit FIFOs

- Built-in Baud-rate generator

- Support 8-bit width and 16-bit width transfers

- Supports DMA operation

•CLOCK

- Main clock oscillator is 33.33 MHz (Max)

- RTC clock oscillator is 32.768 kHz Clock

- Ring Oscillator

•RTC

- One second generated from 32.768 kHz

- Built-in 32-bit counter with one second clock

- Interrupt on 32-bit comparison

• Power Management

- Low-power mode

- HALT mode: Stop the clock supply to CPU and other key components

- STOP mode: Stop the clock supply to CPU and all peripherals except
RTC

- Control the clock supply to each peripherals

- Clock change is dynamically possible in the division ratio of clock input
frequency.

• ML67Q4050/51 Package

- 144-pin LQFP (LQFP144-P-2020-0.50-ZK)

• ML67Q4060/61 Packages

- 64-pin WCSP (P-VFBGA64-5.09x4.84-0.50-W)
– Occupies less than 25 square millimeters

- 64-pin TQFP (TQFP64-P-1010-0.50-K)

- 84-pin LFBGA (P-LFBGA84-0909-0.80)

4

• Oki Semiconductor June 2006, Rev 1.2

Pin Configuration

Figure 1. 144-Pin Plastic LQFP

OE_N/PO0

ROMCS_N/PN0

VDD_CORE

RAMCS_N/PN1

108

107

106

105

IOCS0_N/PN2
104

IOCS1_N/PN3
103

BOOT1/PO4

VDD_IO

EXIROME/PO3

GND

WR_N/PO1

BS0_N/PN4

PB0/TX0

PB1/RX0

PB2/TX1/EFIQ_N

BOOT0/PE3/MCLK

PE4/SSD

PF0/TIMER0/CTS0

PF1/TIMER1/RTS0

PF2/TIMER2/CTS1

PF5/TIMER5/EXINT5

VDD_IO

XD0/PJ0

XD1/PJ1

EXBUSE/PO2

PF3/TIMER3/RTS12

999897969594939291908988878685848382818079787776757473

102

101

100

PF4/TIMER4/EXINT4

GNDNCXD2/PJ2

XD3/PJ3

XD4/PJ4

XD5/PJ5

ML67Q4050/Q4060 SeriesPin Configuration

VDD_CORE

XD6/PJ6

XD7/PJ]7\

BS1_N/PN5

GND

BS2_N/PN6

PB3/RX1/EXINT1

BS3_NPN7

XA1/PG0
XA2/PG1

PB4/SCL/TXD

XA3/PG2
XA4/PG3
XA5/PG4
XA6/PG5

PB5/SDA/RXD

VDD_IO

PE0

GND

PE1

GND

PE2

VDD_IO
PD0/AIN0/EXINT2
PD1/AIN1/EXINT3

PD2/AIN2
PD3/AIN3

XA7/PG6
XA8/PH0
XA9/PH1

XA10/PH2

TEST1
XA11/PH3
XA12/PH4
XA13/PH5

TEST2
XA14/PH6

GND

XA15/PH7

109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144

Index Mark

ML67Q4050/51

144-Pin LQFP

(TOP VIEW)

72

XD8’/PK0

71

GND

70

BOOTCLK/PD5

69

XD9/PK1

68

XD10/PK2

67

XD11/PK3

66

PC0/MISO0DSR0

65

XD12/PK4

64

XD13/PK5

63

VDD_IO

62

XD14/PK6

61

XD15/PK7

60

PC1/MOIS0/DTR0

59

PC2/SCK0/RI0

58

PC3/SSN0/DCD0

57

PC4/MISO1/DSR1

56

PC5/MOSI1/DTR1

55

XD16/PL0

54

RESET_N

53

GND

52

GND

51

RSTOUT_N/PA6/MCLK

50

PC6/SCK1/RI1

49

PC7/SSN1/DCD1

48

BS/PD4

47

XD17/PL1

46

VDD_IO

45

XD18/PL2

44

XD19/PL3

43

PE5/WS

42

XD20/PL4

41

XD21/PL5

40

XD22/PL6

39

PE6/SCK

38

GND

37

XD23/PL7

1234567891011121314151617181920212223242526272829303132333435

GND

XA16/PI0

VDD_IO

XA17/PI1

VDD_CORE

XA18/PI2

XA20/PI4

VDD_PLL

GND_PLL

VDD_PLL

XA21/PI5/DMAREQ

GND_PLL

XA[19[/PI3

GND

RTCCLK_P

RTCCLK_N

TCK/PA0

SYSCLK_P

SYSCLK_N

XA22/PI6/DMACLR

XA0/PI7

VDD_IO

TDI/PA2

TMS/PA1

TDO/PA3

XD31/PM7

XD30/PM6

NTRST/PA4

XD27PM3

XD29/PM5

XD28/PM4

JTAGE/PA5

36

XD26/PM2

XD25/PM1

VDD_CORE

XD2425/PM0

Notes:

1. For pins that have multiple functions, the signals are noted by their
Initial / primary / secondary / tertiary functions. See “Pin Descriptions”
Table for details.

June 2006, Rev 1.2 Oki Semiconductor • 5

ML67Q4050/Q4060 Series Pin Configuration

Figure 2. 84-Pin Plastic LFBGA

JKGHFEDCAB

GND NC NC

10

VDD_IO PB1/

/RX0

PE4/

SD

PF2/

TIMER2/

CTS1

PF5/

TIMER5/

EXINT5

NC VDD_CORE

10

PB3/
RX1/

9

EXINT1

VDD_IO PB4/

8

PE1 PE0 GND

NC VDD_CORE

SCL/
TXD

7

VDD_IO GND PE2

6

PD2/
AIN2

5

TEST2 PD3/

4

NC GND GND_PLL

PD0/

AIN0/

EXINT2

AN3

3

PB5/
SDA/
RXD

PD1/
AIN1/

EXINT3

TEST1

PB0/

TX0

GND PB2/

BOOT0/

PE3/

MCLK

TX1/

EFIQ_N

PF[1[/

TIMER1/

RTS0

PF0/

TIMER0/

CTS0

ML67Q4060/61

84-Pin LFBGA

(TOP VIEW)

RTCCLK_N GND TCK/

PA0

PF4/

TIMER4/

EXINT4

PF3/

TIMER3/

RTS1

TDO/

PA3

GND GND NC

VDD_IO PC0/

PC1/

MOSI0/

DTR0

PC4/

MISO1/

DSR1

GND GND RESET_N

PC6/

SCK1/

RI1

VDD_IO PE5/

MISO0/

DSR0

PC2/

SCK0/

RI0

PC5/

MOSI1/

DTR1

PC7/
SSN1/
DCD1

WS

BOOTCLK/

VDD_IO

SSN0/
DCD0

RSTOUT_N/PA6/

MCLK

PD5

PC3/

BS/

PD4

9

8

7

6

5

4

3

NC NC

2

VDD_CORE VDD_IO VDD_PLL

GND_PLL

VDD_PLL GND SYSCLK_N TDI/

RTCCLK_P SYSCLK_P TMS/

1

NOTES:

1. For pins that have multiple functions, the signals are noted by their
Initial / primary / secondary / tertiary functions. See “Pin Descriptions”
Table for details.

2. NC balls can be connected to VDD_IO or GND.

PA1

PA2

VDD_IO

NTRST/

PA4

JTAGE/

PA5

VDD_CORE PE6/

NC GND

SCK

JKGHFEDCAB

2

1

6

• Oki Semiconductor June 2006, Rev 1.2

Figure 3. 64-Pin WCSP for the ML67Q4060/61

Top View of WCSP Package

BOOTCLK/

PD5

8

NC

PF5/
TIMER5/
EXINT5

PF2/

TIMER2/

CTS1

PE4/

SD

PB0/

TX0

GHEFDCBA

PB4/
SCL/
TXD

ML67Q4050/Q4060 SeriesPin Configuration

PB3/
RX1/

EXINT1

8

7

6

5

RSTOUT_N/PA6/

4

3

2

1

PC0/

MISO0/

DSR0

PC2/

SCK0/

RI0

PC5/

MOSI1/

DTR1

MCLK

PD4

PA4

PA5

GND

PC3/

SSN0/

DCD0

RESET_N

PC6/

SCK1/

RI1

PE5/

WS

PE6/
SCK

VDD_IO

TIMER4/
EXINT4

MISO1/

DSR1

PA2

SSN1/
DCD1

PA3

PF[1[/

TIMER1/

RTS0

PF3/

TIMER3/

RTS1

PC1/

MOSI0/

DTR0

TMS/

PA1

TCK/

PA0

BOOT0/

PE3/

MCLK

PB2/
TX1/

EFIQ_N

PB1/
/RX0

PF0/

TIMER0/

CTS0

VDD_IOBS/

VDD_CORE VDD_CORE GND_PLLVDD_CORE GND VDD_IONTRST/

RTCCLK_P RTCCLK_N VDD_CORESYSCLK_N SYSCLK_P GNDJTAGE/

PB5/
SDA/
RXD

PE2 GND PE1PC4/

PD1/
AIN1/

EXINT3

PD2/
AIN2

TEST2 GND VDD_PLLTDO/

PE0 VDD_IOPF4/

PD0/
AIN0/

EXINT2

PD3/

AN3

7

6

VDD_IOTDI/

5

TEST1PC7/

4

3

2

1

GHEFDCBA

NOTES:

1. For pins that have multiple functions, the signals are noted by their
Initial / primary / secondary / tertiary functions. See “Pin Descriptions”
Table for details.

June 2006, Rev 1.2 Oki Semiconductor • 7

ML67Q4050/Q4060 Series Pin Configuration

Figure 4. 64-Pin Plastic TQFP

VDD_CORE

VDD_IO

PB0/TX0

PB1/RX0

PB2/TX1/EFIQ_N

BOOT0/PE3/MCLK

PE4/SSD

PF0/TIMER0/CTS0

PF1/TIMER1RTS0

PF2/TIMER2/CTS1

PF3/TIMER3/RTS1

PF4/TIMER4/EXINT4

PF5/TIMER5/EXINT5

GNDNCVDD_CORE

PB3/RX1/EXINT1

PB4/SCL/TXD

PB5/SDA/RXD

VDD_IO

PE0

GND

PE1

GND

PE2

VDD_IO
PD0/AIN0/EXINT2
PD1/AIN1/EXINT3

PD2/AIN2
PD3/AIN3

TEST1
TEST2

484746454443424140393837363534

49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

123456789101112131415

GND_PLL

VDD_CORE

ML67Q4060/61

64-Pin TQFP

(TOP VIEW)

Index Mark

GND

VDD_PLL

RTCCLK_P

RTCCLK_N

TDI/PA2

TCK/PA0

TMS/PA1

SYSCLK_P

SYSCLK_N

TDO/PA3

33

32

BOOTCLK/PD5

31

PC0/MISO0DSR0

30

VDD_IO

29

PC1/MOIS0/DTR0

28

PC2/SCK0/RI0

27

PC3/SSN0/DCD0

26

PC4/MISO1/DSR1

25

PC5/MOSI1/DTR1

24

RESET_N

23

GND

22

RSTOUT_N/PA6/MCLK

21

PC6/SCK1/RI1

20

PC7/SSN1/DCD1

19

BS/PD4

18

PE5/WS

17

PE6/SCK

16

VDD_IO

JTAGE/PA5

NTRST/PA4

VDD_CORE

NOTES:

1. For pins that have multiple functions, the signals are noted by their
Initial / primary / secondary / tertiary functions. See “Pin Descriptions”
Table for details.

8

• Oki Semiconductor June 2006, Rev 1.2