NXP Semiconductors QN9080M17 User Manual
QN9080-001-M17
Ultra-low power Bluetooth Smart 4.2 SIP
Rev. 0.1 — 12 March 2018 User Manual
1.
General description
The QN9080-001-M17 is an ultra-low power, high performance surface mount SIP targeted
at Bluetooth Smart applications, enabling users to realize products with minimum time to
market and at the lowest cost. They remove the need for expensive and lengthy
development of custom RF board designs and test suites. The SIPs use NXP’s QN9080001-M17 wireless microcontroller to provide a comprehensive solution with large memory,
high CPU and radio performance and all RF components included. All that is required to
develop and manufacture wireless control or sensing products is to connect a power supply
and peripherals such as switches, actuators and sensors, considerably simplifying product
development.
2.
Features and benefits
Key features:
Bluetooth 4.2 compliant
Integrated antenna
Integrated 32 MHz and 32.768 kHz crystals
Integrated DC-DC circuit
32-bit ARM Cortex-M4F core at 32 MHz
512 kB flash
128 kB RAM
TX power: up to +2 dBm
RX sensitivity: 94 dBm
True single-chip Bluetooth Low Energy (v4.2) SoC solution:
Integrated Bluetooth LE radio, protocol stack and application profiles
Support central and peripherals roles
Support master/slave concurrency
Support 16 simultaneous links
Support secure connections
Support data packet length extension
48-bit unique BD address
94 dBm RX sensitivity
TX output power from 20 dBm to +2 dBm
Very low power consumption:
Single 1.62 V ~3.6 V power supply
1 A power-down mode, to wake up by GPIO
2 A power-down mode, to wake up by 32 kHz sleep timer, RTC and GPIO
3.6 mA RX current at 3 V supply
QN9080-001-M17
NXP Semiconductors
QN9080-001-M17
User Manual
All information provided in this document is subject to legal disclaimers.
Rev. 0.1 — 08 Dec 2017
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Ultra-low power Bluetooth Smart 4.2 SIP
3.4 mA TX current at 0 dBm TX power at 3 V supply
Interface:
32 General-Purpose Input/Output (GPIO) pins, with configurable pull-up/pull-down
resistors
8 external ADC inputs (shared with GPIO pins)
2 Analog Comparator input pins (share with GPIO pins)
Single power supply 1.62 V to 3.6 V
Operating temperature range 40 °C to +85 °C
6 9.7 1.11 mm SIP package
3.
Applications
Ultra-low-power wearable and medical devices with small form factor
Very easy pairing with NFC NTAG
Energy harvesting with the NTAG will allow to create totally new application scenario
the new iOS11 open the NFC reader function, this BLE+NTAG is a perfect match for
that
4.
Ordering information
Table 1. Ordering information
Type number
Package
Name
Description
Version
QN9080-001-M17
LFLGA54
SIP SIP in LGA package; body 6 9.7 1.11 mm
SOT1910
AA1
Table 2. Ordering options
Type number
Device order
part number
Flash/KB
Total
SRAM/KB
Cortex-M4
with FPU
FSP
USB FS
GPIO
QN9080-001-M17
3322 960 18570
512
128 1 1 1 32
5.
Marking
QN9080-1-M17
XXXXX
XXXXXXXXXXXX
EtDYYWWXX
Fig 1. QN9080-001-M17 package marking
QN9080-001-M17
NXP Semiconductors
QN9080-001-M17
User Manual
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Rev. 0.1 — 08 Dec 2017
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Ultra-low power Bluetooth Smart 4.2 SIP
Table 3. Marking code
Line number
Marking code
Line 1
NXP Logo: B&W outline logo
Line 2
part ID: QN9080-1-M17
Line 3
XXXXX: is the STR number request; it will not be mention when we will be on
production
Line 4
XXXXXXXXXXXX: QN batch number
Line 5
• E: TSMC
• t: ASE-K
• D: RoHS indicator (Dark green)
• YY: year; last two digits of year code of assembly
• WW: week code of assembly
• X: C is the QN9080 mask version
• X: for SIP before CQS; it will be removed after
QN9080-001-M17 SIP has the following top-side marking:
Table 4. Device revision table
Revision identifier (R)
Revision description
001
Initial SIP revision
All SIP types have received FCC “Modular Approval”, in compliance with CFR 47 FCC
part 15 regulations and in accordance to FCC public notice DA00-1407. The modular
approvals notice and test reports are available on request.
FCC, IC & Japan ID marking is not mentioned on the package because the device is too
small.
QN9080-001-M17 FCC ID : XXMQN9080M17
QN9080-001-M17 IC ID: 8764A-QN9080M17
QN9080-001-M17 I7 Japan ID:
207-990010
QN9080-001-M17
NXP Semiconductors
QN9080-001-M17
User Manual
All information provided in this document is subject to legal disclaimers.
Rev. 0.1 — 08 Dec 2017
© NXP Semiconductors N.V. 2017. All rights reserved.
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Ultra-low power Bluetooth Smart 4.2 SIP
6.
Block diagram
Fig 2. QN9080-001-M17 block diagram
QN9080-001-M17
NXP Semiconductors
QN9080-001-M17
User Manual
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Rev. 0.1 — 08 Dec 2017
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Ultra-low power Bluetooth Smart 4.2 SIP
QN9080-001-M17 is not certified with external antenna but only with its internal antenna. Customer using external
antenna will have to do new certification.
Fig 3. QN9080-001-M17 block diagram for customer using external antenna (Harmonic filter to be in ad equacy
with customer board)
QN9080-001-M17
NXP Semiconductors
QN9080-001-M17
User Manual
All information provided in this document is subject to legal disclaimers.
Rev. 0.1 — 08 Dec 2017
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Ultra-low power Bluetooth Smart 4.2 SIP
7.
Pinning information
7.1. Pinning
Fig 4. Pin configuration
QN9080-001-M17
NXP Semiconductors
QN9080-001-M17
User Manual
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Ultra-low power Bluetooth Smart 4.2 SIP
7.2. Pin description
Table 5. Pin description
Symbol
Pin
Type
Description
PA30
1
I/O
GPIO
PA29
2
I/O
GPIO
PA28
3
I/O
GPIO
PA27
4
I/O
GPIO
PA26
5
I/O
GPIO
LB 6 I/O
antenna connection LB
LA 7 I/O
antenna connection LA
PA25
8
I/O
GPIO
PA24
9
I/O
GPIO
PA23
10
I/O
GPIO
PA22
11
I/O
GPIO
PA21
12
I/O
GPIO
PA20
13
I/O
GPIO
PA19
14
I/O
GPIO
PA18
15
I/O
GPIO
PA17
16
I/O
GPIO
GND
Fig 5. SIP pin out
QN9080-001-M17
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QN9080-001-M17
User Manual
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Ultra-low power Bluetooth Smart 4.2 SIP
Table 5. Pin description …continued
Symbol
Pin
Type
Description
PA16
17
I/O
GPIO
PA15
18
I/O
GPIO
PA14
19
I/O
GPIO
PA13
20
I/O
GPIO
CHIP_MODE
21 I control the chip into different modes
RSTN
22 I hardware reset, active low
ANT_IN
23
I/O
antenna in
RF_OUT
24
I/O
RF output
GND
25 G ground
PA12
26
I/O
GPIO
PA11
27
I/O
GPIO
PA10
28
I/O
GPIO
PA09
29
I/O
GPIO
PA08
30
I/O
GPIO
PA07
31
I/O
GPIO
PA06
32
I/O
GPIO
PA05
33
I/O
GPIO
PA04
34
I/O
GPIO
PA03
35
I/O
GPIO
PA02
36
I/O
GPIO
NTAG_FD
37 O field detection
VCC
38 P power supply
NTAG_VCC
39 P NTAG power supply
VOUT
40 P output supply voltage (energy harvesting)
GND
41 G ground
PA01
42
I/O
GPIO
PA00
43
I/O
GPIO
PA31
44
I/O
GPIO
GND
45 G ground
GND
46 G ground
GND
47 G ground
ANT_PIN3
48 G ground
ANT_PIN1
49 G ground
ANT_PIN2
50 G ground
GND
51 G ground
GND
52 G ground
GND
53 G ground
GND
54 G ground
QN9080-001-M17
NXP Semiconductors
QN9080-001-M17
User Manual
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Rev. 0.1 — 08 Dec 2017
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Ultra-low power Bluetooth Smart 4.2 SIP
7.2.1 Termination of unused pins
Ta ble 6 shows how to terminate pins that are not used in the application. In many cases,
unused pins should be connected externally or configured correctly by software to
minimize the overall power consumption of the part.
Unused pins with GPIO function should be configured as outputs set to LOW with their
internal pull-up disabled. To configure a GPIO pin as output and drive it LOW, select the
GPIO function in the IOCON register, select output in the GPIO DIR register, and write a 0
to the GPIO PORT register for that pin. Disable the pull-up in the pin’s IOCON register.
In addition, it is recommended to configure all GPIO pins that are not bonded out on
smaller packages as outputs driven LOW with their internal pull-up disabled.
Table 6. Termination of unused pins
Pin
Default state
[1]
Recommended termination of unused pins
RSTN
I; PU
the RSTN pin can be left unconnected if the application does
not use it.
all PAnm
I; PU
can be left unconnected if driven LOW and configured as
GPIO output with pull-up disabled by software
CHIP_MODE
I; PU
can be left unconnected if driven LOW and configured as
GPIO output with pull-up disabled by software
[1] I = Input, IA = Inactive (no pull-up/pull-down enabled), PU = Pull-Up enabled.
7.2.2 Pin states in different power modes
Table 7. Pin states in different power modes
Pin
Active - Sleep - Power Down modes
all PAnm pins
As configured in the SYSCON
[1]
. Default: internal pull-up enabled
RSTN
Reset function enabled. Default: input, internal pull-up enabled
[1] Default and programmed pin states are retained in sleep, and power-down mode.
8.
Characteristics
8.1. Static characteristics
8.1.1 General operating conditions
Table 8. General operating conditions
T
amb
= 40 °C to +85 °C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
f
clk
clock frequency
- - 32
MHz
V
CC
supply voltage
1.7 3 3.6
V
8.1.2 Power consumption
Power measurements in active, sleep, power down modes were performed under the
following conditions:
QN9080-001-M17
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QN9080-001-M17
User Manual
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Ultra-low power Bluetooth Smart 4.2 SIP
• All peripherals disabled
• Analog peripherals (ADC/DAC/ACMP/Capacitive Sense) powered down
• RF off
• 32 MHz HFRCO powered down
Table 9. Static characteristics: Power consumption in active modes
T
amb
= 40 °C to +85 °C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
[1]
Max
Unit
32 MHz HFXO; DC-DC converter enabled, V
CC
= 3.0 V
I
CC
supply current
CoreMark code executed from Flash
CLK_AHB = 16 MHz
[2]
-
830 - A
[1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C).
[2] Characterized through bench measurements using typical samples.
Table 10. Static characteristics: Bluetooth LE power consumption in active modes
T
amb
= 40 °C to +85 °C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
[1][2]
Max
[3]
Unit
32 MHz HFXO, CLK_AHB = 8 MHz; Transmitter mode: fc = 2440 MHz
I
CC
supply current
DC-DC converter enabled, V
CC
= 3 V
TX power = 0 dBm
- 4 -
mA
32 MHz HFXO, CLK_AHB = 8 MHz; Receiver mode: fc = 2440 MHz
I
CC
supply current
DC-DC converter enabled, V
CC
= 3 V
94 dBm RX sensitivity
-
4.4 - mA
[1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C).
[2] Characterized through bench measurements using typical samples, with 50 loading on RF port.
[3] Guaranteed by characterization, not tested in production.
Table 11. Static characteristics: power consumption in Sleep mode and Power-down mode
T
amb
= 40 °C to +85 °C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
[1][2]
Max
[3]
Unit
I
CC
supply current
Sleep mode: all SRAM on, Flash in Standby mode, DC-DC converter
enabled, V
CC
= 3 V
32 MHz HFXO,
CLK_AHB = 16 MHz
-
470
-
A
Power-down mode: 32.768 kHz LFXO on, Flash is powered down, DC-DC
converter disabled, V
CC
= 3 V, T
amb
= 25 °C
8 KB SRAM powered
-
2.6
-
A
Power-down mode: all clocks off, Flash is powered down, DC-DC converter
disabled, V
CC
= 3 V, T
amb
= 25 °C
8 KB SRAM powered
- 1 -
A
[1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C).
[2] Characterized through bench measurements using typical samples.
[3] Guaranteed by characterization, not tested in production.
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