NXP PUMD 2 NXP Datasheet

PEMD2; PIMD2; PUMD2

NPN/PNP resistor-equipped transistors;
R1 = 22 kΩ, R2 = 22 kΩ

Rev. 07 — 24 September 2008 Product data sheet

1. Product profile

1.1 General description

NPN/PNP Resistor-Equipped Transistors (RET).

Table 1. Product overview

Type number Package PNP/PNP

PEMD2 SOT666 - PEMB1 PEMH1
PIMD2 SOT457 SC-74 - ­PUMD2 SOT363 SC-88 PUMB1 PUMH1

1.2 Features

NXP JEITA

complement

NPN/NPN
complement

n Built-in bias resistors
n Simplifies circuit design
n Reduces component count
n Reduces pick and place costs

1.3 Applications

n Low current peripheral driver
n Control of IC inputs
n Replaces general-purpose transistors in digital applications

1.4 Quick reference data

Table 2. Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

V

CEO

I

O

R1 bias resistor 1 (input) 15.4 22 28.6 kΩ
R2/R1 bias resistor ratio 0.8 1 1.2

collector-emitter voltage open base - - 50 V
output current - - 100 mA

NXP Semiconductors

2. Pinning information

Table 3. Pinning

Pin Description Simplified outline Graphic symbol

PEMD2; PUMD2

1 GND (emitter) TR1
2 input (base) TR1
3 output (collector) TR2
4 GND (emitter) TR2
5 input (base) TR2
6 output (collector) TR1

PEMD2; PIMD2; PUMD2

NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ

6 45

1 32

001aab555

65 4

R2

R1

TR1

R2 R1

TR2

PIMD2

1 GND (emitter) TR2
2 input (base) TR2
3 output (collector) TR1
4 GND (emitter) TR1
5 input (base) TR1
6 output (collector) TR2

3. Ordering information

Table 4. Ordering information

Type number Package

PEMD2 - plastic surface-mounted package; 6 leads SOT666
PIMD2 SC-74 plastic surface-mounted package (TSOP6); 6 leads SOT457
PUMD2 SC-88 plastic surface-mounted package; 6 leads SOT363

132

1

4

56

654

TR2

R2

123

23

006aaa143

R1 R2

R1

006aab235

Name Description Version

TR1

PEMD2_PIMD2_PUMD2_7 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 07 — 24 September 2008 2 of 16

NXP Semiconductors

4. Marking

Table 5. Marking codes

Type number Marking code

PEMD2 D4
PIMD2 M5
PUMD2 D*2

[1] * = -: made in Hong Kong

* = p: made in Hong Kong
* = t: made in Malaysia
* = W: made in China

5. Limiting values

Table 6. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

Per transistor; for the PNP transistor with negative polarity

V

CBO

V

CEO

V

EBO

V

I

I

O

I

CM

P

tot

T

j

T

amb

T

stg

PEMD2; PIMD2; PUMD2

NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ

[1]

collector-base voltage open emitter - 50 V
collector-emitter voltage open base - 50 V
emitter-base voltage open collector - 10 V
input voltage TR1

positive - +40 V
negative - −10 V

input voltage TR2

positive - +10 V

negative - −40 V
output current - 100 mA
peak collector current single pulse;

t

≤ 1ms

p

total power dissipation T

amb

≤ 25 °C
PEMD2 (SOT666)
PIMD2 (SOT457) - 300 mW
PUMD2 (SOT363) - 200 mW

junction temperature - 150 °C
ambient temperature −65 +150 °C
storage temperature −65 +150 °C

- 100 mA

[1]
[2]

- 200 mW

PEMD2_PIMD2_PUMD2_7 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 07 — 24 September 2008 3 of 16

NXP Semiconductors

PEMD2; PIMD2; PUMD2

NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ

Table 6. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

Per device

P

tot

total power dissipation T

PEMD2 (SOT666)
PIMD2 (SOT457) - 600 mW
PUMD2 (SOT363) - 300 mW

[1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard

footprint.

[2] Reflow soldering is the only recommended soldering method.

6. Thermal characteristics

Table 7. Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

Per transistor

R

th(j-a)

Per device

R

th(j-a)

thermal resistance from
junction to ambient

PEMD2 (SOT666)
PIMD2 (SOT457) - - 417 K/W
PUMD2 (SOT363) - - 625 K/W

thermal resistance from
junction to ambient

PEMD2 (SOT666)
PIMD2 (SOT457) - - 208 K/W
PUMD2 (SOT363) - - 416 K/W

…continued

≤ 25 °C

amb

in free air

in free air

[1]
[2]

- 300 mW

[1]

[2]

- - 625 K/W

[1]

[2]

- - 416 K/W

[1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
[2] Reflow soldering is the only recommended soldering method.

PEMD2_PIMD2_PUMD2_7 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 07 — 24 September 2008 4 of 16

NXP Semiconductors

7. Characteristics

Table 8. Characteristics

T

= 25°C unless otherwise specified.

amb

Symbol Parameter Conditions Min Typ Max Unit

Per transistor; for the PNP transistor with negative polarity

I

CBO

I

CEO

I

EBO

h

FE

V

CEsat

V

I(off)

V

I(on)

R1 bias resistor 1 (input) 15.4 22 28.6 kΩ
R2/R1 bias resistor ratio 0.8 1 1.2
C

c

PEMD2; PIMD2; PUMD2

NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ

collector-basecut-off
current

collector-emitter
cut-off current

emitter-base cut-off
current

DC current gain VCE=5V; IC= 5 mA 60 - ­collector-emitter

saturation voltage
off-state input

voltage
on-state input

voltage

collector capacitance VCB=10V;IE=ie=0A;

TR1 (NPN) - - 2.5 pF
TR2 (PNP) - - 3 pF

VCB=50V; IE= 0 A - - 100 nA

VCE=30V; IB=0A --1µA

=30V; IB=0A;

V

CE

T

= 150 °C

j

--50µA

VEB=5V; IC= 0 A - - 180 µA

IC= 10 mA; IB= 0.5 mA - - 150 mV

VCE=5V; IC= 100 µA - 1.1 0.8 V

VCE= 0.3 V; IC= 5 mA 2.5 1.7 - V

f=1MHz

PEMD2_PIMD2_PUMD2_7 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 07 — 24 September 2008 5 of 16

NXP Semiconductors

PEMD2; PIMD2; PUMD2

NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ

3

10

h

FE

2

10

10

1

−1

10

(1)
(2)
(3)

006aaa038

2

101

IC (mA)

10

VCE=5V
(1) T
(2) T
(3) T

amb
amb
amb

= 150 °C
=25°C
= −40 °C

Fig 1. TR1 (NPN): DC current gain as a function of

collector current; typical values

−1

10

V

CEsat

(V)

−2

10

110

(1)
(2)

(3)

10

006aaa039

IC (mA)

IC/IB=20
(1) T
(2) T
(3) T

amb
amb
amb

= 100 °C
=25°C
= −40 °C

Fig 2. TR1 (NPN): Collector-emitter saturation

voltage as a function of collector current;

typical values

2

10

V

I(on)

(V)

(1)
(2)

1

−1

10

−1

10

(3)

006aaa040

101

IC (mA)

10

VCE= 0.3 V
(1) T
(2) T
(3) T

amb
amb
amb

= −40 °C
=25°C
= 100 °C

Fig 3. TR1 (NPN): On-state input voltage as a

function of collector current; typical values

10

V

I(off)

(V)

(1)
(2)

1

(3)

−1

2

10

−2

10

−1

006aaa041

1

110

IC (mA)

10

VCE=5V
(1) T
(2) T
(3) T

amb
amb
amb

= −40 °C
=25°C
= 100 °C

Fig 4. TR1 (NPN): Off-state input voltage as a

function of collector current; typical values

PEMD2_PIMD2_PUMD2_7 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 07 — 24 September 2008 6 of 16

NXP Semiconductors

PEMD2; PIMD2; PUMD2

NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ

006aab351

2

101

IC (mA)

10

R

10

CEsat

(Ω)

10

3

2

(1)
(2)

(3)

10

1

−1

10

IC/IB=20
(1) T
(2) T
(3) T

amb
amb
amb

= 100 °C
=25°C
= −40 °C

Fig 5. TR1 (NPN): Collector-emitter saturation resistance as a function of collector

current; typical values

PEMD2_PIMD2_PUMD2_7 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 07 — 24 September 2008 7 of 16

NXP Semiconductors

PEMD2; PIMD2; PUMD2

NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ

3

10

h

FE

2

10

10

1

−1

−10

(1)
(2)
(3)

−10−1

006aab197

IC (mA)

−10

2

VCE= −5V
(1) T
(2) T
(3) T

amb
amb
amb

= 150 °C
=25°C
= −40 °C

Fig 6. TR2 (PNP): DC current gain as a function of

collector current; typical values

(1)
(2)
(3)

IC (mA)

006aab198

−1

V

CEsat

(V)

−

1

−10

−

2

−10

−1 −10

−10

IC/IB=20
(1) T
(2) T
(3) T

amb
amb
amb

= 100 °C
=25°C
= −40 °C

Fig 7. TR2 (PNP): Collector-emitter saturation

voltage as a function of collector current;

typical values

2

−10

V

I(on)

(V)

(1)
(2)

−10

−1

−1

−10

−1

(3)

−10−1

006aab199

IC (mA)

−10

VCE= −0.3 V
(1) T
(2) T
(3) T

amb
amb
amb

= −40 °C
=25°C
= 100 °C

Fig 8. TR2 (PNP): On-state input voltage as a

function of collector current; typical values

−10

V

I(off)

(V)

(1)

−1

−1

2

−10

−10

−2

(2)

(3)

−1

006aab200

IC (mA)

−10−1−10

VCE= −5V
(1) T
(2) T
(3) T

amb
amb
amb

= −40 °C
=25°C
= 100 °C

Fig 9. TR2 (PNP): Off-state input voltage as a

function of collector current; typical values

PEMD2_PIMD2_PUMD2_7 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 07 — 24 September 2008 8 of 16

NXP Semiconductors

PEMD2; PIMD2; PUMD2

NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ

006aab352

IC (mA)

−10

2

R

CEsat

(Ω)

3

10

2

10

(1)
(2)

(3)

10

1

−1

−10

−10−1

IC/IB=20
(1) T
(2) T
(3) T

amb
amb
amb

= 100 °C
=25°C
= −40 °C

Fig 10. TR2 (PNP): Collector-emitter saturation resistance as a function of collector

current; typical values

PEMD2_PIMD2_PUMD2_7 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 07 — 24 September 2008 9 of 16

NXP Semiconductors

8. Package outline

PEMD2; PIMD2; PUMD2

NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ

3.1

2.7

132

0.95

1.9

56

4

0.6

0.2

0.40

0.25

1.7

1.3

1.5

1.1

Dimensions in mm

1.7

1.5

pin 1 index

123

0.5
1

0.6

0.5

456

0.3

0.1

3.0

1.7

2.5

1.3

pin 1 index

0.27

0.17

0.18

0.08

04-11-08

Fig 11. Package outline PEMD2 (SOT666) Fig 12. Package outline PIMD2 (SOT457/SC-74)

2.2

2.0

1.35

1.15

pin 1
index

2.2

1.8

0.45

465

0.15

1.1

0.8

1.1

0.9

0.26

0.10

04-11-08Dimensions in mm

132

0.65

Fig 13. Package outline PUMD2 (SOT363/SC-88)

1.3

0.3

0.2

0.25

0.10

06-03-16Dimensions in mm

PEMD2_PIMD2_PUMD2_7 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 07 — 24 September 2008 10 of 16

NXP Semiconductors

9. Packing information

PEMD2; PIMD2; PUMD2

NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ

10. Soldering

Table 9. Packing methods

The indicated -xxx are the last three digits of the 12NC ordering code.

[1]

Type number Package Description Packing quantity

3000 4000 8000 10000

PEMD2 SOT666 2 mm pitch, 8 mm tape and reel - - -315 -

4 mm pitch, 8 mm tape and reel - -115 - -

[2]

PIMD2 SOT457 4 mm pitch, 8 mm tape and reel; T1

4 mm pitch, 8 mm tape and reel; T2

PUMD2 SOT363 4 mm pitch, 8 mm tape and reel; T1

4 mm pitch, 8 mm tape and reel; T2

[1] For further information and the availability of packing methods, seeSection 13.
[2] T1: normal taping
[3] T2: reverse taping

2.75

2.45

2.1

1.6

-115 - - -135

[3]

-125 - - -165

[2]

-115 - - -135

[3]

-125 - - -165

0.538

1.075

1.72

Reflow soldering is the only recommended soldering method.

0.55
(2×)

0.45
(4×)

0.5

(4×)

1.7

0.6

(2×)

0.65
(2×)

Fig 14. Reflow soldering footprint PEMD2 (SOT666)

0.4

(6×)

0.25
(2×)

0.325
(4×)

0.3

(2×)

0.375
(4×)

solder lands

placement area

solder paste

occupied area

Dimensions in mm

sot666_fr

PEMD2_PIMD2_PUMD2_7 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 07 — 24 September 2008 11 of 16

NXP Semiconductors

PEMD2; PIMD2; PUMD2

NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ

3.45

1.95

0.55

0.95

2.8253.3

0.95

0.7

(6×)

0.8

(6×)

2.4

0.45
(6×)

(6×)

Fig 15. Reflow soldering footprint PIMD2 (SOT457/SC-74)

5.3

1.5

(4×)

1.475

5.05

1.475

0.45
(2×)

solder lands

solder resist

solder paste

occupied area

Dimensions in mm

sot457_fr

solder lands

solder resist

occupied area

Dimensions in mm

preferred transport

direction during soldering

1.45
(6×)

2.85

sot457_fw

Fig 16. Wave soldering footprint PIMD2 (SOT457/SC-74)

PEMD2_PIMD2_PUMD2_7 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 07 — 24 September 2008 12 of 16

NXP Semiconductors

2.35

1.5

PEMD2; PIMD2; PUMD2

NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ

2.65

solder lands

0.6

(4×)

0.5

(4×)

0.4 (2×)
solder resist

solder paste

0.5

(4×)

0.6

(4×)

0.6

(2×)

1.8

Fig 17. Reflow soldering footprint PUMD2 (SOT363/SC-88)

1.5

2.5

4.5

1.3 1.3

2.45

5.3

0.3

1.5

Fig 18. Wave soldering footprint PUMD2 (SOT363/SC-88)

occupied area

Dimensions in mm

sot363_fr

solder lands

solder resist

occupied area

Dimensions in mm

preferred transport

direction during soldering

sot363_fw

PEMD2_PIMD2_PUMD2_7 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 07 — 24 September 2008 13 of 16

NXP Semiconductors

NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ

PEMD2; PIMD2; PUMD2

11. Revision history

Table 10. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PEMD2_PIMD2_PUMD2_7 20080924 Product data sheet - PEMD2_PIMD2_PUMD2_6
Modifications:

PEMD2_PIMD2_PUMD2_6 20040421 Product specification - PEMD2_PIMD2_PUMD2_5

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Table 8 “Characteristics”: V

unit corrected

CEsat

• Figure 1, 2, 3, 4, 5, 6, 7, 8, 9 and 10: added

• Section 12 “Legal information”: updated

PEMD2_PIMD2_PUMD2_7 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 07 — 24 September 2008 14 of 16

NXP Semiconductors

12. Legal information

12.1 Data sheet status

PEMD2; PIMD2; PUMD2

NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL

[1][2]

Product status

12.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shallhave no liability forthe consequences of
use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet
with the same product typenumber(s) and title.A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.

12.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not giveany representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.

Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces allinformation supplied prior
to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental

[3]

http://www.nxp.com.

Definition

damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum RatingsSystem of IEC 60134) maycause permanent
damage to the device. Limitingvalues are stress ratings only and operationof
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at

http://www.nxp.com/profile/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyanceor implication of any license under any copyrights,patents
or other industrial or intellectual property rights.

Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.

12.4 Trademarks

Notice: All referenced brands, product names, service namesand trademarks
are the property of their respective owners.

13. Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [e-mail]

PEMD2_PIMD2_PUMD2_7 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 07 — 24 September 2008 15 of 16

NXP Semiconductors

NPN/PNP resistor-equipped transistors; R1 = 22 kΩ, R2 = 22 kΩ

14. Contents

1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 General description. . . . . . . . . . . . . . . . . . . . . . 1

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.4 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1

2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4

7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5

8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10

9 Packing information. . . . . . . . . . . . . . . . . . . . . 11

10 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

11 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14

12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15

12.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15

12.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

12.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

12.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15

13 Contact information. . . . . . . . . . . . . . . . . . . . . 15

14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

PEMD2; PIMD2; PUMD2

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.

© NXP B.V. 2008. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [e-mail]

Document identifier: PEMD2_PIMD2_PUMD2_7

Date of release: 24 September 2008