NXP PEMD12, PUMD12 Schematic [ru]

PEMD12; PUMD12

NPN/PNP resistor-equipped transistors;
R1 = 47 k, R2 = 47 k

Rev. 4 — 21 November 2011 Product data sheet

1. Product profile

1.1 General description

NPN/PNP double Resistor-Equipped Transistors (RET) in Surface-Mounted
Device (SMD) plastic packages.

Table 1. Product overview

Type number Package PNP/PNP

PEMD12 SOT666 - PEMB2 PEMH2 ultra small and flat

PUMD12 SOT363 SC-88 PUMB2 PUMH2 very small

NXP JEITA

complement

NPN/NPN
complement

Package
configuration

lead

1.2 Features and benefits

 100 mA output current capability  Reduces component count
 Built-in bias resistors  Reduces pick and place costs
 Simplifies circuit design  AEC-Q101 qualified

1.3 Applications

 Low current peripheral driver
 Control of IC inputs
 Replaces general-purpose transistors in digital applications

1.4 Quick reference data

Table 2. Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

Per transistor; for the PNP transistor (TR2) with negative polarity

V

CEO

I

O

R1 bias resistor 1 (input) 33 47 61 k
R2/R1 bias resistor ratio 0.8 1 1.2

collector-emitter voltage open base - - 50 V
output current - - 100 mA

NXP Semiconductors

001aab555

6 45

1 32

65 4

1

23

R2

TR1

TR2

R1

R2 R1

006aaa143

2. Pinning information

Table 3. Pinning

Pin Description Simplified outline Graphic symbol

1 GND (emitter) TR1
2 input (base) TR1
3 output (collector) TR2
4 GND (emitter) TR2
5 input (base) TR2
6 output (collector) TR1

3. Ordering information

PEMD12; PUMD12

NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k

4. Marking

Table 4. Ordering information

Type number Package

Name Description Version

PEMD12 - plastic surface-mounted package; 6 leads SOT666
PUMD12 SC-88 plastic surface-mounted package; 6 leads SOT363

Table 5. Marking codes

Type number Marking code

[1]

PEMD12 D2
PUMD12 D*1

[1] * = placeholder for manufacturing site code

PEMD12_PUMD12 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 4 — 21 November 2011 2 of 16

NXP Semiconductors

5. Limiting values

Table 6. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

Per transistor; for the PNP transistor (TR2) with negative polarity

V

CBO

V

CEO

V

EBO

V

I

I

O

I

CM

P

tot

Per device

P

tot

T

j

T

amb

T

stg

[1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard

footprint.

[2] Reflow soldering is the only recommended soldering method.

PEMD12; PUMD12

NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k

collector-base voltage open emitter - 50 V
collector-emitter voltage open base - 50 V
emitter-base voltage open collector - 10 V
input voltage TR1

positive - +40 V
negative - 10 V

input voltage TR2

positive - +10 V

negative - 40 V
output current - 100 mA
peak collector current single pulse;

 1ms

t

p

total power dissipation T

amb

 25 C
PEMD12 (SOT666)
PUMD12 (SOT363)

total power dissipation T

amb

 25 C
PEMD12 (SOT666)
PUMD12 (SOT363)

junction temperature - 150 C
ambient temperature 65 +150 C
storage temperature 65 +150 C

-100mA

[1][2]

-200mW

[1]

-200mW

[1][2]

-300mW

[1]

-300mW

PEMD12_PUMD12 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 4 — 21 November 2011 3 of 16

NXP Semiconductors

PEMD12; PUMD12

NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k

FR4 PCB, standard footprint

Fig 1. Per device: Power derating curve for SOT363 (SC-88) and SOT666

6. Thermal characteristics

Table 7. Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

Per transistor

R

th(j-a)

Per device

R

th(j-a)

thermal resistance from
junction to ambient

PEMD12 (SOT666)
PUMD12 (SOT363)

thermal resistance from
junction to ambient

PEMD12 (SOT666)
PUMD12 (SOT363)

400

P

tot

(mW)

300

200

100

0

-75 17512525 75-25

in free air

in free air

006aac749

T

(°C)

amb

[1][2]

[1]

[1][2]

[1]

- - 625 K/W

- - 625 K/W

- - 417 K/W

- - 417 K/W

[1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
[2] Reflow soldering is the only recommended soldering method.

PEMD12_PUMD12 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 4 — 21 November 2011 4 of 16

NXP Semiconductors

006aac750

10

-5

1010

-2

10

-4

10

2

10

-1

tp (s)

10

-3

10

3

1

10

2

10

10

3

Z

th(j-a)

(K/W)

1

duty cycle = 1

0.75

0.5

0.33

0.2

0.1

0.05

0.02

0.01

0

PEMD12; PUMD12

NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k

006aac751

2

10

tp (s)

3

10

Z

th(j-a)

(K/W)

3

10

2

10

10

1

10

duty cycle = 1

0.75

0.33

0.1

0.05

0.02

0.01

0

-5

0.5

0.2

-4

10

-3

10

-2

-1

10

1

1010

FR4 PCB, standard footprint

Fig 2. Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration for

PEMD12 (SOT666); typical values

FR4 PCB, standard footprint

Fig 3. Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration for

PUMD12 (SOT363); typical values

PEMD12_PUMD12 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 4 — 21 November 2011 5 of 16

NXP Semiconductors

7. Characteristics

Table 8. Characteristics

T

amb

Symbol Parameter Conditions Min Typ Max Unit

Per transistor; for the PNP transistor (TR2) with negative polarity

I

CBO

I

CEO

I

EBO

h

FE

V

CEsat

V

I(off)

V

I(on)

R1 bias resistor 1 (input) 33 47 61 k
R2/R1 bias resistor ratio 0.8 1 1.2
C

c

f

T

PEMD12; PUMD12

NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k

=25C unless otherwise specified.

collector-base cut-off
current

collector-emitter cut-off
current

emitter-base cut-off
current

DC current gain VCE=5V; IC=5mA 80 - ­collector-emitter

saturation voltage
off-state input voltage VCE=5V; IC= 100 A- 1.20.8V
on-state input voltage VCE=0.3V; IC=2mA 3 1.6 - V

collector capacitance VCB=10V;

TR1 (NPN) - - 2.5 pF
TR2 (PNP) - - 3 pF

transition frequency VCE=5V; IC=10mA;

TR1 (NPN) - 230 - MHz
TR2 (PNP) - 180 - MHz

VCB=50V; IE= 0 A - - 100 nA

VCE=30V; IB=0A --1A

=30V; IB=0A;

V

CE

T

= 150 C

j

--5A

VEB=5V; IC=0A --90A

IC=10mA;

=0.5mA

I

B

--150mV

IE=ie=0A; f=1MHz

[1]

f=100MHz

[1] Characteristics of built-in transistor

PEMD12_PUMD12 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 4 — 21 November 2011 6 of 16

NXP Semiconductors

PEMD12; PUMD12

NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k

3

10

h

FE

2

10

10

1

-1

10

006aac752

(1)
(2)
(3)

2

101

IC (mA)

10

VCE=5V
(1) T
(2) T
(3) T

amb
amb
amb

= 100 C
=25C
= 40 C

Fig 4. TR1 (NPN): DC current gain as a function of

collector current; typical values

006aac753

101

IC (mA)

10

V

CEsat

(V)

1

-1

10

-2

10

10

(1) T
(2) T
(3) T

I

C/IB

-1

amb
amb
amb

(1)

(2)

(3)

=20

= 100 C
=25C
= 40 C

Fig 5. TR1 (NPN): Collector-emitter saturation

voltage as a function of col lector current;
typical values

2

006aac754

101

IC (mA)

10

V

I(on)

(V)

10

(1)
(2)

1

-1

10

-1

10

(3)

VCE=0.3V

amb
amb
amb

= 40 C
=25C
= 100 C

(1) T
(2) T
(3) T

Fig 6. TR1 (NPN): On-state input voltage as a

function of collector current; typical values

IC (mA)

006aac755

101

10

V

I(off)

(V)

(1)
(2)

1

-1

2

10

10

(1) T
(2) T
(3) T

-1

V

CE
amb
amb
amb

=5V

= 40 C
=25C
= 100 C

(3)

Fig 7. TR1 (NPN): Off-state input voltage as a

function of collector current; typical values

PEMD12_PUMD12 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 4 — 21 November 2011 7 of 16

NXP Semiconductors

PEMD12; PUMD12

NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k

006aac756

VCB (V)

C

(pF)

2.0

c

1.6

1.2

0.8

0.4

0.0
0504020 3010

f=1MHz; T

=25CV

amb

Fig 8. TR1 (NPN): Collector capacitance as a function

of collector-base voltage; typical values

3

10

h

FE

2

10

006aac758

(1)
(2)
(3)

10

f

T

(MHz)

10

3

2

10

-1

10

=5V; T

CE

amb

=25C

006aac757

2

101

IC (mA)

10

Fig 9. TR1 (NPN): Transition frequency as a function

of collector current; typical values of built-in
transistor

006aac759

V

CEsat

(V)

-1

10

1

-10

-1

-10-1
IC (mA)

-10

2

VCE= 5V

amb
amb
amb

= 100 C
=25C
= 40 C

(1) T
(2) T
(3) T

Fig 10. TR2 (PNP): DC current gain as a function of

collector current; typical values

-1

-10

(1)
(2)
(3)

-2

-10

-10

(1) T
(2) T
(3) T

I

C/IB

-1

amb
amb
amb

=20

= 100 C
=25C
= 40 C

-10-1
IC (mA)

-10

Fig 11. TR2 (PNP): Collector-emitter saturation

voltage as a function of col lector current;
typical values

2

PEMD12_PUMD12 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 4 — 21 November 2011 8 of 16

NXP Semiconductors

VCB (V)

0 -50-40-20 -30-10

006aac762

3

6

9

C

c

(pF)

0

006aac763

IC (mA)

-10

-1

-10

2

-10-1

10

2

10

3

f

T

(MHz)

10

PEMD12; PUMD12

NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k

006aac760

-10-1
IC (mA)

-10

V

I(on)

(V)

-10

-10

(1)
(2)
(3)

-1

-1

-1

-10

VCE= 0.3 V
(1) T
(2) T
(3) T

amb
amb
amb

= 40 C
=25C
= 100 C

Fig 12. TR2 (PNP): On-state input voltage as a

function of collector current; typical values

IC (mA)

006aac761

-10-1

-10

V

I(off)

(V)

-1

-1

2

-10

-10

(1) T
(2) T
(3) T

-1

V

CE
amb
amb
amb

= 5V

= 40 C
=25C
= 100 C

(1)
(2)

(3)

Fig 13. TR2 (PNP): Off-state input voltage as a

function of collector current; typical values

f=1MHz; T

Fig 14. TR2 (PNP): Collector capacit ance as a functi on

PEMD12_PUMD12 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

of collector-base voltage; typical values of

built-in transistor

=25CV

amb

= 5V; T

CE

amb

=25C

Fig 15. TR2 (PNP): Transition freque nc y as a function

of collector current; typical values of built-in
transistor

Product data sheet Rev. 4 — 21 November 2011 9 of 16

NXP Semiconductors

Dimensions in mm

04-11-08

1.7

1.5

1.7

1.5

1.3

1.1

1

0.18

0.08

0.27

0.17

0.5

pin 1 index

123

456

0.6

0.5

0.3

0.1

06-03-16Dimensions in mm

0.25

0.10

0.3

0.2

pin 1
index

1.3

0.65

2.2

2.0

1.35

1.15

2.2

1.8

1.1

0.8

0.45

0.15

132

465

8. Test information

8.1 Quality information

This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is
suitable for use in automotive applications.

9. Package outline

PEMD12; PUMD12

NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k

Fig 16. Package outline PEMD12 (SOT666) Fig 17. Package outline PUMD12 (SOT363)

10. Packing information

PEMD12_PUMD12 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 4 — 21 November 2011 10 of 16

Table 9. Packing methods

The indicated -xxx are the last three digits of the 12NC ordering code.

Type

Package Description Packing quantity

number

[1]

3000 4000 8000 10000

PEMD12 SOT666 2 mm pitch, 8 mm tape and reel - - -315 -

4 mm pitch, 8 mm tape and reel - -115 - -

[2]

PUMD12 SOT363 4 mm pitch, 8 mm tape and reel; T1

4 mm pitch, 8 mm tape and reel; T2

[1] For further information and the availability of packing methods, see Section 14.
[2] T1: normal taping
[3] T2: reverse taping

-115 - - -135

[3]

-125 - - -165

NXP Semiconductors

solder lands

placement area

occupied area

solder paste

sot666_fr

2.75

2.45

2.1

1.6

0.4

(6×)

0.55
(2×)

0.25
(2×)

0.6

(2×)

0.65
(2×)

0.3

(2×)

0.325
(4×)

0.45
(4×)

0.5

(4×)

0.375
(4×)

1.72

1.7

1.075

0.538

Dimensions in mm

11. Soldering

PEMD12; PUMD12

NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k

Reflow soldering is the only recommended soldering method.

Fig 18. Reflow soldering footprint PEMD12 (SOT666)

PEMD12_PUMD12 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 4 — 21 November 2011 11 of 16

NXP Semiconductors

solder lands

solder resist

occupied area

solder paste

sot363_fr

2.65

2.35

0.4 (2×)

0.6

(2×)

0.5

(4×)

0.5

(4×)

0.6

(4×)

0.6

(4×)

1.5

1.8

Dimensions in mm

sot363_fw

solder lands

solder resist

occupied area

preferred transport

direction during soldering

5.3

1.3 1.3

1.5

0.3

1.5

4.5

2.45

2.5

Dimensions in mm

Fig 19. Reflow soldering footprint PUMD12 (SOT363)

PEMD12; PUMD12

NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k

Fig 20. Wave soldering footprint PUMD12 (SOT363)

PEMD12_PUMD12 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 4 — 21 November 2011 12 of 16

NXP Semiconductors

PEMD12; PUMD12

NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k

12. Revision history

Table 10. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PEMD12_PUMD12 v.4 20111121 Product data sheet - PEMD12_PUMD12 v.3
Modifications:

PEMD12_PUMD12 v.3 20031008 Product data sheet - PEMD12 v.2
PEMD12 v.2 20011107 Product specification - PEMD12 v.1
PEMD12 v.1 20010830 Preliminary specification - ­PUMD12 v.2 20010216 Product specification - PUMD12 v.1
PUMD12 v.1 19990426 Product specification - -

• The format of this document has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Section 1 “Product profile”: updated

• Section 4 “Marking”: updated

• Figure 1 to 15: added

• Section 6 “Thermal characteristics”: updated

• Table 8 “Characteristics”: V

off-state input voltage, I

V

I(off)

redefined to V

i(on)

updated, fT added

CEO

on-state input voltage, V

I(on)

redefined to

i(off)

• Section 8 “Test information”: added

• Section 9 “Package outline”: superseded by minimized package outline drawings

• Section 10 “Packing information”: added

• Section 11 “Soldering”: added

• Section 13 “Legal information”: updated

PEMD12_PUMD12 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 4 — 21 November 2011 13 of 16

NXP Semiconductors

PEMD12; PUMD12

NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k

13. Legal information

13.1 Data sheet status

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this docu ment may have change d since this d ocument was p ublished and may dif fe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

[1][2]

Product status

[3]

Definition

13.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to co nt ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.

Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.

13.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semi conductors’ aggregat e and cumulative liabil ity towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.

Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or cust omer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.

NXP Semiconductors does not accept any liability related to any default ,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third part y
customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.

, unless otherwise

PEMD12_PUMD12 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 4 — 21 November 2011 14 of 16

NXP Semiconductors

PEMD12; PUMD12

NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.

13.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.

14. Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [e-mail]

PEMD12_PUMD12 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.

Product data sheet Rev. 4 — 21 November 2011 15 of 16

NXP Semiconductors

NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k

15. Contents

1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 General description . . . . . . . . . . . . . . . . . . . . . 1

1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1

1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . 1

2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Thermal characteristics . . . . . . . . . . . . . . . . . . 4

7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 6

8 Test information. . . . . . . . . . . . . . . . . . . . . . . . 10

8.1 Quality information . . . . . . . . . . . . . . . . . . . . . 10

9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10

10 Packing information . . . . . . . . . . . . . . . . . . . . 10

11 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

12 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13

13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14

13.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14

13.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

13.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 14

13.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15

14 Contact information. . . . . . . . . . . . . . . . . . . . . 15

15 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

PEMD12; PUMD12

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.

© NXP B.V. 2011. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [e-mail]

Date of release: 21 November 2011

Document identifier: PEMD12_PUMD12