NXP PNEV5190B, AN12550 Application note

AN12550

PNEV5190B evaluation board quick start guide

Rev. 1.5 — 23 April 2021 Application note 562315 COMPANY PUBLIC

Document information

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Keywords PN5190, PNEV5190B, PNEV5190M, PN5190 evaluation board, PN5190

customer board, PN5190 GUI, GUI, PN5190 support tool, NFC Cockpit

Abstract This document describes the PNEV5190B V1.0 (PN5190 evaluation board),

and how to use it. It describes the NFC Cockpit (PN5190 GUI Version 5.5.0 or later), which allows an easy basic access to the PN5190 registers and EEPROM in combination with basic reader functionality.

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1 Revision history

Revision history

Rev Date Description

1.5 20210423

1.4 20201218

1.3 20200929

1.2 20200109

1.1 20191217

1.0 20191128

• The format of this application note has been redesigned to comply with the new identity guidelines of NXP Semiconductors.

• Section 6: updated

Update of the software section

Update versions numbers for PN5190 CQS1

Figure 6 layout corrected

AN number corrected, typos removed

First version

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PNEV5190B evaluation board quick start guide

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2 Introduction

This document describes the PNEV5190B (PN5190 evaluation board), which provides an easy evaluation of the features and functions of the PN5190.

It provides the first steps to operate the board, using the NFC Cockpit (PN5190 GUI Version 5.5.0 or higher).

The default antenna is a 45 mm x 45 mm antenna with some metal layer inside the antenna area. This antenna is not an optimum antenna as such, but intends to demonstrate the performance and register settings of the PN5190 under typical design constraints like LCD or some metal (e.g. PCB) inside the antenna area. The default settings provide an EMVC0 3.0 L1 analog compliance under the assumption that the antenna surface is a few mm above the antenna PCP.

2.1 PN5190 registers and EEPROM concept

The PN5190 uses internal registers to adapt and optimize the functionality and performance for each of the supported protocols and data rates dependent on the connected antenna, matching network and receiver path. It offers an EEPROM, which contains the default settings for all the supported protocols. These settings are loaded into the registers with the LOAD_RF_CONFIGURATION (0Dh) command for each supported protocol and data rate.

AN12550

PNEV5190B evaluation board quick start guide

The default EEPROM configuration settings are optimized for the 45 mm x 45 mm antenna of the board PNEV5190B and can be changed by the user in case a customized antenna and matching network is used. The command LOAD_RF_CONFIGURATION allows initializing multiple registers with an efficient single command and allows distinguishing between transmit and receive configuration. Update of the registers relevant for a selected protocol is done by copying the content of EEPROM addresses to registers. Not all protocols require the initialization of all or the same registers, the command LOAD_RF_ CONFIGURATION considers this by initializing the registers relevant for the currently selected protocol only.

The EEPROM content can be updated using the command UPDATE_RF_CONFIGURATION (0Eh). The command does not require any physical EEPROM address, but works directly with the register address information and the protocol for which this data is intended to be used. This allows a convenient initialization of all relevant values for operation.

Some of these settings can or even must be adapted toward a new antenna design (e.g. the dynamic power control). All those design-specific settings should be stored in the PN5190 EEPROM to allow a proper functionality.

Some EEPROM configuration data is independent from the used protocols and defines e.g. the startup behavior of the PN5190 or the functionality of low-power card detection (LPCD). This configuration data might also be adapted for optimum performance of the chip.

2.2 PNEV5190B concept

The basic concept of the PNEV5190B is to enable the user to perform a quick evaluation of the PN5190 and also connect their own antenna to the PNEV5190B board. In addition, dedicated boards which allow to solder custom antenna matching components are available. The NFC Cockpit can be used to optimize the RF

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performance of the PN5190 antenna tuning, to perform the DPC calibration and the related TX and RX optimization without touching any source code.

All the relevant registers can be modified and fine-tuned using the NFC Cockpit. After successful register optimization, the found settings can be stored in the PN5190 EEPROM.

The NFC Cockpit also allows a dump of the complete user EEPROM content into an XML file. This file then can be loaded again into the EEPROM. That allows to manage and exchange different user or antenna configurations. In addition, the optimized register settings using the NFC Cockpit can be used during user code development as well.

As soon as the register settings for the targeted protocols and data rates are defined, the NFC Reader Library including the HAL can be used to start the development of the user application. Examples illustrate the usage of the library for typical use cases.

The source code examples of the NFC Reader Library can be used to develop an own application directly on the Kinetis MCU K82 (see [4]) or can serve as a starting point for porting the NXP NFC Reader Library to any other microcontroller platform.

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PNEV5190B evaluation board quick start guide

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3 Hardware

The PNEV5190B V1.0, as shown in Figure 1, provides some test functions which might not be used for the typical hardware and software evaluation. The PNEV5190M (module) can be used as a simple standard reader module without modification. In addition, it can be used to define and optimize the analog settings for any connected antenna or it can be used to develop and modify any RFID and NFC application based on the NFC Reader Library.

3.1 Hardware introduction

The PN5190 is supplied with a supply voltage, which can be chosen between internal and external supply. For the internal supply either 5 V, 3.3 V or 1.8 V (for VDDIO) can be used. The external power supply must be between 5 V and 12 V DC (polarity does not matter) since the board provides a rectifier and LDO to supply the circuit with 6 V (optional, supply voltage ≥7.5 V), 5 V, 3.3 V and 1.8 V.

Warning: The PN5190 in default configuration requires an external power supply, i.e. the USB supply does not provide enough current.

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PNEV5190B evaluation board quick start guide

The PN5190 is connected to a Kinetis K82 121BGA µC via SPI. A specific firmware on the K82 allows using the PNEV5190B together with the NFC Cockpit.

The connection to the PC is done via USB micro connection.

Another connection option allows connecting a Linker / LPC-LINK2 board to the PNEV5190B with a debug cable. This allows the development of custom software or the execution of the NXP NFC Reader Library code including samples.

In case a different host microcontroller shall be used, the SPI interface is available for connection to an external host (the onboard K82 is not used in this case).

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AN12550

PNEV5190B evaluation board quick start guide

1. Version 1.0

Figure 1. PNEV5190B Customer evaluation board

The PNEV5190B customer evaluation board consists of 2 PCBs:

The PNEV5190B (base board) and the PNEV5190M (module board), as shown in

Figure 2 and Figure 3. The PNEV5190M is soldered onto the PNEV5190B and contains

the PN5190 itself and the major components, as required to operate the IC, e.g. the DCDC inductor, the EMC filter and some block capacitors. The layout of the module board can be taken as reference.

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Figure 2. PNEV5190B base board top view (placement)

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PNEV5190B evaluation board quick start guide

Figure 3. PNEV5190M Module board top view (placement)

3.2 Schematics

The complete schematics of the PNEV5190B base board are shown in the following figures. The more detailed reference data is available in [5].

3.2.1 K82

The PNEV5190B uses a Kinetis K82 121BGA microcontroller (Figure 4).

An LPC Link can be connected to the K82 via the JTAG/SWD interface (see Figure 5).

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In addition, an OpenSDA interface is provided for debugging the K82 by using a Kinetis MK20DX128VFM5 (Figure 6).

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PNEV5190B evaluation board quick start guide

Figure 4. K82 main schematics

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PNEV5190B evaluation board quick start guide

Figure 5. PNEV5190M interface

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PNEV5190B evaluation board quick start guide

Figure 6. OpenSDA for K82 (MK20DX128VFM5)

3.2.2 Power supply

The default settings use the external power supply from the power jack connector. The external power supply must always be used, if the DC-DC is enabled (default). The DC power input can cover a DC voltage around 7.5 V with a current of at least 800 mA. The polarity does not matter, since there is a rectifier foreseen. The inrush current of the DCDC can be up to 1.6 A, when enabling the RF field.

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Figure 7. Figure title here

AN12550

PNEV5190B evaluation board quick start guide

As soon as the board is supplied with power, the red LED D5 must be on.

The PNEV5190B has different supply pins for the PNEV5190M (module board) as shown in Table 1. For further details on the supply options of the PN5190 itself, refer to [1].

Table 1. PNEV5190M module supply pins

Attention: there are PN5190 (IC) pins with the same name!

Pin Name Type Description

VBAT Supply input 3.3 V Main Input Supply Voltage

VBATPWR Supply input = VBAT = 3.3 V Main Input Supply Voltage

VDDIO Supply input 1.8 V IO power supply

VUP - not used in default configuration

The PN5190B base board provides four LDOs:

1. U8 for supplying the PNEV5190M with VBAT. The default configuration provides VBAT = 3.3 V. Optionally this voltage can be set to 4.8 V.

2. U5 for supplying the VDDIO and the µC supply (VDDIO_BRD = MCU_VDD = MCU_VDDA) with 3.3 V. This LDO is not used in default configuration.

3. U6 for supplying the VDDIO and the µC supply (VDDIO_BRD = MCU_VDD = MCU_VDDA) with 1.8 V. This LDO is used in default configuration.

4. U7 for supplying the overall board with 6 V. This LDO is used in default configuration.

The default configuration uses the following jumpers closed:

J9: 2-3 -> external power supply

J8: closed -> VBATPWR supplied with VBAT = 3.3 V

J12: closed -> VBAT supplied with 3.3 V

The default configuration uses the following jumpers open:

J3: open

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J4: open

J5: open

J6: open

J13: open (this jumper can be used to bypass the DC-DC, but only if the EEPROM settings are done properly AND the required board modifications are made properly)

J14: open

J8 can be used to measure the current consumption of the TX driver circuit including the DC-DC.

J12 can be used to measure the supply current consumption, excluding the TX driver part.

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PNEV5190B evaluation board quick start guide

Figure 8. PBEV5190B jumpers

3.2.3 PNEV5190M module board

The PNEV5190M module board is shown in Figure 9. The module board contains the most relevant components, directly connected to the PN5190, i.e. the EMC filter inductors, the DC-DC inductor, the major block capacitors and the 27.12 MHz crystal.

The default clock is based on this 27.12 MHz crystal, but the board supports the option to test external clock input, if needed.

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