NXP PN512 Schematics

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1. Introduction

1.1 Different available versions

PN512

Transmission module

Rev. 4.2 — 28 August 2012 111342

This document describes the functionality and electrical specifications of the transceiver IC PN512.

The PN512 is a highly integrated transceiver IC for contactless communication at

13.56 MHz. This transceiver IC utilizes an outstanding modulation and demodulation concept completely integrated for different kinds of contactless communication methods and protocols at 13.56 MHz.

The PN512 is available in three versions:

Product data sheet

COMPANY PUBLIC

• PN5120A0HN1/C2 (HVQFN32) and PN5120A0HN/C2 (HVQFN40), hereafte r named

as version 2.0

• PN512AA0HN1/C2 (HVQFN32) and PN512AA0HN1/C2BI (HVQFN32 with Burn In),

hereafter named as industrial version, fulfilling the automotive qualification stated in AEC-Q100 grad 3 from the Automotive Electronics Council, defining the critical stress test qualification for automotive integrated circuits (ICs).

• PN5120A0HN1/C1(HVQFN32) and PN5120A0HN/C1 (HVQFN40), hereafter named

as version 1.0

The data sheet describes the functionality for the industrial version and version 2.0. The differences of the version 1.0 to the version 2.0 are summarized in Section 21 industrial version has only differences within the outlined characteristics and limitations.

2. General description

The PN512 transceiver ICs support 4 different operating modes

• Reader/Writer mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme

• Reader/Writer mode supporting ISO/IEC 14443B

• Card Operation mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme

• NFCIP-1 mode

. The

Enabled in Reader/Writer mode for ISO/IEC 14443A/MIFARE, the PN512’s internal transmitter part is able to drive a reader/writer antenna designed to communicate with ISO/IEC 14443A/ MIF A RE card s and transponder s withou t a dditional active circuitry. The receiver part provides a robust and efficient implementation of a demodulation and

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decoding circuitry for signals from ISO/IEC 14443A/MIFARE compatible cards and transponders. The digital part handles the complete ISO/IEC 14443A framing and error detection (Parity & CRC).

The PN512 supports MIF ARE 1K or MIF ARE 4K emulation p roducts. The PN512 support s contactless communication using MIFARE higher transfer speeds up to 424 kbit/s in both directions.

Enabled in Reader/Writer mode for FeliCa, the PN512 transceiver IC supports the FeliCa communication scheme. The receiver part provides a robust and efficient implementation of the demodulation and decoding circuitry for FeliCa coded signals. The digital part handles the FeliCa framing and error detection like CRC. The PN512 supports contactless communication using FeliCa Higher transfer speeds up to 424 kbit/s in both directions.

The PN512 supports all layers of the ISO/IEC 14443B reader/writer communication scheme, given correct implementation of additional components, like oscillator, power supply, coil etc. and provided that standardized protocols, e.g. like ISO/IEC 14443-4 and/or ISO/IEC 14443B anticollision are correctly implemented.

In Card Operation mode, the PN512 transceiver IC is able to answer to a reader/writer command either according to the FeliCa or ISO/IEC 14443A/MIFARE card interface scheme. The PN512 generates the digital load modulated signals and in addition with an external circuit the answer can be sent back to the re ad e r/ writ er. A complete card functionality is only possible in combination with a secure IC using the S

PN512

Transm ission module

C interface.

Additionally, the PN512 transceiver IC offers the possibility to communicate directly to an NFCIP-1 device in the NFCIP-1 mode. The NFCIP-1 mode of fers dif ferent communication mode and transfer speeds up to 424 kbit/s according to the Ecma 340 a nd ISO/IEC 18092 NFCIP-1 Standard. The digital part handles th e complete NFCIP-1 framing and error detection.

Various host controller interfaces are implemented:

• 8-bit parallel interface

• SPI interface

• serial UART (similar to RS232 with voltage levels according pad voltage supply)

• I

C interface.

A purchaser of this NXP IC has to take care for appropriate third party patent licenses.

1. 8-bit parallel Interface only available in HVQFN40 package.

Product data sheet COMPANY PUBLIC

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3. Features and benefits

 Highly integrated analog circuitry to demodulate and decode responses  Buffered output drivers for connecting an antenna with the minimum number of

external components

 Integrated RF Level detector  Integrated data mode detector  Supports ISO/IEC 14443 A/MIFARE  Supports ISO/IEC 14443 B Read/Write modes  Typical operating distance in Read/Write mode up to 50 mm depending on the

antenna size and tuning

 Typical operating distance in NFCIP-1 mode up to 50 mm depending on the antenna

size and tuning and power supply

 Typical operating distance in ISO/IEC 14443A/MIFARE card or FeliCa Card Op eration

mode of about 100 mm depending on the antenna size and tuning and the external field strength

 Supports MIFARE 1K or MIFARE 4K emulation encryption in Reader/Writer mode  ISO/IEC 14443A higher transfer speed communication at 212 kbit/s and 424 kbit/s  Contactless communication according to the FeliCa scheme at 212 kbit/s and

424 kbit/s

 In te gr at ed RF int er fa ce fo r NF CIP- 1 up to 424 kbit/s

C interface

 S  Additional power supply to directly supply the smart card IC connected via S  Su pp or te d ho st inter fa ce s

 SPI up to 10 Mbit/s

C-bus interface up to 400 kBd in Fast mode, up to 3400 kBd in High-speed mode

 I  RS232 Serial UART up to 1228.8 kBd, with voltage levels dependant on pin

voltage supply

 8-bit parallel interface with and without Address Latch Enable  FIFO buffer handles 64 byte send and receive  Flexible interrupt modes  Hard reset with low power function  Power-down mode per software  Programmable timer  Internal oscillator for connection to 27.12 MHz quartz crystal  2. 5 V to 3.6 V power supply  CRC coprocessor  Programmable I/O pins  Internal self-t es t

PN512

Transm ission module

Product data sheet COMPANY PUBLIC

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4. Quick reference data

PN512

Transm ission module

Table 1. Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

DDA

DDD

DD(TVDD)

DD(PVDD)

DD(SVDD)

DDD

DDA

analog supply voltage V digital supply voltage

DD(PVDD)

SSA=VSSD=VSS(PVSS)=VSS(TVSS)

 V

TVDD supply voltage PVDD supply voltage SVDD supply voltage V power-down current V

SSA=VSSD=VSS(PVSS)=VSS(TVSS) DDA=VDDD

hard power-down; pin NRSTPD set LOW

soft power-down; RF level detector on digital supply current pin DVDD; V analog supply current pin AVDD; V

DDA

= V

DDD

= V

DD(TVDD)

;

=0V

= 0 V 1.6 - 3.6 V

= V

DD(TVDD)

=3V - 6.5 9 mA

DDD

= 3 V, CommandReg register’s

DDA

DD(PVDD)

=3V

[1][2]

2.5 - 3.6 V

[3]

1.6 - 3.6 V

[4]

--5A

[4]

--10A

-710mA

RcvOff bit = 0 pin AVDD; receiver switched off; V

DDA

=3V,

-35mA

CommandReg register’s RcvOff bit = 1

DD(PVDD)

DD(TVDD)

amb

PVDD supply current pin PVDD TVDD supply current pin TVDD; continuous wave ambient temperature HVQFN32, HVQFN40 30 +85 C

[5]

--40mA

[6][7][8]

-60100mA

lndustrial version:

amb

power-down current V

DDA=VDDD

hard power-down; pin NRSTPD set LOW

soft power-down; RF level detector on

= V

DD(TVDD)

DD(PVDD)

=3V

[4]

--15A

[4]

--30A

ambient temperature HVQFN32 40 - +90 C

[1] Supply voltages below 3 V reduce the performance in, for example, the achievable operating distance. [2] V [3] V [4] I [5] I [6] I [7] During typical circuit operation, the overall current is below 100 mA. [8] Typical value using a complementary driver configuration and an antenna matched to 40  between pins TX1 and TX2 at 13.56 MHz.

Product data sheet COMPANY PUBLIC

, V

DDA DD(PVDD)

is the total current for all supplies.

pd DD(PVDD) DD(TVDD)

and V

DDD

must always be the same or lower voltage than V

depends on the overall load at the digital pins. depends on V

must always be the same voltage.

DD(TVDD)

and the external circuit connected to pins TX1 and TX2.

DD(TVDD)

DDD

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5. Ordering information

PN512

Transm ission module

Table 2. Ordering information

Type number Package

PN5120A0HN1/C2 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;

PN5120A0HN/C2 HVQFN40 plastic therma l enhanced very thin quad flat package; no leads;

PN512AA0HN1/C2 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;

PN512AA0HN1/C2BI HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;

PN5120A0HN1/C1 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;

PN5120A0HN/C1 HVQFN40 plastic therma l enhanced very thin quad flat package; no leads;

Name Description Version

32 terminal; body 5  5  0.85 mm

40 terminals; body 6  6  0.85 mm

32 terminal; body 5  5  0.85 mm

40 terminals; body 6  6  0.85 mm

SOT617-1

SOT618-1

SOT617-1

SOT618-1

Product data sheet COMPANY PUBLIC

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HOST

ANTENNA

FIFO

BUFFER

ANALOG

INTERFACE

CONTACTLESS

UART

SERIAL UART

SPI

C-BUS

6. Block diagram

The analog interface handles the modulation and demodulation of the analog signals according to the Card Receiving mode, Reader/Writer mode and NFCIP-1 mode communication scheme.

The RF level detector detects the presence of an external RF-field delivered by the antenna to the RX pin.

The Data mode detector detects a MIFARE, FeliCa or NFCIP-1 mode in order to prepare the internal receiver to demodulate signals, which are sent to the PN512.

The communication (S transfer speeds above 424 kbit/s and digital signals to communicate to a secure IC.

The contactless UART manages the protocol requirements for the communication protocols in cooperation with the host. The FIFO buffer ensures fast and convenient data transfer to and from the host and the contactless UART and vice versa.

Various host interfaces are implemented to meet different customer requirements.

PN512

Transm ission module

C) interface provides digital signals to support communication for

Fig 1. Simplified block diagram of the PN512

Product data sheet COMPANY PUBLIC

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DVDD

NRSTPD

IRQ

MFIN MFOUT SVDD

OSCIN

OSCOUT

VMID AUX1

AUX2

RX TVSS TX1 TX2 TVDD

16 19

17 10, 14 11 13 12

DVSS

AVDD

PVSSPVDDSDA/NSS/RX EA I2C

5224 32 1

D1/ADR_5

D2/ADR_4

D3/ADR_3

D4/ADR_2

D5/ADR_1/ SCK/DTRQ

D6/ADR_0/

MOSI/MX

D7/SCL/

MISO/TX

AVSS

7 8 9

15 18

FIFO CONTROL

MIFARE CLASSIC UNIT

STATE MACHINE

COMMAND REGISTER

PROGRAMABLE TIMER

INTERRUPT CONTROL

CRC16

GENERATION AND CHECK

PARALLEL/SERIAL

CONVERTER

SERIAL DATA SWITCH

TRANSMITTER CONTROL

BIT COUNTER PARITY GENERATION AND CHECK FRAME GENERATION AND CHECK

BIT DECODING BIT ENCODING

RANDOM NUMBER

GENERATOR

ANALOG TO DIGITAL

CONVERTER

I-CHANNEL AMPLIFIER

ANALOG TEST MULTIPLEXOR

AND

DIGITAL TO

ANALOG

CONVERTER

I-CHANNEL

DEMODULATOR

Q-CHANNEL

AMPLIFIER

CLOCK

GENERATION,

FILTERING AND

DISTRIBUTION

Q-CLOCK

GENERATION

OSCILLATOR

TEMPERATURE

SENSOR

Q-CHANNEL

DEMODULATOR

AMPLITUDE

RATING

REFERENCE

VOLTAGE

64-BYTE FIFO

BUFFER

CONTROL REGISTER

BANK

SPI, UART, I2C-BUS INTERFACE CONTROL

VOLTAGE MONITOR

AND

POWER ON

DETECT

RESET

CONTROL

POWER-DOWN

CONTROL

PN512

Transm ission module

Fig 2. Detailed block diagram of the PN512

Product data sheet COMPANY PUBLIC

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PN512

Transparent top view

SIGIN

SIGOUT

AVSS

NRSTPD AUX1

PVSS AUX2

DVSS OSCIN

DVDD OSCOUT

PVDD IRQ

A1 ALE

SVDD

TVSS

TX1

TVDD

TX2

TVSS

AVDD

VMID

A0D7D6D5D4D3D2

8 17

7 18

6 19

5 20

4 21

3 22

2 23

1 24

10111213141516

32313029282726

terminal 1

index area

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PN512

AVSS

NRSTPD

SIGIN

AUX1

PVSS AUX2

DVSS OSCIN

DVDD OSCOUT

PVDD IRQ

A5 NWR

A4 NRD

A3 ALE

A2 NCS

SIGOUT

SVDD

TVSS

TX1

TVDD

TX2

TVSS

AVDD

VMID

A1A0D7D6D5D4D3D2D1

10 21

9 22

8 23

7 24

6 25

5 26

4 27

3 28

2 29

1 30

111213141516171819

403938373635343332

terminal 1

index area

Transparent top view

7. Pinning information

7.1 Pinning

PN512

Transm ission module

Fig 3. Pinning configuration HVQFN32 (SOT617-1)

Product data sheet COMPANY PUBLIC

Fig 4. Pinning configuration HVQFN40 (SOT618-1)

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PN512

Transm ission module

7.2 Pin description

Table 3. Pin description HVQFN32

Pin Symbol Type Description

1A1IAddress Line 2 PVDD PWR Pad power supply 3DVDDPWRDigital Power Supply 4 DVSS PWR Digital Ground 5 PVSS PWR Pad power supply ground 6 NRSTPD I Not Reset and Power Down: When LOW, intern al current sinks are switched off, the

7 SIGIN I Communication Interface Input: accepts a digital, serial data stream 8 SIGOUT O Communication Interface Output: delivers a serial data stream 9 SVDD PWR S2C Pad Power Supply: provides power to the S 10 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2 11 TX1 O Transmitter 1: delivers the modulated 13.56 MHz energy carrier 12 TVDD PWR Transmitter Power Supply: supplies the output stage of TX1 and TX2 13 TX2 O Transmitter 2: delivers the modulated 13.56 MHz energy carrier 14 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2 15 AVDD PWR Analog Power Supply 16 VMID PWR Internal Reference Voltage: This pin delivers the internal reference voltage. 17 RX I Receiver Input 18 AVSS PWR Analog Ground 19 AUX1 O Auxiliary Outputs: These pins are used for testing. 20 AUX2 O 21 OSCIN I Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is

22 OSCOUT O Crystal Oscillator Output: Output of the inverting amplifier of the oscillator. 23 IRQ O Interrupt Request: output to signal an interrupt event 24 ALE I Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch

25 to 31 D1 to D7 I/O 8-bit Bi-directional Data Bus.

32 A0 I Address Line

oscillator is inhibited, and the input pads are disconnected from the outside world. With a positive edge on this pin the internal reset phase starts.

C pads

also the input for an externally generated clock (f

= 27.12 MHz).

osc

when HIGH.

Remark: An 8-bit parallel interface is not available.

Remark: If the host controller selects I can be used to define the I

C address.

C as digital host controller interface, these pins

Remark: For serial interfaces this pins can be used for test signals or I/Os.

Product data sheet COMPANY PUBLIC

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PN512

Transm ission module

Table 4. Pin description HVQFN40

Pin Symbol Type Description

1 to 4 A2 to A5 I Address Line 5 PVDD PWR Pad power supply 6DVDDPWRDigital Power Supply 7 DVSS PWR Digital Ground 8 PVSS PWR Pad power supply ground 9 NRSTPD I Not Reset and Power Down: When LOW, intern al current sinks are switched off, the

oscillator is inhibited, and the input pads are disconnected from the outside world. With

a positive edge on this pin the internal reset phase starts. 10 SIGIN I Communication Interface Input: acce pts a digital, serial data stream 11 SIGOUT O Communica tion Interface Output: delivers a serial data stream

12 SVDD PWR S

C Pad Power Supply: provides power to the S2C pads

13 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2 14 TX1 O Transmitter 1: delivers the modulated 13.56 MHz energy carrier 15 TVDD PWR Transmitter Power Supply: supplies the output stage of TX1 and TX2 16 TX2 O Transmitter 2: delivers the modulated 13.56 MHz energy carrier 17 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2 18 AVDD PWR Analog Power Supply 19 VMID PWR Internal Reference Voltage: This pin delivers the internal reference voltage. 20 RX I Receiver Input 21 AVSS PWR Analog Ground 22 AUX1 O Auxiliary Outputs: These pins are used for testing. 23 AUX2 O 24 OSCIN I Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is

also the input for an externally generated clock (f

= 27.12 MHz).

osc

25 OSCOUT O Crystal Oscillator Output: Output of the inverting amplifier of the oscillator. 26 IRQ O Interrupt Request: output to signal an interrupt event 27 NWR I Not Write: strobe to write data (applied on D0 to D7) into the PN512 register 28 NRD I Not Read: strobe to read data from the PN512 register (applied on D0 to D7) 29 ALE I Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch

when HIGH. 30 NCS I Not Chip Select: selects and activates the host controller interface of the PN512 31 to 38 D0 to D7 I/O 8-bit Bi-directional Data Bus.

Remark: For serial interfaces this pins can be used for test signals or I/Os.

Remark: If the host controller selects I

C as digital host controller interface, these pins

can be used to define the I2C address. 39 to 40 A0 to A1 I Address Line

Product data sheet COMPANY PUBLIC

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BATTERY

reader/writer

contactless card

MICROCONTROLLER

PN512

ISO/IEC 14443 A CARD

(1)

(2)

001aan219

PN512

ISO/IEC 14443 A CARD

ISO/IEC 14443 A

READER

8. Functional description

The PN512 transmission module supports the Read/Write mode for ISO/IEC 14443 A/MIFARE and ISO/IEC 14443 B using various transfer speeds and modulation protocols.

PN512 transceiver IC supports the following operating modes:

• Reader/Writer mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme

• Card Operation mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme

• NFCIP-1 mode

The modes support different transfer speeds and modulation schemes. The following chapters will explain the different modes in detail.

Note: All indicated modulation indices and modes in this chapter are system parameters. This means that beside the IC settings a suitable antenna tuning is require d to achieve the optimum performance.

PN512

Transm ission module

Fig 5. PN512 Read/Write mode

8.1 ISO/IEC 14443 A/MIFARE functionality

The physical level communication is shown in Figure 6.

Fig 6. ISO/IEC 14443 A/MIFARE Read/Write mode communication diagram

The physical parameters are described in Table 4.

T able 5. Communication overview for ISO/IEC 14443 A/MIFARE reader/writer

Communication direction

Reader to card (send data from the PN512 to a card)

Signal type Transfer speed

106 kBd 212 kBd 424 kBd

reader side

100 % ASK 100 % ASK 100 % ASK

modulation bit encoding modified Miller

encoding

modified Miller encoding

bit length 128 (13.56 s) 64 (13.56 s) 32 (13.56 s)

modified Miller encoding

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001aak585

ISO/IEC 14443 A framing at 106 kBd

8-bit data 8-bit data 8-bit data

odd

parity

odd

parity

start

odd

parity

start bit is 1

ISO/IEC 14443 A framing at 212 kBd, 424 kBd and 848 kBd

8-bit data 8-bit data 8-bit data

odd

parity

odd

parity

start

even

parity

start bit is 0

burst of 32

subcarrier clocks

even parity at the

end of the frame

PN512

Transm ission module

T able 5. Communication overview for ISO/IEC 14443 A/MIFARE reader/writer

Communication direction

Card to reader (PN512 receives data from a card)

Signal type Transfer speed

106 kBd 212 kBd 424 kBd

card side modulation

subcarrier

subcarrier load modulation

13.56 MHz/16 13.56 MHz/16 13 .56 MHz/16

subcarrier load modulation

…continued

subcarrier load modulation

frequency bit encoding Manchester

BPSK BPSK

encoding

The PN512’s contactless UART and dedicated external host must manage the complete ISO/IEC 14443 A/MIFARE protocol. Figure 7

shows the data coding and framing

according to ISO/IEC 14443 A/MIFARE.

Fig 7. Data coding and framing according to ISO/IEC 14443 A

The internal CRC coprocessor calculates the CRC value based on ISO/IEC 14443 A part 3 and handles parity generation internally according to the transfer speed. Automatic parity generation can be switched off using th e ManualRCVReg register’s ParityDisable bit.

8.2 ISO/IEC 14443 B functionality

The MFRC523 reader IC fully supports international standard ISO 14443 which includes communication schemes ISO 14443 A and ISO 14443 B.

Refer to the ISO 14443 reference documents Identification cards - Contactless integrated circuit cards - Proximity cards (parts 1 to 4).

Product data sheet COMPANY PUBLIC

Remark: NXP Semiconductors does not of fer a soft ware library to enable design -in of the

ISO 14443 B protocol.

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2. PICC to PCD, > 12 % ASK loadmodulation Manchester coded, baudrate 212 to 424 kbaud

1. PCD to PICC, 8-30 % ASK Manchester coded, baudrate 212 to 424 kbaud

001aan214

PN512

FeliCa CARD

(PICC)

Felica READER

(PCD)

8.3 FeliCa reader/writer functionality

The FeliCa mode is the general reader/writer to card communication scheme according to the FeliCa specification. The following diagram describes the communication on a physical level, the communication overview describes the physical parameters.

Fig 8. FeliCa reader/writer communication diagram

Table 6. Communication overview for FeliCa reader/writer

Communication direction

PN512  card Modulation on reader side 8-30 % ASK 8-30 % ASK

card  PN512 Loadmodulation on card side > 12 % ASK > 12 % ASK

PN512

Transm ission module

FeliCa FeliCa Higher

transfer speeds

Transfer speed 212 kbit/s 424 kbit/s

bit coding Manchester Coding Manchester Coding Bitlength (64/13.56) s (32/13.56) s

bit coding Manchester coding Manchester coding

The contactless UART of PN512 and a dedicated external host controller are required to handle the complete FeliCa protocol.

8.3.1 FeliCa framing and coding

Table 7. FeliCa framing and coding

Preamble Sync Len n-Data CRC

00h 00h 00h 00h 00h 00h B2h 4Dh

To enable the FeliCa communication a 6 byte preamble (00h, 00h, 00h, 00h, 00h, 00h) and 2 bytes Sync bytes (B2h, 4Dh) are sent to synchronize the receiver.

The following Len byte indicates the length of the se nt dat a b ytes plus the LEN byte itself. The CRC calculation is done according to the FeliCa definitions with the MSB first.

To transmit data on the RF interface, the host controller has to send the Len- and databytes to the PN512's FIFO-buffer. The preamble and the sync bytes are generated by the PN512 automatically and must not be written to the FIFO by the host controller. The PN512 performs internally the CRC calculation and adds the result to the data frame.

Example for FeliCa CRC Calculation:

Table 8. Start value for the CRC Polynomial: (00h), (00h)

Preamble Sync Len 2 Data Bytes CRC

00h 00h 00h 00h 00h 00h B2h 4Dh 03h ABh CDh 90h 35h

Product data sheet COMPANY PUBLIC

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BATTERY

initiator: active target:

passive or active

MICROCONTROLLER

PN512

BATTERY

MICROCONTROLLER

PN512

8.4 NFCIP-1 mode

The NFCIP-1 communication differentiates between an active and a Passive Communication mode.

• Active Communication mode means both the initiator and the target are using their

• Passive Communication mode means that the target answers to an initiator command

• Initiator: generates RF field at 13.56 MHz and starts the NFCIP-1 communication

• Target: responds to initiator command either in a load modulation scheme in Passive

In order to fully support the NFCIP-1 standard the PN512 supports the Active and Passive Communication mode at the transfer speeds 106 kbit/s, 212 kbit/s and 42 4 kbit/s as defined in the NFCIP-1 standard.

PN512

Transm ission module

own RF field to transmit data.

in a load modulation scheme. The initiator is active in terms of generating the RF field.

Communication mode or using a self generat ed and self modulated RF field for Active Communication mode.

Fig 9. NFCIP-1 mode

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host

NFC INITIATOR

powered to

generate RF field

1. initiator starts communication at selected transfer speed

Initial command

response

2. target answers at the same transfer speed

host

NFC INITIATOR

powered for digital

processing

host

NFC TARGET

powered for

digital processing

powered to

generate RF field

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8.4.1 Active communication mode

Active communication mode means both the initiator and the target are using their own RF field to transmit data.

PN512

Transm ission module

Fig 10. Active communication mode

Table 9. Communication overview for Active communication mode

Communication direction

Initiator  Target According to Target  Initiator

106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s 1.69 Mbit/s,

3.39 Mbit/s

ISO/IEC 14443A

According to FeliCa, 8-30 % ASK Manchester Coded

digital capability to handle

this communication 100 % ASK, Modified Miller Coded

The contactless UART of PN512 and a dedicated host controller are required to handle the NFCIP-1 protocol.

Note: Transfer Speeds above 424 kbit/s are not defined in the NFCIP-1 standard. The PN512 supports these transfer speeds only with dedicated extern al circuits.

Product data sheet COMPANY PUBLIC

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host

NFC INITIATOR

powered to

generate RF field

1. initiator starts communication at selected transfer speed

2. targets answers using load modulated data at the same transfer speed

host

NFC TARGET

powered for

digital processing

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8.4.2 Passive communication mode

Passive Communication mode means that the target answers to an initiator command in a load modulation scheme. The initiator is active meaning generating the RF field.

Fig 11. Passive communication mode

Table 10. Communication overview for Passive communication mod e

Communication direction

Initiator  Target According to

Target  Initiator According to

PN512

Transm ission module

106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s 1.69 Mbit/s,

3.39 Mbit/s

ISO/IEC 14443A 100 % ASK, Modified Miller Coded

ISO/IEC 14443A subcarrier load modulation, Manchester Coded

According to FeliCa, 8-30 % ASK Manchester Coded

According to FeliCa, > 12 % ASK Manchester Coded

digital capability to handle

this communication

The contactless UART of PN512 and a dedicated host controller are required to handle the NFCIP-1 protocol.

Note: Transfer Speeds above 424 kbit/s are not defined in the NFCIP-1 standard. The PN512 supports these transfer speeds only with dedicated extern al circuits.

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8.4.3 NFCIP-1 framing and coding

The NFCIP-1 framing and coding in Active and Passive Communication mode is defined in the NFCIP-1 standard.

Table 11. Framing and coding overview

Transfer speed Framing and Coding

106 kbit/s According to the ISO/IEC 14443A/MIFARE scheme 212 kbit/s According to the FeliCa scheme 424 kbit/s According to the FeliCa scheme

8.4.4 NFCIP-1 protocol support

The NFCIP-1 protocol is not completely described in this document. For detailed explanation of the protocol refer to the NFCIP-1 standard. However the datalink layer is according to the following policy:

• Speed shall not be changed while continuum data exchange in a transaction.

• Transaction includes initialization and anticollision methods and data exchange (in

PN512

Transm ission module

continuous way, meaning no interruption by another transaction).

In order not to disturb current infrastructure based on 13.56 MHz general rules to start NFCIP-1 communication are defined in the following way.

1. Per default NFCIP-1 device is in Target mode meaning its RF field is switched off.

2. The RF level detector is active.

3. Only if application requires the NFCIP-1 device shall switch to Initiator mode.

4. Initiator shall only switch on its RF field if no external RF field is detected by RF Level detector during a time of TIDT.

5. The initiator performs initialization according to the selected mode.

8.4.5 MIFARE Card operation mode

T able 12. MIFARE Card operation mode

Communication direction

transfer speed 106 kbit/s 212 kbit/s 424 kbit/s

reader/writer  PN512

PN512  reader/ writer

Modulation on reader side

bit coding Modified Miller Modified Miller Modified Miller Bitlength (128/13.56) s (64/13.56) s (32/13.56) s Modulation on

PN512 side subcarrier

frequency bit coding Manchester coding BPSK BPSK

ISO/IEC 14443A/ MIFARE

100 % ASK 100 % ASK 100 % ASK

subcarrier load modulation

13.56 MHz/16 13.56 MHz/16 13.56 MHz/16

MIFARE Higher transfer speeds

subcarrier load modulation

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8.4.6 FeliCa Card operation mode

Table 13. FeliCa Card operation mode

Communication direction

reader/writer  PN512

PN512  reader/ writer

9. PN512 register SET

9.1 PN512 registers overview

Table 14. PN512 registers overview

Addr (hex)

Page 0: Command and Status

0 PageReg Selects the register page 1 CommandReg Starts and stops command execution 2 ComlEnReg Controls bits to enable and disable the passing of Interrupt Requests 3 DivlEnReg Controls bits to enable and disa ble the passing of Interrupt Requests 4 ComIrqReg Contains Interrupt Request bits 5 DivIrqReg Contains Interrupt Request bits 6 ErrorReg Error bits showing the error status of the last command executed 7 St a tus1Reg Cont ains st atus bits for communication 8 St a tus2Reg Cont ains st atus bits of the receiver and transmitter 9 FIFODataReg In- and output of 64 byte FIFO-buffer A FIFOLevelReg Indicates the number of bytes stored in the FIFO B WaterLevelReg Defines the level for FIFO under- and overflow warning C ControlReg Contains miscellaneous Control Registers D BitFramingReg Adjustments for bit oriented frames E CollReg Bit positi on of the first bit collision detected on the RF-interface F RFU Reserved for future use

Page 1: Command

0 PageReg Selects the register page 1 ModeReg Defines general modes for transmitting and receiving 2 TxModeReg Defines the data rate and framing during transmission 3 RxModeReg Defines the data rate and framing during receiving 4 TxControlReg Controls the logical behavior of the antenna driver pins T X1 and TX2 5 TxAutoReg Controls the setting of the antenna drivers

PN512

Transm ission module

FeliCa FeliCa Higher

transfer speeds

Transfer speed 212 kbit/s 424 kbit/s

Modulation on reader side 8-30 % ASK 8-30 % ASK bit coding Manchester Coding Manchester Coding Bitlength (64/13.56) s (32/13.56) s Load modulation on PN512

side bit coding Manchester coding Manchester coding

> 12 % ASK load modulation

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PN512

Transm ission module

Table 14. PN512 registers overview

Addr (hex)

6 TxSelReg Selects the internal sources for the antenna driver 7 RxSelReg Selects internal receiver settings 8 RxThresholdReg Selects thresholds for the bit decoder 9 DemodReg Defines demodulator settings A FelNFC1Reg Defines the length of the valid range for the receive package B FelNFC2Reg Defines the length of the valid range for the receive package C MifNFCReg Controls the communication in ISO/IEC 14443/MIFARE and NFC

D ManualRCVReg Allows manual fine tuning of the internal receiver E TypeBReg Configure th e ISO/IEC 14443 type B F SerialSpeedReg Selects the speed of the serial UART interface

Page 2: CFG

0 PageReg Selects the register page 1 CRCResultReg Shows the actual MSB and LSB values of the CRC calculation 2 3 GsNOffReg Selects the conductance of the antenna driver pins TX1 and TX2 for

4 ModWidthReg Controls the setting of the ModWidth 5 TxBitPhaseReg Adjust the TX bit phase at 106 kbit 6 RFCfgReg Configures the receiver gain and RF level 7 GsNOnReg Selects the conductance of the antenna driver pins TX1 and TX2 for

8 CWGsPReg Selects the conductance of the antenna driver pins TX1 and TX2 for

9 ModGsPReg Selects the conductance of the antenna driver pins TX1 and TX2 for

A TModeReg B C TReloadReg Describes the 16-bit timer reload value D E TCounterValReg Shows the 16-bit actual timer value F

Page 3: TestRegister

0 PageReg selects the register page 1 TestSel1Reg General test signal configuration 2 TestSel2Reg General test signal configuration and PRBS control 3 TestPinEnReg Enables pin output driver on 8-bit parallel bus (Note: For serial

4TestPin

5 TestBusReg Shows the status of the internal testbus 6 AutoTestReg Controls the digital selftest

target mode at 106 kbit

modulation, when the driver is switched off

modulation when the drivers are switched on

modulation during times of no modulation

modulation during modulation Defines settings for the internal timer

TPrescalerReg

interfaces only) Defines the values for the 8-bit parallel bus when it is used as I/O bus

ValueReg

…continued

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PN512

Transm ission module

Table 14. PN512 registers overview

Addr (hex)

7 VersionReg Shows the version 8 AnalogTestReg Controls the pins AUX1 and AUX2 9 TestDAC1Reg Defines the test value for the TestDAC1 A TestDAC2Reg Defines the test value for the TestDAC2 B TestADCReg Shows th e actual value of ADC I and Q C-F RFT Reserved for production tests

9.1.1 Register bit behavior

Depending on the functionality of a register , the access conditions to the register can vary. In principle bits with same behavior are grouped in co mmon registers. In Table 15 access conditions are described.

Table 15. Behavior of register bits and its designation

Abbreviation Behavior Description

r/w read and write These bits can be written and read by the -Controller. Since they

dy dynamic These bits can be written and read by the -Controller.

r read only These registers hold bits, which value is determined by internal

w write only Reading these registers returns always ZERO. RFU - These registers are reserved for future use.

RFT - These registers are reserved for production tests and shall not be

…continued

the

are used only for control means, there content is not influenced by internal state machines, e.g. the PageSelect-Register may be written and read by the -Controller. It will also be read by internal state machines, but never changed by them.

Nevertheless, they may also be written automatically by internal state machines, e.g. the Command-Register changes its value automatically after the execution of the actual command.

states only, e.g. the CRCReady bit can not be written from external but shows internal states.

In case of a PN512 Version version 2.0 (VersionReg = 82h) a read access to these registers returns always the value “0”. Nevertheless this is not guaranteed for future chips versions where the value is undefined. In case of a write access, it is recommended to write always the value “0”.

changed.

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9.2 Register description

9.2.1 Page 0: Command and status

9.2.1.1 PageReg

Selects the register page.

Table 16. PageReg register (address 00h); reset value: 00h, 0000000b

Access Rights

Table 17. Description of PageReg bits

Bit Symbol Description

7 UsePageSelect Set to logic 1, the value of PageSelect is used as register address A5

6 to 2 - Reserved for future use. 1 to 0 PageSelect The value of PageSelect is used only if UsePageSelect is set to

PN512

Transm ission module

7 6 5 4 3 2 1 0

UsePage Select 0 0 0 0 0 PageSelect

r/w RFU RFU RFU RFU RFU r/w r/w

and A4. The LSB-bits of the register address are defined by the address pins or the internal address latch, respectively.

Set to logic 0, the whole content of the internal address latch de fines the register address. The address pins are used as described in

Section 10.1 “

logic 1. In this case it specifies the register page (which is A5 and A4 of the register address).

Automatic microcontroller interface detection”.

9.2.1.2 CommandReg

Starts and stops command execution.

Table 18. CommandReg register (address 01h); reset value: 20h, 00100000b

Access Rights

Table 19. Description of CommandReg bits

Bit Symbol Description

7 to 6 - Reserved for future use. 5 RcvOff Set to logic 1, the analog part of the receiver is switched off. 4 PowerDown Set to logic 1, Soft Power-down mode is entered.

3 to 0 Command Activates a command according to the Command Code. Reading this

RFURFUr/w dy dydydydy

7 6 5 4 3 2 1 0

0 0 RcvOff Power Down Command

Set to logic 0, the PN512 starts the wake up procedure. During this procedure this bit still shows a 1. A 0 indicates that the PN512 is ready for operations; see Section 16.2 “

Soft power-down mode”.

Note: The bit Power Down cannot be set, when the command SoftReset has been activated.

“PN512 command overview”).

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9.2.1.3 CommIEnReg

Control bits to enable and disable the passing of interrupt requests.

Table 20. CommIEnReg register (address 02h); reset value: 80h, 10000000b

Access Rights

Table 21. Description of CommIEnReg bits

Bit Symbol Description

7 IRqInv Set to logic 1, the signal on pin IRQ is inverted with respect to bit IRq in the

6 TxIEn Allows the transmitter interrupt request (ind i cat e d by bit TxIRq) to be

5 RxIEn Allows the receiver interrupt request (indicated by bit RxIRq) to be

4 IdleIEn Allows the idle interrupt request (indicated by bit IdleIRq) to be propagated to

3 HiAlertIEn Allows the high alert interrupt request (indicated by bit HiAlertIRq) to be

2 LoAlertIEn Allows the low alert interrupt request (indicated by bit LoAlertIRq) to be

1 ErrIEn Allows the error interrupt request (indicated by bit ErrIRq) to be propagated

0 TimerIEn Allows the timer interrupt request (indicated by bit TimerIRq) to be

PN512

Transm ission module

7 6 5 4 3 2 1 0

IRqInv TxIEn RxIEn IdleIEn HiAlertIEn LoAlertIEn ErrIEn TimerIEn

r/w r/w r/w r/w r/w r/w r/w r/w

register Status1Reg. Set to logic 0, the signal on pin IRQ is equal to bit IRq. In combination with bit IRqPushPull in register DivIEnReg, the default value of 1 ensures, that the output level on pin IRQ is 3-state.

propagated to pin IRQ.

pin IRQ.

propagated to pin IRQ.

to pin IRQ.

propagated to pin IRQ.

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9.2.1.4 DivIEnReg

Control bits to enable and disable the passing of interrupt requests.

Table 22. DivIEnReg register (address 03h); reset value: 00h, 00000000b

Access Rights

Table 23. Description of DivIEnReg bi ts

Bit Symbol Description

7 IRQPushPull Set to logic 1, the pin IRQ works as standard CMOS output pad.

6 to 5 - Reserved for future use. 4 SiginActIEn Allows the SIGIN active inte rrupt request to be propagated to pin IRQ. 3 ModeIEn Allows the mode interrupt request (indicated by bit ModeIRq) to be

2 CRCIEn Allows the CRC interrupt request (indicated by bit CRCIRq) to be

1 RfOnIEn Allows the RF field on interrupt request (indicated by bit RfOnIRq) to

0 RfOffIEn Allows the RF field off interrupt request (indicated by bit RfOffIRq) to

PN512

Transm ission module

7 6 5 4 3 2 1 0

IRQPushPull 0 0 SiginActIEn ModeIEn CRCIEn RFOnIEn RFOffIEn

r/w RFU RFU r/w r/w r/w r/w r/w

Set to logic 0, the pin IRQ works as open drain output pad.

propagated to pin IRQ.

be propagated to pin IRQ.

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9.2.1.5 CommIRqReg

Contains Interrupt Request bits.

Table 24. CommIRqReg register (address 04h); rese t value: 14h, 00010100b

Access Rights

Table 25. Description of CommIRqR eg bits

All bits in the register CommIRqReg shall be cleared by software.

Bit Symbol Description

7 Set1 Set to logic 1, Set1 defines that the marked bits in the register CommIRqReg

6 TxIRq Set to logic 1 immediately after the last bit of the transmitted data was sent out. 5 RxIRq Set to logic 1 when the receiver detects the end of a valid datastream.

4 IdleIRq Set to logic 1, when a command terminates by itself e.g. when the

3 HiAlertIRq Set to logic 1, when bit HiAlert in register Status1Reg is set. In opposition to

2 LoAlertIRq Set to logic 1, when bit LoAl ert in register Status1Reg is set. In opposition to

1 ErrIRq Set to logic 1 if any error bit in the Error Register is set. 0 TimerIRq Set to logic 1 when the timer decrements the TimerValue Register to zero.

PN512

Transm ission module

7 6 5 4 3 2 1 0

Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq

wdydydy dy dy dydy

are set. Set to logic 0, Set1 defines, that the marked bits in the register CommIRqReg

are cleared.

If the bit RxNoErr in register RxModeReg is set to logic 1, bit RxIRq is only set to logic 1 when data bytes are available in the FIFO.

CommandReg changes its value from any command to the Idle Command. If an unknown command is started, the CommandReg changes its content to

the idle state and the bit IdleIRq is set. Starting the Idle Command by the -Controller does not set bit IdleIRq.

HiAlert, HiAlertIRq stores this event and can only be reset as indicated by bit Set1.

LoAlert, LoAlertIRq stores this event and can only be reset as indicated by bit Set1.

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9.2.1.6 DivIRqReg

Contains Interrupt Request bits

Table 26. DivIRqReg register (address 05h); reset value: XXh, 000X00XXb

Access Rights

Table 27. Description of DivIRqReg bits

All bits in the register DivIRqReg shall be cleared by software.

Bit Symbol Description

7 Set2 Set to logic 1, Set2 defines that the marked bits in the register

6 to 5 - Reserved for future use. 4 SiginActIRq Set to logic 1, when SIGIN is active. See Section 12.6 “

3 ModeIRq Set to logic 1, when the mode has been detected by the Data mode

2 CRCIRq Set to logic 1, when the CRC command is active and all data are

1 RFOnIRq Set to logic 1, when an external RF field is detected. 0 RFOffIRq Set to logic 1, when a present external RF field is switched off.

PN512

Transm ission module

7 6 5 4 3 2 1 0

Set2 0 0 SiginActIRq ModeIRq CRCIRq RFOnIRq RFOffIRq

wRFURFU dy dy dy dy dy

DivIRqReg are set. Set to logic 0, Set2 defines, that the marked bits in the register

DivIRqReg are cleared

S2C interface support”. This interrupt is set when either a rising or falling signal edge

is detected.

detector. Note: The Data mode detector can only be activated by the AutoColl

command and is terminated automatically having detected the Communication mode.

Note: The Data mode detector is automatically restarted after each RF Reset.

processed.

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9.2.1.7 ErrorReg

Error bit register showing the error status of the last command executed.

Table 28. ErrorReg register (address 06h); reset value: 00h, 00000000b

Access Rights

Table 29. Description of ErrorReg bits

Bit Symbol Description

7 WrErr Set to logic 1, when data is written into FIFO by the host controller

6 TempErr

5 RFErr Set to logic 1, if in Active Communication mode the counterpart does

4 BufferOvfl Set to logic 1, if the host controller or a PN512’s internal state machine

3 CollErr Set to logic 1, if a bit-collision is detected. It is cleared automatically at

2 CRCErr Set to logic 1, if bit RxCRCEn in register RxModeReg is set and the

1 ParityErr Set to logic 1, if the parity check has failed. It is cleared automatically

0 ProtocolErr Set to logic 1, if one out of the following cases occur:

PN512

Transm ission module

7 6 5 4 3 2 1 0

WrErr TempErr RFErr BufferOvfl CollErr CRCErr ParityErr ProtocolErr

rrrrrrr r

during the AutoColl command or MFAuthent command or if data is written into FIFO by the host controller during the time between sending the last bit on the RF interface and receiving the last bit on the RF interface.

[1]

Set to logic 1, if the internal temperature sensor detects overheating. In this case, the antenna drivers are switched off automatically.

not switch on the RF field in time as defined in NFCIP-1 standard. Note: RFErr is only used in Active Communication mode. The bits

RxFraming or the bits TxFraming has to be set to 01 to enable this functionality.

(e.g. receiver) tries to write data into the FIFO-bufferFIFO-buffer although the FIFO-buffer is already full.

receiver start-up phase. This bit is only valid during the bitwise anticollision at 106 kbit. During communication sch emes at 212 and 424 kbit this bit is always set to logic 1.

CRC calculation fails. It is cleared to 0 automatically at receiver start-up phase.

at receiver start-up phase. Only valid for ISO/IEC 14443A/MIFARE or NFCIP-1 communication at 106 kbit.

• Set to logic 1 if the SOF is incorrect. It is cleared automatically at

receiver start-up phase. The bit is only valid for 106 kbit in Active and Passive Communication mode.

• If bit DetectSync in register ModeReg is set to logic 1 during

FeliCa communication or active communication with transfer speeds higher than 106 kbit, the bit ProtocolErr is set to logic 1 in case of a byte length violation.

• During the AutoColl command, bit ProtocolErr is set to logic 1, if

the bit Initiator in register ControlReg is set to logic 1.

• During the MFAuthent Command, bit ProtocolErr is set to logic 1,

if the number of bytes received in one data stream is incorrect.

• Set to logic 1, if the Miller Decoder detects 2 pulses below the

minimum time according to the ISO/IEC 14443A definitions.

[1] Command execution will clear all error bits except for bit TempErr. A setting by software is impossible.

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HiAlert 64 FIFOLength–  WaterLevel=

LoAlert FIFOLength WaterLevel=

9.2.1.8 Status1Reg

Contains status bits of the CRC, Interrupt and FIFO-buffer.

Table 30. Status1Reg register (address 07h); reset value: XXh, X100X01Xb

Access Rights

Table 31. Description of Status1Reg bits

Bit Symbol Description

7 RFFreqOK Indicates if the frequency detected at the RX pin is in the range of

6 CRCOk Set to logic 1, if the CRC Result is zero. For data transmission and

5 CRCReady Set to logic 1, whe n the CRC calculation has finished. This bit is only

4 IRq This bit shows, if any interrupt source requests attention (with respect

3 TRunning Set to logic 1, if the PN512’s timer unit is running, e.g. the timer will

2 RFOn Set to logic 1, if an external RF field is detected. This bit does not store

1 HiAlert Set to logic 1, when the number of bytes stored in the FIFO-buffer

PN512

Transm ission module

7 6 5 4 3 2 1 0

RFFreqOK CRCOk CRCReady IRq TRunning RFOn HiAlert LoAlert

rrrrrrrr

13.56 MHz. Set to logic 1, if the frequency at the RX pin is in the range

12 MHz < RX pin frequency < 15 MHz. Note: The value of RFFreqOK is not defined if the external RF

frequency is in the range from 9 to 12 MHz or in the range from 15 to 19 MHz.

reception the bit CRCOk is undefined (use CRCErr in register ErrorReg). CRCOk indicates the status of the CRC co-processor, during calculation the value changes to ZERO, when the calculation is done correctly, the value changes to ONE.

valid for the CRC co-processor calculation using the command CalcCRC.

to the setting of the interrupt enable bits, see register CommIEnReg and DivIEnReg).

decrement the TCounterValReg with the next timer clock. Note: In the gated mode the bit TRunning is set to logic 1, when the

timer is enabled by the register bits. This bit is not influenced by the gated signal.

the state of the RF field.

fulfills the following equation:

Example:

FIFOLength = 60, WaterLevel = 4  HiAlert = 1 FIFOLength = 59, WaterLevel = 4  HiAlert = 0

0 LoAlert Set to logic 1, when the number of bytes stored in the FIFO-buffer

fulfills the following equation: Example:

FIFOLength = 4, WaterLevel = 4  LoAlert = 1 FIFOLength = 5, WaterLevel = 4  LoAlert = 0

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9.2.1.9 Status2Reg

Contains status bits of the Receiver, Transmitter and Data mode detector.

Table 32. Status2Reg register (address 08h); reset value: 00h, 00000000b

Access Rights

Table 33. Description of Status2Reg bits

Bit Symbol Description

7 TempSensClear Set to logic 1, this bit clears the temperature error, if the temperature

5 - Reserved for future use. 4 TargetActivated Set to logic 1 if the Select command or if the Polling command was

3 MFCrypto1On This bit indicates that the MIFARE Crypto1 unit is switched on and

2 to 0 Modem State ModemState shows the state of the transmitter and receiver state

PN512

Transm ission module

7 6 5 4 3 2 1 0

TempSensClear I

r/w r/w RFU dy dy r r r

CForceHS I2C input filter settings. Set to logic 1, the I2C input filter is set to the

CForceHS 0 TargetActivated MFCrypto1On Modem State

is below the alarm limit of 125 C.

High-speed mode independent of the I2C protocol. Set to logic 0, the I2C input filter is set to the used I2C protocol.

answered. Note: This bit can only be set during the AutoColl command in Passive Communication mode.

Note: This bit is cleared automatically by switching off the external RF field.

therefore all data communication with the card is encrypted. This bit can only be set to logic 1 by a successful execution of the

MFAuthent Command. This bit is only valid in Reader/Writer mode for MIFARE cards. This bit shall be cleared by software.

machines.

Value Description

000 IDLE 001 Wait for StartSend in register BitFramingReg 010 TxWait: Wait until RF field is present, if the bit TxWaitRF is

set to logic 1. The minimum time for TxWait is defined by the

TxWaitReg register. 011 Sending 100 RxWait: Wait until RF field is present, if the bit RxWaitRF is

set to logic 1. The minimum time for RxWait is defined by the

RxWaitReg register. 101 Wait for data 110 Receiving

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9.2.1.10 FIFODataReg

In- and output of 64 byte FIFO-buffer.

Table 34. FIFODataReg register (address 09h); reset value: XXh, XXXXXXXXb

Access Rights

Table 35. Description of FIFODataReg bits

Bit Symbol Description

7 to 0 FIFOData Data input and output port for th e internal 64 byte FIFO-buffer. The

9.2.1.11 FIFOLevelReg

Indicates the number of bytes stored in the FIFO.

Table 36. FIFOLevelReg register (address 0Ah); reset value: 00h, 000 00000b

Access Rights

PN512

Transm ission module

7 6 5 4 3 2 1 0

FIFOData

dy dy dy dy dy dy dy dy

FIFO-buffer acts as parallel in/parallel out converter for all serial data stream in- and outputs.

7 6 5 4 3 2 1 0

FlushBuffer FIFOLevel

w rrrrrrr

Table 37. Description of FIFOLevelReg bits

Bit Symbol Description

7 FlushBuffer Set to logic 1, this bit clears the internal FIFO-buffer’s read- and

write-pointer and the bit BufferOvfl in the register ErrReg immediately. Reading this bit will always return 0.

6 to 0 FIFOLevel Indicates the number of bytes stored in the FIFO-buffer. Writing to the

FIFODataReg increments, reading decrements the FIFOLevel.

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9.2.1.12 WaterLevelReg

Defines the level for FIFO under- and overflow warning.

Table 38. WaterLevelReg register (address 0Bh); reset value: 08h, 00001000b

Access Rights

Table 39. Description of WaterLevelReg bits

Bit Symbol Description

7 to 6 - Reserved for future use. 5 to 0 WaterLevel This register defines a warning level to indicate a FIFO-buffer over- or

PN512

Transm ission module

7 6 5 4 3 2 1 0

0 0 WaterLevel

RFU RFU r/w r/w r/w r/w r/w r/w

underflow: The bit HiAlert in Status1Reg is set to logic 1, if the remaining number

of bytes in the FIFO-buffer space is equal or less than the defined number of WaterLevel bytes.

The bit LoAlert in Status1Reg is set to logic 1, if equal or less than WaterLevel bytes are in the FIFO.

Note: For the calculation of HiAlert and LoAlert see Table 30

9.2.1.13 ControlReg

Miscellaneous control bits.

Table 40. ControlReg register (address 0C h); reset value: 00h, 00000000b

TStopNow TStartNow WrNFCIDtoFIFO Initiator 0 RxLastBits

Access Rights

Table 41. Description of Control Reg bits

Bit Symbol Description

7 TStopNow Set to logic 1, the timer stops immediately.

6 TStartNow Set to logic 1 starts the timer immediately.

5 WrNFCIDtoFIFO Set to logic 1, the internal stored NFCID (10 bytes) is copied into the

4 In itiator Set to logic 1, the PN512 acts as initiator, otherwise it acts as target 3 - Reserved for future use. 2 to 0 RxLastBits Shows the number of valid bits in the last received byte. If zero, the

7 6 5 4 3 2 1 0

w w dy r/wRFUrrr

Reading this bit will always return 0.

FIFO. Afterwards the bit is cleared automatically

whole byte is valid.

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9.2.1.14 BitFramingReg

Adjustments for bit oriented frames.

Table 42. BitFramingReg register (address 0Dh); reset value: 00h, 00000000b

Access Rights

Table 43. Description of BitFramingReg bits

Bit Symbol Description

7 StartSend Set to logic 1, the transmission of data starts.

6 to 4 RxAlign Used for reception of bit oriented frames: RxAlign defines the bit position

3 - Reserved for future use. 2 to 0 TxLastBits Used for transmission of bit oriented frames: TxLastBits defines the

PN512

Transm ission module

7 6 5 4 3 2 1 0

StartSend RxAlign 0 TxLastBits

w r/w r/w r/w RFU r/w r/w r/w

This bit is only valid in combination with the Transceive command.

for the first bit received to be stored in the FIFO. Further received bits are stored at the following bit positions.

Example: RxAlign = 0: the LSB of the received bit is stored at bit 0, the second

received bit is stored at bit position 1.

RxAlign = 1: the LSB of the received bit is stored at bit 1, the second

received bit is stored at bit position 2.

RxAlign = 7: the LSB of the received bit is stored at bit 7, the second

received bit is stored in the following byte at bit position 0.

This bit shall only be used for bitwise anticollision at 106 kbit/s in Passive Communication mode. In all other modes it shall be set to logic 0.

number of bits of the last byte that shall be transmitted. A 000 indicates that all bits of the last byte shall be transmitted.

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9.2.1.15 CollReg

Defines the first bit collision detected on the RF interface.

Table 44. CollReg register (address 0Eh); reset value: XXh, 101XXXXXb

Access Rights

Table 45. Description of CollReg bits

Bit Symbol Description

7 ValuesAfterColl If this bit is set to logic 0, all receiving bits will be cleared after a

6 - Reserved for future use. 5 CollPosNotValid Set to logic 1, if no Collision is detected or the Position of the

4 to 0 CollPos These bits show the bit position of the first detected collision in a

PN512

Transm ission module

7 6 5 4 3 2 1 0

Values

AfterColl

r/wRFUrrrrrr

0CollPos

CollPos

NotValid

collision. This bit shall only be used during bitwise anticollision at 106 kbit, otherwise it shall be set to logic 1.

Collision is out of the range of bits CollPos. This bit shall only be interpreted in Passive Communication mode at 106 kbit or ISO/IEC 14443A/MIFARE Reader/Writer mode.

received frame, only data bits are interpreted. Example:

00h indicates a bit collision in the 32 01h indicates a bit collision in the 1 08h indicates a bit collision in the 8

bit

These bits shall only be interpreted in Passive Communication mode at 106 kbit or ISO/IEC 14443A/MIFARE Reader/Writer mode if bit CollPosNotValid is set to logic 0.

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9.2.2 Page 1: Communication

9.2.2.1 PageReg

Selects the register page.

Table 46. PageReg register (address 10h); reset value: 00h, 00000000b

Access Rights

Table 47. Description of PageReg bits

Bit Symbol Description

7 UsePage Select Set to logic 1, the value of PageSelect is used as register address A5

6 to 2 - Reserved for future use. 1 to 0 PageSelect The value of PageSelect is used only, if UsePageSelect is set to

PN512

Transm ission module

7 6 5 4 3 2 1 0

UsePage Select00000PageSelect

r/w RFU RFU RFU RFU RFU r/w r/w

and A4. The LSB-bits of the register address are defined by the address pins or the internal address latch, respectively.

Set to logic 0, the whole content of the internal address latch defines the register address. The address pins are used as described in

Section 10.1 “

logic 1. In this case it specifies the register page (which is A5 and A4 of the register address).

Automatic microcontroller interface detection”.

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9.2.2.2 ModeReg

Defines general mode settings for transmitting and receiving.

Table 48. ModeReg register (address 11h); reset value: 3Bh, 00111011b

Access Rights

Table 49. Description of ModeReg bits

Bit Symbol Description

7 MSBFirst Set to logic 1, the CRC co-processor calculates the CRC with MSB

6 Detect Sync If set to logic 1, the contactless UART waits for the value F0h before

5 TxWaitRF Set to logic 1 the transmitter in reader/writer or initiator mode for

4 RxWaitRF Set to logic 1, the counter for RxWait starts only if an external RF field

3 PolSigin PolSigin defines the polarity of the SIGIN pin. Set to logic 1, the

2 ModeDetOff Set to logic 1, the internal mode detector is switch ed off.

1 to 0 CRCPreset Defines the preset value for the CRC co-processor for the command

PN512

Transm ission module

7 6 5 4 3 2 1 0

MSBFirst Detect Sync TxWaitRF RxWaitRF PolSigin ModeDetOff CRCPreset

r/w r/w r/w r/w r/w r/w r/w r/w

first and the CRCResultMSB and the CRCResultLSB in the CRCResultReg register are bit reversed.

Note: During RF communication this bit is ignored.

the receiver is activated and F0h is added as a Sync-byte for transmission.

This bit is only valid for 106 kbit during NFCIP-1 data exchange protocol.

In all other modes it shall be set to logic 0.

NFCIP-1 can only be started, if an RF field is generated.

is detected in Target mode for NFCIP-1 or in Card Communication mode.

polarity of SIGIN pin is active high. Set to logic 0 the polarity of SIGIN pin is active low.

Note: The internal envelope signal is coded active low. Note: Changing this bit will generate a SiginActIRq event.

Note: The mode detector is only active during the AutoColl command.

CalCRC. Note: During any communication, the preset values is selected

automatically according to the definition in the bits RxMode and TxMode.

Value Description

00 0000 01 6363 10 A671 11 FFFF

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9.2.2.3 TxModeReg

Defines the data rate and framing during transmission.

Table 50. TxModeReg register (a ddress 12h); reset value: 00h, 00000000b

Access Rights

Table 51. Description of TxModeReg bits

Bit Symbol Description

7 TxCRCEn Set to logic 1, this bit enables the CRC generation during data

6 to 4 TxSpeed Defines the bit rate while data transmission.

3 InvMod Set to logic 1, the modulation for transmitting data is inverted. 2 TxMix Set to logic 1, the sign al at pin SIGIN is mixed with the internal coder

1 to 0 TxFraming Defines the framing used for data transmission.

PN512

Transm ission module

7 6 5 4 3 2 1 0

TxCRCEn TxSpeed InvMod TxMix TxFraming

r/w dy dy dy r/w r/w dy dy

transmission. Note: This bit shall only be set to logic 0 at 106 kbit.

Value Description

000 106 kbit 001 212 kbit 010 424 kbit 011 848 kbit 100 1696 kbit 101 3392 kbit 110 Reserved 111 Reserved Note: The bit coding for transfer speeds above 424 kbit is equivalent to

the bit coding of Active Communication mode 424 kbit (Ecma 340).

(see Section 12.6 “

Value Description

00 ISO/IEC 14443A/MIFARE and Passive Communication mode

106 kbit 01 Active Communication mode 10 FeliCa and Passive communication mode 212 and 424 kbit 1 1 ISO/IEC 14443B

S2C interface support”).

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9.2.2.4 RxModeReg

Defines the data rate and framing during reception.

Table 52. RxModeReg register (address 13h); reset value: 00h, 00000000b

Access Rights

Table 53. Description of RxModeReg bits

Bit Symbol Description

7 RxCRCEn Set to logic 1, this bit enables the CRC calculation during reception.

6 to 4 RxSpeed Defi nes the bit rate while data transmission.

3 RxNoErr If set to logic 1 a not valid received data stream (less than 4 bits

2 RxMultiple Set to logic 0, the receiver is deactivated after receiving a data frame.

PN512

Transm ission module

7 6 5 4 3 2 1 0

RxCRCEn RxSpeed RxNoErr RxMultiple RxFraming

r/w dydydyr/w r/w dy dy

Note: This bit shall only be set to logic 0 at 106 kbit.

The PN512’s analog part handles only transfer speeds up to 424 kbit internally, the digital UART handles the higher transfer speeds as well.

Value Description

000 106 kbit 001 212 kbit 010 424 kbit 011 848 kbit 100 1696 kbit 101 3392 kbit 110 Reserved 111 Reserved Note: The bit coding for transfer speeds above 424 kbit is equivalent to

the bit coding of Active Communication mode 424 kbit (Ecma 340).

received) will be ignored. The receiver will remain active. For ISO/IEC14443B also RxSOFReq logic 1 is required to ignore a non

valid datastream.

Set to logic 1, it is possible to receive more than one data frame. Having set this bit, the receive and transceive commands will not terminate automatically. In this case the multiple receiving can only be deactivated by writing any command (except the Receive command) to the CommandReg register or by clearing the bit by the host controller.

At the end of a received data stream an error byte is added to the FIFO. The error byte is a copy of the ErrorReg register.

The behaviour for version 1.0 is described in Section 21 “

on page 106.

Errata sheet”

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NXP Semiconductors

Table 53. Description of RxModeReg bits

Bit Symbol Description

1 to 0 RxFraming Defines the expected framing for data reception.

9.2.2.5 TxControlReg

Controls the logical behavior of the antenna driver pins Tx1 and Tx2.

Table 54. TxControlReg register (address 14h); reset value: 80h, 10000000b

Access Rights

PN512

Transm ission module

Value Description

00 ISO/IEC 14443A/MIFARE and Passive Communication

mode 106 kbit 01 Active Communication mode 10 FeliCa and Passive Communication mode 212 and 424 kbit 11 ISO/IEC 14443B

7 6 5 4 3 2 1 0

InvTx2RFOnInvTx1RFOnInvTx2RF

Off

r/w r/w r/w r/w r/w w r/w r/w

InvTx1RF

Off

Tx2CW CheckRF Tx2RFEnTx1RF

Table 55. Description of TxCont rolReg bits

Bit Symbol Description

7 InvTx2RFOn Set to logic 1, the output signal at pin TX2 will be inverted, if driver TX2

is enabled.

6 InvTx1RFOn Set to logic 1, the output signal at pin TX1 will be inverted, if driver TX1

is enabled.

5 InvTx2RFOff Set to logic 1, the output signal at pin TX2 will be inverted, if driver TX2

is disabled.

4 InvTx1RFOff Set to logic 1, the output signal at pin TX1 will be inverted, if driver TX1

is disabled.

3 Tx2CW Set to logic 1, the output signal on pin TX2 will deliver continuously the

un-modulated 13.56 MHz energy carrier. Set to logic 0, Tx2CW is enabled to modulate the 13.56 MHz energy

carrier.

2 CheckRF Set to logic 1, Tx2RFEn and Tx1RFEn can not be set if an external RF

field is detected. Only valid when using in combination with bit Tx2RFEn or Tx1RFEn

1 Tx2RFEn Set to logic 1, the output signal on pin TX2 will deliver the 13.56 MHz

energy carrier modulated by the transmission data.

0 Tx1RFEn Set to logic 1, the output signal on pin TX1 will deliver the 13.56 MHz

energy carrier modulated by the transmission data.

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9.2.2.6 TxAutoReg

Controls the settings of the antenna driver.

T able 56. TxAutoReg register (address 15h); reset value: 00h, 00000000b

Access Rights

Table 57. Description of TxAutoReg bits

Bit Symbol Description

7 AutoRFOFF Set to logic 1, all active antenna drivers are switched off after the last

6 Force100ASK Set to logic 1, Force100ASK forces a 100% ASK modulation

5 AutoWakeUp Set to logic 1, the PN512 in soft Power-down mode will be started by

4 - Reserved for future use. 3 CAOn Set to logic 1, the collision avoidance is activated and internally the

2 InitialRFOn Set to logic 1, the initial RF collision avoidance is performed and the bit

1 Tx2RFAutoEn Set to logic 1, the driver Tx2 is switched on after the external RF field

0 Tx1RFAutoEn Set to logic 1, the driver Tx1 is switched on after the external RF field

PN512

Transm ission module

7 6 5 4 3 2 1 0

AutoRF

OFF

r/w r/w r/w RFU r/w r/w r/w r/w

Force100

ASK

Auto

WakeUp

0 CAOn InitialRFOnTx2RFAut

oEn

data bit has been transmitted as defined in the NFCIP-1.

independent of the setting in register ModGsPReg.

the RF level detector.

value n is set in accordance to the NFCIP-1 Standard.

InitialRFOn is cleared automatically, if the RF is switched on. Note: The driver, which should be switched on, has to be enabled by

bit Tx2RFAutoEn or bit Tx1RFAutoEn.

is switched off according to the time TADT. If the bits InitialRFOn and Tx2RFAutoEn are set to logic 1, T x2 is switched on if no external RF field is detected during the time TIDT.

Note: The times T ADT and TIDT are defined in the NFC IP-1 standard (ISO/IEC 18092).

is switched off according to the time TADT. If the bit InitialRFOn and Tx1RFAutoEn are set to logic 1, T x1 is switched on if no external RF field is detected during the time TIDT.

Note: The times T ADT and TIDT are defined in the NFC IP-1 standard (ISO/IEC 18092).

Tx1RFAuto

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9.2.2.7 TxSelReg

Selects the sources for the analog part.

T able 58. TxSelReg register (address 16h); reset value: 10h, 00010000b

Access Rights

Table 59. Description of TxSelReg bits

Bit Symbol Description

7 to 6 - Reserved for future use. 5 to 4 DriverSel Selects the input of driver Tx1 and Tx2.

PN512

Transm ission module

7 6 5 4 3 2 1 0

0 0 DriverSel SigOutSel

RFU RFU r/w r/w r/w r/w r/w r/w

Value Description

00 Tristate

Note: In soft power down the drivers are only in Tristate mode

if DriverSel is set to Tristate mode. 01 Modulation signal (envelope) from the internal coder 10 Modulation signal (envelope) from SIGIN 11 HIGH

Note: The HIGH level depends on the setting of InvTx1RFOn/

InvTx1RFOff and InvTx2RFOn/InvTx2RFOff.

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PN512

Transm ission module

Table 59. Description of TxSelReg bits

Bit Symbol Description

3 to 0 SigOutSel Selects the input for the SIGOUT Pin.

Value Description

0000 Tristate 0001 Low 0010 High 0011 TestBus signal as defined by bit TestBusBitSel in register

0100 Modulation signal (envelope) from the internal coder 0101 Serial data stream to be transmitted 01 10 Output signal of the receiver circuit (card modulation signal

0111 Serial data stream received.

1000-1011 FeliCa Sam modulation

1100-1111 MIFARE Sam modulation

…continued

TestSel1Reg.

regenerated and delayed). This signal is used as data output

signal for SAM interface connection using 3 lines.

Note: To have a valid signal the PN512 has to be set to the

receiving mode by either the Transceive or Receive

command. The bit RxMultiple can be used to keep the PN512

in receiving mode.

Note: Do not use this setting in MIFARE mode. Manchester

coding as data collisions will not be transmitted on the

SIGOUT line.

Note: Do not use this setting in MIFARE mode. Miller coding

parameters as the bit length can vary.

1000 RX* 1001 TX 1010 Demodulator comparator output 1011 RFU

Note: * To have a valid signal the PN512 has to be set to the

receiving mode by either the Transceive or Receive

command. The bit RxMultiple can be used to keep the PN512

in receiving mode.

1100 RX* with RF carrier 1101 TX with RF carrier 1 110 RX with RF carrier un-filtered 1 111 RX envelope un-filtered

Note: *To have a valid signal the PN512 has to be set to the

receiving mode by either the Transceive or Receive

command. The bit RxMultiple can be used to keep the PN512

in receiving mode.

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9.2.2.8 RxSelReg

Selects internal receiver settings.

Table 60. RxSelReg register (address 17h); reset value: 84h, 10000100b

Access Rights

Table 61. Description of RxSelReg bits

Bit Symbol Description

7 to 6 UartSel Selects the input of the contactless UART

5 to 0 RxWait After data transmission, the activation of the receiver is delayed for

PN512

Transm ission module

7 6 5 4 3 2 1 0

UartSel RxWait

r/w r/w r/w r/w r/w r/w r/w r/w

Value Description

00 Constant Low 01 Envelope signal at SIGIN 10 Modulation signal from the internal analog part 1 1 Modulation signal from SIGIN pin. Only valid for transfer

speeds above 424 kbit

RxWait bit-clocks. During this ‘frame guard time’ any signal at pin RX is ignored. This parameter is ignored by the Receive command. All other commands (e.g. Transceive, Autocoll, MFAuthent) use this parameter. Depending on the mode of the PN512, the counter starts different. In Passive Communication mode the counter starts with the last modulation pulse of the transmitted data stream. In Active Communication mode the counter starts immediately after the external RF field is switched on.

9.2.2.9 RxThresholdReg

Selects thresholds for the bit decoder.

Table 62. RxThresholdReg register (address 18h); rese t value: 84h , 10000100b

7 6 5 4 3 2 1 0

MinLevel 0 CollLevel

Access Rights

Table 63. Description of RxThresholdReg bits

Bit Symbol Description

7 to 4 MinLevel Defines the minimum signal strength at the decoder input that shall be

3 - Reserved for future use. 2 to 0 CollLevel Defines the minimum signal strength at the decoder input that has to be

Product data sheet COMPANY PUBLIC

r/w r/w r/w r/w RFU r/w r/w r/w

accepted. If the signal strength is below this level, it is not evaluated.

reached by the weaker half-bit of the Manchester-coded signal to generate a bit-collision relatively to the amplitude of the stronger half-bit.

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9.2.2.10 DemodReg

Defines demodulator settings.

T able 64. DemodReg register (address 19h); reset value: 4Dh, 01001101b

Access Rights

Table 65. Description of DemodReg bits

Bit Symbol Description

7 to 6 AddIQ Defines the use of I and Q channel during reception

5 FixIQ If set to logic 1 and the bits of AddIQ are set to X0, the reception is fixed to

PN512

Transm ission module

7 6 5 4 3 2 1 0

AddIQ FixIQ TPrescal

Even

r/w r/w r/w r/w r/w r/w r/w r/w

Note: FixIQ has to be set to logic 0 to enable the following settings.

Value Description

00 Select the stronger channel 01 Select the stronger and freeze the selected during communication 10 combines the I and Q channel 11 Reserved

I channel. If set to logic 1 and the bits of AddIQ are set to X1, the reception is fixed to

Q channel.

TauRcv TauSync

NOTE: If SIGIN/SIGOUT is used as S2C interface FixIQ set to 1 and AddIQ set to X0 is rewired.

4 TPrescalE

ven

If set to logic 0 the following formula is used to calculate fTimer of the prescaler:

= 13.56 MHz / (2 * TPreScaler + 1).

Timer

If set to logic 1 the following formula is used to calculate fTimer of the prescaler:

fTimer = 13.56 MHz / (2 * TPreScaler + 2). (Default TPrescalEven is logic 0) The behaviour for the version 1.0 is described in Section 21 “

sheet” on page 106.

3 to 2 TauRcv Changes the time constant of the internal during data reception.

Note: If set to 00, the PLL is frozen during data reception.

1 to 0 TauSync Changes the time constant of the internal PLL during burst.

Errata

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9.2.2.11 FelNFC1Reg

Defines the length of the FeliCa Sync bytes and the minimum length of the received packet.

Table 66. FelNFC1Reg register (address 1Ah); reset value: 00h, 00000000b

Access Rights

Table 67. Description of FelNFC1Reg bits

Bit Symbol Description

7 to 6 FelSyncLen Defines the length of the Sync bytes.

5 to 0 DataLenMin These bits define the minimum length of the accepted packet length:

PN512

Transm ission module

7 6 5 4 3 2 1 0

FelSyncLen DataLenMin

r/w r/w r/w r/w r/w r/w r/w r/w

Value Sync- bytes in hex

00 B2 4D 01 00 B2 4D 10 00 00 B2 4D 11 00 00 00 B2 4D

DataLenMin * 4  data packet length This parameter is ignored at 106 kbit if the bit DetectSync in register

ModeReg is set to logic 0. If a received data packet is shorter than the defined DataLenMin value, the data packet will be ignored.

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9.2.2.12 FelNFC2Reg

Defines the maximum length of the received packet.

Table 68. FelNFC2Reg register (address1Bh); reset value: 00h, 00000000b

Access Rights

Table 69. Description of FelNFC2Reg bits

Bit Symbol Description

7 WaitForSelected Set to logic 1, the AutoColl command is only terminated

6 ShortTimeSlot Defines the time slot length for Passive Communication mode at

5 to 0 DataLenMax These bits define the maximum length of the accepted packet

PN512

Transm ission module

7 6 5 4 3 2 1 0

WaitForSelected ShortTimeSlot DataLenMax

r/w r/w r/w r/w r/w r/w r/w r/w

automatically when:

1. A valid command has been received after performing a valid Select procedure according ISO/IEC 14443A.

2. A valid command has been received after performing a valid Polling procedure according to the FeliCa specification.

Note: If this bit is set, no active communication is possible. Note: Setting this bit reduces the host controller interaction in case

of a communication to another device in the same RF field during Passive Communication mode.

424 kbit. Set to logic 1 a short time slot is used (half of the timeslot at 212 kbit). Set to logic 0 a long timeslot is used (equal to the timeslot for 212 kbit).

length: DataLenMax * 4  data packet length Note: If set to logic 0 the maximum data length is 256 bytes. This parameter is ignored at 106 kbit if the bit DetectSync in

register ModeReg is set to logic 0. If a received packet is larger than the defined DataLenMax value, the packet will be ignored.

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9.2.2.13 MifNFCReg

Defines ISO/IEC 14443A/MIFARE/NFC specific settings in target or Card Operating mode.

Table 70. MifNFCReg register (address 1Ch); reset value: 62h, 01100010b

Access Rights

Table 71. Description of MifNFCReg bits

Bit Symbol Description

7 to 5 SensMiller These bits define the sensitivity of the Miller decoder. 4 to 3 TauMiller These bits define the time constant of the Miller decoder. 2 MFHalted Set to logic 1, this bit indicates that the PN512 is set to HALT mode in

1 to 0 TxWait These bits define the additional response time for the target at 106 kbit

PN512

Transm ission module

7 6 5 4 3 2 1 0

SensMiller TauMiller MFHalted TxWait

r/w r/w r/w r/w r/w r/w r/w r/w

Card Operation mode at 106 kbit. This bit is either set by the host controller or by the internal state machine and indicates that only the code 52h is accepted as a request command. This bit is cleared automatically by a RF reset.

in Passive Communication mode and during the AutoColl command. Per default 7 bits are added to the value of the register bit.

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NXP Semiconductors

9.2.2.14 ManualRCVReg

Allows manual fine tuning of the internal receiver.

Remark: For standard applications it is not recommende d to change this registe r settings.

Table 72. ManualRCVReg register (address 1Dh); reset value: 00h, 00000000b

Access Rights

Table 73. Description of ManualRCVReg bits

Bit Symbol Description

7 - Reserved for future use. 6FastFilt

5 Delay MF_SO If this bit is set to logic 1, the Signal at SIGOUT-pin is delayed, so that

4 Parity Disable If this bit is set to logic 1, the ge neration of the Parity bit for

3 LargeBWPLL Set to logic 1, the bandwidth of the internal PLL used for clock

2 ManualHPCF Set to logic 0, the HPCF bits are ignored and the HPCF settings are

1 to 0 HPFC Selects the High Pass Corner Frequency (HPCF) of the filter in the

PN512

Transm ission module

7 6 5 4 3 2 1 0

0FastFilt

MF_SO

RFU r/w r/w r/w r/w r/w r/w r/w

MF_SO

Delay

MF_SO

Parity

Disable

LargeBW

PLL

Manual

HPCF

HPFC

If this bit is set to logic 1, the internal filter for the Miller-Delay Circuit is set to Fast mode.

Note: This bit should only set to logic 1, if Millerpulses of less than 400 ns Pulse length are expected. At 106 kBaud the typical value is 3us.

in SAM mode the Signal at SIGIN must be 128/fc faster compared to the ISO/IEC 14443A, to reach the ISO/IEC 14443A restrictions on the RF-Field.

Note: This delay shall only be activated for setting bits SigOutSel to (1110b) or (1111b) in register TxSelReg.

transmission and the Parity-Check for receiving is switched off. The received Parity bit is handled like a data bit.

recovery is extended.

adapted automatically to the receiving mode. Set to logic 1, values of HPCF are valid.

internal receiver chain

00 For signals with frequency spectrum down to 106 kHz. 01 For signals with frequency spectrum down to 212 kHz. 10 For signals with frequency spectrum down to 424 kHz. 11 For signals with frequency spectrum down to 848 kHz

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9.2.2.15 TypeBReg

T able 74. TypeBReg register (address 1Eh); reset value: 00h, 00000000b

Access Rights

Table 75. Description of TypeBReg bits

Bit Symbol Description

7 RxSOFReq If this bit is set to logic 1, the SOF is required. A datastream starting

6 RxEOFReq If this bit is set to logic 1, the EOF is required. A datastream ending

5 - Reserved for future use. 4 EOFSOFWidth If this bit is set to logic 1 and EOFSOFAdjust bit is logic 0, the SOF

3 NoTxSOF If this bit is set to logic 1, the generation of the SOF is suppressed. 2 NoTxEOF If this bit is set to logic 1, the generation of the EOF is suppressed. 1 to 0 TxEGT These bits define the length of the EGT.

PN512

Transm ission module

7 6 5 4 3 2 1 0

RxSOF

Req

r/w r/w RFU r/w r/w r/w r/w r/w

RxEOF

Req

0EOFSO

NoTxSOF NoTxEOF TxEGT

FWidth

without SOF is ignored. If this bit is cleared, a datastream with and without SOF is accepted.

The SOF will be removed and not written into the FIFO.

without EOF will generate a Protocol-Error. If this bit is cleared, a datastream with and without EOF is accepted. The EOF will be removed and not written into the FIFO.

For the behaviour in version 1.0, see Section 21 “

Errata sheet” on

page 106.

and EOF will have the maximum length defined in ISO/IEC 14443B. If this bit is cleared and EOFSOFAdjust bit is logic 0, the SOF and

EOF will have the minimum length defined in ISO/IEC 14443B. If this bit is set to 1 and the EOFSOFadjust bit is logic 1 will result in

SOF low = (11etu  8 cycles) /fc SOF high = (2 etu + 8 cycles)/fc EOF low = (11 etu  8 cycles)/fc If this bit is set to 0 and the EOFSOFAdjust bit is logic 1 will result in

an incorrect system behavior in respect to ISO specification. For the behaviour in version 1.0, see Section 21 “

Errata sheet” on

page 106.

Value Description

00 0 bit 01 1 bit 10 2 bits 11 3 bits

9.2.2.16 SerialSpeedReg

Selects the speed of the serial UART interface.

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NXP Semiconductors

Table 76. SerialSpeedReg register (address 1Fh); reset value: EBh, 11101011b

Access Rights

Table 77. Description of SerialSpeedReg bits

Bit Symbol Description

7 to 5 BR_T0 Factor BR_T0 to adjust the transfer speed, for description see Section

3 to 0 BR_T1 Factor BR_T1 to adjust the transfer speed, for description see Section

PN512

Transm ission module

7 6 5 4 3 2 1 0

BR_T0 BR_T1

r/w r/w r/w r/w r/w r/w r/w r/w

10.3.2 “Selectable UART transfer speeds”.

Product data sheet COMPANY PUBLIC

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NXP Semiconductors

9.2.3 Page 2: Configuration

9.2.3.1 PageReg

Selects the register page.

Table 78. PageReg register (address 20h); reset value: 00h, 00000000b

Access Rights r/w RFU RFU RFU RFU RFU r/w r/w

Table 79. Description of PageReg bits

Bit Symbol Description

7 UsePageSelect Set to logic 1, the value of PageSelect is used as register address A5

6 to 2 - Reserved for fu ture use. 1 to 0 PageSelect The value of PageSelect is used only if UsePageSelect is set to

PN512

Transm ission module

7 6 5 4 3 2 1 0

UsePageSelect 0 0 0 0 0 PageSelect

and A4. The LSB-bits of the register address are defined by the address pins or the internal address latch, respectively.

Set to logic 0, the whole content of the internal address latch defines the register address. The address pins are used as described in

Section 10.1 “Automatic microcontroller interface detection”.

logic 1. In this case, it specifies the register page (which is A5 and A4of the register address).

9.2.3.2 CRCResultReg

Shows the actual MSB and LSB values of the CRC calculation. Note: The CRC is split into two 8-bit register. Note: Setting the bit MSBFirst in ModeReg register reverses the bit order , the byte or der is

not changed.

Table 80. CRCResultReg register (address 21h); reset value: FFh, 11111111b

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Table 81. Description of CRCResultReg bits

Bit Symbol Description

7 to 0 CRCResultMSB This register shows the actual value of the most significant byte of

Table 82. CRCResultReg register (address 22h); reset value: FFh, 11111111b

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Table 83. Description of CRCResultReg bits

Bit Symbol Description

7 to 0 CRCResultLSB This register shows the actual value of the least significan t byte of

7 6 5 4 3 2 1 0

CRCResultMSB

the CRCResultReg register. It is valid only if bit CRCReady in register Status1Reg is set to logic 1.

7 6 5 4 3 2 1 0

CRCResultLSB

the CRCResult register. It is valid only if bit CRCReady in register Status1Reg is set to logic 1.

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9.2.3.3 GsNOffReg

Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 wh en the driver is switched off.

Table 84. GsNOffReg register (address 23h); rese t value: 88h, 10001000b

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Table 85. Description of GsNOffReg bits

Bit Symbol Description

7 to 4 CWGsNOff The value of this register defines the conductance of the output

3 to 0 ModGsNOff The value of this register defines the conductance of the output

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7 6 5 4 3 2 1 0

CWGsNOff ModGsNOff

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N-driver during times of no modulation. Note: The conductance value is binary weighted. Note: During soft Power-down mode the highest bit is forced to 1. Note: The value of the register is only used if the driver is switched

off. Otherwise the bit value CWGsNOn of register GsNOnReg is used.

Note: This value is used for LoadModulation.

N-driver for the time of modulation. This may be used to regulate the modulation index.

Note: The conductance value is binary weighted. Note: During soft Power-down mode the highest bit is forced to 1. Note: The value of the register is only used if the driver is switched

off. Otherwise the bit value ModGsNOn of register GsNOnReg is used

Note: This value is used for LoadModulation.

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9.2.3.4 ModWidthReg

Controls the modulation width settings.

Table 86. ModWidthReg register (address 24h); reset value: 26h, 00100110b

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Table 87. Description of ModWidthReg bits

Bit Symbol Description

7 to 0 ModWidth These bits define the width of the Miller modulation as initiator in Active

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7 6 5 4 3 2 1 0

ModWidth

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and Passive Communication mode as multiples of the carrier frequency (ModWidth + 1/fc). The maximum value is half the bit period.

Acting as a target in Passive Communication mode at 106 kbit or in Card Operating mode for ISO/IEC 14443A/MIFARE these bits are used to change the duty cycle of the subcarrier frequency.

The resulting number of carrier periods are calculated according to the following formulas:

LOW value: #clocksLOW = (ModWidth modulo 8) + 1. HIGH value: #clocksHIGH = 16-#clocksLOW.

9.2.3.5 TxBitPhaseReg

Adjust the bitphase at 106 kbit during transmission.

T able 88. TxBitPhaseReg register (address 25h); reset value: 87h, 10000111b

RcvClkChange TxBitPhase

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Table 89. Description of TxBitPhaseReg bits

Bit Symbol Description

7 RcvClkChange Set to logic 1, the demodulator’s clock is derived by the external RF

6 to 0 TxBitPhase These bits are representing the number of carrier frequency clock

7 6 5 4 3 2 1 0

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field.

cycles, which are added to the waiting period before transmitting data in all communication modes. TXBitPhase is used to adjust the TX bit synchronization during passive NFCIP-1 communication mode at 106 kbit and in ISO/IEC 14443A/MIFARE card mode.

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9.2.3.6 RFCfgReg

Configures the receiver gain and RF level detector sensitivity.

Table 90. RFCfgReg register (address 26h); reset value: 48h, 01001000b

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Table 91. Description of RFCfgReg bits

Bit Symbol Description

7 RFLevelAmp Set to logic 1, this bit activates the RF level detectors’ amplifier. 6 to 4 RxGain This register defines the receivers signal voltage gain factor:

3 to 0 RFLevel Defines the sensitivity of the RF level detector, for description see

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7 6 5 4 3 2 1 0

RFLevelAmp RxGain RFLevel

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Value Description

000 18 dB 001 23 dB 010 18 dB 011 23 dB 100 33 dB 101 38 dB 110 43 dB 111 48 dB

Section 12.3 “

RF level detector”.

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9.2.3.7 GsNOnReg

Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 wh en the driver is switched on.

Table 92. GsNOnReg register (address 27h); reset value: 88h, 10001000b

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Table 93. Description of GsNOnReg bits

Bit Symbol Description

7 to 4 CWGsNOn The value of this register defines the conductance of the output

3 to 0 ModGsNOn The value of this register defines the conductance of the output

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7 6 5 4 3 2 1 0

CWGsNOn ModGsNOn

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N-driver during times of no modulation. This may be used to regulate the output power and subsequently current consumption and operating distance.

Note: The conductance value is binary weighted. Note: During soft Power-down mode the highest bit is forced to 1. Note: This value is only used if the driver TX1 or TX2 are switched on.

Otherwise the value of the bits CWGsNOff of register GsNOffReg is used.

N-driver for the time of modulation. This may be used to regulate the modulation index.

Note: The conductance value is binary weighted. Note: During soft Power-down mode the highest bit is forced to 1. Note: This value is only used if the driver TX1 or Tx2 are switched on.

Otherwise the value of the bits ModsNOff of register GsNOffReg is used.

9.2.3.8 CWGsPReg

Defines the conductance of the P-driver during times of no modulation

Table 94. CWGsPReg register (address 28h); reset value: 20h, 00100000b

7 6 5 4 3 2 1 0

00 CWGsP

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Table 95. Description of CWGsPReg bits

Bit Symbol Description

7 to 6 - Reserved for future use. 5 to 0 CWGsP The value of this register defines the conductance of the output

Product data sheet COMPANY PUBLIC

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P-driver. This may be used to regulate the output power and subsequently current consumption and operating distance.

Note: The conductance value is binary weighted. Note: During soft Power-down mode the highest bit is forced to 1.

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9.2.3.9 ModGsPReg

Defines the driver P-output conductance during modulation.

Table 96. ModGsPReg register (address 29h); reset value: 20h, 00100000 b

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Table 97. Description of ModGsPReg bits

Bit Symbol Description

7 to 6 - Reserved for future use. 5 to 0 ModGsP

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7 6 5 4 3 2 1 0

00 ModGsP

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[1]

The value of this register defines the conductance of the output P-driver for the time of modulation. This may be used to regulate the modulation index.

Note: The conductance value is binary weighted. Note: During soft Power-down mode the highest bit is forced to 1.

[1] If Force100ASK is set to logic 1, the value of ModGsP has no effect.

9.2.3.10 TMode Register, TPrescaler Register

Defines settings for the timer. Note: The Prescaler value is split into two 8-bit registers

Table 98. TModeReg register (address 2Ah); reset value: 00h, 00000 000b

7 6 5 4 3 2 1 0

TAuto TGated TAutoRestart TPrescaler_Hi

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Table 99. Description of TModeReg bits

Bit Symbol Description

7 TAuto Set to logic 1, the timer starts automatically at the end of the transmission

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in all communication modes at all speeds or when bit InitialRFOn is set to logic 1 and the RF field is switched on.

In mode MIFARE and ISO14443-B 106kbit/s the timer stops after the 5th bit (1 startbit, 4 databits) if the bit RxMultiple in the register RxModeReg is not set. In all other modes, the timer stops after the 4th bit if the bit RxMultiple the register RxModeReg is not set.

If RxMultiple is set to logic 1, the timer never stops. In this case the timer can be stopped by setting the bit TStopNow in register ControlReg to 1. Set to logic 0 indicates, that the timer is not influ enced by the protocol.

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Table 99. Description of TModeReg bits …continued

Bit Symbol Description

6 to 5 TGated The internal timer is running in gated mode.

4 TAutoRestart Set to logic 1, the timer automa tically restart its count-down from

3 to 0 TPrescaler_Hi Defines higher 4 bits for TPrescaler.

PN512

Transm ission module

Note: In the gated mode, the bit TRunning is 1 when the timer is enabled by the register bits. This bit does not influence the gating signal.

Value Description

00 Non gated mode 01 Gated by SIGIN 10 Gated by AUX1 11 Gated by A3

TReloadValue, instead of counting down to zero. Set to logic 0 the timer decrements to ZERO and the bit TimerIRq is set

to logic 1.

The following formula is used to calculate f Demot Reg is set to logic 0:

= 13.56 MHz/(2*TPreScaler+1).

Timer

Where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo] (TPrescaler value on 12 bits) (Default TPrescalEven is logic 0)

The following formula is used to calculate fTimer if TPrescalEven bit in Demot Reg is set to logic 1:

= 13.56 MHz/(2*TPreScaler+2).

Timer

For detailed description see Section 15 “Timer unit”. Fo r the behavio ur within version 1.0, see Section 21 “Errata sheet” on page 106.

if TPrescalEven bit in

Timer

Table 100. TPrescalerReg register (address 2Bh); re set value: 00h, 00000000b

7 6 5 4 3 2 1 0

TPrescaler_Lo

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Rights

Table 101. Description of TPrescalerReg bits

Bit Symbol Description

7 to 0 TPrescaler_Lo Defines lower 8 bits for TPrescaler.

The following formula is used to calculate f

if TPrescalEven bit in

Timer

Demot Reg is set to logic 0:

= 13.56 MHz/(2*TPreScaler+1).

Timer

Where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo] ( TPrescaler value on 12 bits)

The following formula is used to calculate fTimer if TPrescalEven bit in Demot Reg is set to logic 1:

= 13.56 MHz/(2*TPreScaler+2).

Timer

Where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo] ( TPrescaler value on 12 bits)

For detailed description see Section 15 “

Timer unit”.

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9.2.3.11 TReloadReg

Describes the 16-bit long timer reload value. Note: The Reload value is split into two 8-bit registers.

Table 102. TReloadReg (Higher bits) register (address 2Ch); reset value: 00h, 00000000b

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Table 103. Description of the higher TReloadReg bits

Bit Symbol Description

7 to 0 TReloadVal_Hi Defines the higher 8 bits for the TReloadReg.

Table 104. TReloadReg (Lower bits) register (address 2Dh); reset value: 00h, 00000000b

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7 6 5 4 3 2 1 0

TReloadVal_Hi

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With a start event the timer loads the TReloadVal. Changing this register affects the timer only at the next start event.

7 6 5 4 3 2 1 0

TReloadVal_Lo

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Table 105. Description of lower TReloadReg bits

Bit Symbol Description

7 to 0 TReloadVal_Lo Defines the lower 8 bits for the TReloadReg.

With a start event the timer loads the TReloadVal. Changing this register affects the timer only at the next start event.

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9.2.3.12 TCounterValReg

Contains the current value of the timer. Note: The Counter value is split into two 8-bit register.

Table 106. TCounterValReg (Higher bits) register (address 2Eh); reset value: XXh,

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Table 107. Description of the higher TCounterValReg bits

Bit Symbol Description

7 to 0 TCounterVal_Hi Current value of the timer, higher 8 bits.

Table 108. TCounterValReg (Lower bits) register (address 2Fh); reset value: XXh,

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Transm ission module

XXXXXXXXb

7 6 5 4 3 2 1 0

TCounterVal_Hi

rrrrrrrr

XXXXXXXXb

7 6 5 4 3 2 1 0

TCounterVal_Lo

rrrrrrrr

Table 109. Description of lower TCounterValReg bits

Bit Symbol Description

7 to 0 TCounterVal_Lo Current value of the timer, lower 8 bits.

9.2.4 Page 3: Test

9.2.4.1 PageReg

Selects the register page.

Table 110. PageReg register (address 30h); reset value: 00h, 00000000b

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7 6 5 4 3 2 1 0

UsePageSelect 0 0 0 0 0 PageSelect

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Table 111. Description of PageReg bits

Bit Symbol Description

7 UsePageSelect Set to logic 1, the value of PageSelect is used as register address

6 to 2 - Reserved for future use. 1 to 0 PageSelect The value of PageSelect is used only if UsePageSelect is set to

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Transm ission module

A5 and A4. The LSB-bits of the register address are defined by the address pins or the internal address latch, respectively.

Set to logic 0, the whole content of the internal address latch defines the register address. The address pins are used as described in

Section 10.1 “

logic 1. In this case, it specifies the register page (which is A5 and A4 of the register address).

Automatic microcontroller interface detection”.

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9.2.4.2 TestSel1Reg

General test signal configuration.

Table 112. TestSel1Reg register (address 31h); reset value: 00h, 00000000b

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Table 113. Description of TestSel1Reg bits

Bit Symbol Description

7 to 6 - Reserved for future use. 5 to 4 SAMClockSel Defines the source fo r the 13.56 MHz SAM clock

3 SAMClkD1 Set to logic 1, the SAM clock is delivered to D1.

2 to 0 TstBusBitSel Select the TestBus bit from the testbus to be propagated to SIGOUT.

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7 6 5 4 3 2 1 0

- - SAMClockSel SAMClkD1 TstBusBitSel

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Value Description

00 GND- Sam Clock switched off 01 clock derived by the internal oscillator 10 internal UART clock 1 1 clock derived by the RF field

Note: Only possible if the 8bit parallel interface is not used.

9.2.4.3 TestSel2Reg

General test signal configuration and PRBS control

Table 114. TestSel2Reg register (address 32h); reset value: 00h, 00000000b

TstBusFlip PRBS9 PRBS15 TestBusSel

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Table 115. Description of TestSel2Reg bits

Bit Symbol Description

7 TstBusFlip If set to logic 1, the te stbus is mapped to the parallel port by the

6 PRBS9 Starts and enables the PRBS9 sequence according ITU-TO150.

5 PRBS15 Starts and enables the PRBS15 sequence according ITU-TO150.

4 to 0 TestBusSel Selects the testbus. See Section 20 “

7 6 5 4 3 2 1 0

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following order: D4, D3, D2, D6, D5, D0, D1. See Section 20 “

Testsignals”.

Note: All relevant registers to transmit data have to be configured before entering PRBS9 mode.

Note: The data transmission of the defined sequence is started by the send command.

Note: All relevant registers to transmit data have to be configured before entering PRBS15 mode.

Note: The data transmission of the defined sequence is started by the send command.

Testsignals”

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9.2.4.4 TestPinEnReg

Enables the pin output driver on the 8-bit parallel bus.

Table 116. TestPinEnReg register (address 33h); reset value: 80h, 10000000b

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Table 117. Description of TestPinEnReg bits

Bit Symbol Description

7 RS232LineEn Set to logic 0, the lines MX and DTRQ for the serial UART are

6 to 0 TestPinEn Enables the pin output driver on the 8-bit parallel interface.

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RS232LineEn TestPinEn

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disabled.

Example:

Setting bit 0 to 1 enables D0

Setting bit 5 to 1 enables D5 Note: Only valid if one of serial interfaces is used. If the SPI interface is used only D0 to D4 can be used. If the serial

UART interface is used and RS232LineEn is set to logic 1 only D0 to D4 can be used.

9.2.4.5 TestPinValueReg

Defines the values for the 7-bit parallel port when it is used as I/O.

Table 118. TestPinValueReg register (address 34h); reset value: 00h, 00000000b

7 6 5 4 3 2 1 0

UseIO TestPinValue

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Table 119. Description of TestPinValueReg bits

Bit Symbol Description

7 UseIO Set to logic 1, this bit enables the I/O functionality for the 7-bit parallel

6 to 0 T estPinValue Defines the value of the 7-bit parallel port, when it is used as I/O. Each

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port in case one of the serial interfaces is used. The input/output behavior is defined by TestPinEn in register TestPinEnReg. The value for the output behavior is defined in the bits TestPinVal.

Note: If SAMClkD1 is set to logic 1, D1 can not be used as I/O.

output has to be enabled by the TestPinEn bits in register TestPinEnReg.

Note: Reading the register indicates the actual status of the pins D6 D0 if UseIO is set to logic 1. If UseIO is set to logic 0, the value of the register TestPinValueReg is read back.

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9.2.4.6 TestBusReg

Shows the status of the internal testbus.

Table 120. TestBusReg register (address 35h); reset value: XXh, XXXXXXXXb

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Table 121. Description of TestBusReg bits

Bit Symbol Description

7 to 0 TestBus Shows the status of the internal testbus. The testbus is selected by the

9.2.4.7 AutoTestReg

Controls the digital selftest.

Table 122. AutoTestReg register (address 36h); reset value: 40h, 01000000b

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7 6 5 4 3 2 1 0

TestBus

7 6 5 4 3 2 1 0

0AmpRcvEOFSO

- SelfTest

FAdjust

Testsignals”.

Table 123. Description of bits

Bit Symbol Description

7 - Reserved for production tests. 6 AmpRcv If set to logic 1, the internal signal processing in the receiver chain is

performed non-linear. This increases the operating distance in communication modes at 106 kbit.

Note: Due to the non linearity the effect of the bits MinLevel and CollLevel in the register RxThreshholdReg are as well non linear.

5 EOFSOFAdjust If set to logic 0 and the EOFSOFwidth is set to 1 will result in the

Maximum length of SOF and EOF according to ISO/IEC14443B If set to logic 0 and the EOFSOFwidth is set to 0 will result in the

Minimum length of SOF and EOF according to ISO/IEC14443B If this bit is set to 1 and the EOFSOFwidth bit is logic 1 will result in

SOF low = (11 etu  8 cycles)/fc SOF high = (2 etu + 8 cycles)/fc EOF low = (11 etu  8 cycles)/fc For the behaviour in version 1.0, see Section 21 “

Errata sheet” on

page 106.

4 - Reserved for future use. 3 to 0 SelfTest Enables the digital self test. The selftest can be started by the selftest

command in the command register. The selftest is enabled by 1001.

Note: For default operation the selftest has to be disabled by 0000.

9.2.4.8 VersionReg

Shows the version.

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Table 124. VersionReg register (address 37h); reset value: XXh, XXXXXXXXb

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Table 125. Description of VersionReg bits

Bit Symbol Description

7 to 0 Version 80h indicates PN512 version 1.0, differences to version 2.0 are

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Transm ission module

7 6 5 4 3 2 1 0

Version

described within Section 21 “ 82h indicates PN512 version 2.0, which covers also the industrial

version.

Errata sheet” on page 106.

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9.2.4.9 AnalogTestReg

Controls the pins AUX1 and AUX2

Table 126. AnalogTestReg register (address 38h); reset value: 00h, 00000000b

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7 6 5 4 3 2 1 0

AnalogSelAux1 AnalogSelAux2

Table 127. Description of AnalogTestReg bits

Bit Symbol Description

7 to 4 3to 0

AnalogSelAux1 AnalogSelAux2

Controls the AUX pin. Note: All test signals are described in Section 20 “Testsignals”.

Value Description

0000 Tristate 0001 Output of TestDAC1 (AUX1), output of TESTDAC2 (AUX2)

Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.

0010 Testsignal Corr1

Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.

0011 Testsignal Corr2

Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.

0100 Testsignal MinLevel

Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.

0101 Testsignal ADC channel I

Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.

0110 Testsignal ADC channel Q

Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.

0111 Testsignal ADC channel I combined with Q

Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.

1000 Testsignal for production test

Note: Current output. The use of 1 k pull-down resistor on AUX is recommended. 1001 SAM clock (13.56 MHz) 1010 HIGH 1011 LOW 1100 TxActive

At 106 kbit: HIGH during Startbit, Data bit, Parity and CRC. At 212 and 424 kbit: High

during Preamble, Sync, Data and CRC. 1101 RxActive

At 106 kbit: High during databit, Parity and CRC.

At 212 and 424 kbit: High during data and CRC. 1 110 Subcarrier detected

106 kbit: not applicable

212 and 424 kbit: High during last part of Preamble, Sync data and CRC 1111 TestBus-Bit as defined by the TstBusBitSel in register TestSel1Reg.

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9.2.4.10 TestDAC1Reg

Defines the testvalues for TestDAC1.

Table 128. TestDAC1Reg register (address 39h); reset value: XXh, 00XXXXXXb

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Table 129. Description of TestDAC1Reg bits

Bit Symbol Description

7 - Reserved for production tests. 6 - Reserved for future use. 5 to 0 TestDAC1 Defines the testvalue for TestDAC1. The output of the DAC1 can be

9.2.4.11 TestDAC2Reg

Defines the testvalue for TestDAC2.

Table 130. TestDAC2Reg register (address 3Ah); reset value: XXh, 00XXXXXXb

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7 6 5 4 3 2 1 0

0 0 TestDAC1

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switched to AUX1 by setting AnalogSelAux1 to 0001 in register AnalogTestReg.

7 6 5 4 3 2 1 0

0 0 TestDAC2

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Table 131. Description ofTestDAC2Reg bits

Bit Symbol Description

7 to 6 - Reserved for future use. 5 to 0 TestDAC2 Defines the testvalue for TestDAC2. The output of the DAC2 can be

9.2.4.12 TestADCReg

Shows the actual value of ADC I and Q channel.

Table 132. TestADCReg register (address 3Bh); reset value: XXh, XXXXXXXXb

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Table 133. Description of TestADCReg bits

Bit Symbol Description

7 to 4 ADC_I Shows the actual value of ADC I channel. 3 to 0 ADC_Q Shows the actual value of ADC Q channel.

switched to AUX2 by setting AnalogSelAux2 to 0001 in register AnalogTestReg.

7 6 5 4 3 2 1 0

ADC_I ADC_Q

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9.2.4.13 RFTReg

Table 134. RFTReg registe r (address 3Ch); reset va lue: FFh, 11111111b

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Table 135. Description of RFTReg bits

Bit Symbol Description

7 to 0 - Reserved for production tests.

Table 136. RFTReg register (address 3Dh, 3Fh); reset value: 00h, 00000000b

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7 6 5 4 3 2 1 0

11111111

RFT RFT RFT RFT RFT RFT RFT RFT

7 6 5 4 3 2 1 0

00000000

RFT RFT RFT RFT RFT RFT RFT RFT

Table 137. Description of RFTReg bits

Bit Symbol Description

7 to 0 - Reserved for production tests.

T able 138. RFTReg register (address 3Eh); reset value: 03h, 00000011b

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Table 139. Description of RFTReg bits

Bit Symbol Description

7 to 0 - Reserved for production tests.

10. Digital interfaces

10.1 Automatic microcontroller interface detection

The PN512 supports direct interfacing of hosts using SPI, I2C-bus or serial UART interfaces. The PN512 resets its interface and checks the current host interface type automatically after performing a power-on or hard reset. The PN512 identifies the host interface by sensing the logic levels on the control pins afte r the reset phase. This is done using a combination of fixed pin connections. Table 140 configurations.

7 6 5 4 3 2 1 0

00000011

RFT RFT RFT RFT RFT RFT RFT RFT

shows the different connection

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NXP Semiconductors

Table 140. Connection protocol for detecting different interface types

Pin Interface type

SDA RX NSS SDA

C001

I EA01EA D7 TX MISO SCL D6 MX MOSI ADR_0 D5 DTRQ SCK ADR_1 D4 - - ADR_2 D3 - - ADR_3 D2 - - ADR_4 D1 - - ADR_5

Table 141. Connection scheme for detecting the different interface types

PN512 Parallel Interface Type Serial Interface Types

Pin Dedicated

ALE 1 ALE 1 AS RX NSS SDA A5 A4 A3 A2 A1A1 1 A1 1 001 A0A0 1 A0 0 01EA NRD NWR NCS D7 D6 D5 D4 D3 D2 D1 D0

Remark: Overview on the pin behavior

Pin behavior Input

PN512

Transm ission module

UART (input) SPI (output) I2C-bus (I/O)

Separated Read/Write Strobe Common Read/Write Strobe

Multiplexed

Address Bus

[1]

A5 0 A5 0 000

[1]

A4 0 A4 0 000

[2]

A3 0 A3 0 000

[2]

A2 1 A2 1 000

[2]

NRD NRD NDS NDS 1 1 1

[2]

NWR NWR RD/NWR RD/NWR 1 1 1

[2]

NCS NCS NCS NCS NCS NCS NCS

Address Bus

D7 D7 D7 D7 TX MISO SCL D6 D6 D6 D6 MX MOSI ADR_0 D5 AD5 D5 AD5 DTRQ SCK ADR_1 D4 AD4 D4 AD4 --ADR_2 D3 AD3 D3 AD3 --ADR_3 D2 AD2 D2 AD2 --ADR_4 D1 AD1 D1 AD1 --ADR_5 D0 AD0 D0 AD0 --ADR_6

Dedicated

Address Bus

Multiplexed

Address Bus

Output In/Out

UART SPI

I2C

[1] only available in HVQFN 40. [2] not available in HVQFN 32.

Product data sheet COMPANY PUBLIC

Rev. 4.2 — 28 August 2012

111342 66 of 132

NXP Semiconductors

001aan220

PN512

SCK

MOSI

MISO

NSS

10.2 Serial Peripheral Interface

A serial peripheral interface (SPI compatible) is supported to enable high-speed communication to the host. The interface can handle dat a speeds up to 10 Mbit/s. When communicating with a host, the PN512 acts as a slave, receiving data from the external host for register settings, sending and receiving data relevant for RF interface communication.

An interface compatible with SPI enables high-speed serial communication between the PN512 and a microcontroller. The implemented interface is in accordance with the SPI standard.

PN512

Transm ission module

The timing specification is given in Section 26.1 on page 113

Fig 12. SPI connection to host

The PN512 acts as a slave during SPI communication. The SPI clock signal SCK must be generated by the master. Data communication from the master to the slave uses the MOSI line. The MISO line is used to send data from the PN512 to the master.

Data bytes on both MOSI and MISO lines are sent with the MSB first. Dat a on both M OSI and MISO lines must be stable on the rising edge of the clock and can be changed on the falling edge. Data is provided by the PN512 on the falling clock edge and is stable during the rising clock edge.

10.2.1 SPI read data

Reading data using SPI requires the byte order shown in Table 142 to be used. It is possible to read out up to n-data bytes.

The first byte sent defines both the mode and the address.

Table 142. MOSI and MISO byte order

Line Byte 0 Byte 1 Byte 2 To Byte n Byte n + 1

MOSI address 0 address 1 address 2 ... address n 00 MISO X

[1] X = Do not care.

[1]

data 0 data 1 ... data n  1data n

Remark: The MSB must be sent first.

10.2.2 SPI write data

To write data to the PN512 using SPI requires the byte order shown in Table 143. It is

Product data sheet COMPANY PUBLIC

possible to write up to n data bytes by only sending one address byte.

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NXP Semiconductors

001aan221

PN512

DTRQ

The first send byte defines both the mode and the address byte.

Table 143. MOSI and MISO byte order

Line Byte 0 Byte 1 Byte 2 To Byte n Byte n + 1

MOSI address 0 data 0 data 1 ... data n  1data n MISO X

[1] X = Do not care.

Remark: The MSB must be sent first.

10.2.3 SPI address byte

The address byte has to meet the following format. The MSB of the first byte defines the mode used. To read data from the PN512 the MSB is

set to logic 1. To write dat a to the PN512 the MSB must be set to logic 0. Bits 6 to 1 define the address and the LSB is set to logic 0.

T able 144. Address byte 0 register; address MOSI

7 (MSB) 6 5 4 3 2 1 0 (LSB)

1 = read 0 = write

PN512

Transm ission module

[1]

address 0

[1]

... X

[1]

10.3 UART interface

10.3.1 Connection to a host

Fig 13. UART connection to microcontrollers

Remark: Signals DTRQ and MX can be disabled by clearing TestPinEnReg register’s

RS232LineEn bit.

10.3.2 Selectable UART transfer speeds

The internal UART interface is compatible with an RS232 serial interface. The default transfer speed is 9.6 kBd. To change the transfer speed, the host controller

must write a value for the new transfer speed to the SerialSpeedReg register. Bits BR_T0[2:0] and BR_T1[4:0] define the facto rs for se ttin g th e tra n sfe r sp ee d in th e SerialSpeed Reg register.

The BR_T0[2:0] and BR_T1[4:0] settings are described in Table 9

Product data sheet COMPANY PUBLIC

transfer speeds and the relevant register settings are given in Table 10

Rev. 4.2 — 28 August 2012

111342 68 of 132

. Examples of different

NXP Semiconductors

transfer speed

27.12 10



BR_T0 1+

------------------------------- -

transfer speed

27.12 10



BR_T1 33+

BR_T0 1–

---------------------------------- -







Table 145. BR_T0 and BR_T1 settings

BR_Tn Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

BR_T0 factor11248163264 BR_T1 range 1 to 32 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64

Table 146. Selectable UART transfer speeds

Transfer speed (kBd) SerialSpeedReg value Transfer speed accuracy (%)

7.2 250 FAh 0.25

9.6 235 EBh 0.32

14.4 218 DAh 0.25

19.2 203 CBh 0.32

38.4 171 ABh 0.32

57.6 154 9Ah 0.25 1 15.2 122 7Ah 0.25 128 116 74h 0.06

230.4 90 5Ah 0.25

460.8 58 3Ah 0.25

921.6 28 1Ch 1.45

1228.8 21 15h 0.32

PN512

Transm ission module

[1]

Decimal Hexadecimal

[1] The resulting transfer speed error is less than 1.5 % for all described transfer speeds.

The selectable transfer speeds shown in Table 10 are calculated according to the following equations:

If BR_T0[2:0] = 0:

If BR_T0[2:0] > 0:

Remark: Transfer speeds above 1228.8 kBd are not supported.

10.3.3 UART framing

Table 147. UART framing

Bit Length Value

Start 1-bit 0 Data 8 bits data Stop 1-bit 1

(1)

(2)

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NXP Semiconductors

001aak588

ADDRESS

DTRQ

A0 A1 A2 A3 A4 A5 (1) SO

SA D0 D1 D2 D3 D4 D5 D6 D7 SO

DATA

R/W

Remark: The LSB for data and address bytes must be sent first. No parity bit is used during transmission.

PN512

Transm ission module

Read data: To read data using the UART interface, the flow shown in Table 148

used. The first byte sent defines both the mod e and th e ad dr e ss.

Table 148. Read data byte order

Pin Byte 0 Byte 1

RX (pin 24) address TX (pin 31) - data 0

must be

(1) Reserved.

Fig 14. UART read data timing diagram

Write data: To write data to the PN512 using the UART interface, the structure shown in

Table 149

must be used.

The first byte sent defines both the mode and the address.

Table 149. Write data byte order

Pin Byte 0 Byte 1

RX (pin 24) address 0 data 0 TX (pin 31) - address 0

Product data sheet COMPANY PUBLIC

Rev. 4.2 — 28 August 2012

111342 70 of 132

Product data sheet

001aak589

ADDRESS

DTRQ

A0 A1 A2 A3 A4 A5

(1)

SO SA D0 D1 D2 D3 D4 D5 D6 D7 SO

SA A0 A1 A2 A3 A4 A5

(1)

DATA

ADDRESS

R/W

COMPANY PUBLIC

Rev. 4.2 — 28 August 2012

111342 71 of 132

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

NXP Semiconductors

(1) Reserved.

Fig 15. UART write data timing diagram

Remark: The data byte can be sent directly after the address byte on pin RX. Address byte: The address byte has to meet the following format:

Transmission module

PN512

NXP Semiconductors

001aan222

PN512

SDA SCL

I2C EA ADR_[5:0]

PULL-UP

NETWORK

CONFIGURATION

WIRING

PULL-UP

NETWORK

MICROCONTROLLER

The MSB of the first byte sets the mode used. To read data from the PN512, the MSB is set to logic 1. To write data to the PN512 the MSB is set to logic 0. Bit 6 is reserved for future use, and bits 5 to 0 define the address; see Table 150

T able 150. Address byte 0 register; address MOSI

7 (MSB) 6 5 4 3 2 1 0 (LSB)

1 = read 0 = write

10.4 I2C Bus Interface

PN512

Transm ission module

reserved address

An I2C-bus (Inter-IC) interface is supported to enable a low-cost, low pin count serial bus interface to the host. The I NXP Semiconductors’ I

C-bus interface is implemented according to

C-bus interface specification, rev. 2.1, January 2000. The

interface can only act in Slave mode. Therefore the PN512 does not implement clock generation or access arbitration.

Fig 16. I2C-bus interface

The PN512 can act either as a slave receiver or slave transmitter in Standard mode, Fast mode and High-speed mode.

SDA is a bidirectional line connected to a positive supply voltage using a current sour ce or a pull-up resistor . Both SDA and SCL lines ar e set HIGH when data is not transmitted. The

PN512 has a 3-state output stage to perform the wired-AND functio n. Data on the I

C-bus can be transferred at data rates of up to 10 0 kBd in Standard mode, up to 400 kBd in Fast mode or up to 3.4 Mbit/s in High-speed mode.

Product data sheet COMPANY PUBLIC

If the I as defined in the I

C-bus interface is selected, spike suppression is activated on lines SCL and SDA

C-bus interface specification.

See Table 170 on page 114

Rev. 4.2 — 28 August 2012

for timing requirements.

111342 72 of 132

NXP Semiconductors

mbc621

data line

stable;

data valid

change

of data

allowed

SDA

SCL

mbc622

SDA

SCL

STOP condition

SDA

SCL

START condition

10.4.1 Data validity

Data on the SDA line must be stable during the HIGH clock period. The HIGH or LOW state of the data line must only change when the clock signal on SCL is LOW.

Fig 17. Bit transfer on the I2C-bus

10.4.2 START and STOP conditions

To manage the data transfer on the I2C-bus, unique START (S) and STOP (P) conditions are defined.

PN512

Transm ission module

• A START condition is defined with a HIGH-to-LOW transition on the SDA line while

SCL is HIGH.

• A STOP condition is defined with a LOW-to-HIGH transition on the SDA line while

SCL is HIGH.

C-bus master always generates the START and STOP conditions. The bus is busy

The I after the START condition. The bus is free again a certain time after the STOP condition.

The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. The START (S) and repeated START (Sr) conditions are functionally identical. Therefore, S is used as a generic term to represent both the START (S) and repeated START (Sr ) conditions.

Fig 18. START and STOP conditions

10.4.3 Byte format

Each byte must be followed by an acknowledge bit. Data is transfer red with the M SB first; see Figure 21 but must meet the read/write cycle format.

Product data sheet COMPANY PUBLIC

. The number of transmitted bytes during one data transfer is unrestricted

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NXP Semiconductors

mbc602

START

condition

9821

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output by receiver

SCL from

master

msc608

Sr or

SDA

SCL

STOP or

repeated START

condition

START or

repeated START

condition

1 2 3 - 8 9

ACK

7812

MSB

acknowledgement

signal from slave

byte complete,

interrupt within slave

clock line held LOW while interrupts are serviced

acknowledgement

signal from receiver

10.4.4 Acknowledge

An acknowledge must be sent at the end of one data byte. The acknowledge-related clock pulse is generated by the master . Th e transmitter of dat a, either master or slave, releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver pulls down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse.

The master can then generate either a STOP (P) condition to stop the transfer or a repeated START (Sr) condition to start a new transfer.

A master-receiver indicates the end of data to the slave-transmitter by not generating an acknowledge on the last byte that was clocked out by the slave. The slave-transmitter releases the data line to allow the master to gener ate a ST OP (P) or repeated START (Sr) condition.

PN512

Transm ission module

Fig 19. Acknowledge on the I2C-bus

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111342 74 of 132

Fig 20. Data transfer on the I2C-bus

Product data sheet COMPANY PUBLIC

NXP Semiconductors

001aak591

slave address

bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W

MSB LSB

10.4.5 7-Bit addressing

During the I2C-bus address procedure, the first byte after the START condition is used to determine which slave will be selected by the master.

PN512

Transm ission module

Several address numbers are reserved. During device configuration, the designer must

ensure that collisions with these reserved addresses cannot occur. Check the I

C-bus

specification for a complete list of reserved addresses.

C-bus address specification is dependent on the definition of pin EA. Immediately

The I after releasing pin NRSTPD or after a power-o n reset, the device defines the I

C-bus

address according to pin EA. If pin EA is set LOW, the upper 4 bits of the device bus address are reserved by

NXP Semiconductors and set to 0101b for all PN512 devices. The remaining 3 bits (ADR_0, ADR_1, ADR_2) of the slave address can be freely configured by the customer

to prevent collisions with other I

C-bus devices.

If pin EA is set HIGH, ADR_0 to ADR_5 can be completely specified at the external pins according to Table 140 on page 66

. ADR_6 is always set to logic 0.

In both modes, the external address coding is latched immediately after releasing the reset condition. Further changes at the used pins are not taken into consideration.

Depending on the external wiring, the I

C-bus address pins can be used for test signal

outputs.

Fig 21. First byte following the START procedure

10.4.6 Register write access

To write data from the host controll er using the I2C-bus to a specific register in the PN512 the following frame format must be used.

• The first byte of a frame indicates the device address according to the I

• The second byte indicates the register address followed by up to n-data bytes.

In one frame all data bytes are written to the same register address. This enables fast FIFO buffer access. The Read/Write (R/W

Product data sheet COMPANY PUBLIC

) bit is set to logic 0.

Rev. 4.2 — 28 August 2012

111342 75 of 132

C-bus rules.

NXP Semiconductors

001aak592

SA00

I2C-BUS

SLAVE ADDRESS

[A7:A0]

JOINER REGISTER

ADDRESS [A5:A0]

write cycle

(W)

DATA

[7:0]

[0:n]

SA00

I2C-BUS

SLAVE ADDRESS

[A7:A0]

JOINER REGISTER

ADDRESS [A5:A0]

read cycle

optional, if the previous access was on the same register address

(W)

S start condition P stop condition A acknowledge

A not acknowledge W write cycle R read cycle

I2C-BUS

SLAVE ADDRESS

[A7:A0]

sent by master

sent by slave

DATA

[7:0]

(R)

DATA

[7:0]

10.4.7 Register read access

To read out data from a specific register address in the PN512, the host controller must use the following procedure:

• Firstly, a write access to the specific register address must be per formed as indicate d

• The first byte of a frame indicates the device address according to the I

• The second byte indicates the register address. No data bytes are added

• The Read/Write bit is 0

After the write access, read access can start. The host sends the device address of the PN512. In response, the PN512 sends the content of the read access register. In one frame all data bytes can be read from the same register address. This enables fast FIFO buffer access or register polling.

The Read/Write (R/W) bit is set to logic 1.

in the frame that follows

PN512

Transm ission module

C-bus rules

Fig 22. Register read and write access

Product data sheet COMPANY PUBLIC

Rev. 4.2 — 28 August 2012

111342 76 of 132

NXP Semiconductors

F/S mode

HS mode (current-source for SCL HIGH enabled)

F/S mode

001aak749

AA A/ADATA

(n-bytes + A)

S R/WMASTER CODE Sr SLAVE ADDRESS

HS mode continues

SLAVE ADDRESS

10.4.8 High-speed mode

In High-speed mode (HS mode), the device can transfer information at data rates of up to

3.4 Mbit/s, while remaining fully downward-compatible with Fast or Standard mode (F/S mode) for bidirectional communication in a mixed-speed bus system.

10.4.9 High-speed transfer

To achieve data rates of up to 3.4 Mbit/s the following improvements have been made to

C-bus operation.

• The inputs of the device in HS mode incorporate spike suppression, a Schmitt trigger

• The output buffers of the device in HS mode incorporate slope control of the falling

10.4.10 Serial data transfer format in HS mode

The HS mode serial data transfer format meets the Standard mode I2C-bus specification. HS mode can only start after all of the following conditions (all of which are in F/S mode ):

PN512

Transm ission module

on the SDA and SCL inputs and diff erent timing constants when compared to F/S m ode

edges of the SDA and SCL signals with different fall times compared to F/S mode

1. START condition (S)

2. 8-bit master code (00001XXXb)

3. Not-acknowledge bit (A

)

When HS mode starts, the active master sends a r epeated STAR T condition (Sr) followed by a 7-bit slave address with a R/W bit addr ess and receives an a cknowled ge bit (A) fr om the selected PN512.

Data transfer continues in HS mode after the next repeated START (Sr), only switching back to F/S mode after a ST OP condition (P). To reduce the overhead of the master code, a master links a number of HS mode transfers, separated by repeated START conditions (Sr).

Fig 23. I2C-bus HS mode protocol switch

Product data sheet COMPANY PUBLIC

Rev. 4.2 — 28 August 2012

111342 77 of 132

NXP Semiconductors

msc618

8-bit master code 0000 1xxx

F/S mode

HS mode

If P then F/S mode

If Sr (dotted lines) then HS mode

16789 67891

1 2 to 5

2 to 5

6789

SDA high

SCL high

SDA high

SCL high

Sr Sr P

n + (8-bit data + A/A)

7-bit SLA

R/W A

= Master current source pull-up

= Resistor pull-up

PN512

Transm ission module

Fig 24. I2C-bus HS mode protocol frame

Product data sheet COMPANY PUBLIC

Rev. 4.2 — 28 August 2012

111342 78 of 132

NXP Semiconductors

10.4.11 Switching between F/S mode and HS mode

After reset and initialization, the PN512 is in Fast mode (which is in effect F/S mode as Fast mode is downward-compatible with Standard mode). The connected PN512 recognizes the “S 00001XXX A” sequence and switches its internal circuitry from the Fast mode setting to the HS mode setting.

The following actions are taken:

1. Adapt the SDA and SCL input filters according to the spike suppression requirement

2. Adapt the slope control of the SDA output stages.

It is possible for system configurations that do not have other I the communication to switch to HS mode permanently. This is implemented by setting Status2Reg register’s I is not required to be sent. This is not defined in the specification and must only be used when no other devices are connected on the bus. In addition, spikes on the I must be avoided because of the reduced spike suppression.

in HS mode.

PN512

Transm ission module

C-bus devices involved in

CForceHS bit to logic 1. In permanent HS mode, the master code

C-bus lines

10.4.12 PN512 at lower speed modes

PN512 is fully downward-compatible and can be connected to an F/S mode I2C-bus system. The device stays in F/S mode and communicates at F/S mode speeds because a master code is not transmitted in this configuration.

11. 8-bit parallel interface

The PN512 supports two different types of 8-bit parallel interfaces, Intel and Motorola compatible modes.

11.1 Overview of supported host controller interfaces

The PN512 supports direct interfacing to various -Controlle rs. The follo wing t abl e shows the parallel interface types supported by the PN512.

Table 151. Supported interface types

Supported interface types Bus Separated Address and

Separated Read and Write Strobes (INTEL compatible)

Multiplexed Read and Write Strobe (Motorola compatible)

Multiplexed Address

Data Bus

control NRD, NWR, NCS NRD, NWR, NCS, ALE address A0 … A3 [..A5*] AD0 … AD7 data D0 … D7 AD0 … AD7 control R/NW, NDS, NCS R/NW, NDS, NCS, AS address A0 … A3 [..A5*] AD0 … AD7 data D0 … D7 AD0 … AD7

and Data Bus

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Rev. 4.2 — 28 August 2012

111342 79 of 132

NXP Semiconductors

001aan223

PN512

NCS

A0...A3[A5*]

D0...D7

A4*

A5*

address bus (A0...A3[A5*])

ALE NRD NWR

ADDRESS

DECODER

data bus (D0...D7)

high not data strobe (NRD) not write (NWR)

address bus

remark: *depending on the package type.

multiplexed address/data AD0...AD7)

PN512

NCS

D0...D7 ALE

NRD NWR

ADDRESS

DECODER

low low high high high

low

address latch enable (ALE) not read strobe (NRD) not write (NWR)

non multiplexed address

001aan224

PN512

NCS

A0...A3[A5*]

D0...D7

A4*

A5*

address bus (A0...A3[A5*])

ALE NRD NWR

ADDRESS

DECODER

Data bus (D0...D7)

high not data strobe (NDS) read not write (RD/NWR)

address bus

remark: *depending on the package type.

multiplexed address/data AD0...AD7)

PN512

NCS

D0...D7 ALE

NRD NWR

ADDRESS

DECODER

low low high high low

low

address strobe (AS) not data strobe (NDS) read not write (RD/NWR)

non multiplexed address

1 1.2 Separated Read/Write strobe

PN512

Transm ission module

Product data sheet COMPANY PUBLIC

Fig 25. Connection to host controller with separated Read/Write strobes

For timing requirements refer to Section 26.2 “8-bit parallel interface timing”.

11.3 Common Read/Write strobe

Fig 26. Connection to host controller with common Read/Write strobes

For timing requirements refer to Section 26.2 “8-bit parallel interface timing”

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NXP Semiconductors

12. Analog interface and contactless UART

12.1 General

The integrated contactless UART supports the external host online with framing and error checking of the protocol requirements up to 84 8 kBd. An external circuit can be connected to the communication interface pins MFIN and MFOUT to modulate and demodulate the data.

The contactless UART handles the protocol requir ements for the communication protocols in cooperation with the host. Protocol handling generates bit and byte-oriented framing. In addition, it handles error detection such as parity and CRC, based on the various supported contactless communication protocols.

Remark: The size and tuning of the antenna and the power supply voltage have an important impact on the achievable operating distance.

12.2 TX driver

The signal on pins TX1 and TX2 is the 13.56 MHz energy carrier modulated by an envelope signal. It can be used to drive an antenna directly using a few passive components for matching and filtering; see Section 15 on page 93 and TX2 can be configured using the TxControlReg register; see Section 9.2.2.5 on

page 37.

PN512

Transm ission module

. The signal on pins TX1

The modulation index can be set by adjusting the impedance of the drivers. The impedance of the p-driver can be configured using registers CWGsPReg and ModGsPReg. The impedance of the n-driver can be configured using the GsNReg register. The modulation index also depends on the antenna design and tuning.

The TxModeReg and TxSelReg registers control the data rate and framing during transmission and the antenna driver setting to support the different requirements at the different modes and transfer speeds.

Table 152. Register and bit settings controlling the signal on pin TX1

Bit Tx1RFEn

100 X

[1] X = Do not care.

Bit Force 100ASK

[1]

01 X

11 X

Bit InvTx1RFOn

[1]

Bit InvTx1RFOff

[1]

Envelope Pin

TX1

[1]

0 RF pMod nMod 100 % ASK: pin TX1 1RFpCWnCW 0 RF pMod nMod 1RFpCWnCW 0 0 pMod nMod 1RF_npCWnCW

[1]

GSPMos GSNMos Remarks

[1]

not specified if RF is switched off

pulled to logic 0, independent of the InvTx1RFOff bit

Product data sheet COMPANY PUBLIC

Rev. 4.2 — 28 August 2012

111342 81 of 132

NXP Semiconductors

PN512

Transm ission module

Table 153. Register and bit settings controlling the signal on pin TX2

Bit Tx1RFEn

Bit Force

Bit Tx2CW

Bit InvTx2RFOn

Bit InvTx2RFOff

Envelope Pin

100ASK

[1]

1000 X

[1]

0 RF pMod nMod 1RFpCWnCW

[1]

0 RF_n pMod nMod 1RF_npCWnCW

10 X

100 X

[1] [1]

[1]

X 0 0 pMod nMod 100 % ASK: pin

1RFpCWnCW

[1]

0 0 pMod nMod 1RF_npCWnCW

[1] X = Do not care.

10 X

[1] [1]

[1]

GSPMos GSNMos Remarks

TX2

[1]

not specified if RF is switched off

RF pCW nCW conductance RF_n pCW nCW

always CW for the Tx2CW bit

TX2 pulled to logic 0 (independent of the

RF pCW nCW

InvTx2RFOn/Inv Tx2RFOff bits)

RF_n pCW nCW

The following abbreviations have been used in Table 152 and Table 153:

• RF: 13.56 MHz clock derived from 27.12 MHz quartz crystal oscillator divided by 2

• RF_n: inverted 13.56 MHz clock

• GSPMos: conductance, configuration of the PMOS array

• GSNMos: conductance, configuration of the NMOS array

• pCW: PMOS conductance value for continuous wave defin ed by the CWGsPReg

• pMod: PMOS conductance value for modulation defined by the ModGsPReg register

• nCW: NMOS conductance value for continuous wave defined by the GsNReg

• nMod: NMOS conductance value for modulation defined by the GsNReg register’s

ModGsN[3:0] bits

• X = do not care.

Remark: If only one driver is switched on, the values for CWGsPReg, ModGsPReg and

GsNReg registers are used for both drivers.

12.3 RF level detector

The RF level detector is integrated to fulfill NFCIP1 protocol requirements (e.g. RF collision avoidance). Furthermore the RF level detector can be used to wake up the PN512 and to generate an interrupt.

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The sensitivity of the RF level detector is adjustable in a 4-bit range using the bits RFLevel in register RFCfgReg. The sensitivity itself depends on the antenna configuration and tuning.

PN512

Transm ission module

Possible sensitivity levels at the RX pin are listed in the Table 153

Table 154. Setting of the bits RFlevel in register RFCfgReg (RFLevel amplifier deactivated)

V~Rx [Vpp] RFLevel

~2 1111 ~1.4 1110 ~0.99 1101 ~0.69 1100 ~0.49 1011 ~0.35 1010 ~0.24 1001 ~0.17 1000 ~0.12 0111 ~0.083 0110 ~0.058 0101 ~0.041 0100 ~0.029 0011 ~0.020 0010 ~0.014 0001 ~0.010 0000

To increase the sensitivity of the RF level detector an amplifier can be activated by setting the bit RFLevelAmp in register RFCfgReg to 1.

Remark: During soft Power-down mode the RF level detector amplifier is automatically switched off to ensure that the power consumption is less than 10 Aat3V.

Remark: With typical antennas lower sensitivity levels can provoke misleading resu lts because of intrinsic noise in the environment.

Note: It is recommended to use the bit RFLevelAmp only with higher RF level settings.

12.4 Data mode detector

The Data mode detector gives the possibility to detect received signals according to the ISO/IEC 14443A/MIFARE, FeliCa or NFCIP-1 schemes at the standard transfer speeds for 106 kbit, 212 kbit and 424 kbit in order to prepare the internal receiver in a fast and convenient way for further data processing.

The Data mode detector can only be activated by the AutoColl command. The mode detector resets, when no external RF field is detected by the RF level detector. The Data mode detector could be switched off during the AutoColl command by setting bit ModeDetOff in register ModeReg to 1.

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001aan225

HOST INTERFACES

RECEIVER

I/Q DEMODULATOR

REGISTERS

REGISTERSETTING

FOR THE

DETECTED MODE

DATA MODE DETECTOR

PN512

NFC @ 106 kbit/s NFC @ 212 kbit/s NFC @ 424 kbit/s

PN512

Transm ission module

Fig 27. Data mode detector

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001aak593

INTERNAL

CODER

INVERT IF

InvMod = 1

DriverSel[1:0]

00 01 10 11

3-state

to driver TX1 and TX2 0 = impedance = modulated 1 = impedance = CW

INVERT IF

PolMFin = 0

MFIN

envelope

12.5 Serial data switch

Two main bloc ks are implemented in the PN512. The digital block comprises the state machines, encoder/decoder logic. The analog block comprises the modulator and antenna drivers, the receiver and amplifiers. The interface between these two blocks can be configured in the way, that the interfacing signals may be routed to the pins SIGIN and SIGOUT. SIGIN is capable of processing digital NFC signals on transfer speeds above 424 kbit. The SIGOUT pin can provide a digital signal that can be used with an additional external circuit to generate transfer speeds above 424 kbit (including 106, 212 and 424 kbit). Furthermore SIGOUT and SIGIN can be used to enable the S card SAM mode to emulate a card functionality with the PN512 and a secu re IC. A secure IC can be the SmartMX smart card controller IC.

This topology allows the analog block of the PN512 to be connected to the digi t al block of another device.

The serial signal switch is controlled by the TxSelReg and RxSelReg registers.

PN512

Transm ission module

C interface in the

Figure 28

shows the serial data switch for TX1 and TX2.

Fig 28. Serial data switch for TX1 and TX2

12.6 S2C interface support

The S2C provides the possibility to directly connect a secure IC to the PN512 in order act as a contactless smart card IC via the PN512. The inter facing signals can be routed to the pins SIGIN and SIGOUT. SIGIN can receive either a digital FeliCa or digitized ISO/IEC 14443A signal sent by the secure IC. The SIGOUT pin can provide a digital signal and a clock to communicate to the secure IC. A secure IC can be the smart card IC provided by NXP Semiconductors.

The PN512 has an extra supply pin (SVDD and PVSS as Ground line) for the SIGIN and SIGOUT pads.

Figure 30

Product data sheet COMPANY PUBLIC

outlines possible ways of communications via the PN512 to the secure IC.

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001aan226

CONTACTLESS UART

SERIAL SIGNAL SWITCH

FIFO AND STATE MACHINE

SPI, I

C, SERIAL UART

HOST CONTROLLER

PN512

SECURE CORE IC

SIGOUT

SIGIN

2. contactless card mode

1. secure access module (SAM) mode

Fig 29. Communication flows using the S2C interface

PN512

Transm ission module

Configured in the Secure Access Mode the host controller can directly communicate to the Secure IC via SIGIN/SIGOUT. In this mode the PN512 generates the RF clock and performs the communication on the SIGOUT line. To enable the Secure Access module mode the clock has to be derived by the internal oscillator of the PN512, see bits SAMClockSel in register TestSel1Reg.

Configured in Contactless Card mode the secure IC can act as conta ctless smart card IC via the PN512. In this mode the signal on the SIGOUT line is p rovid ed by the extern al RF field of the external reader/writer. To enable the Contactless Card mode the clock derived by the external RF field has to be used.

The configuration of the S

C interface differs for the FeliCa and MIFARE scheme as

outlined in the following chapters.

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001aan227

clock

signal on

SIGIN

signal on

antenna

001aan228

clock

demodulated

signal

signal on

SIGOUT

12.6.1 Signal shape for Felica S2C interface support

The FeliCa secure IC is connected to the PN512 via the pins SIGOUT and SIGIN. The signal at SIGOUT contains the information of the 13.56 MHz clock and the digitized

demodulated signal. The clock and the demodulated signal is combined by using the logical function exclusive or.

To ensure that this signal is free of spikes, the demodulated signal is digitally filtere d first. The time delay for that digital filtering is in the range of one bit length. The demodulated signal changes only at a positive edge of the clock.

The register TxSelReg controls the setting at SIGOUT.

PN512

Transm ission module

Fig 30. Signal shape for SIGOUT in FeliCa card SAM mode

The answer of the FeliCa SAM is transferred from SIGIN directly to the antenna driver. The modulation is done according to the register settings of the antenna drivers.

The clock is switched to AUX1 or AUX2 (see AnalogSelAux). Note: A HIGH signal on AUX1 and AUX2 has the same level as AVDD. A HIGH signal at

SIGOUT has the same level as SVDD. Alternatively it is possible to use pin D0 as clock output if a serial interface is used. The HIGH level at D0 is the same as PVDD.

Fig 31. Signal shape for SIGIN in SAM mode

Note: The signal on the antenna is shown in principle only. In reality the waveform is sinusoidal.

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001aan229

bit

value RF

signal on

antenna

signal on

SIGOUT

01001

001aan230

0011

bit

value

signal on

antenna

signal on

SIGIN

12.6.2 Waveform shape for ISO/IEC 14443A and MIFARE S2C support

The secure IC, e.g. the SmartMX is connected to the PN512 via the pins SIGOUT and SIGIN.

The waveform shape at SIGOUT is a digital 13.56 MHz Miller coded signal with levels between PVSS and PVDD derived out of the external 13.56 MHz carrier signal in case of the Contactless Card mode or internally generated in terms of Secure Access mode.

The register TxSelReg controls the setting at SIGOUT. Note: The clock settings for the Secure Access mode and the Contactless Card mode

differ, refer to the description of the bits SAMClockSel in register TestSel1Reg.

PN512

Transm ission module

Fig 32. Signal shape for SIGOUT in MIFARE Card SAM mode

The signal at SIGIN is a digital Manchester coded signal according to the requirement s of the ISO/IEC 14443A with the subcarrier frequency of 847.5 kHz generated by the secure IC.

Fig 33. Signal shape for SIGIN in MIFARE Card SAM mode

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12.7 Hardware support for FeliCa and NFC polling

12.7.1 Polling sequence functionality for initiator

1. Timer: The PN512 has a timer, which can be programmed in a way that it generates

2. The receiver can be configured in a way to receive continuously. In this mode it can

3. The internal UART adds one byte to the end of every received packet, before it is

4. The length of one packet is 18 or 20 bytes (+ 1 byte Error-Info). The FIFO has a

PN512

Transm ission module

an interrupt at the end of each timeslot, or if required an interrupt is generated at the end of the last timeslot.

receive any number of packets. The receiver is ready to receive the next packet directly after the last packet has been received. This mode is active by setting the bit RxMultiple in register RxModeReg to 1 and has to be stopped by software.

transferred into the FIFO-buffer. This byte indicates if the received byte packet is correct (see register ErrReg). The first byte of each packet contains the length byte of the packet.

length of 64 bytes. This means three packets can be stored in the FIFO at the same time. If more than three packets are expected, the host controller has to empty the FIFO, before the FIFO is filled completely . In case of a FIFO-overflow data is lost (See bit BufferOvfl in register ErrorReg).

12.7.2 Polling sequence functionality for target

1. The host controller has to configure the PN512 with the correct polling response parameters for the polling command.

2. To activate the automatic polling in Target mode, the AutoColl Command has to be activated.

3. The PN512 receives the polling command send out by an initiator and answers with the polling response. The timeslot is selected automatically (The timeslot itself is randomly generated, but in the range 0 to TSN, which is defined by the Polling command). The PN512 compares the system code, stored in byte 17 and 18 of the Config Command with the system code received by the polling command of an initiator. If the system code is equal, the PN512 answers according to the configured polling response. The system code FF (hex) acts as a wildcard for the system code bytes, i.e. a target of a system code 1234 (hex) answers to the polling command with one of the following system codes 1234 (hex), 12FF (hex), FF34 (hex) or FFFF (hex). If the system code does not match no answer is sent back by the PN512.

If a valid command is received by the PN512, which is not a Polling command, no answer is sent back and the command AutoColl is stopped. The received packet is stored in the FIFO.

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12.7.3 Additional hardware support for FeliCa and NFC

Additionally to the polling sequence support for the Felica mode, the PN512 supports the check of the Len-byte.

The received Len-byte in accordance to the registers FelNFC1Reg and FelNFC2Reg: DataLenMin in register FelNFC1Reg defines the minimum length of the accepted packet

length. This register is six bit long. Each bit represents a length of four bytes. DataLenMax in register FelNFC2Reg defines the maximum length of the accepted

package. This register is six bit long. Each bit represents a length of four bytes. If set to logic 1 this limit is ignored. If the length is not in the supposed range, the packet is not transferred to the FIFO and receiving is kept active.

Example 1:

• DataLenMin = 4

• DataLenMax = 5

PN512

Transm ission module

– The length shall be greater or equal 16.

– The length shall be smaller than 20. Valid area: 16, 17, 18, 19

Example 2:

• DataLenMin = 9

– The length shall be greater or equal 36.

• DataLenMax = 0

– The length shall be smaller than 256. Valid area: 36 to 255

12.7.4 CRC coprocessor

The following CRC coprocessor parameters can be configured:

• The CRC preset value can be either 0000h, 6363h, A671h or FFFFh depending on

the ModeReg register’s CRCPreset[1:0] bits setting

• The CRC polynomial for the 16-bit CRC is fixed to x

• The CRCResultReg register indicates the result of the CRC calculation. This register

is split into two 8-bit registers representing the higher and lower bytes.

• The ModeReg register’s MSBFirst bit indicates that data will be loaded with the MSB

first.

Table 155. CRC coprocessor parameters

Parameter Value

CRC register length 16-bit CRC CRC algorithm algorithm according to ISO/IEC 14443 A and ITU-T CRC preset value 0000h, 6363h, A671h or FFFFh depending on the setting of the

16+x12+x5

ModeReg register’s CRCPreset[1:0] bits

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HiAlert 64 FIFOLength–WaterLevel=

13. FIFO buffer

An 8  64 bit FIFO buffer is used in the PN512. It buffers the inpu t and output dat a stream between the host and the PN512’s internal state machine. This makes it possible to manage data streams up to 64 bytes long without the need to take timing constraints into account.

13.1 Accessing the FIFO buffer

The FIFO buffer input and output data bus is connected to the FIFODataReg register. Writing to this register stores one byte in the FIFO buffer and increments the internal FIFO buffer write pointer. Reading from this register shows the FIFO buffer contents stored in the FIFO buffer read pointer and decrements the FIFO buffer read pointer. The distance between the write and read pointer can be obtained by reading the FIFOLevelReg register.

When the microcontroller starts a command, the PN512 can, while the command is in progress, access the FIFO buffer according to that command. Only one FIFO buffer has been implemented which can be used for input and output. The microcontroller must ensure that there are not any unintentional FIFO buffer accesses.

PN512

Transm ission module

13.2 Controlling the FIFO buffer

The FIFO buffer pointers can be reset by setting FIFOLevelReg register’s FlushBuffer bit to logic 1. Consequently, the FIFOLevel[6:0] bits are all set to logic 0 and the ErrorReg register’s BufferOvfl bit is cleared. The bytes stored in the FIFO buffer are no longer accessible allowing the FIFO buffer to be filled with another 64 bytes.

13.3 FIFO buffer status information

The host can get the following FIFO buffer status information:

• Number of bytes stored in the FIFO buffer: FIFOLevelReg register’s FIFOLevel[6:0]

• FIFO buffer almost full warning: Status1Reg register’s HiAlert bit

• FIFO buffer almost empty warning: Status1Reg register’s LoAlert bit

• FIFO buffer overflow warning: ErrorReg register’s BufferOvfl bit. The BufferOvfl bit

can only be cleared by setting the FIFOLevelReg register’s FlushBuffer bit.

The PN512 can generate an interrupt signal when:

• ComIEnReg register’s LoAlertIEn bit is set to logic 1. It activates pin IRQ when

Status1Reg re gister’s LoAlert bit changes to logic 1.

• ComIEnReg register’s HiAlertIEn bit is set to logic 1. It activates pin IRQ when

Status1Reg register’s HiAlert bit changes to logic 1.

If the maximum number of WaterLevel bytes (as set in the W ate rLevelReg register) or less are stored in the FIFO buffer, the HiAlert bit is set to logic 1. It is generated according to

Equation 3

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(3)

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NXP Semiconductors

LoAlert FIFOLength WaterLevel=

If the number of WaterLevel bytes (as set in the WaterLevelReg register) or less are stored in the FIFO buffer, the LoAlert bit is set to logic 1. It is generated according to

Equation 4

14. Interrupt request system

The PN512 indicates certain events by setting the Status1Reg register’s IRq bit and, if activated, by pin IRQ. The signal on pin IRQ can be used to interrupt the host using its interrupt handling capabilities. This allows the implementation of efficient host software.

14.1 Interrupt sources overview

Table 156 shows the available interrupt bits, the corresponding source and the condition

for its activation. The ComIrqReg register’s T imerIRq interrupt bit in dicates an interrupt set by the timer unit which is set when the timer decrements from 1 to 0.

The ComIrqReg register’s TxIRq bit indicates that the transmitter has finished. If the state changes from sending data to transmitting the end of the frame pattern, the transmitter unit automatically sets the interrupt bit. The CRC coprocessor sets the DivIrqReg register’s CRCIRq bit after processing all the FIFO buffer data which is indicated by CRCReady bit = 1.

PN512

Transm ission module

(4)

The ComIrqReg register’s RxIRq bit indicates an interrupt when the end of the received data is detected. The ComIrqReg register’s IdleIRq bit is set if a command finishes and the Command[3:0] value in the CommandReg register changes to idle (see Table 157 on

page 98).

The ComIrqReg register’s HiAlertIRq bit is set to logic 1 when the Status1Reg register’s HiAlert bit is set to logic 1 which means that the FIFO buffer has reached the level indicated by the WaterLevel[5:0] bits.

The ComIrqReg register’s LoAlertIRq bit is set to logic 1 when the Status1Reg register’s LoAlert bit is set to logic 1 which means that the FIFO buffer has reached the level indicated by the WaterLevel[5:0] bits.

The ComIrqReg register’s ErrIRq bit indicates an error detected by the contactless UART during send or receive. This is indicated when any bit is set to logic 1 in register ErrorReg.

Table 156. Interrupt sources

Interrupt flag Interrupt source Trigger action

TimerIRq timer unit the timer counts from 1 to 0 TxIRq transmitter a transmitted data stream ends CRCIRq CRC coprocessor all data from the FIFO buffer has been processed RxIRq receiver a received data stream ends IdleIRq ComIrqReg register command execution finishes HiAlertIRq FIFO buffer the FIFO buffer is almost full LoAlertIRq FIFO buffer the FIFO buffer is almost empty ErrIRq contactless UART an error is detected

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15. Timer unit

A timer unit is implemented in the PN512. The external host controller may use this timer to manage timing relevant tasks. The timer unit may be used in one of the following configurations:

• Time-out counter

• Watch-dog counter

• Stop watch

• Programmable one-shot

• Periodical trigger

The timer unit can be used to measure the time interval between two events or to indicate that a specific event occurred after a specific time. The timer can be triggered by events which will be explained in the following, but the timer itself does not influence any internal event (e.g. A time-out during data reception does not influence the reception process automatically). Furthermore, several timer related bits are set and these bits can be used to generate an interrupt.

PN512

Transm ission module

Timer

The timer has an input clock of 13.56 MHz (derived from the 27.12 MHz quartz). The timer consists of two stages: 1 prescaler and 1 counter.

The prescaler is a 12-bit counte r . Th e reload value for TPrescaler can be defined be tween 0 and 4095 in register TModeReg and TPrescalerReg.

The reload value for the counter is defined by 16 bits in a range of 0 to 65535 in the register TReloadReg.

The current value of the timer is indicated by the register TCounterValReg. If the counter reaches 0 an interrupt will be generated automatically indicated by setting

the TimerIRq bit in the register CommonIRqReg. If enabled, this e vent can be indicated o n the IRQ line. The bit TimerIRq can be set and reset by the host controller. Depend ing on the configuration the timer will stop at 0 or restart with the value from register TReloadReg.

The status of the timer is indicated by bit TRunning in register Status1Reg. The timer can be manually started by TStartNow in register ControlReg or manually

stopped by TStopNow in register Control Reg. Furthermore the timer can be activated automatically by setting the bit TAuto in the register TModeReg to fulfill dedicated protocol requirements automatically.

The time delay of a timer stage is the reload value +1. The definition of total time is: t = ((TPrescaler*2+1)*TReload+1)/13.56MHz or if TPrescaleEven bit is set: t = ((TPrescaler*2+2)*TReload+1)/13.56MHz

Maximum time: TPrescaler = 4095,TReloadVal = 65535

=> (2*4095 +2)*65536/13.56 MHz = 39.59 s

Example:

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To indicate 25 us it is required to count 339 clock cycles. This means the value for TPrescaler has to be set to TPrescaler = 169.The timer has now an input clock of 25 us. The timer can count up to 65535 timeslots of each 25 s. For the behaviour in version

1.0, see Section 21 “

PN512

Transm ission module

Errata sheet” on page 106.

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16. Power reduction modes

16.1 Hard power-down

Hard power-down is enabled when pin NRSTPD is LOW. This turns off all internal current sinks including the oscillator. All digital input buf fers are sep arated from the input pins and clamped internally (except pin NRSTPD). The output pins are frozen at either a HIGH or LOW level.

16.2 Soft power-down mode

Soft Power-down mode is entered immediately after the CommandReg register’s PowerDown bit is set to logic 1. All internal current sinks are switched off, including the oscillator buffer. However, the digital input buffers are not separated from the input pins and keep their functionality. The digital output pins do not change their state.

During soft power-down, all register values, the FIFO buffer content and the configuration keep their current contents.

After setting the PowerDown bit to logic 0, it takes 1024 clocks until the Soft power-down mode is exited indicated by the PowerDown bit. Setting it to logic0 does not immediately clear it. It is cleared automatically by the PN512 when Soft power-down mode is exited.

PN512

Transm ission module

Remark: If the internal oscillator is used, you must take into account that it is supplied by

pin AVDD and it will take a certain time (t cycles can be detected by the internal logic. It is recommended for the serial UART, to first send the value 55h to the PN512. The oscillator must be stable for further access to the registers. To ensure this, perform a read access to address 0 until the PN512 answers to the last read command with the register content of address 0. This indicates that the PN512 is ready.

16.3 Transmitter power-down mode

The Transmitter Power-down mode switches off the internal antenna drivers thereby, turning off the RF field. Transmitter power-down mode is entered by setting either the TxControlReg register’s Tx1RFEn bit or Tx2RFEn bit to logic 0.

) until the oscillator is stable and the clock

osc

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001aan231

PN512

27.12 MHz

OSCOUT OSCIN

1024

27 s

------------- -

37.74 s==

17. Oscillator circuitry

Fig 34. Quartz crystal connection

The clock applied to the PN512 provides a time basis for the synchronous system’s encoder and decoder. The stability of the clock frequency, therefore, is an important factor for correct operation. To obtain optimum performance, clock jitter must be reduced as much as possible. This is best achieved using the internal oscillator buffer with the recommended circuitry.

PN512

Transm ission module

If an external clock source is used, the clock signal must be applied to pin OSCIN. In this case, special care must be taken with the clock duty cycle and clock jitter and the clock quality must be verified.

18. Reset and oscillator start-up time

18.1 Reset timing requirements

The reset signal is filtered by a hysteresis circuit and a spike filter before it enters the digital circuit. The spike filter rejects signals shorter than 10 ns. In order to perform a reset, the signal must be LOW for at least 100 ns.

18.2 Oscillator start-up time

If the PN512 has been set to a Power-down mode or is powered by a V start-up time for the PN512 depends on the oscillator used and is shown in Figure 35

The time (t start-up time is defined by the crystal.

The time (t the PN512 can be addressed.

The delay time is calculated by:

) is the start-up time of the crystal oscillator circuit. The crystal oscillator

startup

) is the internal delay time of the PN512 when the clock signal is stab le before

supply, the

DDX

(5)

The time (t

Product data sheet COMPANY PUBLIC

) is the sum of td and t

osc

Rev. 4.2 — 28 August 2012

startup

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001aak596

startup

osc

device activation

oscillator

clock stable

clock ready

Fig 35. Os cillato r start-up time

19. PN512 command set

The PN512 operation is determined by a state machine capable of performing a set of commands. A command is executed by writing a command code (see Table 157 CommandReg register.

PN512

Transm ission module

) to the

Arguments and/or data necessary to pro cess a command are exchanged via the FIFO buffer.

19.1 General description

The PN512 operation is determined by a state machine capable of performing a set of commands. A command is executed by writing a command code (see Table 157 CommandReg register.

Arguments and/or data necessary to pro cess a command are exchanged via the FIFO buffer.

19.2 General behavior

Each command that needs a data bit stream (or data byte stream) as an input

•

immediately processes any data in the FIFO buffer. An exception to this rule is the Transceive command. Using this command, transmission is started with the BitFramingReg register’s St artSend bit.

• Each command that needs a certain number of arguments, starts processing only

when it has received the correct number of arguments from the FIFO buffer.

• The FIFO buffer is not automatically cleared when commands star t. This makes it

possible to write command arguments and/or the data bytes to the FIFO buffer and then start the command.

• Each command can be interrupted by the host writing a new command code to the

CommandReg register, for example, the Idle command.

) to the

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19.3 PN512 command overview

Table 157. Command overview

Command Command

Idle 0000 no action, cancels current command execution Configure 0001 Configures th e PN512 for FeliCa, MIFARE and NFCIP-1

Generate RandomID 0010 generates a 10-byte random ID number CalcCRC 0011 activates the CRC coprocessor or performs a self test Transmit 0100 transmits data from the FIFO buffer NoCmdChange 0111 no command change, can be used to modify the

Receive 1000 activates the receiver circuits Transceive 1100 transmits data from FIFO buffer to antenna and automatically

AutoColl 1101 Handles FeliCa polling (Card Operation mode only) and

MFAuthent 1110 performs the MIFARE standard authentication as a reader SoftReset 1111 resets the PN512

PN512

Transm ission module

Action

code

communication

CommandReg register bits without affecting the command, for example, the PowerDown bit

activates the receiver after transmission

MIFARE anticollision (Card Operation mode only)

19.3.1 PN512 command descriptions

19.3.1.1 Idle

Places the PN512 in Idle mode. The Idle command also terminates itself.

19.3.1.2 Config command

To use the automatic MIFARE Anticollision, FeliCa Polling and NFCID3 the data used for these transactions has to be stored internally. All the following data have to be written to the FIFO in this order:

SENS_RES (2 bytes); in order byte 0, byte 1 NFCID1 (3 Bytes); in order byte 0, byte 1, byte 2; the first NFCID1 byte is fixed to 08h an d

the check byte is calculated automatically. SEL_RES (1 Byte) polling response (2 bytes (shall be 01h, FEh) + 6 bytes NFCID2 + 8 bytes Pad + 2 bytes

system code) NFCID3 (1 byte) In total 25 bytes are transferred into an internal buffer. The complete NFCID3 is 10 bytes long and consists of the 3 NFCID1 bytes, the 6 NFCID2

bytes and the one NFCID3 byte which are listed above. To read out this configuration the command Config with an empty FIFO-buffer has to be

started. In this case the 25 bytes are transferred from the internal buffer to the FIFO.

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The PN512 has to be configured after each power up, before using the automatic Anticollision/Polling function (AutoColl command). During a hard power down (reset pin) this configuration remains unchanged.

This command terminates automatically when finished and the active command is idle.

19.3.1.3 Generate RandomID

This command generates a 10-byte random number which is initially stored in the inter nal buffer. This then overwrites the 10 bytes in the internal 25-byte buffer. This command automatically terminates when finished and the PN512 returns to Idle mode.

19.3.1.4 CalcCRC

The FIFO buffer content is transferred to the CRC coprocessor and the CRC calcu lation is started. The calculation result is stored in the CRCResultReg register. The CRC calculation is not limited to a dedicated number of bytes. The calculation is not stopped when the FIFO buffer is empty during the data stream. The next byte wr itten to the FIFO buffer is added to the calculation.

The CRC preset value is controlled by the ModeReg register’s CRCPreset[1:0] bits. The value is loaded in to the CRC coprocessor when the command starts.

PN512

Transm ission module

This command must be terminated by writing a command to the CommandReg register, such as, the Idle command.

If the AutoTestReg register’s SelfTest[3:0] bits are set correctly, the PN512 enters Self Test mode. Starting the CalcCRC command initiates a digital self test. The result of the self test is written to the FIFO buffer.

19.3.1.5 Transmit

The FIFO buffer content is immediately transmitted after starting this command. Before transmitting the FIFO buffer content, all relevant registers must be set for data transmission.

This command automatically terminates when the FIFO buffer is empty. It can be terminated by another command written to the CommandReg register.

19.3.1.6 NoCmdChange

This command does not influence any running command in the CommandReg register. It can be used to manipulate any bit except the CommandReg register Command[3:0] bits, for example, the RcvOff bit or the PowerDown bit.

19.3.1.7 Receive

The PN512 activates the receiver path and waits for a data stream to be received. The correct settings must be chosen before starting this command.

This command automatically terminates when the data stream ends. This is indicated either by the end of frame pattern or by the length byte depending on the selected frame type and speed.

Remark: If the RxModeReg register’s RxMultiple bit is set to logic 1, the Receive command will not automatically terminate. It must be terminated by starting another command in the CommandReg register.

Product data sheet COMPANY PUBLIC

Rev. 4.2 — 28 August 2012

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NXP Semiconductors

19.3.1.8 Transceive

This command continuously repeats the transmission of data from the FIFO buffer a nd the reception of data from the RF field. The first action is transmit and after transmission the command is changed to receive a data stream.

Each transmit process must be started by setting the BitFramingReg register’s StartSend bit to logic 1. This command must be cleared by writing any command to the CommandReg register.

Remark: If the RxModeReg register’s RxMultiple bit is set to logic 1, the Transceive command never leaves the receive state because this state cannot be cancelled automatically.

19.3.1.9 AutoColl

This command automatically handles the MIFARE activation and the FeliCa polling in the Card Operation mode. The bit Initiator in the register ControlReg has to be set to logic 0 for correct operation. During this command also the mode detector is active if not deactivated by setting the bit ModeDetOff in the ModeReg register. After the mode detector detects a mode, all the mode dependent registers are set according to the received data. In case of no external RF field the command resets the internal state machine and returns to the initial state but it will not be terminated. When the command terminates the transceive command gets active.

PN512

Transm ission module

During protocol processing the IRQ bits are not supported. Only the last received frame will serve the IRQ’s. The treatment of the TxCRCEn and RxCRCEn bits is different to the protocol. During ISO/IEC 14443A activation the enable bits are defined by the comm and AutoColl. The changes cannot be observed at the register TXMod eReg and RXModeReg. After the Transceive command is active, the value of the register bit is relevant.

The FIFO will also receive the two CRC check bytes of the last command even if they already checked and correct, if the state machine (Anticollision and Select routine) has to not been executed and 106 kbit is detected.

During Felica activation the register bit is always relevant and is not overruled by the command settings. This command can be cleared by software by writing any other command to the CommandReg register, e.g. the idle command. W riting the same conten t again to the CommandReg register resets the state machine.

Product data sheet COMPANY PUBLIC

Rev. 4.2 — 28 August 2012

111342 100 of 132

NXP PN512 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual

1. Introduction

1.1 Different available versions

2. General description

3. Features and benefits

4. Quick reference data

5. Ordering information

6. Block diagram

7. Pinning information

7.1 Pinning

7.2 Pin description

8. Functional description

8.1 ISO/IEC 14443 A/MIFARE functionality

8.2 ISO/IEC 14443 B functionality

8.3 FeliCa reader/writer functionality

8.3.1 FeliCa framing and coding

8.4 NFCIP-1 mode

8.4.1 Active communication mode

8.4.2 Passive communication mode

8.4.3 NFCIP-1 framing and coding

8.4.4 NFCIP-1 protocol support

8.4.5 MIFARE Card operation mode

8.4.6 FeliCa Card operation mode

9. PN512 register SET

9.1 PN512 registers overview

9.1.1 Register bit behavior

9.2 Register description

9.2.1 Page 0: Command and status

9.2.1.1 PageReg

9.2.1.2 CommandReg

9.2.1.3 CommIEnReg

9.2.1.4 DivIEnReg

9.2.1.5 CommIRqReg

9.2.1.6 DivIRqReg

9.2.1.7 ErrorReg

9.2.1.8 Status1Reg

9.2.1.9 Status2Reg

9.2.1.10 FIFODataReg

9.2.1.11 FIFOLevelReg

9.2.1.12 WaterLevelReg

9.2.1.13 ControlReg

9.2.1.14 BitFramingReg

9.2.1.15 CollReg

9.2.2 Page 1: Communication

9.2.2.1 PageReg

9.2.2.2 ModeReg

9.2.2.3 TxModeReg

9.2.2.4 RxModeReg

9.2.2.5 TxControlReg

9.2.2.6 TxAutoReg

9.2.2.7 TxSelReg

9.2.2.8 RxSelReg

9.2.2.9 RxThresholdReg

9.2.2.10 DemodReg

9.2.2.11 FelNFC1Reg

9.2.2.12 FelNFC2Reg

9.2.2.13 MifNFCReg

9.2.2.14 ManualRCVReg

9.2.2.15 TypeBReg

9.2.2.16 SerialSpeedReg

9.2.3 Page 2: Configuration

9.2.3.1 PageReg

9.2.3.2 CRCResultReg

9.2.3.3 GsNOffReg

9.2.3.4 ModWidthReg

9.2.3.5 TxBitPhaseReg

9.2.3.6 RFCfgReg

9.2.3.7 GsNOnReg

9.2.3.8 CWGsPReg

9.2.3.9 ModGsPReg

9.2.3.10 TMode Register, TPrescaler Register

9.2.3.11 TReloadReg

9.2.3.12 TCounterValReg

9.2.4 Page 3: Test

9.2.4.1 PageReg

9.2.4.2 TestSel1Reg

9.2.4.3 TestSel2Reg