NXP PN512 Schematics

1. Introduction

1.1 Different available versions

PN512

Transmission module

Rev. 4.2 — 28 August 2012 111342

This document describes the functionality and electrical specifications of the transceiver IC PN512.

The PN512 is a highly integrated transceiver IC for contactless communication at

13.56 MHz. This transceiver IC utilizes an outstanding modulation and demodulation concept completely integrated for different kinds of contactless communication methods and protocols at 13.56 MHz.

The PN512 is available in three versions:

Product data sheet

COMPANY PUBLIC

• PN5120A0HN1/C2 (HVQFN32) and PN5120A0HN/C2 (HVQFN40), hereafte r named

as version 2.0

• PN512AA0HN1/C2 (HVQFN32) and PN512AA0HN1/C2BI (HVQFN32 with Burn In),

hereafter named as industrial version, fulfilling the automotive qualification stated in AEC-Q100 grad 3 from the Automotive Electronics Council, defining the critical stress test qualification for automotive integrated circuits (ICs).

• PN5120A0HN1/C1(HVQFN32) and PN5120A0HN/C1 (HVQFN40), hereafter named

as version 1.0

The data sheet describes the functionality for the industrial version and version 2.0. The differences of the version 1.0 to the version 2.0 are summarized in Section 21 industrial version has only differences within the outlined characteristics and limitations.

2. General description

The PN512 transceiver ICs support 4 different operating modes

• Reader/Writer mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme

• Reader/Writer mode supporting ISO/IEC 14443B

• Card Operation mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme

• NFCIP-1 mode

. The

Enabled in Reader/Writer mode for ISO/IEC 14443A/MIFARE, the PN512’s internal transmitter part is able to drive a reader/writer antenna designed to communicate with ISO/IEC 14443A/ MIF A RE card s and transponder s withou t a dditional active circuitry. The receiver part provides a robust and efficient implementation of a demodulation and

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decoding circuitry for signals from ISO/IEC 14443A/MIFARE compatible cards and transponders. The digital part handles the complete ISO/IEC 14443A framing and error detection (Parity & CRC).

The PN512 supports MIF ARE 1K or MIF ARE 4K emulation p roducts. The PN512 support s contactless communication using MIFARE higher transfer speeds up to 424 kbit/s in both directions.

Enabled in Reader/Writer mode for FeliCa, the PN512 transceiver IC supports the FeliCa communication scheme. The receiver part provides a robust and efficient implementation of the demodulation and decoding circuitry for FeliCa coded signals. The digital part handles the FeliCa framing and error detection like CRC. The PN512 supports contactless communication using FeliCa Higher transfer speeds up to 424 kbit/s in both directions.

The PN512 supports all layers of the ISO/IEC 14443B reader/writer communication scheme, given correct implementation of additional components, like oscillator, power supply, coil etc. and provided that standardized protocols, e.g. like ISO/IEC 14443-4 and/or ISO/IEC 14443B anticollision are correctly implemented.

In Card Operation mode, the PN512 transceiver IC is able to answer to a reader/writer command either according to the FeliCa or ISO/IEC 14443A/MIFARE card interface scheme. The PN512 generates the digital load modulated signals and in addition with an external circuit the answer can be sent back to the re ad e r/ writ er. A complete card functionality is only possible in combination with a secure IC using the S

PN512

Transm ission module

C interface.

Additionally, the PN512 transceiver IC offers the possibility to communicate directly to an NFCIP-1 device in the NFCIP-1 mode. The NFCIP-1 mode of fers dif ferent communication mode and transfer speeds up to 424 kbit/s according to the Ecma 340 a nd ISO/IEC 18092 NFCIP-1 Standard. The digital part handles th e complete NFCIP-1 framing and error detection.

Various host controller interfaces are implemented:

• 8-bit parallel interface

• SPI interface

• serial UART (similar to RS232 with voltage levels according pad voltage supply)

• I

C interface.

A purchaser of this NXP IC has to take care for appropriate third party patent licenses.

1. 8-bit parallel Interface only available in HVQFN40 package.

Product data sheet COMPANY PUBLIC

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3. Features and benefits

 Highly integrated analog circuitry to demodulate and decode responses  Buffered output drivers for connecting an antenna with the minimum number of

external components

 Integrated RF Level detector  Integrated data mode detector  Supports ISO/IEC 14443 A/MIFARE  Supports ISO/IEC 14443 B Read/Write modes  Typical operating distance in Read/Write mode up to 50 mm depending on the

antenna size and tuning

 Typical operating distance in NFCIP-1 mode up to 50 mm depending on the antenna

size and tuning and power supply

 Typical operating distance in ISO/IEC 14443A/MIFARE card or FeliCa Card Op eration

mode of about 100 mm depending on the antenna size and tuning and the external field strength

 Supports MIFARE 1K or MIFARE 4K emulation encryption in Reader/Writer mode  ISO/IEC 14443A higher transfer speed communication at 212 kbit/s and 424 kbit/s  Contactless communication according to the FeliCa scheme at 212 kbit/s and

424 kbit/s

 In te gr at ed RF int er fa ce fo r NF CIP- 1 up to 424 kbit/s

C interface

 S  Additional power supply to directly supply the smart card IC connected via S  Su pp or te d ho st inter fa ce s

 SPI up to 10 Mbit/s

C-bus interface up to 400 kBd in Fast mode, up to 3400 kBd in High-speed mode

 I  RS232 Serial UART up to 1228.8 kBd, with voltage levels dependant on pin

voltage supply

 8-bit parallel interface with and without Address Latch Enable  FIFO buffer handles 64 byte send and receive  Flexible interrupt modes  Hard reset with low power function  Power-down mode per software  Programmable timer  Internal oscillator for connection to 27.12 MHz quartz crystal  2. 5 V to 3.6 V power supply  CRC coprocessor  Programmable I/O pins  Internal self-t es t

PN512

Transm ission module

Product data sheet COMPANY PUBLIC

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4. Quick reference data

PN512

Transm ission module

Table 1. Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

DDA

DDD

DD(TVDD)

DD(PVDD)

DD(SVDD)

DDD

DDA

analog supply voltage V digital supply voltage

DD(PVDD)

SSA=VSSD=VSS(PVSS)=VSS(TVSS)

 V

TVDD supply voltage PVDD supply voltage SVDD supply voltage V power-down current V

SSA=VSSD=VSS(PVSS)=VSS(TVSS) DDA=VDDD

hard power-down; pin NRSTPD set LOW

soft power-down; RF level detector on digital supply current pin DVDD; V analog supply current pin AVDD; V

DDA

= V

DDD

= V

DD(TVDD)

;

=0V

= 0 V 1.6 - 3.6 V

= V

DD(TVDD)

=3V - 6.5 9 mA

DDD

= 3 V, CommandReg register’s

DDA

DD(PVDD)

=3V

[1][2]

2.5 - 3.6 V

[3]

1.6 - 3.6 V

[4]

--5A

[4]

--10A

-710mA

RcvOff bit = 0 pin AVDD; receiver switched off; V

DDA

=3V,

-35mA

CommandReg register’s RcvOff bit = 1

DD(PVDD)

DD(TVDD)

amb

PVDD supply current pin PVDD TVDD supply current pin TVDD; continuous wave ambient temperature HVQFN32, HVQFN40 30 +85 C

[5]

--40mA

[6][7][8]

-60100mA

lndustrial version:

amb

power-down current V

DDA=VDDD

hard power-down; pin NRSTPD set LOW

soft power-down; RF level detector on

= V

DD(TVDD)

DD(PVDD)

=3V

[4]

--15A

[4]

--30A

ambient temperature HVQFN32 40 - +90 C

[1] Supply voltages below 3 V reduce the performance in, for example, the achievable operating distance. [2] V [3] V [4] I [5] I [6] I [7] During typical circuit operation, the overall current is below 100 mA. [8] Typical value using a complementary driver configuration and an antenna matched to 40  between pins TX1 and TX2 at 13.56 MHz.

Product data sheet COMPANY PUBLIC

, V

DDA DD(PVDD)

is the total current for all supplies.

pd DD(PVDD) DD(TVDD)

and V

DDD

must always be the same or lower voltage than V

depends on the overall load at the digital pins. depends on V

must always be the same voltage.

DD(TVDD)

and the external circuit connected to pins TX1 and TX2.

DD(TVDD)

DDD

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5. Ordering information

PN512

Transm ission module

Table 2. Ordering information

Type number Package

PN5120A0HN1/C2 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;

PN5120A0HN/C2 HVQFN40 plastic therma l enhanced very thin quad flat package; no leads;

PN512AA0HN1/C2 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;

PN512AA0HN1/C2BI HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;

PN5120A0HN1/C1 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;

PN5120A0HN/C1 HVQFN40 plastic therma l enhanced very thin quad flat package; no leads;

Name Description Version

32 terminal; body 5  5  0.85 mm

40 terminals; body 6  6  0.85 mm

32 terminal; body 5  5  0.85 mm

40 terminals; body 6  6  0.85 mm

SOT617-1

SOT618-1

SOT617-1

SOT618-1

Product data sheet COMPANY PUBLIC

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001aaj627

HOST

ANTENNA

FIFO

BUFFER

ANALOG

INTERFACE

CONTACTLESS

UART

SERIAL UART

SPI

C-BUS

6. Block diagram

The analog interface handles the modulation and demodulation of the analog signals according to the Card Receiving mode, Reader/Writer mode and NFCIP-1 mode communication scheme.

The RF level detector detects the presence of an external RF-field delivered by the antenna to the RX pin.

The Data mode detector detects a MIFARE, FeliCa or NFCIP-1 mode in order to prepare the internal receiver to demodulate signals, which are sent to the PN512.

The communication (S transfer speeds above 424 kbit/s and digital signals to communicate to a secure IC.

The contactless UART manages the protocol requirements for the communication protocols in cooperation with the host. The FIFO buffer ensures fast and convenient data transfer to and from the host and the contactless UART and vice versa.

Various host interfaces are implemented to meet different customer requirements.

PN512

Transm ission module

C) interface provides digital signals to support communication for

Fig 1. Simplified block diagram of the PN512

Product data sheet COMPANY PUBLIC

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DVDD

NRSTPD

IRQ

MFIN MFOUT SVDD

OSCIN

OSCOUT

VMID AUX1

AUX2

RX TVSS TX1 TX2 TVDD

16 19

17 10, 14 11 13 12

DVSS

AVDD

PVSSPVDDSDA/NSS/RX EA I2C

5224 32 1

D1/ADR_5

D2/ADR_4

D3/ADR_3

D4/ADR_2

D5/ADR_1/ SCK/DTRQ

D6/ADR_0/

MOSI/MX

D7/SCL/

MISO/TX

AVSS

7 8 9

15 18

FIFO CONTROL

MIFARE CLASSIC UNIT

STATE MACHINE

COMMAND REGISTER

PROGRAMABLE TIMER

INTERRUPT CONTROL

CRC16

GENERATION AND CHECK

PARALLEL/SERIAL

CONVERTER

SERIAL DATA SWITCH

TRANSMITTER CONTROL

BIT COUNTER PARITY GENERATION AND CHECK FRAME GENERATION AND CHECK

BIT DECODING BIT ENCODING

RANDOM NUMBER

GENERATOR

ANALOG TO DIGITAL

CONVERTER

I-CHANNEL AMPLIFIER

ANALOG TEST MULTIPLEXOR

AND

DIGITAL TO

ANALOG

CONVERTER

I-CHANNEL

DEMODULATOR

Q-CHANNEL

AMPLIFIER

CLOCK

GENERATION,

FILTERING AND

DISTRIBUTION

Q-CLOCK

GENERATION

OSCILLATOR

TEMPERATURE

SENSOR

Q-CHANNEL

DEMODULATOR

AMPLITUDE

RATING

REFERENCE

VOLTAGE

64-BYTE FIFO

BUFFER

CONTROL REGISTER

BANK

SPI, UART, I2C-BUS INTERFACE CONTROL

VOLTAGE MONITOR

AND

POWER ON

DETECT

RESET

CONTROL

POWER-DOWN

CONTROL

PN512

Transm ission module

Fig 2. Detailed block diagram of the PN512

Product data sheet COMPANY PUBLIC

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001aan212

PN512

Transparent top view

SIGIN

SIGOUT

AVSS

NRSTPD AUX1

PVSS AUX2

DVSS OSCIN

DVDD OSCOUT

PVDD IRQ

A1 ALE

SVDD

TVSS

TX1

TVDD

TX2

TVSS

AVDD

VMID

A0D7D6D5D4D3D2

8 17

7 18

6 19

5 20

4 21

3 22

2 23

1 24

10111213141516

32313029282726

terminal 1

index area

001aan213

PN512

AVSS

NRSTPD

SIGIN

AUX1

PVSS AUX2

DVSS OSCIN

DVDD OSCOUT

PVDD IRQ

A5 NWR

A4 NRD

A3 ALE

A2 NCS

SIGOUT

SVDD

TVSS

TX1

TVDD

TX2

TVSS

AVDD

VMID

A1A0D7D6D5D4D3D2D1

10 21

9 22

8 23

7 24

6 25

5 26

4 27

3 28

2 29

1 30

111213141516171819

403938373635343332

terminal 1

index area

Transparent top view

7. Pinning information

7.1 Pinning

PN512

Transm ission module

Fig 3. Pinning configuration HVQFN32 (SOT617-1)

Product data sheet COMPANY PUBLIC

Fig 4. Pinning configuration HVQFN40 (SOT618-1)

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PN512

Transm ission module

7.2 Pin description

Table 3. Pin description HVQFN32

Pin Symbol Type Description

1A1IAddress Line 2 PVDD PWR Pad power supply 3DVDDPWRDigital Power Supply 4 DVSS PWR Digital Ground 5 PVSS PWR Pad power supply ground 6 NRSTPD I Not Reset and Power Down: When LOW, intern al current sinks are switched off, the

7 SIGIN I Communication Interface Input: accepts a digital, serial data stream 8 SIGOUT O Communication Interface Output: delivers a serial data stream 9 SVDD PWR S2C Pad Power Supply: provides power to the S 10 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2 11 TX1 O Transmitter 1: delivers the modulated 13.56 MHz energy carrier 12 TVDD PWR Transmitter Power Supply: supplies the output stage of TX1 and TX2 13 TX2 O Transmitter 2: delivers the modulated 13.56 MHz energy carrier 14 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2 15 AVDD PWR Analog Power Supply 16 VMID PWR Internal Reference Voltage: This pin delivers the internal reference voltage. 17 RX I Receiver Input 18 AVSS PWR Analog Ground 19 AUX1 O Auxiliary Outputs: These pins are used for testing. 20 AUX2 O 21 OSCIN I Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is

22 OSCOUT O Crystal Oscillator Output: Output of the inverting amplifier of the oscillator. 23 IRQ O Interrupt Request: output to signal an interrupt event 24 ALE I Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch

25 to 31 D1 to D7 I/O 8-bit Bi-directional Data Bus.

32 A0 I Address Line

oscillator is inhibited, and the input pads are disconnected from the outside world. With a positive edge on this pin the internal reset phase starts.

C pads

also the input for an externally generated clock (f

= 27.12 MHz).

osc

when HIGH.

Remark: An 8-bit parallel interface is not available.

Remark: If the host controller selects I can be used to define the I

C address.

C as digital host controller interface, these pins

Remark: For serial interfaces this pins can be used for test signals or I/Os.

Product data sheet COMPANY PUBLIC

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NXP Semiconductors

PN512

Transm ission module

Table 4. Pin description HVQFN40

Pin Symbol Type Description

1 to 4 A2 to A5 I Address Line 5 PVDD PWR Pad power supply 6DVDDPWRDigital Power Supply 7 DVSS PWR Digital Ground 8 PVSS PWR Pad power supply ground 9 NRSTPD I Not Reset and Power Down: When LOW, intern al current sinks are switched off, the

oscillator is inhibited, and the input pads are disconnected from the outside world. With

a positive edge on this pin the internal reset phase starts. 10 SIGIN I Communication Interface Input: acce pts a digital, serial data stream 11 SIGOUT O Communica tion Interface Output: delivers a serial data stream

12 SVDD PWR S

C Pad Power Supply: provides power to the S2C pads

13 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2 14 TX1 O Transmitter 1: delivers the modulated 13.56 MHz energy carrier 15 TVDD PWR Transmitter Power Supply: supplies the output stage of TX1 and TX2 16 TX2 O Transmitter 2: delivers the modulated 13.56 MHz energy carrier 17 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2 18 AVDD PWR Analog Power Supply 19 VMID PWR Internal Reference Voltage: This pin delivers the internal reference voltage. 20 RX I Receiver Input 21 AVSS PWR Analog Ground 22 AUX1 O Auxiliary Outputs: These pins are used for testing. 23 AUX2 O 24 OSCIN I Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is

also the input for an externally generated clock (f

= 27.12 MHz).

osc

25 OSCOUT O Crystal Oscillator Output: Output of the inverting amplifier of the oscillator. 26 IRQ O Interrupt Request: output to signal an interrupt event 27 NWR I Not Write: strobe to write data (applied on D0 to D7) into the PN512 register 28 NRD I Not Read: strobe to read data from the PN512 register (applied on D0 to D7) 29 ALE I Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch

when HIGH. 30 NCS I Not Chip Select: selects and activates the host controller interface of the PN512 31 to 38 D0 to D7 I/O 8-bit Bi-directional Data Bus.

Remark: For serial interfaces this pins can be used for test signals or I/Os.

Remark: If the host controller selects I

C as digital host controller interface, these pins

can be used to define the I2C address. 39 to 40 A0 to A1 I Address Line

Product data sheet COMPANY PUBLIC

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001aan218

BATTERY

reader/writer

contactless card

MICROCONTROLLER

PN512

ISO/IEC 14443 A CARD

(1)

(2)

001aan219

PN512

ISO/IEC 14443 A CARD

ISO/IEC 14443 A

READER

8. Functional description

The PN512 transmission module supports the Read/Write mode for ISO/IEC 14443 A/MIFARE and ISO/IEC 14443 B using various transfer speeds and modulation protocols.

PN512 transceiver IC supports the following operating modes:

• Reader/Writer mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme

• Card Operation mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme

• NFCIP-1 mode

The modes support different transfer speeds and modulation schemes. The following chapters will explain the different modes in detail.

Note: All indicated modulation indices and modes in this chapter are system parameters. This means that beside the IC settings a suitable antenna tuning is require d to achieve the optimum performance.

PN512

Transm ission module

Fig 5. PN512 Read/Write mode

8.1 ISO/IEC 14443 A/MIFARE functionality

The physical level communication is shown in Figure 6.

Fig 6. ISO/IEC 14443 A/MIFARE Read/Write mode communication diagram

The physical parameters are described in Table 4.

T able 5. Communication overview for ISO/IEC 14443 A/MIFARE reader/writer

Communication direction

Reader to card (send data from the PN512 to a card)

Signal type Transfer speed

106 kBd 212 kBd 424 kBd

reader side

100 % ASK 100 % ASK 100 % ASK

modulation bit encoding modified Miller

encoding

modified Miller encoding

bit length 128 (13.56 s) 64 (13.56 s) 32 (13.56 s)

modified Miller encoding

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001aak585

ISO/IEC 14443 A framing at 106 kBd

8-bit data 8-bit data 8-bit data

odd

parity

odd

parity

start

odd

parity

start bit is 1

ISO/IEC 14443 A framing at 212 kBd, 424 kBd and 848 kBd

8-bit data 8-bit data 8-bit data

odd

parity

odd

parity

start

even

parity

start bit is 0

burst of 32

subcarrier clocks

even parity at the

end of the frame

PN512

Transm ission module

T able 5. Communication overview for ISO/IEC 14443 A/MIFARE reader/writer

Communication direction

Card to reader (PN512 receives data from a card)

Signal type Transfer speed

106 kBd 212 kBd 424 kBd

card side modulation

subcarrier

subcarrier load modulation

13.56 MHz/16 13.56 MHz/16 13 .56 MHz/16

subcarrier load modulation

…continued

subcarrier load modulation

frequency bit encoding Manchester

BPSK BPSK

encoding

The PN512’s contactless UART and dedicated external host must manage the complete ISO/IEC 14443 A/MIFARE protocol. Figure 7

shows the data coding and framing

according to ISO/IEC 14443 A/MIFARE.

Fig 7. Data coding and framing according to ISO/IEC 14443 A

The internal CRC coprocessor calculates the CRC value based on ISO/IEC 14443 A part 3 and handles parity generation internally according to the transfer speed. Automatic parity generation can be switched off using th e ManualRCVReg register’s ParityDisable bit.

8.2 ISO/IEC 14443 B functionality

The MFRC523 reader IC fully supports international standard ISO 14443 which includes communication schemes ISO 14443 A and ISO 14443 B.

Refer to the ISO 14443 reference documents Identification cards - Contactless integrated circuit cards - Proximity cards (parts 1 to 4).

Product data sheet COMPANY PUBLIC

Remark: NXP Semiconductors does not of fer a soft ware library to enable design -in of the

ISO 14443 B protocol.

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2. PICC to PCD, > 12 % ASK loadmodulation Manchester coded, baudrate 212 to 424 kbaud

1. PCD to PICC, 8-30 % ASK Manchester coded, baudrate 212 to 424 kbaud

001aan214

PN512

FeliCa CARD

(PICC)

Felica READER

(PCD)

8.3 FeliCa reader/writer functionality

The FeliCa mode is the general reader/writer to card communication scheme according to the FeliCa specification. The following diagram describes the communication on a physical level, the communication overview describes the physical parameters.

Fig 8. FeliCa reader/writer communication diagram

Table 6. Communication overview for FeliCa reader/writer

Communication direction

PN512  card Modulation on reader side 8-30 % ASK 8-30 % ASK

card  PN512 Loadmodulation on card side > 12 % ASK > 12 % ASK

PN512

Transm ission module

FeliCa FeliCa Higher

transfer speeds

Transfer speed 212 kbit/s 424 kbit/s

bit coding Manchester Coding Manchester Coding Bitlength (64/13.56) s (32/13.56) s

bit coding Manchester coding Manchester coding

The contactless UART of PN512 and a dedicated external host controller are required to handle the complete FeliCa protocol.

8.3.1 FeliCa framing and coding

Table 7. FeliCa framing and coding

Preamble Sync Len n-Data CRC

00h 00h 00h 00h 00h 00h B2h 4Dh

To enable the FeliCa communication a 6 byte preamble (00h, 00h, 00h, 00h, 00h, 00h) and 2 bytes Sync bytes (B2h, 4Dh) are sent to synchronize the receiver.

The following Len byte indicates the length of the se nt dat a b ytes plus the LEN byte itself. The CRC calculation is done according to the FeliCa definitions with the MSB first.

To transmit data on the RF interface, the host controller has to send the Len- and databytes to the PN512's FIFO-buffer. The preamble and the sync bytes are generated by the PN512 automatically and must not be written to the FIFO by the host controller. The PN512 performs internally the CRC calculation and adds the result to the data frame.

Example for FeliCa CRC Calculation:

Table 8. Start value for the CRC Polynomial: (00h), (00h)

Preamble Sync Len 2 Data Bytes CRC

00h 00h 00h 00h 00h 00h B2h 4Dh 03h ABh CDh 90h 35h

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001aan215

BATTERY

initiator: active target:

passive or active

MICROCONTROLLER

PN512

BATTERY

MICROCONTROLLER

PN512

8.4 NFCIP-1 mode

The NFCIP-1 communication differentiates between an active and a Passive Communication mode.

• Active Communication mode means both the initiator and the target are using their

• Passive Communication mode means that the target answers to an initiator command

• Initiator: generates RF field at 13.56 MHz and starts the NFCIP-1 communication

• Target: responds to initiator command either in a load modulation scheme in Passive

In order to fully support the NFCIP-1 standard the PN512 supports the Active and Passive Communication mode at the transfer speeds 106 kbit/s, 212 kbit/s and 42 4 kbit/s as defined in the NFCIP-1 standard.

PN512

Transm ission module

own RF field to transmit data.

in a load modulation scheme. The initiator is active in terms of generating the RF field.

Communication mode or using a self generat ed and self modulated RF field for Active Communication mode.

Fig 9. NFCIP-1 mode

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host

NFC INITIATOR

powered to

generate RF field

1. initiator starts communication at selected transfer speed

Initial command

response

2. target answers at the same transfer speed

host

NFC INITIATOR

powered for digital

processing

host

NFC TARGET

powered for

digital processing

powered to

generate RF field

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8.4.1 Active communication mode

Active communication mode means both the initiator and the target are using their own RF field to transmit data.

PN512

Transm ission module

Fig 10. Active communication mode

Table 9. Communication overview for Active communication mode

Communication direction

Initiator  Target According to Target  Initiator

106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s 1.69 Mbit/s,

3.39 Mbit/s

ISO/IEC 14443A

According to FeliCa, 8-30 % ASK Manchester Coded

digital capability to handle

this communication 100 % ASK, Modified Miller Coded

The contactless UART of PN512 and a dedicated host controller are required to handle the NFCIP-1 protocol.

Note: Transfer Speeds above 424 kbit/s are not defined in the NFCIP-1 standard. The PN512 supports these transfer speeds only with dedicated extern al circuits.

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host

NFC INITIATOR

powered to

generate RF field

1. initiator starts communication at selected transfer speed

2. targets answers using load modulated data at the same transfer speed

host

NFC TARGET

powered for

digital processing

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8.4.2 Passive communication mode

Passive Communication mode means that the target answers to an initiator command in a load modulation scheme. The initiator is active meaning generating the RF field.

Fig 11. Passive communication mode

Table 10. Communication overview for Passive communication mod e

Communication direction

Initiator  Target According to

Target  Initiator According to

PN512

Transm ission module

106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s 1.69 Mbit/s,

3.39 Mbit/s

ISO/IEC 14443A 100 % ASK, Modified Miller Coded

ISO/IEC 14443A subcarrier load modulation, Manchester Coded

According to FeliCa, 8-30 % ASK Manchester Coded

According to FeliCa, > 12 % ASK Manchester Coded

digital capability to handle

this communication

The contactless UART of PN512 and a dedicated host controller are required to handle the NFCIP-1 protocol.

Note: Transfer Speeds above 424 kbit/s are not defined in the NFCIP-1 standard. The PN512 supports these transfer speeds only with dedicated extern al circuits.

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8.4.3 NFCIP-1 framing and coding

The NFCIP-1 framing and coding in Active and Passive Communication mode is defined in the NFCIP-1 standard.

Table 11. Framing and coding overview

Transfer speed Framing and Coding

106 kbit/s According to the ISO/IEC 14443A/MIFARE scheme 212 kbit/s According to the FeliCa scheme 424 kbit/s According to the FeliCa scheme

8.4.4 NFCIP-1 protocol support

The NFCIP-1 protocol is not completely described in this document. For detailed explanation of the protocol refer to the NFCIP-1 standard. However the datalink layer is according to the following policy:

• Speed shall not be changed while continuum data exchange in a transaction.

• Transaction includes initialization and anticollision methods and data exchange (in

PN512

Transm ission module

continuous way, meaning no interruption by another transaction).

In order not to disturb current infrastructure based on 13.56 MHz general rules to start NFCIP-1 communication are defined in the following way.

1. Per default NFCIP-1 device is in Target mode meaning its RF field is switched off.

2. The RF level detector is active.

3. Only if application requires the NFCIP-1 device shall switch to Initiator mode.

4. Initiator shall only switch on its RF field if no external RF field is detected by RF Level detector during a time of TIDT.

5. The initiator performs initialization according to the selected mode.

8.4.5 MIFARE Card operation mode

T able 12. MIFARE Card operation mode

Communication direction

transfer speed 106 kbit/s 212 kbit/s 424 kbit/s

reader/writer  PN512

PN512  reader/ writer

Modulation on reader side

bit coding Modified Miller Modified Miller Modified Miller Bitlength (128/13.56) s (64/13.56) s (32/13.56) s Modulation on

PN512 side subcarrier

frequency bit coding Manchester coding BPSK BPSK

ISO/IEC 14443A/ MIFARE

100 % ASK 100 % ASK 100 % ASK

subcarrier load modulation

13.56 MHz/16 13.56 MHz/16 13.56 MHz/16

MIFARE Higher transfer speeds

subcarrier load modulation

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8.4.6 FeliCa Card operation mode

Table 13. FeliCa Card operation mode

Communication direction

reader/writer  PN512

PN512  reader/ writer

9. PN512 register SET

9.1 PN512 registers overview

Table 14. PN512 registers overview

Addr (hex)

Page 0: Command and Status

0 PageReg Selects the register page 1 CommandReg Starts and stops command execution 2 ComlEnReg Controls bits to enable and disable the passing of Interrupt Requests 3 DivlEnReg Controls bits to enable and disa ble the passing of Interrupt Requests 4 ComIrqReg Contains Interrupt Request bits 5 DivIrqReg Contains Interrupt Request bits 6 ErrorReg Error bits showing the error status of the last command executed 7 St a tus1Reg Cont ains st atus bits for communication 8 St a tus2Reg Cont ains st atus bits of the receiver and transmitter 9 FIFODataReg In- and output of 64 byte FIFO-buffer A FIFOLevelReg Indicates the number of bytes stored in the FIFO B WaterLevelReg Defines the level for FIFO under- and overflow warning C ControlReg Contains miscellaneous Control Registers D BitFramingReg Adjustments for bit oriented frames E CollReg Bit positi on of the first bit collision detected on the RF-interface F RFU Reserved for future use

Page 1: Command

0 PageReg Selects the register page 1 ModeReg Defines general modes for transmitting and receiving 2 TxModeReg Defines the data rate and framing during transmission 3 RxModeReg Defines the data rate and framing during receiving 4 TxControlReg Controls the logical behavior of the antenna driver pins T X1 and TX2 5 TxAutoReg Controls the setting of the antenna drivers

PN512

Transm ission module

FeliCa FeliCa Higher

transfer speeds

Transfer speed 212 kbit/s 424 kbit/s

Modulation on reader side 8-30 % ASK 8-30 % ASK bit coding Manchester Coding Manchester Coding Bitlength (64/13.56) s (32/13.56) s Load modulation on PN512

side bit coding Manchester coding Manchester coding

> 12 % ASK load modulation

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PN512

Transm ission module

Table 14. PN512 registers overview

Addr (hex)

6 TxSelReg Selects the internal sources for the antenna driver 7 RxSelReg Selects internal receiver settings 8 RxThresholdReg Selects thresholds for the bit decoder 9 DemodReg Defines demodulator settings A FelNFC1Reg Defines the length of the valid range for the receive package B FelNFC2Reg Defines the length of the valid range for the receive package C MifNFCReg Controls the communication in ISO/IEC 14443/MIFARE and NFC

D ManualRCVReg Allows manual fine tuning of the internal receiver E TypeBReg Configure th e ISO/IEC 14443 type B F SerialSpeedReg Selects the speed of the serial UART interface

Page 2: CFG

0 PageReg Selects the register page 1 CRCResultReg Shows the actual MSB and LSB values of the CRC calculation 2 3 GsNOffReg Selects the conductance of the antenna driver pins TX1 and TX2 for

4 ModWidthReg Controls the setting of the ModWidth 5 TxBitPhaseReg Adjust the TX bit phase at 106 kbit 6 RFCfgReg Configures the receiver gain and RF level 7 GsNOnReg Selects the conductance of the antenna driver pins TX1 and TX2 for

8 CWGsPReg Selects the conductance of the antenna driver pins TX1 and TX2 for

9 ModGsPReg Selects the conductance of the antenna driver pins TX1 and TX2 for

A TModeReg B C TReloadReg Describes the 16-bit timer reload value D E TCounterValReg Shows the 16-bit actual timer value F

Page 3: TestRegister

0 PageReg selects the register page 1 TestSel1Reg General test signal configuration 2 TestSel2Reg General test signal configuration and PRBS control 3 TestPinEnReg Enables pin output driver on 8-bit parallel bus (Note: For serial

4TestPin

5 TestBusReg Shows the status of the internal testbus 6 AutoTestReg Controls the digital selftest

target mode at 106 kbit

modulation, when the driver is switched off

modulation when the drivers are switched on

modulation during times of no modulation

modulation during modulation Defines settings for the internal timer

TPrescalerReg

interfaces only) Defines the values for the 8-bit parallel bus when it is used as I/O bus

ValueReg

…continued

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PN512

Transm ission module

Table 14. PN512 registers overview

Addr (hex)

7 VersionReg Shows the version 8 AnalogTestReg Controls the pins AUX1 and AUX2 9 TestDAC1Reg Defines the test value for the TestDAC1 A TestDAC2Reg Defines the test value for the TestDAC2 B TestADCReg Shows th e actual value of ADC I and Q C-F RFT Reserved for production tests

9.1.1 Register bit behavior

Depending on the functionality of a register , the access conditions to the register can vary. In principle bits with same behavior are grouped in co mmon registers. In Table 15 access conditions are described.

Table 15. Behavior of register bits and its designation

Abbreviation Behavior Description

r/w read and write These bits can be written and read by the -Controller. Since they

dy dynamic These bits can be written and read by the -Controller.

r read only These registers hold bits, which value is determined by internal

w write only Reading these registers returns always ZERO. RFU - These registers are reserved for future use.

RFT - These registers are reserved for production tests and shall not be

…continued

the

are used only for control means, there content is not influenced by internal state machines, e.g. the PageSelect-Register may be written and read by the -Controller. It will also be read by internal state machines, but never changed by them.

Nevertheless, they may also be written automatically by internal state machines, e.g. the Command-Register changes its value automatically after the execution of the actual command.

states only, e.g. the CRCReady bit can not be written from external but shows internal states.

In case of a PN512 Version version 2.0 (VersionReg = 82h) a read access to these registers returns always the value “0”. Nevertheless this is not guaranteed for future chips versions where the value is undefined. In case of a write access, it is recommended to write always the value “0”.

changed.

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9.2 Register description

9.2.1 Page 0: Command and status

9.2.1.1 PageReg

Selects the register page.

Table 16. PageReg register (address 00h); reset value: 00h, 0000000b

Access Rights

Table 17. Description of PageReg bits

Bit Symbol Description

7 UsePageSelect Set to logic 1, the value of PageSelect is used as register address A5

6 to 2 - Reserved for future use. 1 to 0 PageSelect The value of PageSelect is used only if UsePageSelect is set to

PN512

Transm ission module

7 6 5 4 3 2 1 0

UsePage Select 0 0 0 0 0 PageSelect

r/w RFU RFU RFU RFU RFU r/w r/w

and A4. The LSB-bits of the register address are defined by the address pins or the internal address latch, respectively.

Set to logic 0, the whole content of the internal address latch de fines the register address. The address pins are used as described in

Section 10.1 “

logic 1. In this case it specifies the register page (which is A5 and A4 of the register address).

Automatic microcontroller interface detection”.

9.2.1.2 CommandReg

Starts and stops command execution.

Table 18. CommandReg register (address 01h); reset value: 20h, 00100000b

Access Rights

Table 19. Description of CommandReg bits

Bit Symbol Description

7 to 6 - Reserved for future use. 5 RcvOff Set to logic 1, the analog part of the receiver is switched off. 4 PowerDown Set to logic 1, Soft Power-down mode is entered.

3 to 0 Command Activates a command according to the Command Code. Reading this

RFURFUr/w dy dydydydy

7 6 5 4 3 2 1 0

0 0 RcvOff Power Down Command

Set to logic 0, the PN512 starts the wake up procedure. During this procedure this bit still shows a 1. A 0 indicates that the PN512 is ready for operations; see Section 16.2 “

Soft power-down mode”.

Note: The bit Power Down cannot be set, when the command SoftReset has been activated.

“PN512 command overview”).

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9.2.1.3 CommIEnReg

Control bits to enable and disable the passing of interrupt requests.

Table 20. CommIEnReg register (address 02h); reset value: 80h, 10000000b

Access Rights

Table 21. Description of CommIEnReg bits

Bit Symbol Description

7 IRqInv Set to logic 1, the signal on pin IRQ is inverted with respect to bit IRq in the

6 TxIEn Allows the transmitter interrupt request (ind i cat e d by bit TxIRq) to be

5 RxIEn Allows the receiver interrupt request (indicated by bit RxIRq) to be

4 IdleIEn Allows the idle interrupt request (indicated by bit IdleIRq) to be propagated to

3 HiAlertIEn Allows the high alert interrupt request (indicated by bit HiAlertIRq) to be

2 LoAlertIEn Allows the low alert interrupt request (indicated by bit LoAlertIRq) to be

1 ErrIEn Allows the error interrupt request (indicated by bit ErrIRq) to be propagated

0 TimerIEn Allows the timer interrupt request (indicated by bit TimerIRq) to be

PN512

Transm ission module

7 6 5 4 3 2 1 0

IRqInv TxIEn RxIEn IdleIEn HiAlertIEn LoAlertIEn ErrIEn TimerIEn

r/w r/w r/w r/w r/w r/w r/w r/w

register Status1Reg. Set to logic 0, the signal on pin IRQ is equal to bit IRq. In combination with bit IRqPushPull in register DivIEnReg, the default value of 1 ensures, that the output level on pin IRQ is 3-state.

propagated to pin IRQ.

pin IRQ.

propagated to pin IRQ.

to pin IRQ.

propagated to pin IRQ.

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9.2.1.4 DivIEnReg

Control bits to enable and disable the passing of interrupt requests.

Table 22. DivIEnReg register (address 03h); reset value: 00h, 00000000b

Access Rights

Table 23. Description of DivIEnReg bi ts

Bit Symbol Description

7 IRQPushPull Set to logic 1, the pin IRQ works as standard CMOS output pad.

6 to 5 - Reserved for future use. 4 SiginActIEn Allows the SIGIN active inte rrupt request to be propagated to pin IRQ. 3 ModeIEn Allows the mode interrupt request (indicated by bit ModeIRq) to be

2 CRCIEn Allows the CRC interrupt request (indicated by bit CRCIRq) to be

1 RfOnIEn Allows the RF field on interrupt request (indicated by bit RfOnIRq) to

0 RfOffIEn Allows the RF field off interrupt request (indicated by bit RfOffIRq) to

PN512

Transm ission module

7 6 5 4 3 2 1 0

IRQPushPull 0 0 SiginActIEn ModeIEn CRCIEn RFOnIEn RFOffIEn

r/w RFU RFU r/w r/w r/w r/w r/w

Set to logic 0, the pin IRQ works as open drain output pad.

propagated to pin IRQ.

be propagated to pin IRQ.

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9.2.1.5 CommIRqReg

Contains Interrupt Request bits.

Table 24. CommIRqReg register (address 04h); rese t value: 14h, 00010100b

Access Rights

Table 25. Description of CommIRqR eg bits

All bits in the register CommIRqReg shall be cleared by software.

Bit Symbol Description

7 Set1 Set to logic 1, Set1 defines that the marked bits in the register CommIRqReg

6 TxIRq Set to logic 1 immediately after the last bit of the transmitted data was sent out. 5 RxIRq Set to logic 1 when the receiver detects the end of a valid datastream.

4 IdleIRq Set to logic 1, when a command terminates by itself e.g. when the

3 HiAlertIRq Set to logic 1, when bit HiAlert in register Status1Reg is set. In opposition to

2 LoAlertIRq Set to logic 1, when bit LoAl ert in register Status1Reg is set. In opposition to

1 ErrIRq Set to logic 1 if any error bit in the Error Register is set. 0 TimerIRq Set to logic 1 when the timer decrements the TimerValue Register to zero.

PN512

Transm ission module

7 6 5 4 3 2 1 0

Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq

wdydydy dy dy dydy

are set. Set to logic 0, Set1 defines, that the marked bits in the register CommIRqReg

are cleared.

If the bit RxNoErr in register RxModeReg is set to logic 1, bit RxIRq is only set to logic 1 when data bytes are available in the FIFO.

CommandReg changes its value from any command to the Idle Command. If an unknown command is started, the CommandReg changes its content to

the idle state and the bit IdleIRq is set. Starting the Idle Command by the -Controller does not set bit IdleIRq.

HiAlert, HiAlertIRq stores this event and can only be reset as indicated by bit Set1.

LoAlert, LoAlertIRq stores this event and can only be reset as indicated by bit Set1.

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9.2.1.6 DivIRqReg

Contains Interrupt Request bits

Table 26. DivIRqReg register (address 05h); reset value: XXh, 000X00XXb

Access Rights

Table 27. Description of DivIRqReg bits

All bits in the register DivIRqReg shall be cleared by software.

Bit Symbol Description

7 Set2 Set to logic 1, Set2 defines that the marked bits in the register

6 to 5 - Reserved for future use. 4 SiginActIRq Set to logic 1, when SIGIN is active. See Section 12.6 “

3 ModeIRq Set to logic 1, when the mode has been detected by the Data mode

2 CRCIRq Set to logic 1, when the CRC command is active and all data are

1 RFOnIRq Set to logic 1, when an external RF field is detected. 0 RFOffIRq Set to logic 1, when a present external RF field is switched off.

PN512

Transm ission module

7 6 5 4 3 2 1 0

Set2 0 0 SiginActIRq ModeIRq CRCIRq RFOnIRq RFOffIRq

wRFURFU dy dy dy dy dy

DivIRqReg are set. Set to logic 0, Set2 defines, that the marked bits in the register

DivIRqReg are cleared

S2C interface support”. This interrupt is set when either a rising or falling signal edge

is detected.

detector. Note: The Data mode detector can only be activated by the AutoColl

command and is terminated automatically having detected the Communication mode.

Note: The Data mode detector is automatically restarted after each RF Reset.

processed.

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9.2.1.7 ErrorReg

Error bit register showing the error status of the last command executed.

Table 28. ErrorReg register (address 06h); reset value: 00h, 00000000b

Access Rights

Table 29. Description of ErrorReg bits

Bit Symbol Description

7 WrErr Set to logic 1, when data is written into FIFO by the host controller

6 TempErr

5 RFErr Set to logic 1, if in Active Communication mode the counterpart does

4 BufferOvfl Set to logic 1, if the host controller or a PN512’s internal state machine

3 CollErr Set to logic 1, if a bit-collision is detected. It is cleared automatically at

2 CRCErr Set to logic 1, if bit RxCRCEn in register RxModeReg is set and the

1 ParityErr Set to logic 1, if the parity check has failed. It is cleared automatically

0 ProtocolErr Set to logic 1, if one out of the following cases occur:

PN512

Transm ission module

7 6 5 4 3 2 1 0

WrErr TempErr RFErr BufferOvfl CollErr CRCErr ParityErr ProtocolErr

rrrrrrr r

during the AutoColl command or MFAuthent command or if data is written into FIFO by the host controller during the time between sending the last bit on the RF interface and receiving the last bit on the RF interface.

[1]

Set to logic 1, if the internal temperature sensor detects overheating. In this case, the antenna drivers are switched off automatically.

not switch on the RF field in time as defined in NFCIP-1 standard. Note: RFErr is only used in Active Communication mode. The bits

RxFraming or the bits TxFraming has to be set to 01 to enable this functionality.

(e.g. receiver) tries to write data into the FIFO-bufferFIFO-buffer although the FIFO-buffer is already full.

receiver start-up phase. This bit is only valid during the bitwise anticollision at 106 kbit. During communication sch emes at 212 and 424 kbit this bit is always set to logic 1.

CRC calculation fails. It is cleared to 0 automatically at receiver start-up phase.

at receiver start-up phase. Only valid for ISO/IEC 14443A/MIFARE or NFCIP-1 communication at 106 kbit.

• Set to logic 1 if the SOF is incorrect. It is cleared automatically at

receiver start-up phase. The bit is only valid for 106 kbit in Active and Passive Communication mode.

• If bit DetectSync in register ModeReg is set to logic 1 during

FeliCa communication or active communication with transfer speeds higher than 106 kbit, the bit ProtocolErr is set to logic 1 in case of a byte length violation.

• During the AutoColl command, bit ProtocolErr is set to logic 1, if

the bit Initiator in register ControlReg is set to logic 1.

• During the MFAuthent Command, bit ProtocolErr is set to logic 1,

if the number of bytes received in one data stream is incorrect.

• Set to logic 1, if the Miller Decoder detects 2 pulses below the

minimum time according to the ISO/IEC 14443A definitions.

[1] Command execution will clear all error bits except for bit TempErr. A setting by software is impossible.

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HiAlert 64 FIFOLength–  WaterLevel=

LoAlert FIFOLength WaterLevel=

9.2.1.8 Status1Reg

Contains status bits of the CRC, Interrupt and FIFO-buffer.

Table 30. Status1Reg register (address 07h); reset value: XXh, X100X01Xb

Access Rights

Table 31. Description of Status1Reg bits

Bit Symbol Description

7 RFFreqOK Indicates if the frequency detected at the RX pin is in the range of

6 CRCOk Set to logic 1, if the CRC Result is zero. For data transmission and

5 CRCReady Set to logic 1, whe n the CRC calculation has finished. This bit is only

4 IRq This bit shows, if any interrupt source requests attention (with respect

3 TRunning Set to logic 1, if the PN512’s timer unit is running, e.g. the timer will

2 RFOn Set to logic 1, if an external RF field is detected. This bit does not store

1 HiAlert Set to logic 1, when the number of bytes stored in the FIFO-buffer

PN512

Transm ission module

7 6 5 4 3 2 1 0

RFFreqOK CRCOk CRCReady IRq TRunning RFOn HiAlert LoAlert

rrrrrrrr

13.56 MHz. Set to logic 1, if the frequency at the RX pin is in the range

12 MHz < RX pin frequency < 15 MHz. Note: The value of RFFreqOK is not defined if the external RF

frequency is in the range from 9 to 12 MHz or in the range from 15 to 19 MHz.

reception the bit CRCOk is undefined (use CRCErr in register ErrorReg). CRCOk indicates the status of the CRC co-processor, during calculation the value changes to ZERO, when the calculation is done correctly, the value changes to ONE.

valid for the CRC co-processor calculation using the command CalcCRC.

to the setting of the interrupt enable bits, see register CommIEnReg and DivIEnReg).

decrement the TCounterValReg with the next timer clock. Note: In the gated mode the bit TRunning is set to logic 1, when the

timer is enabled by the register bits. This bit is not influenced by the gated signal.

the state of the RF field.

fulfills the following equation:

Example:

FIFOLength = 60, WaterLevel = 4  HiAlert = 1 FIFOLength = 59, WaterLevel = 4  HiAlert = 0

0 LoAlert Set to logic 1, when the number of bytes stored in the FIFO-buffer

fulfills the following equation: Example:

FIFOLength = 4, WaterLevel = 4  LoAlert = 1 FIFOLength = 5, WaterLevel = 4  LoAlert = 0

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9.2.1.9 Status2Reg

Contains status bits of the Receiver, Transmitter and Data mode detector.

Table 32. Status2Reg register (address 08h); reset value: 00h, 00000000b

Access Rights

Table 33. Description of Status2Reg bits

Bit Symbol Description

7 TempSensClear Set to logic 1, this bit clears the temperature error, if the temperature

5 - Reserved for future use. 4 TargetActivated Set to logic 1 if the Select command or if the Polling command was

3 MFCrypto1On This bit indicates that the MIFARE Crypto1 unit is switched on and

2 to 0 Modem State ModemState shows the state of the transmitter and receiver state

PN512

Transm ission module

7 6 5 4 3 2 1 0

TempSensClear I

r/w r/w RFU dy dy r r r

CForceHS I2C input filter settings. Set to logic 1, the I2C input filter is set to the

CForceHS 0 TargetActivated MFCrypto1On Modem State

is below the alarm limit of 125 C.

High-speed mode independent of the I2C protocol. Set to logic 0, the I2C input filter is set to the used I2C protocol.

answered. Note: This bit can only be set during the AutoColl command in Passive Communication mode.

Note: This bit is cleared automatically by switching off the external RF field.

therefore all data communication with the card is encrypted. This bit can only be set to logic 1 by a successful execution of the

MFAuthent Command. This bit is only valid in Reader/Writer mode for MIFARE cards. This bit shall be cleared by software.

machines.

Value Description

000 IDLE 001 Wait for StartSend in register BitFramingReg 010 TxWait: Wait until RF field is present, if the bit TxWaitRF is

set to logic 1. The minimum time for TxWait is defined by the

TxWaitReg register. 011 Sending 100 RxWait: Wait until RF field is present, if the bit RxWaitRF is

set to logic 1. The minimum time for RxWait is defined by the

RxWaitReg register. 101 Wait for data 110 Receiving

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9.2.1.10 FIFODataReg

In- and output of 64 byte FIFO-buffer.

Table 34. FIFODataReg register (address 09h); reset value: XXh, XXXXXXXXb

Access Rights

Table 35. Description of FIFODataReg bits

Bit Symbol Description

7 to 0 FIFOData Data input and output port for th e internal 64 byte FIFO-buffer. The

9.2.1.11 FIFOLevelReg

Indicates the number of bytes stored in the FIFO.

Table 36. FIFOLevelReg register (address 0Ah); reset value: 00h, 000 00000b

Access Rights

PN512

Transm ission module

7 6 5 4 3 2 1 0

FIFOData

dy dy dy dy dy dy dy dy

FIFO-buffer acts as parallel in/parallel out converter for all serial data stream in- and outputs.

7 6 5 4 3 2 1 0

FlushBuffer FIFOLevel

w rrrrrrr

Table 37. Description of FIFOLevelReg bits

Bit Symbol Description

7 FlushBuffer Set to logic 1, this bit clears the internal FIFO-buffer’s read- and

write-pointer and the bit BufferOvfl in the register ErrReg immediately. Reading this bit will always return 0.

6 to 0 FIFOLevel Indicates the number of bytes stored in the FIFO-buffer. Writing to the

FIFODataReg increments, reading decrements the FIFOLevel.

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9.2.1.12 WaterLevelReg

Defines the level for FIFO under- and overflow warning.

Table 38. WaterLevelReg register (address 0Bh); reset value: 08h, 00001000b

Access Rights

Table 39. Description of WaterLevelReg bits

Bit Symbol Description

7 to 6 - Reserved for future use. 5 to 0 WaterLevel This register defines a warning level to indicate a FIFO-buffer over- or

PN512

Transm ission module

7 6 5 4 3 2 1 0

0 0 WaterLevel

RFU RFU r/w r/w r/w r/w r/w r/w

underflow: The bit HiAlert in Status1Reg is set to logic 1, if the remaining number

of bytes in the FIFO-buffer space is equal or less than the defined number of WaterLevel bytes.

The bit LoAlert in Status1Reg is set to logic 1, if equal or less than WaterLevel bytes are in the FIFO.

Note: For the calculation of HiAlert and LoAlert see Table 30

9.2.1.13 ControlReg

Miscellaneous control bits.

Table 40. ControlReg register (address 0C h); reset value: 00h, 00000000b

TStopNow TStartNow WrNFCIDtoFIFO Initiator 0 RxLastBits

Access Rights

Table 41. Description of Control Reg bits

Bit Symbol Description

7 TStopNow Set to logic 1, the timer stops immediately.

6 TStartNow Set to logic 1 starts the timer immediately.

5 WrNFCIDtoFIFO Set to logic 1, the internal stored NFCID (10 bytes) is copied into the

4 In itiator Set to logic 1, the PN512 acts as initiator, otherwise it acts as target 3 - Reserved for future use. 2 to 0 RxLastBits Shows the number of valid bits in the last received byte. If zero, the

7 6 5 4 3 2 1 0

w w dy r/wRFUrrr

Reading this bit will always return 0.

FIFO. Afterwards the bit is cleared automatically

whole byte is valid.

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+ 103 hidden pages

NXP PN512 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual

1. Introduction

1.1 Different available versions

2. General description

3. Features and benefits

4. Quick reference data

5. Ordering information

6. Block diagram

7. Pinning information

7.1 Pinning

7.2 Pin description

8. Functional description

8.1 ISO/IEC 14443 A/MIFARE functionality

8.2 ISO/IEC 14443 B functionality

8.3 FeliCa reader/writer functionality

8.3.1 FeliCa framing and coding

8.4 NFCIP-1 mode

8.4.1 Active communication mode

8.4.2 Passive communication mode

8.4.3 NFCIP-1 framing and coding

8.4.4 NFCIP-1 protocol support

8.4.5 MIFARE Card operation mode

8.4.6 FeliCa Card operation mode

9. PN512 register SET

9.1 PN512 registers overview

9.1.1 Register bit behavior

9.2 Register description

9.2.1 Page 0: Command and status

9.2.1.1 PageReg

9.2.1.2 CommandReg

9.2.1.3 CommIEnReg

9.2.1.4 DivIEnReg

9.2.1.5 CommIRqReg

9.2.1.6 DivIRqReg

9.2.1.7 ErrorReg

9.2.1.8 Status1Reg

9.2.1.9 Status2Reg

9.2.1.10 FIFODataReg

9.2.1.11 FIFOLevelReg

9.2.1.12 WaterLevelReg

9.2.1.13 ControlReg