DATA SH EET
DISCRETE SEMICONDUCTORS
PDTA115E series
PNP resistor-equipped transistors;
R1 = 100 kΩ, R2 = 100 kΩ
Product data sheet
Supersedes data of 2004 May 05
2004 Jul 30
NXP Semiconductors Product data sheet
PNP resistor-equipped transistors;
PDTA115E series
R1 = 100 kΩ, R2 = 100 kΩ
FEATURES
• Built-in bias resistors
• Simplified circuit design
• Reduction of component count
• Reduced pick and place costs.
APPLICATIONS
• General purpose switching and amplification
• Inverter and interface circuits
• Circuit driver.
PRODUCT OVERVIEW
PACKAGE
TYPE NUMBER
PHILIPS EIAJ
PDTA115EE SOT416 SC-75 5E PDTC115EE
PDTA115EEF SOT490 SC-89 6B PDTC115EEF
PDTA115EK SOT346 SC-59 62 PDTC115EK
PDTA115EM SOT883 SC-101 F6 PDTC115EM
PDTA115ES SOT54 (TO-92) SC-43 TA115E PDTC115ES
PDTA115ET SOT23 − *AB
PDTA115EU SOT323 SC-70 *7C
QUICK REFERENCE DATA
SYMBOL PARAMETER TYP. MAX. UNIT
V
CEO
I
O
R1 bias resistor 100 − kΩ
R2 bias resistor 100 − kΩ
DESCRIPTION
PNP resistor-equipped transistor (see “Simplified outline,
symbol and pinning” for package details).
collector-emitter
voltage
output current (DC) − −20 mA
MARKING CODE NPN COMPLEMENT
(1)
(1)
− −50 V
PDTC115ET
PDTC115EU
Note
1. * = p: Made in Hong Kong.
* = t: Made in Malaysia.
* = W: Made in China.
2004 Jul 30 2
NXP Semiconductors Product data sheet
MAM338
MDB267
PNP resistor-equipped transistors;
PDTA115E series
R1 = 100 kΩ, R2 = 100 kΩ
SIMPLIFIED OUTLINE, SYMBOL AND PINNING
T YPE NUMBER SIMPLIFIED OUTLINE AND SYMBOL
PDTA115ES 1 base
handbook, halfpage
1
2
3
R1
1
R2
2
3
PDTA115EE 1 base
PDTA115EEF 2 emitter
PDTA115EK 3 collector
handbook, halfpage
PDTA115ET
PDTA115EU
1
Top view
3
2
R1
1
R2
MDB271
3
2
PINNING
PIN DESCRIPTION
2 collector
3 emitter
PDTA115EM 1 base
2 emitter
handbook, halfpage
2
1
Bottom view
R1
3
1
R2
3
2
3 collector
2004 Jul 30 3
NXP Semiconductors Product data sheet
PNP resistor-equipped transistors;
PDTA115E series
R1 = 100 kΩ, R2 = 100 kΩ
ORDERING INFORMATION
T YPE NUMBER
NAME DESCRIPTION VERSION
PDTA115EE − plastic surface mounted package; 3 leads SOT416
PDTA115EEF − plastic surface mounted package; 3 leads SOT490
PDTA115EK − plastic surface mounted package; 3 leads SOT346
PDTA115EM − leadless ultra small plastic package; 3 solder lands; body
× 0.6 × 0.5 mm
1.0
PDTA115ES − plastic single-ended leaded (through hole) package; 3 leads SOT54
PDTA115ET − plastic surface mounted package; 3 leads SOT23
PDTA115EU − plastic surface mounted package; 3 leads SOT323
LIMITING VALUES
In accordance with the Absolu te Maximum Rating System (IEC 60134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
V
V
V
CBO
CEO
EBO
I
collector-base voltage open emitter − −50 V
collector-emitter voltage open base − −50 V
emitter-base voltage open collector − −10 V
input voltage
positive − +10 V
negative − −40 V
I
I
P
O
CM
tot
output current (DC) − −20 mA
peak collector current − −100 mA
total power dissipation T
amb
≤ 25 °C
SOT23 note 1 − 250 mW
SOT54 note 1 − 500 mW
SOT323 note 1 − 200 mW
SOT346 note 1 − 250 mW
SOT416 note 1 − 150 mW
SOT490 notes 1 and 2 − 250 mW
SOT883 notes 2 and 3 − 250 mW
T
T
T
stg
j
amb
storage temperature −65 +150 °C
junction temperature − 150 °C
operating ambient temperature −65 +150 °C
PACKAGE
SOT883
Notes
1. Refer to standard mounting conditions.
2. Reflow soldering is the only recommended soldering method.
3. Refer to SOT883 standard mounting conditions; FR4 with 60 μm copper strip line.
2004 Jul 30 4
NXP Semiconductors Product data sheet
PNP resistor-equipped transistors;
PDTA115E series
R1 = 100 kΩ, R2 = 100 kΩ
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS VALUE UNIT
R
th(j-a)
Notes
1. Refer to standard mounting conditions.
2. Reflow soldering is the only recommended soldering method.
3. Refer to SOT883 standard mounting conditions; FR4 with 60 μm copper strip line.
CHARACTERISTICS
T
= 25 °C unless otherwise specified.
amb
thermal resistance from junction to ambient T
amb
≤ 25 °C
SOT23 note 1 500 K/W
SOT54 note 1 250 K/W
SOT323 note 1 625 K/W
SOT346 note 1 500 K/W
SOT416 note 1 833 K/W
SOT490 notes 1 and 2 500 K/W
SOT883 notes 2 and 3 500 K/W
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I
CBO
I
CEO
I
EBO
h
V
V
V
FE
CEsat
i(off)
i(on)
collector-base cut-off curren t VCB = −50 V; IE = 0 A − − −100 nA
collector-emitter cut-off current VCE = −30 V; IB = 0 A − − −1 μA
VCE = −30 V; IB = 0 A;
T
= 150 °C
j
− − −50 μA
emitter-base cut-off current VEB = −5 V; IC = 0 A − − −50 μA
DC current gain VCE = −5 V; IC = −5 mA 80 − −
collector-emitter saturation voltage IC = −5 mA; IB = −0.25 mA − − −150 mV
input-off voltage IC = −100 μA; VCE = −5 V − −1.2 −0.5 V
input-on voltage IC = −1 mA; VCE = −0.3 V −3 −1.6 − V
R1 input resistor 70 100 130 kΩ
R2
------- R1
C
c
resistor ratio 0.8 1 1.2
collector capacitance IE = ie = 0 A; VCB = −10 V;
= 1 MHz
f
− − 3 pF
2004 Jul 30 5
NXP Semiconductors Product data sheet
6
PNP resistor-equipped transistors;
PDTA115E series
R1 = 100 kΩ, R2 = 100 kΩ
PACKAGE OUTLINES
Plastic surface-mounted package; 3 leads SOT41
D
v
M
A
3
E
AB
X
H
E
12
e
b
1
p
e
DIMENSIONS (mm are the original dimensions)
A
1
UNIT
A
0.95
mm
0.60
OUTLINE
VERSION
SOT416 SC-75
max
0.1
b
cD
p
0.30
0.25
0.10
1.8
1.4
0.15
IEC JEDEC JEITA
e
E
0.9
1
0.7
REFERENCES
w
A
M
B
0 0.5 1 mm
scale
e1H
0.5
1.75
1.45
L
p
E
0.45
0.15
A
1
L
p
detail X
v
Qw
0.23
0.13
0.2
0.2
EUROPEAN
PROJECTION
Q
c
ISSUE DATE
04-11-04
06-03-16
2004 Jul 30 6
NXP Semiconductors Product data sheet
0
PNP resistor-equipped transistors;
PDTA115E series
R1 = 100 kΩ, R2 = 100 kΩ
Plastic surface-mounted package; 3 leads SOT49
D
3
E
H
E
AB
X
v M
A
12
e
b
1
p
e
0 1 2 mm
DIMENSIONS (mm are the original dimensions)
UNIT b
A
0.8
0.6
0.33
0.23
mm
OUTLINE
VERSION
SOT490 SC-89
cD
p
0.2
1.7
1.5
0.95
0.75
0.1
IEC JEDEC JEITA
e
E
e
0.5
1.0
REFERENCES
1
w M
B
H
1.7
1.5
scale
E
L
0.5
0.3
A
c
L
p
detail X
0.1
wv
0.1
EUROPEAN
PROJECTION
ISSUE DATE
05-07-28
06-03-16
p
2004 Jul 30 7
NXP Semiconductors Product data sheet
6
PNP resistor-equipped transistors;
PDTA115E series
R1 = 100 kΩ, R2 = 100 kΩ
Plastic surface-mounted package; 3 leads SOT34
D
B
E
H
E
3
A
X
v
M
A
12
e
1
DIMENSIONS (mm are the original dimensions)
1.3
1.0
A
1
0.1
0.013
b
p
0.50
0.26
0.35
0.10
IEC JEDEC JEITA
A
UNIT
mm
OUTLINE
VERSION
SOT346 TO-236 SC-59A
b
p
e
cD
3.1
2.7
0 1 2 mm
e
E
1.7
1.9
1.3
REFERENCES
Q
A
A
1
c
L
w
M
B
detail X
scale
e
H
L
Qwv
p
E
0.33
0.6
0.2
0.23
0.2
0.95
1
3.0
2.5
p
0.2
EUROPEAN
PROJECTION
ISSUE DATE
04-11-11
06-03-16
2004 Jul 30 8
NXP Semiconductors Product data sheet
L
3
PNP resistor-equipped transistors;
PDTA115E series
R1 = 100 kΩ, R2 = 100 kΩ
eadless ultra small plastic package; 3 solder lands; body 1.0 x 0.6 x 0.5 mm SOT88
L
2
b
e
1
e
1
L
1
3
b
1
E
DIMENSIONS (mm are the original dimensions)
A
(1)
UNIT
A
0.50
mm
0.46
Note
1. Including plating thickness
OUTLINE
VERSION
SOT883 SC-101
max.
0.03
1
bb
0.20
0.12
IEC JEDEC JEITA
1
0.55
0.47
DE
0.62
0.55
eLL
1.02
0.35 0.65
0.95
REFERENCES
A
A
1
D
0 0.5 1 mm
scale
e
1
0.30
0.22
0.30
0.22
1
EUROPEAN
PROJECTION
ISSUE DATE
03-02-05
03-04-03
2004 Jul 30 9
NXP Semiconductors Product data sheet
4
PNP resistor-equipped transistors;
PDTA115E series
R1 = 100 kΩ, R2 = 100 kΩ
Plastic single-ended leaded (through hole) package; 3 leads SOT5
c
E
d
1
D
2
A L
b
e
1
e
3
b
1
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
5.2
mm
5.0
Note
1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.
OUTLINE
VERSION
SOT54 TO-92 SC-43A
b
0.48
0.40
b
c
D
d
1.7
4.2
1.4
3.6
REFERENCES
E
2.54
1
0.66
0.45
0.38
4.8
4.4
0.55
IEC JEDEC JEITA
e
e
1
1.27
L
14.5
12.7
L
1
(1)
L
1
max.
2.5
EUROPEAN
PROJECTION
ISSUE DATE
04-06-28
04-11-16
2004 Jul 30 10
NXP Semiconductors Product data sheet
3
PNP resistor-equipped transistors;
PDTA115E series
R1 = 100 kΩ, R2 = 100 kΩ
Plastic surface-mounted package; 3 leads SOT2
D
3
E
H
E
AB
X
v
M
A
12
e
1
DIMENSIONS (mm are the original dimensions)
A
1
UNIT
A
1.1
mm
0.9
OUTLINE
VERSION
SOT23 TO-236AB
max.
0.1
b
p
0.48
0.15
0.38
0.09
IEC JEDEC JEITA
b
p
e
cD
3.0
2.8
w
M
B
0 1 2 mm
scale
e
0.95
H
1
2.5
2.1
E
1.4
1.9
1.2
REFERENCES
e
Q
A
A
1
c
L
p
detail X
L
Qwv
p
E
0.55
0.45
0.15
0.45
0.2
0.1
EUROPEAN
PROJECTION
ISSUE DATE
04-11-04
06-03-16
2004 Jul 30 11
NXP Semiconductors Product data sheet
3
PNP resistor-equipped transistors;
PDTA115E series
R1 = 100 kΩ, R2 = 100 kΩ
Plastic surface-mounted package; 3 leads SOT32
D
y
3
E
AB
X
H
E
v
M
A
12
e
b
1
p
e
DIMENSIONS (mm are the original dimensions)
A
1
mm
1.1
0.8
A
max
0.1
0.4
0.3
b
p
cD
0.25
2.2
0.10
1.8
UNIT
A
A
1
B
w
M
0 1 2 mm
scale
e
E
1.35
1.15
1.3
e1H
0.65
2.2
2.0
L
p
E
0.45
0.15
Qwv
0.23
0.13
detail X
Q
c
L
p
0.20.2
OUTLINE
VERSION
SOT323 SC-70
IEC JEDEC JEITA
REFERENCES
EUROPEAN
PROJECTION
ISSUE DATE
04-11-04
06-03-16
2004 Jul 30 12
NXP Semiconductors Product data sheet
PNP resistor-equipped transistors;
PDTA115E series
R1 = 100 kΩ, R2 = 100 kΩ
DATA SHEET STATUS
DOCUMENT
STATUS
Objective data sheet Development This document contains data from the objective specification for product
Preliminary data sheet Qualification This document contains data from the preliminary specification.
Product data sheet Production This document contains the product specification.
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
http://www.nxp.com.
URL
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(1)
PRODUCT
STATUS
(2)
DEFINITION
development.
the device. Limiting values are stress ratings only and
operation of the device at these or any other conditions
above those given in the Characteristics sections of this
document is not implied. Exposure to limiting values for
extended periods may affect device reliability.
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Applications ⎯ Applications that are described herein for
any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or
warranty that such applications will be suitable for the
specified use without further testing or modificati on .
Limiting values ⎯ Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC
2004 Jul 30 13
60134) may cause permanent damage to
Quick reference data ⎯ The Quick reference data is an
extract of the product data given in the Limiting values and
Characteristics sections of this document, and as such is
not complete, exhaustive or legally binding.
NXP Semiconductors
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimers. No changes were made to the technical content, except for package outline
drawings which were updated to the latest version.
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The information presented in this documen t d oes not form part of any quotation or contract, is believed t o b e a ccur ate a nd re li a ble and may be chan ged
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Printed in The Netherlands R75/03/pp14 Date of release: 2004 Jul 30 Document order number: 9397 750 13648
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