DISCRETE SEMICONDUCTORS
PDTA115E series
PNP resistor-equipped transistors;
R1 = 100 kΩ, R2 = 100 kΩ
Product data sheet
Supersedes data of 2004 May 05
2004 Jul 30
NXP Semiconductors Product data sheet
PNP resistor-equipped transistors;
PDTA115E series
R1 = 100 kΩ, R2 = 100 kΩ
FEATURES
• Built-in bias resistors
• Simplified circuit design
• Reduction of component count
• Reduced pick and place costs.
APPLICATIONS
• General purpose switching and amplification
• Inverter and interface circuits
• Circuit driver.
PRODUCT OVERVIEW
PACKAGE
TYPE NUMBER
PHILIPS EIAJ
PDTA115EE SOT416 SC-75 5E PDTC115EE
PDTA115EEF SOT490 SC-89 6B PDTC115EEF
PDTA115EK SOT346 SC-59 62 PDTC115EK
PDTA115EM SOT883 SC-101 F6 PDTC115EM
PDTA115ES SOT54 (TO-92) SC-43 TA115E PDTC115ES
PDTA115ET SOT23 − *AB
PDTA115EU SOT323 SC-70 *7C
QUICK REFERENCE DATA
SYMBOL PARAMETER TYP. MAX. UNIT
V
CEO
I
O
R1 bias resistor 100 − kΩ
R2 bias resistor 100 − kΩ
DESCRIPTION
PNP resistor-equipped transistor (see “Simplified outline,
symbol and pinning” for package details).
collector-emitter
voltage
output current (DC) − −20 mA
MARKING CODE NPN COMPLEMENT
(1)
(1)
− −50 V
PDTC115ET
PDTC115EU
Note
1. * = p: Made in Hong Kong.
* = t: Made in Malaysia.
* = W: Made in China.
2004 Jul 30 2
NXP Semiconductors Product data sheet
PNP resistor-equipped transistors;
PDTA115E series
R1 = 100 kΩ, R2 = 100 kΩ
SIMPLIFIED OUTLINE, SYMBOL AND PINNING
T YPE NUMBER SIMPLIFIED OUTLINE AND SYMBOL
PDTA115ES 1 base
handbook, halfpage
1
2
3
R1
1
R2
2
3
PDTA115EE 1 base
PDTA115EEF 2 emitter
PDTA115EK 3 collector
handbook, halfpage
PDTA115ET
PDTA115EU
1
Top view
3
2
R1
1
R2
MDB271
3
2
PINNING
PIN DESCRIPTION
2 collector
3 emitter
PDTA115EM 1 base
2 emitter
handbook, halfpage
2
1
Bottom view
R1
3
1
R2
3
2
3 collector
2004 Jul 30 3
NXP Semiconductors Product data sheet
PNP resistor-equipped transistors;
PDTA115E series
R1 = 100 kΩ, R2 = 100 kΩ
ORDERING INFORMATION
T YPE NUMBER
NAME DESCRIPTION VERSION
PDTA115EE − plastic surface mounted package; 3 leads SOT416
PDTA115EEF − plastic surface mounted package; 3 leads SOT490
PDTA115EK − plastic surface mounted package; 3 leads SOT346
PDTA115EM − leadless ultra small plastic package; 3 solder lands; body
× 0.6 × 0.5 mm
1.0
PDTA115ES − plastic single-ended leaded (through hole) package; 3 leads SOT54
PDTA115ET − plastic surface mounted package; 3 leads SOT23
PDTA115EU − plastic surface mounted package; 3 leads SOT323
LIMITING VALUES
In accordance with the Absolu te Maximum Rating System (IEC 60134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
V
V
V
CBO
CEO
EBO
I
collector-base voltage open emitter − −50 V
collector-emitter voltage open base − −50 V
emitter-base voltage open collector − −10 V
input voltage
positive − +10 V
negative − −40 V
I
I
P
O
CM
tot
output current (DC) − −20 mA
peak collector current − −100 mA
total power dissipation T
amb
≤ 25 °C
SOT23 note 1 − 250 mW
SOT54 note 1 − 500 mW
SOT323 note 1 − 200 mW
SOT346 note 1 − 250 mW
SOT416 note 1 − 150 mW
SOT490 notes 1 and 2 − 250 mW
SOT883 notes 2 and 3 − 250 mW
T
T
T
stg
j
amb
storage temperature −65 +150 °C
junction temperature − 150 °C
operating ambient temperature −65 +150 °C
PACKAGE
SOT883
Notes
1. Refer to standard mounting conditions.
2. Reflow soldering is the only recommended soldering method.
3. Refer to SOT883 standard mounting conditions; FR4 with 60 μm copper strip line.
2004 Jul 30 4
NXP Semiconductors Product data sheet
PNP resistor-equipped transistors;
PDTA115E series
R1 = 100 kΩ, R2 = 100 kΩ
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS VALUE UNIT
R
th(j-a)
Notes
1. Refer to standard mounting conditions.
2. Reflow soldering is the only recommended soldering method.
3. Refer to SOT883 standard mounting conditions; FR4 with 60 μm copper strip line.
CHARACTERISTICS
T
= 25 °C unless otherwise specified.
amb
thermal resistance from junction to ambient T
amb
≤ 25 °C
SOT23 note 1 500 K/W
SOT54 note 1 250 K/W
SOT323 note 1 625 K/W
SOT346 note 1 500 K/W
SOT416 note 1 833 K/W
SOT490 notes 1 and 2 500 K/W
SOT883 notes 2 and 3 500 K/W
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I
CBO
I
CEO
I
EBO
h
V
V
V
FE
CEsat
i(off)
i(on)
collector-base cut-off curren t VCB = −50 V; IE = 0 A − − −100 nA
collector-emitter cut-off current VCE = −30 V; IB = 0 A − − −1 μA
VCE = −30 V; IB = 0 A;
T
= 150 °C
j
− − −50 μA
emitter-base cut-off current VEB = −5 V; IC = 0 A − − −50 μA
DC current gain VCE = −5 V; IC = −5 mA 80 − −
collector-emitter saturation voltage IC = −5 mA; IB = −0.25 mA − − −150 mV
input-off voltage IC = −100 μA; VCE = −5 V − −1.2 −0.5 V
input-on voltage IC = −1 mA; VCE = −0.3 V −3 −1.6 − V
R1 input resistor 70 100 130 kΩ
R2
------- R1
C
c
resistor ratio 0.8 1 1.2
collector capacitance IE = ie = 0 A; VCB = −10 V;
= 1 MHz
f
− − 3 pF
2004 Jul 30 5