NXP PCF8593T/1 Datasheet

Page 1

PCF8593

Low power clock and calendar

Rev. 04 — 6 October 2010 Product data sheet

1. General description

The PCF8593 is a CMOS1 clock and calendar circuit, optimized for low power consumption. Addresses and data are transferred serially via the two-line bidirectional

C-bus. The built-in word address register is incremented automatically after e ach written or read data byte. The built-in 32.768 kHz oscillator circuit and the first 8 bytes of the RAM are used for the clock, calendar, and counter functions. The next 8 bytes can be programmed as alarm registers or used as free RAM space.

2. Features and benefits

 I2C-bus interface operating supply voltage: 2.5 V to 6.0 V  Clock operating supply voltage 1.0 V to 6.0 V at 0 °Cto+70°C  8 bytes scratchpad RAM (when alarm not used)  Data retention voltage: 1.0 V to 6.0 V  External RESET  Operating current (at f  Clock function with four year calendar  Universal timer with alarm and overflow indication  24 hour or 12 hour format  32.768 kHz or 50 Hz time base  Serial input and output bus (I  Automatic word address incrementing  Programmable alarm, timer, and interrupt function  Space-saving SO8 package available  Slave addresses: A3h for reading, A2h for writing

input resets I2C interface only

= 0 Hz, 32 kHz time base, VDD= 2.0 V): typical 1 μA

SCL

C-bus)

3. Ordering information

Table 1. Ordering information

Type number Package

Name Description Version

PCF8593P DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1 PCF8593T SO8 plastic small outline package; 8 leads;

body width 3.9 mm

1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 14.

SOT96-1

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NXP Semiconductors

4. Marking

Table 2. Marking codes

Type number Marking code

PCF8593P PCF8593P PCF8593T 8583T

5. Block diagram

OSCO

RESET

OSCI

INT

SCL

SDA

OSCILLATOR

RESET

C-BUS

INTERFACE

PCF8593

Low power clock and calendar

DIVIDER

00h

control/status

01h

hundredth second

CONTROL

LOGIC

ADDRESS

PCF8593

02h

03h

04h

05h

06h

07h

08htoalarm control

0Fh

seconds

minutes

hours

year/date

weekdays/months

timer

alarm or RAM

013aaa37

Fig 1. Block diagram of PCF8593

Product data sheet Rev. 04 — 6 October 2010 2 of 35

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NXP Semiconductors

6. Pinning information

6.1 Pinning

PCF8593

Low power clock and calendar

OSCI

OSCO

RESET

PCF8593P

013aaa380

INT

SCL

SDA

Top view. For mechanical details, see Figure24.

Fig 2. Pin configuration for DIP8 (PCF8593P)

OSCI

OSCO

RESET

PCF8593T

013aaa381

INT

SCL

SDA

Top view. For mechanical details, see Figure25.

Fig 3. Pin configuration for SO8 (PCF8593T)

6.2 Pin description

Table 3. Pin description

Symbol Pin Type Description

DIP8 (PCF8593P)

OSCI 1 1 input oscillator input, 50 Hz or event-pulse

OSCO 2 2 output oscillator output RESET V

3 3 input reset

4 4 supply ground supply voltage SDA 5 5 input/output serial data line SCL 6 6 input serial clock line INT V

7 7 output open-drain interrupt output (active LOW)

8 8 supply supply voltage

SO8 (PCF8593T)

input

Product data sheet Rev. 04 — 6 October 2010 3 of 35

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NXP Semiconductors

7. Functional description

The PCF8593 contains sixteen 8 bit registers with an 8 bit auto-incrementing address register, an on-chip 32.768kHz oscillator circuit, a frequency divider and a serial two-line bidirectional I

The first 8 registers (memory addresses 00h to 07h) are designed as addressable 8 bit parallel registers. The first register (memory address 00h) is used as a control and status register. The memory addresses 01h to 07h are used as counters for the clock function. The memory addresses 08h to 0Fh may be programmed as alarm registers or used as free RAM locations.

7.1 Counter function modes

When the control and status register is programmed, a 32.768 kHz clock mode, a 50 Hz clock mode or an event-counter mode can be selected.

In the clock modes the hundredths of a second, seconds, minutes, hours, date, month (four year calendar) and weekday are sto re d in a Bina ry Coded Decimal (BCD) format. The timer register stores up to 99 days. The event counter mode is used to count pulses applied to the oscillator input (OSCO left open-circuit). The event counter stores up to 6 digits of data.

C-bus interface.

PCF8593

Low power clock and calendar

When one of the counters is read (memory locations 01h to 07h), the contents of all counters are strobed into capture latches at the beginning of a read cycle. Therefore, faulty reading of the counter during a carry condition is prevented. When a counter is written, other counters are not affected.

7.2 Alarm function modes

By setting the alarm enable bit of the control and status register the alarm control register (address 08h) is activated.

By setting the alarm control register, a dated alarm, a daily alarm, a weekday alarm, or a timer alarm may be programmed. In the clock modes, the timer register (address 07h) may be programmed to count hundredths of a second, seconds, minutes, hours, or days. Days are counted when an alarm is not programmed .

Whenever an alarm event occurs the alarm flag of the contro l and status register is set. A timer alarm event will set the alarm flag and an overflow condition of the timer will set the timer flag. The open-drain interrupt output is switched on ( active LOW) when the al arm o r timer flag is set (enabled). The flags remain set until directly reset by a write operation.

When the alarm is disabled (bit 2 of control and status register set logic 0) the alarm registers at addresses 08h to 0Fh may be used as free RAM.

Product data sheet Rev. 04 — 6 October 2010 4 of 35

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NXP Semiconductors

7.3 Control and status register

PCF8593

Low power clock and calendar

The control and status register is defined as the memory location 00h with free access for reading and writing via the I contents of the control and status register (see Figure 4

MSB LSB

76 543210

013aaa382

C-bus. All functions and options are controlled by the

memory location 00h

timer flag:

alarm flag:

alarm enable bit:

logic 0:

logic 1:

mask flag:

logic 0:

logic 1:

function mode: 00 01 10 11

hold last count flag: logic 0: logic 1:

stop counting flag: logic 0: logic 1:

50 % duty factor seconds flag if alarm enable bit is logic 0

50 % duty factor minutes flag if alarm enable bit is logic 0

alarm disabled: flags toggle alarm control register to disabled (memory locations 08h to 0Fh are free RAM space)

enable alarm control register (memory location 08h is the alarm control register)

read locations 05h to 06h unmasked read date and month count directly

clock mode 32.768 kHz clock mode 50 Hz

event-counter mode

test modes

count store and hold last count in

capture latches

count pulses

stop counting, reset divider

Fig 4. Control and status register

Product data sheet Rev. 04 — 6 October 2010 5 of 35

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NXP Semiconductors

7.4 Counter registers

The format for 24 hour or 12 hour clock modes can be selected by setting the most significant bit of the hours counter register. The format of the hours counter is shown in

Figure 5

PCF8593

Low power clock and calendar

MSB LSB

76543210

013aaa383

memory location 04h (hours counter)

hours in BCD format:

unit place

ten's place (0 to 2 binary)

AM/PM flag: logic 0: AM logic 1: PM

format: logic 0: 24 hour format, AM/PM flag remains unchanged

logic 1: 12 h format, AM/PM flag will be updated

Fig 5. Format of the hours counter

The year and date are stored in memory location 05h (see Figure 6). The weekdays and months are in memory location 06h (see Figure 7

MSB LSB

7 65 432 10

013aaa384

memory location 05h (year/date)

days in BCD format:

unit place

ten's place (0 to 3 binary)

year (0 to 3 binary, read as logic 0 if the mask flag is set)

Fig 6. Format of the year and date counter

MSB LSB

76 543 210

013aaa385

memory location 06h (weekdays/months)

months in BCD format:

unit place

ten's place

weekdays (0 to 6 binary, read as logic 0 if the mask flag is set)

Fig 7. Format of the weekdays and month counter

When reading these memory locations the year and weekdays are masked out when the mask flag of the control and status register is set. This allows the user to read the date and month count directly.

Product data sheet Rev. 04 — 6 October 2010 6 of 35

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NXP Semiconductors

In the event-counter mode, events are stored in BCD format. D5 is the most significant and D0 the least significant digit. The divider is by-passed.

In the different modes the counter registers are programmed and arranged as shown in

Figure 8

PCF8593

Low power clock and calendar

. Counter cycles are listed in Table 4.

control/status

hundredth of a second

1/10 s

seconds

10 s

minutes

10 min

hours

10 h

year/date

10 day

weekdays/months

10 month

10 day

alarm control

hundredth of a second alarm

1/10 s 1/100 s

alarm seconds

1/100 s

1 s

1 min

1 h

1 day

1 month

timer

1 day

control/status

free

timer

alarm control

alarm alarm

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

alarm minutes

alarm hours

alarm date

alarm month

alarm timer

CLOCK MODES EVENT COUNTER

free

alarm timer

0Bh

0Ch

0Dh

0Eh

0Fh

013aaa386

Fig 8. Register arrangement

Product data sheet Rev. 04 — 6 October 2010 7 of 35

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NXP Semiconductors

T able 4. Cycle length of the time counters, clock modes

Unit Counting cycle Carry to next unit Contents of month

hundredths of a second 00 to 99 99 to 00 seconds 00 to 59 59 to 00 minutes 00 to 59 59 to 00 hours (24) 00 to 23 23 to 00 hours (12) 12 am - -

date 01 to 31 31 to 01 1, 3, 5, 7, 8, 10, and 12

months 01 to 12 12 to 01 year 0 to 3 - weekdays 0 to 6 6 to 0 timer 00 to 99 no carry -

PCF8593

Low power clock and calendar

calendar

01 am to 11 am - 12 pm - 01 pm to 11 pm 11 pm to 12 am -

01 to 30 30 to 01 4, 6, 9, and 11 01 to 29 29 to 01 2, year = 0 01 to 28 28 to 01 2, year = 1, 2, and 3

7.5 Alarm control register

When the alarm enable bit of the control and stat us r egister is set (add re ss 00 h, bit2) the alarm control register (address 08h) is activated. All alarm, timer, and interrupt output functions are controlled by the contents of the alarm control register (see Figure 9

Product data sheet Rev. 04 — 6 October 2010 8 of 35

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NXP Semiconductors

PCF8593

Low power clock and calendar

MSB LSB

7 654 321 0

013aaa387

memory location 08h

timer function:

000 001 010 011 100 101 110 111

timer interrupt enable:

0 1

clock alarm function:

00 01 10 11

timer alarm enable:

0 1

alarm interrupt enable:

(only valid when alarm enable in the control and status register is set)

0 1

no timer hundredths of a second seconds minutes hours days not used test mode, all counters in parallel

timer flag, no interrupt timer flag, interrupt

no clock alarm daily alarm weekday alarm dated alarm

no timer alarm timer alarm

alarm flag, no interrupt alarm flag, interrupt

Fig 9. Alarm control registers, clock mode

7.6 Alarm registers

All alarm registers are allocated with a constant address offset of 08h to the corresponding counter registers (see Figure 8

An alarm signal is generated when the contents of the alarm re gisters match bit-by-bit the contents of the involved counter registers. The yea r and weekday bits are ignored in a dated alarm. A daily alarm ignores the month and date bits. When a weekday alarm is selected, the contents of the alarm weekday a nd month register selects the weekdays on which an alarm is activated (see Figure 10

Remark: In the 12 hour mode, bits 6 and 7 of the alarm hours register must be the same as the hours counter.

Product data sheet Rev. 04 — 6 October 2010 9 of 35

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NXP Semiconductors

MSB LSB

76543210

PCF8593

Low power clock and calendar

memory location 0Eh (alarm_weekday/month)

weekday 0 enabled when set

weekday 1 enabled when set

weekday 2 enabled when set

weekday 3 enabled when set

weekday 4 enabled when set

weekday 5 enabled when set

weekday 6 enabled when set

013aaa375

not used

Fig 10. Selection of alarm weekdays

7.7 Timer

The timer (location 07h) is enabled by setting the control and status register to XX0X X1XX. The timer counts up from 0 (or a programmed value) to 99. On overflow, the timer resets to 0. The timer flag (LSB of control and status register) is set on overflow of the timer. This flag must be reset by software. The inverted value of this flag can be transferred to the external interrupt by setting bit 3 of the alarm control register.

Additionally, a timer alarm can be programmed by setting the timer alarm ena ble (bit 6 of the alarm control register). When the value of the timer equals a pre-programmed value in the alarm timer register (location 0Fh), the alarm flag is set (bit 1 of the control and status register). The inverted value of the alarm flag can be transferred to the external interrupt by enabling the alarm interrupt (bit 6 of the alarm control register).

Resolution of the timer is programmed via the 3 LSBs of the alarm control register (see

Figure 11

Product data sheet Rev. 04 — 6 October 2010 10 of 35

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NXP Semiconductors

mode

select

PCF8593

Low power clock and calendar

MUX

oscillator

counter

control

clock

alarm

7 654 321 0 76543210

CONTROL/STATUS

(1)

interrupt

CLOCK/CALENDAR

alarm

control

timer

alarm

TIMERALARM

overflow

timer overflow

interrupt

timer

control

INT

ALARM CONTROL

013aaa377

(1) If the alarm enable bit of the control and status register is reset (logic 0), a 1 Hz signal is observed on the interrupt pin INT.

Fig 11. Alarm and timer interrupt logic diagram

7.8 Event counter mode

Event counter mode is selected by bits 4 and 5 which are logic 10 in the control and st atus register. The event counter mode is used to count pulses externally applied to the oscillator input (OSCO left open-circuit).

The event counter stores up to 6 digits of data, which are stored as 6 hexadecimal valu es located in the registers 1h, 2h, and 3h. Therefore, up to 1 million events may be recorded.

An event counter alarm occurs when the event counter registers match the value programmed in the registers 9h, Ah, and Bh, and the event alar m is enabled ( bits 4 and 5 which are logic 01 in the alarm control register). In this event, the alarm flag (bit 1 of the control and status register) is set. The inverted value of this flag can be transferred to the interrupt pin (pin 7) by setting the alarm interrupt enable in the alarm control register. In

Product data sheet Rev. 04 — 6 October 2010 11 of 35

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NXP Semiconductors

this mode, the timer (location 07h) increments once for every one, one hundred, ten thousand, or 1 million events, depending on the value programmed in bits 0, 1 and 2 of the alarm control register. In all other events, the timer functions are as in the clock mode.

PCF8593

Low power clock and calendar

MSB LSB

7 654 321 0

013aaa376

memory location 08h reset state: 0000 0000

timer function:

no timer

000

units

001

100

010

10 000

011

1 000 000

100

not allowed

101

not allowed

110

test mode, all counters

111

in parallel

timer interrupt enable:

timer flag, no interrupt

timer flag, interrupt

clock alarm function:

no event alarm

event alarm

not allowed

timer alarm enable:

no timer alarm

timer alarm

alarm interrupt enable:

alarm flag, no interrupt

alarm flag, interrupt

Fig 12. Alarm control register, event counter mode

7.9 Interrupt control

The conditions for activating the output INT (active LOW) are determined by appropriate programming of the alarm control register. These conditions are clock alarm, timer alarm, timer overflow, and event counter alarm. An interrupt occurs when the alarm flag or the timer flag is set, and the corresponding interr up t is enabled. In all events, the interrupt is cleared only by software resetting of the flag which initiated the interrupt.

In the clock mode, if the alarm enable is not activated (alarm enable bit of the control and status register is logic 0), the interrupt output toggles at 1 Hz with a 50 % duty cycle (may be used for calibration). The OFF voltage of the interrupt output may exceed the supply voltage, up to a maximum of 6.0 V. A logic diagram of the interrupt output is shown in

Figure 11

7.10 Oscillator and divider

A 32.768 kHz quartz crystal has to be connected to OSCI and OSCO. A trimmer capacitor between OSCI and V signal is derived from the quartz oscillator for the clock counters.

Product data sheet Rev. 04 — 6 October 2010 12 of 35

is used for tuning the oscillator (see Section 11.1). A 100 Hz clock

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NXP Semiconductors

In the 50 Hz clock mode or event-counter mode the oscillator is disabled and the oscillator input is switched to a high-impedance state. This allows the user to feed the 50 Hz reference frequency or an external hig h spe e d ev en t si gn al int o th e input OSCI.

7.10.1 Designing

When designing the printed-circuit board layout, keep the oscillator components as close to the IC package as possible, and keep all other signal lines as far away as possible. In applications involving tight packing of components, shielding of the oscillator may be necessary. AC coupling of extraneous signals can introduce oscillator inaccuracy.

7.1 1 Initialization

Note that immediately following power-on, all internal registers are undefined and, following a RESET to the possibility that the device may be initially in event-counter mode, in which event the oscillator will not operate. Over-ride can be achieved via software.

PCF8593

Low power clock and calendar

pulse on pin 3, must be defined via software . Atten tion sho uld be paid

Reset is accomplished by applying an external RESET reset occurs only the I clock counters are not affected by RESET

C-bus interface is reset. The control and status register and all

. RESET must return HIGH during device

pulse (active LOW) at pin 3. When

operation. An RC combination can also be utilized to provide a power-on RESET

signal at pin 3. In this event, the values of the PCF8593 must fulfil the following relationship to guarantee power-on reset (see Figure 13

T o avoid overload of the internal diode by falling VDD, an external diode should be added in parallel to R

if CR ≥ 0.2 μF. Note that RC must be evaluated with the actual VDD of the application, as their

value will be V

Fig 13. PCF8593 reset

rise-time dependent.

reset input

RESET

PCF8593

013aaa38

RESET input must be input must be ≤ 0.3VDD when VDD reaches V

DD(min)

(or higher).

It is recommended to set the stop counting flag of the control and status register before loading the actual time into the counters. Loading of illegal states may lead to a temporary clock malfunction.

Product data sheet Rev. 04 — 6 October 2010 13 of 35

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NXP Semiconductors

8. Characteristics of the I2C-bus

8.1 Characteristics

The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer is initiated only when the bus is not busy.

8.1.1 Bit transfer

One data bit is transferred during each clock pulse (see Figure 14). The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time are interpreted as a control signal.

SDA

SCL

PCF8593

Low power clock and calendar

Fig 14. Bit transfer

8.1.2 Start and stop conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START

condition - S. A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition - P (see Figure 15

SDA

SCL

START condition

Fig 15. Definition of st art and stop conditions

data line

stable;

data valid

change

of data

allowed

mbc62

STOP condition

SDA

SCL

mbc62

8.1.3 System configuration

A device generating a message is a transmitter; a device receiving a message is the receiver (see Figure 16 devices which are controlled by the master are the slaves.

Product data sheet Rev. 04 — 6 October 2010 14 of 35

). The device that controls the message is the master; and the

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NXP Semiconductors

SDA

SCL

PCF8593

Low power clock and calendar

MASTER

TRANSMITTER

RECEIVER

Fig 16. System configuration

8.1.4 Acknowledge

The number of data bytes transferred between th e START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle.

• A slave receiver, which is addressed, must generate an acknowledge after the

reception of each byte.

• Also a master receiver must generate an acknowledge after the reception of each

byte that has been clocked out of the slave transmitter.

• The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration).

• A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.

SLAVE

RECEIVER

SLAVE

TRANSMITTER

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER

RECEIVER

mba60

START

condition

C-bus is illustrated in Figure 17.

not acknowledge

acknowledge

9821

clock pulse for

acknowledgement

mbc60

Acknowledgement on the I

data output

by transmitter

data output

by receiver

SCL from

master

Fig 17. Acknowledgement on the I2C-bus

Product data sheet Rev. 04 — 6 October 2010 15 of 35

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NXP Semiconductors

8.2 I2C-bus protocol

8.2.1 Addressing

Before any data is transmitted on the I2C-bus, the device which must respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure.

The clock and calendar acts as a slave receiver or slave transmitter. The clock signal SCL is only an input signal but the data signal SDA is a bidirectional line.

PCF8593

Low power clock and calendar

The clock and calendar slave address is shown in Table 5

Table 5. I2C slave address byte

Slave address

Bit 7 6 5 4 3 2 1 0

MSB LSB

1010001R/W

8.2.2 Clock and calendar READ or WRITE cycles

The I2C-bus configuration for the different PCF 8593 READ and WRITE cycles is shown in

Figure 18

, Figure 19 and Figure 20.

acknowledgement

from slave

0ASLAVE ADDRESS REGISTER ADDRESS A ADATA

R/W

acknowledgement

from slave

acknowledgement

n bytes

auto increment

memory register address

from slave

013aaa34

Fig 18. Master transmits to slave receiver (WRITE mode)

Product data sheet Rev. 04 — 6 October 2010 16 of 35

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NXP Semiconductors

PCF8593

Low power clock and calendar

SLAVE ADDRESS

acknowledgement

from slave

R/W

acknowledgement

from slave

SLAVE ADDRESS

(1)

acknowledgement

from slave

R/W

acknowledgement

from slave

DATA

n bytes

auto increment

memory register address

no acknowledgement

DATA

last byte

auto increment

memory register address

(1) At this moment master transmitter becomes master receiver and PCF8593 slave receiver becomes slave transmitter.

Fig 19. Master reads after setting word address (write word address; READ data)

acknowledgement

from slave

acknowledgement

from master

no acknowledgement

from master

013aaa041

SLAVE ADDRESS DATA

R/W

n bytes last byte

A1DATA

auto increment

Fig 20. Master reads slave immediately after first byte (READ mode)

auto increment

013aaa347

Product data sheet Rev. 04 — 6 October 2010 17 of 35

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NXP Semiconductors

9. Limiting values

Table 6. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

tot

ESD

stg

amb

[1] Pass level; Human Body Model (HBM), according to Ref. 5 “JESD22-A114”. [2] Pass level; Machine Model (MM), according to Ref. 6 “ [3] Pass level; latch-up testing according to Ref. 7 “ [4] According to the NXP store and transport requirements (see Ref. 9 “

stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to 75 %. For long term storage products deviant conditions are described in that document.

PCF8593

Low power clock and calendar

supply voltage −0.8 +0.7 V supply current - 50 mA ground supply current - 50 mA input voltage −0.8 VDD + 0.8 V input current - 10 mA output current - 10 mA total power dissipation - 300 mW output power - 50 mW electrostatic discharge

voltage

HBM

MM latch-up current storage temperature ambient temperature operating device −40 +85 °C

JESD22-A115”.

JESD78” at maximum ambient temperature (T

[1]

- ±3000 V

[2]

- ±300 V

[3]

- 100 mA

[4]

−65 +150 °C

amb(max)

NX3-00092”) the devices have to be

Product data sheet Rev. 04 — 6 October 2010 18 of 35

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NXP Semiconductors

Low power clock and calendar

10. Characteristics

10.1 Static characteristics

Table 7. Static characteristics

= 2.5 V to 6.0 V; VSS = 0 V; T

Symbol Parameter Conditions Min Typ

supply voltage operating mode

supply current operating mode

Pin SDA, SCL and INT

LOW-level input voltage 0 - 0.3V HIGH-level input voltage 0.7V LOW-level output current VOL=0.4V 3 - - mA input leakage current VI = VDD or V input capacitance

Pins OSCI and RESET

input leakage current VI = VDD or V

Pin INT

LOW-level output current VOL = 0.4 V 1 - - mA input leakage current VI = VDD or V

Pin SCL

input leakage current VI = VDD or V input capacitance

= −40 °C to +85 °C unless otherwise specified.

amb

C-bus active 2.5 - 6.0 V

C-bus inactive 1.0 - 6.0 V

quartz oscillator

= 0 °C to +70 °C

amb

= −40 °C to +85 °C

amb

= 100 kHz clock mode

SCL

clock mode; f

= 2.0 V - 1.0 8.0 μA

= 5.0 V - 4 15 μA

SCL

= 0 Hz

[2]

1.0 - 6.0 V

[2]

1.2 - 6.0 V

[3]

- - 200 μA

-VDDV

−1- +1μA

[4]

--7pF

−250 - +250 nA

−1- +1μA

[4]

--7pF

PCF8593

[1]

Max Unit

[1] Typical values measured at T [2] When the device is powered on, V

oscillator. [3] Event counter mode: supply current dependant upon input frequency. [4] Tested on a sample basis.

Product data sheet Rev. 04 — 6 October 2010 19 of 35

= 25 °C.

amb

must exceed the specified minimum value by 300 mV to guarantee correct start-up of the

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NXP Semiconductors

001aam493

Fig 21. Typical supply current in clock mode as a function of supply voltage

= 32 kHz; T

SCL

(μA)

0642

= 25 °C

amb

PCF8593

Low power clock and calendar

VDD (V)

Product data sheet Rev. 04 — 6 October 2010 20 of 35

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NXP Semiconductors

PCF8593

Low power clock and calendar

10.2 Dynamic characteristics

Table 8. Dynamic characteristics

= 2.5 V to 6.0 V; VSS = 0 V; T

Symbol Parameter Conditions Min Typ Max Unit

Oscillator

OSCO

Δf

osc/fosc

capacitance on pin OSCO 20 25 30 pF relative oscillator frequency

variation

clk(ext)

external clock frequency

Quartz crystal parameters (f = 32.768 kHz)

trim

C-bus timing (see Figure 21)

SCL

series resistance - - 40 kΩ parallel load capacitance - 10 - pF trimmer capacitance 5 - 25 pF

SCL clock frequency - - 100 kHz pulse width of spikes that

must be suppressed by the input filter

BUF

bus free time between a STOP and START condition

SU;STA

set-up time for a repeated START condition

HD;STA

hold time (repeated) START condition

LOW

HIGH

LOW period of the SCL clock 4.7 - - μs HIGH period of the SCL clock 4.0 - - μs rise time of both SDA and

SCL signals

fall time of both SDA and SCL signals

SU;DAT

HD;DAT

VD;DAT

SU;STO

data set-up time 250 - - ns data hold time 0 - - ns data valid time - - 3.4 μs set-up time for STOP

condition

= −40 °C to +85 °C unless otherwise specified.

amb

for ΔVDD = 100 mV; T

amb

=25°C;

-0.2-ppm

VDD = 1.5 V

[1]

--1MHz

[2]

--100ns

4.7 - - μs

4.0 - - μs

--1.0μs

--0.3μs

4.0 - - μs

[1] Event counter mode only. [2] All timing values are valid within the operating supply voltage, ambient temperature range, reference to V

voltage swing of V

Product data sheet Rev. 04 — 6 October 2010 21 of 35

to VDD.

and VIH and with an input

Page 22

NXP Semiconductors

PCF8593

Low power clock and calendar

PROTOCOL

SCL

SDA

START

CONDITION

SU;STA

BUF

(S)

HD;STA

BIT 7

MSB

(A7)

LOWtHIGH

SU;DAT

1 / f

BIT 6

(A6)

SCL

HD;DAT

Fig 22. I2C-bus timing diagram; rise and fall times refer to VIL and V

BIT 0

ACKNOWLEDGE

LSB

(R/W)

VD;DAT

(A)

STOP

CONDITION

(P)

SU;STO

mbd82

Product data sheet Rev. 04 — 6 October 2010 22 of 35

Page 23

NXP Semiconductors

11. Application information

11.1 Oscillator frequency adjustment

11.1.1 Method 1: Fixed OSCI capacitor

By evaluating the average capacitance necessary for the application layout a fixed capacitor can be used. The frequency is best measured via the 1 Hz signal which can be programmed to occur at the interrupt output (pin 7). The frequency tolerance depends on the quartz crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average ±5 × 10

11.1.2 Method 2: OSCI trimmer

Using the alarm function (via the I2C-bus) a signal faster than the 1 Hz is generated at the interrupt output for fast setting of a trimmer.

Procedure:

• Power the device on

• Apply RESET.

PCF8593

Low power clock and calendar

−

6). Average deviations of ±5 minutes per year can be achieved.

Routine:

• Set clock to time t and set alarm to time t + Δt

• at time t + Δt (interrupt) repeat routine.

11.1.3 Method 3: Direct measurement

Direct measurement of oscillator output (allowing for test probe capacitance).

Product data sheet Rev. 04 — 6 October 2010 23 of 35

Page 24

NXP Semiconductors

PCF8593

Low power clock and calendar

1 F

CLOCK/CALENDAR

OSCI

PCF8593

OSCO

RESET

SCL

SDA

RESET

SDA

SCL

TRANSMITTER/

RECEIVER

MASTER

R: pull-up resistor

R =

Fig 23. Application example

SDA SCL

(I2C-bus)

013aaa38

Product data sheet Rev. 04 — 6 October 2010 24 of 35

Page 25

NXP Semiconductors

-1

12. Package outline

PCF8593

Low power clock and calendar

IP8: plastic dual in-line package; 8 leads (300 mil)

seating plane

pin 1 index

w M

(e )

SOT97

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

min.

max.

050G01 MO-001 SC-504-8

1.73

1.14

0.068

0.021

0.045

0.015

IEC JEDEC JEITA

OUTLINE VERSION

SOT97-1

max.

UNIT

inches

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

0.53

0.38

0 5 10 mm

scale

0.36

1.07

0.23

0.89

0.014

0.042

0.009

0.035

REFERENCES

(1) (1)

cD E e M

9.8

6.48

9.2

6.20

0.39

0.26

0.36

0.24

3.60

3.05

0.14

0.12

8.25

7.80

0.32

0.31

EUROPEAN

PROJECTION

10.0

0.39

0.33

8.3

max.

0.2542.54 7.62

1.154.2 0.51 3.2

0.010.1 0.3

0.0450.17 0.02 0.13

ISSUE DATE

99-12-27 03-02-13

(1)

Fig 24. Package outline SOT97-1 (DIP8) of PCF8593P

Product data sheet Rev. 04 — 6 October 2010 25 of 35

Page 26

NXP Semiconductors

-1

PCF8593

Low power clock and calendar

O8: plastic small outline package; 8 leads; body width 3.9 mm

pin 1 index

w M

detail X

v M

(A )

SOT96

0 2.5 5 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

OUTLINE VERSION

SOT96-1

A1A2A3b

max.

0.25

1.75

0.10

0.010

0.069

0.004

1.45

1.25

0.057

0.049

IEC JEDEC JEITA

076E03 MS-012

0.25

0.01

0.49

0.36

0.019

0.014

0.25

0.19

0.0100

0.0075

UNIT

inches

Notes

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

(1)E(2)

5.0

4.8

0.20

0.19

REFERENCES

eHELLpQZywv θ

4.0

3.8

0.16

0.15

1.27

0.05

6.2

5.8

0.244

0.228

1.05

1.0

0.4

0.039

0.016

0.7

0.6

0.028

0.024

0.25 0.10.25

0.010.010.041 0.004

EUROPEAN

PROJECTION

(1)

0.7

0.3

0.028

0.012

ISSUE DATE

99-12-27 03-02-18

Fig 25. Package outline SOT96-1 (SO8) of PCF8593T

Product data sheet Rev. 04 — 6 October 2010 26 of 35

Page 27

NXP Semiconductors

13. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”.

13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.

13.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by so lder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:

PCF8593

Low power clock and calendar

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are exposed to the wave

• Solder bath specifications, including temperature and impurities

Product data sheet Rev. 04 — 6 October 2010 27 of 35

Page 28

NXP Semiconductors

13.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually lea ds to

• Solder paste printing issues including smearing, release, and adjusting the process

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

Table 9. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

< 2.5 235 220 ≥ 2.5 220 220

PCF8593

Low power clock and calendar

higher minimum peak temperatures (see Figure 26 reducing the process window

window for a mix of large and small components on one board

heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joint s (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with

Table 9

and 10

Volume (mm3) < 350 ≥ 350

) than a SnPb process, thus

Table 10. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm3) < 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245 > 2.5 250 245 245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all times.

Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 26

Product data sheet Rev. 04 — 6 October 2010 28 of 35

Page 29

NXP Semiconductors

Fig 26. Temperature profiles for large and small components

maximum peak temperature

temperature

MSL: Moisture Sensitivity Level

= MSL limit, damage level

minimum peak temperature

= minimum soldering temperature

PCF8593

Low power clock and calendar

peak

temperature

time

001aac84

For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”.

Product data sheet Rev. 04 — 6 October 2010 29 of 35

Page 30

NXP Semiconductors

14. Abbreviations

Table 11. Abbreviations

Acronym Description

AM Ante Meridiem BCD Binary Coded Decimal CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model

C Inter-Integrated Circuit bus

I IC Integrated Circuit LSB Least Significant Bit MM Machine Model MSB Most Significant Bit MSL Moisture Sensitivity Level MUX Multiplexer PCB Printed-Circuit Board PM Post Meridiem POR Power-On Reset PPM Parts Per Million RF Radio Frequency RAM Random Access Memory SCL Serial Clock Line SDA Serial DAta line SMD Surface-Mount Device

PCF8593

Low power clock and calendar

Product data sheet Rev. 04 — 6 October 2010 30 of 35

Page 31

NXP Semiconductors

15. References

[1] AN10365 — Surface mount reflow soldering description [2] IEC 60134 — Rating systems for electronic tubes and valves and analogous

[3] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena [4] IPC/JEDEC J-STD-020 — Moisture/Reflow Sensitivity Classification for

[5] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body

[6] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model

[7] JESD78 — IC Latch-Up Test [8] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive

[9] NX3-00092 — NXP store and transport requirements [10] SNV-FA-01-02 — Marking Formats Integrated Circuits [11] UM10204 — I

semiconductor devices

Nonhermetic Solid State Surface Mount Devices

Model (HBM)

(MM)

(ESDS) Devices

C-bus specification and user manual

PCF8593

Low power clock and calendar

Product data sheet Rev. 04 — 6 October 2010 31 of 35

Page 32

NXP Semiconductors

PCF8593

Low power clock and calendar

16. Revision history

Table 12. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PCF8593 v.4 20101006 Product data sheet - PCF8593_3 Modifications:

PCF8593_3 19970325 Product specification - PCF8593_2 PCF8593_2 19940829 Product specification - PCF8593_1 PCF8593_1 19940606 Product specification - -

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

Product data sheet Rev. 04 — 6 October 2010 32 of 35

Page 33

NXP Semiconductors

PCF8593

Low power clock and calendar

17. Legal information

17.1 Data sheet status

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) d escribed i n this docume nt may have changed since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

[1][2]

Product status

[3]

Definition

17.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied u pon to co nt ain det ailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

17.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.

In no event shall NXP Semiconductors be lia ble for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semi conductors’ aggregat e and cumulative liabil ity towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonabl y be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.

NXP Semiconductors does not accept any liability related to any default , damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third part y customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell product s that is ope n for accept ance or the gr ant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.

, unless otherwise

Product data sheet Rev. 04 — 6 October 2010 33 of 35

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NXP Semiconductors

PCF8593

Low power clock and calendar

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It i s neither qua lif ied nor test ed in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equ ipment or applications.

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, da mages or failed produ ct cl aims resulting from custome r design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

17.4 Trademarks

Notice: All referenced brands, prod uct names, service names and trad emarks are the property of their respective owners.

C-bus — logo is a trademark of NXP B.V.

18. Contact information

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Product data sheet Rev. 04 — 6 October 2010 34 of 35

Page 35

NXP Semiconductors

19. Contents

PCF8593

Low power clock and calendar

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Functional description . . . . . . . . . . . . . . . . . . . 4

7.1 Counter function modes . . . . . . . . . . . . . . . . . . 4

7.2 Alarm function modes. . . . . . . . . . . . . . . . . . . . 4

7.3 Control and status register . . . . . . . . . . . . . . . . 5

7.4 Counter registers . . . . . . . . . . . . . . . . . . . . . . . 6

7.5 Alarm control register . . . . . . . . . . . . . . . . . . . . 8

7.6 Alarm registers . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.7 Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7.8 Event counter mode . . . . . . . . . . . . . . . . . . . . 11

7.9 Interrupt control . . . . . . . . . . . . . . . . . . . . . . . 12

7.10 Oscillator and divider . . . . . . . . . . . . . . . . . . . 12

7.10.1 Designing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.11 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

8 Characteristics of the I

C-bus . . . . . . . . . . . . 14

8.1 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 14

8.1.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

8.1.2 Start and stop conditions . . . . . . . . . . . . . . . . 14

8.1.3 System configuration . . . . . . . . . . . . . . . . . . . 14

8.1.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 15

8.2 I

C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 16

8.2.1 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

8.2.2 Clock and calendar READ or WRITE cycles . 16

9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 18

10 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 19

10.1 Static characteristics. . . . . . . . . . . . . . . . . . . . 19

10.2 Dynamic characteristics . . . . . . . . . . . . . . . . . 21

11 Application information. . . . . . . . . . . . . . . . . . 23

11.1 Oscillator frequency adjustment . . . . . . . . . . . 23

11.1.1 Method 1: Fixed OSCI capacitor. . . . . . . . . . . 23

11.1.2 Method 2: OSCI trimmer. . . . . . . . . . . . . . . . . 23

11.1.3 Method 3: Direct measurement . . . . . . . . . . . 23

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 25

13 Soldering of SMD packages . . . . . . . . . . . . . . 27

13.1 Introduction to soldering . . . . . . . . . . . . . . . . . 27

13.2 Wave and reflow soldering. . . . . . . . . . . . . . . 27

13.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 27

13.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 28

14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 30

15 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

16 Revision history . . . . . . . . . . . . . . . . . . . . . . . 32

17 Legal information . . . . . . . . . . . . . . . . . . . . . . 33

17.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 33

17.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

17.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 33

17.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 34

18 Contact information . . . . . . . . . . . . . . . . . . . . 34

19 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 6 October 2010

Document identifier: PCF8593

NXP PCF8593T/1 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1. General description

2. Features and benefits

3. Ordering information

4. Marking

5. Block diagram

6. Pinning information

6.1 Pinning

6.2 Pin description

7. Functional description

7.1 Counter function modes

7.2 Alarm function modes

7.3 Control and status register

7.4 Counter registers

7.5 Alarm control register

7.6 Alarm registers

7.7 Timer

7.8 Event counter mode

7.9 Interrupt control

7.10 Oscillator and divider

7.10.1 Designing

7.1 1 Initialization

8. Characteristics of the I2C-bus

8.1 Characteristics

8.1.1 Bit transfer

8.1.2 Start and stop conditions

8.1.3 System configuration

8.1.4 Acknowledge

8.2 I2C-bus protocol

8.2.1 Addressing

8.2.2 Clock and calendar READ or WRITE cycles

9. Limiting values

10. Characteristics

10.1 Static characteristics

10.2 Dynamic characteristics

11. Application information

11.1 Oscillator frequency adjustment

11.1.1 Method 1: Fixed OSCI capacitor

11.1.2 Method 2: OSCI trimmer

11.1.3 Method 3: Direct measurement

12. Package outline

13. Soldering of SMD packages

13.1 Introduction to soldering

13.2 Wave and reflow soldering

13.3 Wave soldering

13.4 Reflow soldering

14. Abbreviations

15. References

16. Revision history

17. Legal information

17.1 Data sheet status

17.2 Definitions

17.3 Disclaimers

17.4 Trademarks

18. Contact information

19. Contents