NXP PCF8593T/1 Datasheet

PCF8593

Low power clock and calendar

Rev. 04 — 6 October 2010 Product data sheet

1. General description

The PCF8593 is a CMOS1 clock and calendar circuit, optimized for low power consumption. Addresses and data are transferred serially via the two-line bidirectional

C-bus. The built-in word address register is incremented automatically after e ach written or read data byte. The built-in 32.768 kHz oscillator circuit and the first 8 bytes of the RAM are used for the clock, calendar, and counter functions. The next 8 bytes can be programmed as alarm registers or used as free RAM space.

2. Features and benefits

 I2C-bus interface operating supply voltage: 2.5 V to 6.0 V  Clock operating supply voltage 1.0 V to 6.0 V at 0 °Cto+70°C  8 bytes scratchpad RAM (when alarm not used)  Data retention voltage: 1.0 V to 6.0 V  External RESET  Operating current (at f  Clock function with four year calendar  Universal timer with alarm and overflow indication  24 hour or 12 hour format  32.768 kHz or 50 Hz time base  Serial input and output bus (I  Automatic word address incrementing  Programmable alarm, timer, and interrupt function  Space-saving SO8 package available  Slave addresses: A3h for reading, A2h for writing

input resets I2C interface only

= 0 Hz, 32 kHz time base, VDD= 2.0 V): typical 1 μA

SCL

C-bus)

3. Ordering information

Table 1. Ordering information

Type number Package

Name Description Version

PCF8593P DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1 PCF8593T SO8 plastic small outline package; 8 leads;

body width 3.9 mm

1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 14.

SOT96-1

NXP Semiconductors

4. Marking

Table 2. Marking codes

Type number Marking code

PCF8593P PCF8593P PCF8593T 8583T

5. Block diagram

OSCO

RESET

OSCI

INT

SCL

SDA

OSCILLATOR

RESET

C-BUS

INTERFACE

PCF8593

Low power clock and calendar

DIVIDER

00h

control/status

01h

hundredth second

CONTROL

LOGIC

ADDRESS

PCF8593

02h

03h

04h

05h

06h

07h

08htoalarm control

0Fh

seconds

minutes

hours

year/date

weekdays/months

timer

alarm or RAM

013aaa37

Fig 1. Block diagram of PCF8593

Product data sheet Rev. 04 — 6 October 2010 2 of 35

NXP Semiconductors

6. Pinning information

6.1 Pinning

PCF8593

Low power clock and calendar

OSCI

OSCO

RESET

PCF8593P

013aaa380

INT

SCL

SDA

Top view. For mechanical details, see Figure24.

Fig 2. Pin configuration for DIP8 (PCF8593P)

OSCI

OSCO

RESET

PCF8593T

013aaa381

INT

SCL

SDA

Top view. For mechanical details, see Figure25.

Fig 3. Pin configuration for SO8 (PCF8593T)

6.2 Pin description

Table 3. Pin description

Symbol Pin Type Description

DIP8 (PCF8593P)

OSCI 1 1 input oscillator input, 50 Hz or event-pulse

OSCO 2 2 output oscillator output RESET V

3 3 input reset

4 4 supply ground supply voltage SDA 5 5 input/output serial data line SCL 6 6 input serial clock line INT V

7 7 output open-drain interrupt output (active LOW)

8 8 supply supply voltage

SO8 (PCF8593T)

input

Product data sheet Rev. 04 — 6 October 2010 3 of 35

NXP Semiconductors

7. Functional description

The PCF8593 contains sixteen 8 bit registers with an 8 bit auto-incrementing address register, an on-chip 32.768kHz oscillator circuit, a frequency divider and a serial two-line bidirectional I

The first 8 registers (memory addresses 00h to 07h) are designed as addressable 8 bit parallel registers. The first register (memory address 00h) is used as a control and status register. The memory addresses 01h to 07h are used as counters for the clock function. The memory addresses 08h to 0Fh may be programmed as alarm registers or used as free RAM locations.

7.1 Counter function modes

When the control and status register is programmed, a 32.768 kHz clock mode, a 50 Hz clock mode or an event-counter mode can be selected.

In the clock modes the hundredths of a second, seconds, minutes, hours, date, month (four year calendar) and weekday are sto re d in a Bina ry Coded Decimal (BCD) format. The timer register stores up to 99 days. The event counter mode is used to count pulses applied to the oscillator input (OSCO left open-circuit). The event counter stores up to 6 digits of data.

C-bus interface.

PCF8593

Low power clock and calendar

When one of the counters is read (memory locations 01h to 07h), the contents of all counters are strobed into capture latches at the beginning of a read cycle. Therefore, faulty reading of the counter during a carry condition is prevented. When a counter is written, other counters are not affected.

7.2 Alarm function modes

By setting the alarm enable bit of the control and status register the alarm control register (address 08h) is activated.

By setting the alarm control register, a dated alarm, a daily alarm, a weekday alarm, or a timer alarm may be programmed. In the clock modes, the timer register (address 07h) may be programmed to count hundredths of a second, seconds, minutes, hours, or days. Days are counted when an alarm is not programmed .

Whenever an alarm event occurs the alarm flag of the contro l and status register is set. A timer alarm event will set the alarm flag and an overflow condition of the timer will set the timer flag. The open-drain interrupt output is switched on ( active LOW) when the al arm o r timer flag is set (enabled). The flags remain set until directly reset by a write operation.

When the alarm is disabled (bit 2 of control and status register set logic 0) the alarm registers at addresses 08h to 0Fh may be used as free RAM.

Product data sheet Rev. 04 — 6 October 2010 4 of 35

NXP Semiconductors

7.3 Control and status register

PCF8593

Low power clock and calendar

The control and status register is defined as the memory location 00h with free access for reading and writing via the I contents of the control and status register (see Figure 4

MSB LSB

76 543210

013aaa382

C-bus. All functions and options are controlled by the

memory location 00h

timer flag:

alarm flag:

alarm enable bit:

logic 0:

logic 1:

mask flag:

logic 0:

logic 1:

function mode: 00 01 10 11

hold last count flag: logic 0: logic 1:

stop counting flag: logic 0: logic 1:

50 % duty factor seconds flag if alarm enable bit is logic 0

50 % duty factor minutes flag if alarm enable bit is logic 0

alarm disabled: flags toggle alarm control register to disabled (memory locations 08h to 0Fh are free RAM space)

enable alarm control register (memory location 08h is the alarm control register)

read locations 05h to 06h unmasked read date and month count directly

clock mode 32.768 kHz clock mode 50 Hz

event-counter mode

test modes

count store and hold last count in

capture latches

count pulses

stop counting, reset divider

Fig 4. Control and status register

Product data sheet Rev. 04 — 6 October 2010 5 of 35

NXP Semiconductors

7.4 Counter registers

The format for 24 hour or 12 hour clock modes can be selected by setting the most significant bit of the hours counter register. The format of the hours counter is shown in

Figure 5

PCF8593

Low power clock and calendar

MSB LSB

76543210

013aaa383

memory location 04h (hours counter)

hours in BCD format:

unit place

ten's place (0 to 2 binary)

AM/PM flag: logic 0: AM logic 1: PM

format: logic 0: 24 hour format, AM/PM flag remains unchanged

logic 1: 12 h format, AM/PM flag will be updated

Fig 5. Format of the hours counter

The year and date are stored in memory location 05h (see Figure 6). The weekdays and months are in memory location 06h (see Figure 7

MSB LSB

7 65 432 10

013aaa384

memory location 05h (year/date)

days in BCD format:

unit place

ten's place (0 to 3 binary)

year (0 to 3 binary, read as logic 0 if the mask flag is set)

Fig 6. Format of the year and date counter

MSB LSB

76 543 210

013aaa385

memory location 06h (weekdays/months)

months in BCD format:

unit place

ten's place

weekdays (0 to 6 binary, read as logic 0 if the mask flag is set)

Fig 7. Format of the weekdays and month counter

When reading these memory locations the year and weekdays are masked out when the mask flag of the control and status register is set. This allows the user to read the date and month count directly.

Product data sheet Rev. 04 — 6 October 2010 6 of 35

NXP Semiconductors

In the event-counter mode, events are stored in BCD format. D5 is the most significant and D0 the least significant digit. The divider is by-passed.

In the different modes the counter registers are programmed and arranged as shown in

Figure 8

PCF8593

Low power clock and calendar

. Counter cycles are listed in Table 4.

control/status

hundredth of a second

1/10 s

seconds

10 s

minutes

10 min

hours

10 h

year/date

10 day

weekdays/months

10 month

10 day

alarm control

hundredth of a second alarm

1/10 s 1/100 s

alarm seconds

1/100 s

1 s

1 min

1 h

1 day

1 month

timer

1 day

control/status

free

timer

alarm control

alarm alarm

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

alarm minutes

alarm hours

alarm date

alarm month

alarm timer

CLOCK MODES EVENT COUNTER

free

alarm timer

0Bh

0Ch

0Dh

0Eh

0Fh

013aaa386

Fig 8. Register arrangement

Product data sheet Rev. 04 — 6 October 2010 7 of 35

NXP Semiconductors

T able 4. Cycle length of the time counters, clock modes

Unit Counting cycle Carry to next unit Contents of month

hundredths of a second 00 to 99 99 to 00 seconds 00 to 59 59 to 00 minutes 00 to 59 59 to 00 hours (24) 00 to 23 23 to 00 hours (12) 12 am - -

date 01 to 31 31 to 01 1, 3, 5, 7, 8, 10, and 12

months 01 to 12 12 to 01 year 0 to 3 - weekdays 0 to 6 6 to 0 timer 00 to 99 no carry -

PCF8593

Low power clock and calendar

calendar

01 am to 11 am - 12 pm - 01 pm to 11 pm 11 pm to 12 am -

01 to 30 30 to 01 4, 6, 9, and 11 01 to 29 29 to 01 2, year = 0 01 to 28 28 to 01 2, year = 1, 2, and 3

7.5 Alarm control register

When the alarm enable bit of the control and stat us r egister is set (add re ss 00 h, bit2) the alarm control register (address 08h) is activated. All alarm, timer, and interrupt output functions are controlled by the contents of the alarm control register (see Figure 9

Product data sheet Rev. 04 — 6 October 2010 8 of 35

NXP Semiconductors

PCF8593

Low power clock and calendar

MSB LSB

7 654 321 0

013aaa387

memory location 08h

timer function:

000 001 010 011 100 101 110 111

timer interrupt enable:

0 1

clock alarm function:

00 01 10 11

timer alarm enable:

0 1

alarm interrupt enable:

(only valid when alarm enable in the control and status register is set)

0 1

no timer hundredths of a second seconds minutes hours days not used test mode, all counters in parallel

timer flag, no interrupt timer flag, interrupt

no clock alarm daily alarm weekday alarm dated alarm

no timer alarm timer alarm

alarm flag, no interrupt alarm flag, interrupt

Fig 9. Alarm control registers, clock mode

7.6 Alarm registers

All alarm registers are allocated with a constant address offset of 08h to the corresponding counter registers (see Figure 8

An alarm signal is generated when the contents of the alarm re gisters match bit-by-bit the contents of the involved counter registers. The yea r and weekday bits are ignored in a dated alarm. A daily alarm ignores the month and date bits. When a weekday alarm is selected, the contents of the alarm weekday a nd month register selects the weekdays on which an alarm is activated (see Figure 10

Remark: In the 12 hour mode, bits 6 and 7 of the alarm hours register must be the same as the hours counter.

Product data sheet Rev. 04 — 6 October 2010 9 of 35

NXP Semiconductors

MSB LSB

76543210

PCF8593

Low power clock and calendar

memory location 0Eh (alarm_weekday/month)

weekday 0 enabled when set

weekday 1 enabled when set

weekday 2 enabled when set

weekday 3 enabled when set

weekday 4 enabled when set

weekday 5 enabled when set

weekday 6 enabled when set

013aaa375

not used

Fig 10. Selection of alarm weekdays

7.7 Timer

The timer (location 07h) is enabled by setting the control and status register to XX0X X1XX. The timer counts up from 0 (or a programmed value) to 99. On overflow, the timer resets to 0. The timer flag (LSB of control and status register) is set on overflow of the timer. This flag must be reset by software. The inverted value of this flag can be transferred to the external interrupt by setting bit 3 of the alarm control register.

Additionally, a timer alarm can be programmed by setting the timer alarm ena ble (bit 6 of the alarm control register). When the value of the timer equals a pre-programmed value in the alarm timer register (location 0Fh), the alarm flag is set (bit 1 of the control and status register). The inverted value of the alarm flag can be transferred to the external interrupt by enabling the alarm interrupt (bit 6 of the alarm control register).

Resolution of the timer is programmed via the 3 LSBs of the alarm control register (see

Figure 11

Product data sheet Rev. 04 — 6 October 2010 10 of 35

NXP Semiconductors

mode

select

PCF8593

Low power clock and calendar

MUX

oscillator

counter

control

clock

alarm

7 654 321 0 76543210

CONTROL/STATUS

(1)

interrupt

CLOCK/CALENDAR

alarm

control

timer

alarm

TIMERALARM

overflow

timer overflow

interrupt

timer

control

INT

ALARM CONTROL

013aaa377

(1) If the alarm enable bit of the control and status register is reset (logic 0), a 1 Hz signal is observed on the interrupt pin INT.

Fig 11. Alarm and timer interrupt logic diagram

7.8 Event counter mode

Event counter mode is selected by bits 4 and 5 which are logic 10 in the control and st atus register. The event counter mode is used to count pulses externally applied to the oscillator input (OSCO left open-circuit).

The event counter stores up to 6 digits of data, which are stored as 6 hexadecimal valu es located in the registers 1h, 2h, and 3h. Therefore, up to 1 million events may be recorded.

An event counter alarm occurs when the event counter registers match the value programmed in the registers 9h, Ah, and Bh, and the event alar m is enabled ( bits 4 and 5 which are logic 01 in the alarm control register). In this event, the alarm flag (bit 1 of the control and status register) is set. The inverted value of this flag can be transferred to the interrupt pin (pin 7) by setting the alarm interrupt enable in the alarm control register. In

Product data sheet Rev. 04 — 6 October 2010 11 of 35

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NXP PCF8593T/1 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1. General description

2. Features and benefits

3. Ordering information

4. Marking

5. Block diagram

6. Pinning information

6.1 Pinning

6.2 Pin description

7. Functional description

7.1 Counter function modes

7.2 Alarm function modes

7.3 Control and status register

7.4 Counter registers

7.5 Alarm control register

7.6 Alarm registers

7.7 Timer

7.8 Event counter mode