NXP PCF8563T/5 Datasheet

PCF8563

Real-time clock/calendar

Rev. 11 — 26 October 2015 Product data sheet

1. General description

The PCF8563 is a CMOS1 Real-Time Clock (RTC) and calendar optimized for low power consumption. A programmable clock output, interrupt output, and volt age-low detector are also provided. All addresses and data are transferred serially via a two-line bidirectional

C-bus. Maximum bus speed is 400 kbit/s. The register address is incremented

automatically after each written or read data byte.

2. Features and benefits

 Provides year, month, day, weekday, hours, minutes, and seconds based on a

32.768 kHz quartz crystal

 Century flag  Clock operating voltage: 1.0 V to 5.5 V at room temperature  Low backup current; typical 0.25 Aat V  400 kHz two-wire I  Programmable clock output for peripheral devices (32.768 kHz, 1.024 kHz, 32 Hz, and

1Hz)

 Alarm and timer functions  Integrated oscillator capacitor  Internal Power-On Reset (POR)

C-bus slave address: read A3h and write A2h

 I  Open-drain interrupt pin

= 3.0 V and T

C-bus interface (at VDD= 1.8 V to 5.5 V)

amb

=25C

3. Applications

 Mobile telephones  Portable instruments  Electronic metering  Battery powered products

1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 18.

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4. Ordering information

Table 1. Ordering information

Type number Package

PCF8563BS/4 HVSON10 plastic thermal enhanced very thin small outl ine

PCF8563T/5 SO8 plastic small outline package; 8 leads;

PCF8563T/F4

PCF8563TS/4

PCF8563TS/5 TSSOP8 plastic thin shrink small outline package; 8 leads;

[1] Not recommended for new designs. Replacement part is PCF8563T/5. [2] Not recommended for new designs. Replacement part is PCF8563TS/5.

PCF8563

Real-time clock/calendar

Name Description Version

package; no leads; 10 terminals; body 3  3  0.85 mm

body width 3.9 mm

[1]

SO8 plastic small outline package; 8 leads;

body width 3.9 mm

[2]

TSSOP8 plastic thin shrink small outline package; 8 leads;

body width 3 mm

SOT650-1

SOT96-1

SOT505-1

5. Marking

Table 2. Marking codes

Type number Marking code

PCF8563BS/4 8563S PCF8563T/5 PCF8563 PCF8563T/F4 8563T PCF8563TS/4 8563 PCF8563TS/5 P8563

Product data sheet Rev. 11 — 26 October 2015 2 of 45

NXP Semiconductors

001aah658

PCF8563

OSCILLATOR

32.768 kHz

DIVIDER CLOCK OUT

INTERRUPT

CLKOUT

INT

MONITOR

POWER ON

RESET

WATCH

DOG

I2C-BUS

INTERFACE

OSCI

SCL

SDA

OSCO

TIMER FUNCTION

TIMER_CONTROL0E

TIMER0F

CONTROL CONTROL_STATUS_100 CONTROL_STATUS_201

CLKOUT_CONTROL0D

TIME

VL_SECONDS02

MINUTES03

HOURS04

DAYS05

ALARM FUNCTION

MINUTE_ALARM09

HOUR_ALARM0A

DAY_ALARM0B

WEEKDAY_ALARM0C

WEEKDAYS06

CENTURY_MONTHS07

YEARS08

(1)

6. Block diagram

PCF8563

Real-time clock/calendar

(1) C

Fig 1. Block diagram of PCF8563

; values see Table 30.

OSCO

Product data sheet Rev. 11 — 26 October 2015 3 of 45

NXP Semiconductors

001aaf981

PCF8563BS

SDA

INT

SCL

n.c. CLKOUT

OSCO V

OSCI n.c.

Transparent top view

4 7

3 8

2 9

1 10

terminal 1

index area

PCF8563T

OSCI V

OSCO CLKOUT

INT

SCL

SDA

001aaf975

1 2 3 4

6 5

8 7

PCF8563TS

OSCI V

OSCO CLKOUT

INT SCL

SDA

001aaf976

1 2 3 4

6 5

8 7

7. Pinning information

7.1 Pinning

For mechanical details, see Figure 29. Top view. For mechanical details, see

Fig 2. Pin configuration for HVSON10

(PCF8563BS)

PCF8563

Real-time clock/calendar

Figure 30

Fig 3. Pin configuration for SO8

(PCF8563T)

Product data sheet Rev. 11 — 26 October 2015 4 of 45

Top view. For mechanical details, see Figure 31.

Fig 4. Pin configuration for TSSOP8 (PCF8563TS)

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7.2 Pin description

Table 3. Pin description

Symbol Pin Description

OSCI 1 1 oscillator input OSCO 2 2 oscillator output INT V

SDA 5 6 serial data input and output SCL 6 7 serial clock input CLKOUT 7 8 clock output, open-drain V

n.c. - 3, 10 not connected; do not connect and do not

[1] The die paddle (exposed pad) is connected to VSS through high ohmic (non-conductive) silicon attach and

PCF8563

Real-time clock/calendar

SO8, TSSOP8 HVSON10

3 4 interrupt output (open-drain; active LOW) 45

8 9 supply voltage

should be electrically isolated. It is good engineering practice to solder the exposed pad to an electrically isolated PCB copper pad for better heat transfer but it is not required as the RTC doesn’t consume much power. In no case should traces be run under the package exposed pad.

[1]

ground

use as feed through

Product data sheet Rev. 11 — 26 October 2015 5 of 45

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8. Functional description

The PCF8563 contains sixteen 8-bit registers with an auto-incr ementing register add ress, an on-chip 32.768 kHz oscillator with one integrated capacitor, a frequency divider which provides the source clock for the Real-Time Clock (RTC) and calender, a programmable clock output, a timer, an alarm, a voltage-low detector, and a 400 kHz I

All 16 registers are designed as addressable 8-bit parallel registers although not all bits are implemented. The first two registers (memory address 00h and 01h) are used as control and/or status registers. The memory addresses 02h through 08h are used as counters for the clock function (seconds up to years counters). Address locations 09h through 0 Ch contain alar m re gis te rs wh ich de fin e the cond itio ns for an alar m . Address 0 Dh contro ls the CLKO UT ou tp ut fr eque n cy. 0Eh and 0Fh are the Timer_control and Timer registers, respectively.

The Seconds, Minutes, Hours, Days, Months, Years as well as the Minute_alarm, Hour_alarm, and Day_alarm registers are all coded in Binary Coded Decimal (BCD) format.

When one of the RTC registers is written or read, the contents of all time counters are frozen. Therefore, faulty writing or reading of the clock and calendar during a carry condition is prevented.

PCF8563

Real-time clock/calendar

C-bus interface.

8.1 CLKOUT output

A programmable square wave is available at the CLKOUT pin. Operation is controlled by the register CLKOUT_control at address 0Dh. Frequencies of 32.768 kHz (default),

1.024 kHz, 32 Hz, and 1 Hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. CLKOUT is an open-drain output and enabled at power-on. If disabled it becomes high-impedance.

8.2 Register organization

Table 4. Formatted registers overview

Bit positions labelled as x are not relevant. Bit positions labelled with N should always be written with logic 0; if read they could be either logic 0 or logic 1 . After reset, all registers are set according to Table 27

Address Register name Bit

Control and status registers

00h Control_status_1 TEST1 N STOP N TESTC N N N 01h Control_status_2 N N N TI_TP AF TF AIE TIE

Time and date registers

02h VL_seconds VL SECONDS (0 to 59) 03h Minutes x MINUTES (0 to 59) 04h Hours x x HOURS (0 to 23) 05h Days x x DAYS (1 to 31) 06hWeekdaysxxxxxWEEKDAYS (0 to 6) 07h Century_months C x x M ONTHS (1 to 12) 08h Years YEARS (0 to 99)

7 6 5 4 3 2 1 0

Product data sheet Rev. 11 — 26 October 2015 6 of 45

NXP Semiconductors

PCF8563

Real-time clock/calendar

Table 4. Formatted registers overview

…continued

Address Register name Bit

7 6 5 4 3 2 1 0

Alarm registers

09h Minute_alarm AE_M MINUTE_ALARM (0 to 59) 0Ah Hour_alarm AE_H x HOUR_ALARM (0 to 23) 0Bh Day_alarm AE_D x DAY_ALARM (1 to 31) 0ChWeekday_alarmAE_WxxxxWEEKDAY_ALARM (0 to 6)

CLKOUT control register

0DhCLKOUT_controlFExxxxxFD[1:0]

Timer registers

0EhTimer_controlTExxxxxTD[1:0] 0Fh Timer TIMER[7:0]

8.3 Control registers

8.3.1 Register Control_status_1

Table 5. Control_status_1 - control and status register 1 (address 00h) bit description

Bit Symbol Value Description Reference

7 TEST1 0

6N 0 5STOP0

4N 0 3 TESTC 0 Power-On Reset (POR) override facility is disabled; set to logic 0 for

2to0 N 000

[1]

normal mode

must be set to logic 0 during normal operations

1 EXT_CLK test mode

[2] [1]

unused RTC source clock runs Section 8.10

1 all RTC divider chain flip-flops are asynchronously set to logic 0; the RTC

clock is stopped (CLKOUT at 32.768 kHz is still available)

[2]

unused

normal operation

[1]

Power-On Reset (POR) override may be enabled

[2]

unused

Section 8.9

Section 8.11.1

[1] Default value. [2] Bits labeled as N should always be written with logic 0.

8.3.2 Register Control_status_2

Table 6. Control_status_2 - control and status register 2 (address 01h) bit description

Bit Symbol Value Description Reference

7to5 N 000 4TI_TP0

Product data sheet Rev. 11 — 26 October 2015 7 of 45

[1]

[2]

unused INT is active when TF is active (subject to the status of TIE) Section 8.3.2.1

1INT pulses active according to Table 7 (subject to the status of TIE);

Remark: note that if AF and AIE are active then INT

will be

permanently active

and

Section 8.8

NXP Semiconductors

013aaa087

COUNTDOWN COUNTER

AF: ALARM

FLAG

CLEAR

SET

to interface: read AF

0 1

TF: TIMER

CLEAR

SET

PULSE

GENERATOR 2

CLEAR

TRIGGER

TIE

INT

from interface:

clear TF

from interface:

clear AF

set alarm

flag AF

to interface: read TF

TI_TP

AIE

e.g. AIE

0 1

PCF8563

Real-time clock/calendar

Table 6. Control_status_2 - control and status register 2 (address 01h) bit description …continued

Bit Symbol Value Description Reference

3AF 0

2TF 0

1AIE 0

0TIE 0

[2]

read: alarm flag inactive Section 8.3.2.1 write: alarm flag is cleared

1 read: alarm flag active

write: alarm flag remains unchanged

[2]

read: timer flag inactive write: timer flag is cleared

1 read: timer flag active

write: timer flag remains unchanged

[2]

alarm interrupt disabled

1 alarm interrupt enabled

[2]

timer interrupt disabled

1 timer interrupt enabled

[1] Bits labeled as N should always be written with logic 0. [2] Default value.

8.3.2.1 Interrupt output

Bits TF and AF: When an alarm occurs, AF is set to logic 1. Similarly, at the end of a

timer countdown, TF is set to logic 1. These bits maintain their value until overwritten using the interface. If both timer and alarm interrupts are required in the application, the source of the interrupt can be determined by reading these bit s. To prevent one flag being overwritten while clearing another, a logic AND is performed during a write access.

Fig 5. Interrupt scheme

Product data sheet Rev. 11 — 26 October 2015 8 of 45

When bits TIE and AIE are disabled, pin INT will remain high-impedance.

Bits TIE and AIE: These bits activate or deactivate the generation of an interrupt when

TF or AF is asserted, respectively. The interrupt is the logical OR of these two conditions when both AIE and TIE are set.

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Countdown timer interrupts: The pulse generator for the countdown timer interrupt uses

an internal clock and is dependent on the selected source clock for the countdown timer and on the countdown value n. As a consequence, the width of the interrupt pulse varies (see Table 7

Table 7. INT operation (bit TI_TP = 1)

Source clock (Hz) INT period (s)

4096 64 1

⁄

[1] TF and INT become active simultaneously. [2] n = loaded countdown value. Timer stops when n = 0.

8.4 Time and date registers

The majority of the registers are coded in the BCD form at to simp lify ap plic at ion use .

PCF8563

Real-time clock/calendar

[1]

n=1

⁄

8192

⁄

128

⁄

[2]

n>1

⁄

4096

⁄

[2]

8.4.1 Register VL_seconds

Table 8. VL_seconds - seconds and clock integrity status register (address 02h) bi t

description

Bit Symbol Value Place value Description

7 VL 0 - clock integrity is guaranteed

[1]

1 6 to 4 SECONDS 0 to 5 ten’s place actual seconds coded in BCD format, see Table 9 3 to 0 0 to 9 unit place

[1] Start-up value.

Table 9. Seconds coded in BCD format

Seconds value (decimal)

00 0000000 01 0000001 02 0000010 : ::::::: 09 0001001 10 0010000 : ::::::: 58 1011000 59 1011001

Upper-digit (ten’s place) Digit (unit place) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

- integrity of the clock information is not guaranteed

Product data sheet Rev. 11 — 26 October 2015 9 of 45

NXP Semiconductors

VL set

normal power operation

period of battery operation

low

mgr887

8.4.1.1 Voltage-low detector and clock monitor

PCF8563

Real-time clock/calendar

The PCF8563 has an on-chip voltage-low detector (see Figure 6 V

, bit VL in the VL_seconds register is set to indicate that the integrity of the clock

low

information is no longer guaranteed. The VL flag can only be cleared by using the interface.

Fig 6. Voltage-low detection

The VL flag is intended to detect the situation when VDD is decreasing slowly, for example under battery operation. Should the oscillator stop or V re-asserted, then the VL flag is set. This will indicate that the time may be corrupted.

8.4.2 Register Minutes

Table 10. Minutes - minutes register (address 03h) bit description

Bit Symbol Value Place value Description

7 - - - unused 6 to 4 MINUTES 0 to 5 ten’s place actual minutes coded in BCD format 3 to 0 0 to 9 unit place

reach V

). When VDD drops below

before power is

low

8.4.3 Register Hours

Table 11. Hours - hours register (address 04h) bit descrip tion

Bit Symbol Value Place value Description

7 to 6 - - - unused 5 to 4 HOURS 0 to 2 ten’s place actual hours coded in BCD format 3to0 0to9 unit place

8.4.4 Register Days

Table 12. Days - days register (address 05h) bit description

Bit Symbol Value Place value Description

7 to 6 - - - unused

[1]

5to4 DAYS

Product data sheet Rev. 11 — 26 October 2015 10 of 45

3to0 0to9 unit place

[1] The PCF8563 compensates for leap years by adding a 29th day to February if the year counter contains a

value which is exactly divisible by 4, including the year 00.

0 to 3 ten’s place actual day coded in BCD format

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8.4.5 Register Weekdays

Table 13. Weekdays - weekdays register (address 06h) bit descriptio n

Bit Symbol Value Description

7 to 3 - - unuse d 2 to 0 WEEKDAYS 0 to 6 actual weekday values, see Table 14

Table 14. Weekday assignments

Day

Sunday 0 0 0 Monday 0 0 1 Tuesday 0 1 0 Wednesday 0 1 1 Thursday 1 0 0 Friday 1 0 1 Saturday110

[1]

PCF8563

Real-time clock/calendar

Bit 2 1 0

[1] Definition may be re-assigned by the user.

8.4.6 Register Century_months

Table 15. Century_months - century flag and months register (addres s 07h) bit description

Bit Symbol Value Place value Description

[1]

6 to 5 - - - unused 4 MONTHS 0 to 1 ten’s place actual month coded in BCD format, see Table 16 3 to 0 0 to 9 unit place

[1] This bit may be re-assigned by the user. [2] This bit is toggled when the register Years overflows from 99 to 00.

Table 16. Month assignments in BCD format

Month Upper-digit

January 0 0 0 0 1 February 0 0 0 1 0 March 0 0 0 1 1 April00100 May00101 June00110 July00111 August01000 September 0 1 0 0 1

[2]

- indicates the century is x

1 - indicates the century is x + 1

Digit (unit place)

(ten’s place) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Product data sheet Rev. 11 — 26 October 2015 11 of 45

NXP Semiconductors

013aaa092

1 Hz tick

WEEKDAY

SECONDS

MINUTES

HOURS

DAYS

LEAP YEAR CALCULATION

MONTHS

YEARS

PCF8563

Real-time clock/calendar

Table 16. Month assignments

Month Upper-digit

…continuedin BCD format

Digit (unit place)

(ten’s place) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

October10000 November10001 December10010

8.4.7 Register Years

Table 17. Years - years register (08h) bit description

Bit Symbol Value Place value Description

7 to 4 YEARS 0 to 9 ten’s place actual year coded in BCD format 3to0 0to9 unit place

[1] When the register Years overflows from 99 to 00, the century bit C in the register Century_months is

toggled.

8.5 Setting and reading the time

Figure 7 shows the data flow and data dependencies starting from the 1 Hz clock tick.

[1]

Fig 7. Data flow for the time function

During read/write operations, the time counting circuits (memory locations 02h through 08h) are blocked.

This prevents

• Faulty reading of the clock and calendar during a carry condition

• Incrementing the time registers, during the read cycle

Product data sheet Rev. 11 — 26 October 2015 12 of 45

NXP Semiconductors

t < 1 s

013aaa215

SLAVE ADDRESS DATA STOPDATA

START

After this read/write access is completed, the time circuit is released again and any pending request to increment the time counters that occurred during the read access is serviced. A maximum of 1 request can be stored; therefore, all accesses must be completed within 1 second (see Figure 8

Fig 8. Access time for read/write operations

As a consequence of this method, it is very important to make a read or write access in one go, that is, setting or reading seconds through to years should be made in on e single access. Failing to comply with this method could result in the time becoming corrupted.

As an example, if the time (seconds through to hours) is set in one access and then in a second access the date is set, it is possible that the time may increment between the two accesses. A similar problem exists when reading. A roll over may occu r be twe e n read s thus giving the minutes from one moment and the hours from the next.

PCF8563

Real-time clock/calendar

Recommended method for reading the time:

1. Send a START condition and the slave address for write (A2h).

2. Set the address pointer to 2 (VL_seconds) by sending 02h.

3. Send a RESTART condition or STOP followed by START.

4. Send the slave address for read (A3h).

5. Read VL_seconds.

6. Read Minutes.

7. Read Hours.

8. Read Days.

9. Read Weekdays.

10. Read Century_months.

11. Read Years.

12. Send a STOP condition.

8.6 Alarm registers

8.6.1 Register Minute_alarm

Table 18. Minute_alarm - minute alarm register (address 09h ) bi t description

Bit Symbol Value Place value Description

7 AE_M 0 - minute alarm is enabled

6 to 4 MINUTE_ALARM 0 to 5 ten’s place minute alarm information coded in BCD 3 to 0 0 to 9 unit place

[1]

- minute alarm is disabled

format

Product data sheet Rev. 11 — 26 October 2015 13 of 45

NXP Semiconductors

[1] Default value.

8.6.2 Register Hour_alarm

Table 19. Hour_alarm - hour alarm register (address 0Ah) bit descri ption

Bit Symbol Value Place value Description

7 AE_H 0 - hour alarm is enabled

6 - - - unused 5 to 4 HOUR_ALARM 0 to 2 ten’s place hour alarm information coded in BCD 3 to 0 0 to 9 unit place

[1] Default value.

8.6.3 Register Day_alarm

Table 20. Day_alarm - day alarm register (address 0Bh) bit description

Bit Symbol Value Place value Description

7 AE_D 0 - day alarm is enabled

6 - - - unused 5 to 4 DAY_ALARM 0 to 3 ten’s place day alarm information coded in BCD 3 to 0 0 to 9 unit place

PCF8563

Real-time clock/calendar

[1]

- hour alarm is disabled

format

- day alarm is disabled

format

[1] Default value.

8.6.4 Register Weekday_alarm

Table 21. Weekday_alarm - weekday alarm register (address 0Ch) bit description

Bit Symbol Value Description

7 AE_W 0 weekday alarm is enabled

1 6 to 3 - - unused 2 to 0 WEEKDAY_ALARM 0 to 6 weekday alarm information

[1] Default value.

8.6.5 Alarm flag

By clearing the alarm enable bit (AE_x) of one or more of the alarm registers, the corresponding alarm condition(s) are active. When an alarm occurs, AF is set to logic 1. The asserted AF can be used to generate an interrupt (INT interface.

The registers at addresses 09h through 0Ch contain alarm information. When one or more of these registers is loaded with minute, hour, day or weekday, and its corresponding AE_x is logic 0, then that information is compared with the current minute, hour, day, and weekday. When all enabled comparisons first match, the alarm flag (AF in register Control_2) is set to logic 1.

[1]

weekday alarm is disabled

). The AF is cleared using the

Product data sheet Rev. 11 — 26 October 2015 14 of 45

+ 31 hidden pages

NXP PCF8563T/5 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1. General description

2. Features and benefits

3. Applications

4. Ordering information

5. Marking

6. Block diagram

7. Pinning information

7.1 Pinning

7.2 Pin description

8. Functional description

8.1 CLKOUT output

8.2 Register organization

8.3 Control registers

8.3.1 Register Control_status_1

8.3.2 Register Control_status_2

8.3.2.1 Interrupt output

8.4 Time and date registers

8.4.1 Register VL_seconds

8.4.1.1 Voltage-low detector and clock monitor

8.4.2 Register Minutes

8.4.3 Register Hours

8.4.4 Register Days

8.4.5 Register Weekdays

8.4.6 Register Century_months

8.4.7 Register Years

8.5 Setting and reading the time

8.6 Alarm registers

8.6.1 Register Minute_alarm

8.6.2 Register Hour_alarm

8.6.3 Register Day_alarm

8.6.4 Register Weekday_alarm

8.6.5 Alarm flag