NXP PCF8563T/5 Datasheet

PCF8563

Real-time clock/calendar

Rev. 11 — 26 October 2015 Product data sheet

1. General description

The PCF8563 is a CMOS1 Real-Time Clock (RTC) and calendar optimized for low power consumption. A programmable clock output, interrupt output, and volt age-low detector are also provided. All addresses and data are transferred serially via a two-line bidirectional

C-bus. Maximum bus speed is 400 kbit/s. The register address is incremented

automatically after each written or read data byte.

2. Features and benefits

 Provides year, month, day, weekday, hours, minutes, and seconds based on a

32.768 kHz quartz crystal

 Century flag  Clock operating voltage: 1.0 V to 5.5 V at room temperature  Low backup current; typical 0.25 Aat V  400 kHz two-wire I  Programmable clock output for peripheral devices (32.768 kHz, 1.024 kHz, 32 Hz, and

1Hz)

 Alarm and timer functions  Integrated oscillator capacitor  Internal Power-On Reset (POR)

C-bus slave address: read A3h and write A2h

 I  Open-drain interrupt pin

= 3.0 V and T

C-bus interface (at VDD= 1.8 V to 5.5 V)

amb

=25C

3. Applications

 Mobile telephones  Portable instruments  Electronic metering  Battery powered products

1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 18.

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4. Ordering information

Table 1. Ordering information

Type number Package

PCF8563BS/4 HVSON10 plastic thermal enhanced very thin small outl ine

PCF8563T/5 SO8 plastic small outline package; 8 leads;

PCF8563T/F4

PCF8563TS/4

PCF8563TS/5 TSSOP8 plastic thin shrink small outline package; 8 leads;

[1] Not recommended for new designs. Replacement part is PCF8563T/5. [2] Not recommended for new designs. Replacement part is PCF8563TS/5.

PCF8563

Real-time clock/calendar

Name Description Version

package; no leads; 10 terminals; body 3  3  0.85 mm

body width 3.9 mm

[1]

SO8 plastic small outline package; 8 leads;

body width 3.9 mm

[2]

TSSOP8 plastic thin shrink small outline package; 8 leads;

body width 3 mm

SOT650-1

SOT96-1

SOT505-1

5. Marking

Table 2. Marking codes

Type number Marking code

PCF8563BS/4 8563S PCF8563T/5 PCF8563 PCF8563T/F4 8563T PCF8563TS/4 8563 PCF8563TS/5 P8563

Product data sheet Rev. 11 — 26 October 2015 2 of 45

NXP Semiconductors

001aah658

PCF8563

OSCILLATOR

32.768 kHz

DIVIDER CLOCK OUT

INTERRUPT

CLKOUT

INT

MONITOR

POWER ON

RESET

WATCH

DOG

I2C-BUS

INTERFACE

OSCI

SCL

SDA

OSCO

TIMER FUNCTION

TIMER_CONTROL0E

TIMER0F

CONTROL CONTROL_STATUS_100 CONTROL_STATUS_201

CLKOUT_CONTROL0D

TIME

VL_SECONDS02

MINUTES03

HOURS04

DAYS05

ALARM FUNCTION

MINUTE_ALARM09

HOUR_ALARM0A

DAY_ALARM0B

WEEKDAY_ALARM0C

WEEKDAYS06

CENTURY_MONTHS07

YEARS08

(1)

6. Block diagram

PCF8563

Real-time clock/calendar

(1) C

Fig 1. Block diagram of PCF8563

; values see Table 30.

OSCO

Product data sheet Rev. 11 — 26 October 2015 3 of 45

NXP Semiconductors

001aaf981

PCF8563BS

SDA

INT

SCL

n.c. CLKOUT

OSCO V

OSCI n.c.

Transparent top view

4 7

3 8

2 9

1 10

terminal 1

index area

PCF8563T

OSCI V

OSCO CLKOUT

INT

SCL

SDA

001aaf975

1 2 3 4

6 5

8 7

PCF8563TS

OSCI V

OSCO CLKOUT

INT SCL

SDA

001aaf976

1 2 3 4

6 5

8 7

7. Pinning information

7.1 Pinning

For mechanical details, see Figure 29. Top view. For mechanical details, see

Fig 2. Pin configuration for HVSON10

(PCF8563BS)

PCF8563

Real-time clock/calendar

Figure 30

Fig 3. Pin configuration for SO8

(PCF8563T)

Product data sheet Rev. 11 — 26 October 2015 4 of 45

Top view. For mechanical details, see Figure 31.

Fig 4. Pin configuration for TSSOP8 (PCF8563TS)

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7.2 Pin description

Table 3. Pin description

Symbol Pin Description

OSCI 1 1 oscillator input OSCO 2 2 oscillator output INT V

SDA 5 6 serial data input and output SCL 6 7 serial clock input CLKOUT 7 8 clock output, open-drain V

n.c. - 3, 10 not connected; do not connect and do not

[1] The die paddle (exposed pad) is connected to VSS through high ohmic (non-conductive) silicon attach and

PCF8563

Real-time clock/calendar

SO8, TSSOP8 HVSON10

3 4 interrupt output (open-drain; active LOW) 45

8 9 supply voltage

should be electrically isolated. It is good engineering practice to solder the exposed pad to an electrically isolated PCB copper pad for better heat transfer but it is not required as the RTC doesn’t consume much power. In no case should traces be run under the package exposed pad.

[1]

ground

use as feed through

Product data sheet Rev. 11 — 26 October 2015 5 of 45

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8. Functional description

The PCF8563 contains sixteen 8-bit registers with an auto-incr ementing register add ress, an on-chip 32.768 kHz oscillator with one integrated capacitor, a frequency divider which provides the source clock for the Real-Time Clock (RTC) and calender, a programmable clock output, a timer, an alarm, a voltage-low detector, and a 400 kHz I

All 16 registers are designed as addressable 8-bit parallel registers although not all bits are implemented. The first two registers (memory address 00h and 01h) are used as control and/or status registers. The memory addresses 02h through 08h are used as counters for the clock function (seconds up to years counters). Address locations 09h through 0 Ch contain alar m re gis te rs wh ich de fin e the cond itio ns for an alar m . Address 0 Dh contro ls the CLKO UT ou tp ut fr eque n cy. 0Eh and 0Fh are the Timer_control and Timer registers, respectively.

The Seconds, Minutes, Hours, Days, Months, Years as well as the Minute_alarm, Hour_alarm, and Day_alarm registers are all coded in Binary Coded Decimal (BCD) format.

When one of the RTC registers is written or read, the contents of all time counters are frozen. Therefore, faulty writing or reading of the clock and calendar during a carry condition is prevented.

PCF8563

Real-time clock/calendar

C-bus interface.

8.1 CLKOUT output

A programmable square wave is available at the CLKOUT pin. Operation is controlled by the register CLKOUT_control at address 0Dh. Frequencies of 32.768 kHz (default),

1.024 kHz, 32 Hz, and 1 Hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. CLKOUT is an open-drain output and enabled at power-on. If disabled it becomes high-impedance.

8.2 Register organization

Table 4. Formatted registers overview

Bit positions labelled as x are not relevant. Bit positions labelled with N should always be written with logic 0; if read they could be either logic 0 or logic 1 . After reset, all registers are set according to Table 27

Address Register name Bit

Control and status registers

00h Control_status_1 TEST1 N STOP N TESTC N N N 01h Control_status_2 N N N TI_TP AF TF AIE TIE

Time and date registers

02h VL_seconds VL SECONDS (0 to 59) 03h Minutes x MINUTES (0 to 59) 04h Hours x x HOURS (0 to 23) 05h Days x x DAYS (1 to 31) 06hWeekdaysxxxxxWEEKDAYS (0 to 6) 07h Century_months C x x M ONTHS (1 to 12) 08h Years YEARS (0 to 99)

7 6 5 4 3 2 1 0

Product data sheet Rev. 11 — 26 October 2015 6 of 45

NXP Semiconductors

PCF8563

Real-time clock/calendar

Table 4. Formatted registers overview

…continued

Address Register name Bit

7 6 5 4 3 2 1 0

Alarm registers

09h Minute_alarm AE_M MINUTE_ALARM (0 to 59) 0Ah Hour_alarm AE_H x HOUR_ALARM (0 to 23) 0Bh Day_alarm AE_D x DAY_ALARM (1 to 31) 0ChWeekday_alarmAE_WxxxxWEEKDAY_ALARM (0 to 6)

CLKOUT control register

0DhCLKOUT_controlFExxxxxFD[1:0]

Timer registers

0EhTimer_controlTExxxxxTD[1:0] 0Fh Timer TIMER[7:0]

8.3 Control registers

8.3.1 Register Control_status_1

Table 5. Control_status_1 - control and status register 1 (address 00h) bit description

Bit Symbol Value Description Reference

7 TEST1 0

6N 0 5STOP0

4N 0 3 TESTC 0 Power-On Reset (POR) override facility is disabled; set to logic 0 for

2to0 N 000

[1]

normal mode

must be set to logic 0 during normal operations

1 EXT_CLK test mode

[2] [1]

unused RTC source clock runs Section 8.10

1 all RTC divider chain flip-flops are asynchronously set to logic 0; the RTC

clock is stopped (CLKOUT at 32.768 kHz is still available)

[2]

unused

normal operation

[1]

Power-On Reset (POR) override may be enabled

[2]

unused

Section 8.9

Section 8.11.1

[1] Default value. [2] Bits labeled as N should always be written with logic 0.

8.3.2 Register Control_status_2

Table 6. Control_status_2 - control and status register 2 (address 01h) bit description

Bit Symbol Value Description Reference

7to5 N 000 4TI_TP0

Product data sheet Rev. 11 — 26 October 2015 7 of 45

[1]

[2]

unused INT is active when TF is active (subject to the status of TIE) Section 8.3.2.1

1INT pulses active according to Table 7 (subject to the status of TIE);

Remark: note that if AF and AIE are active then INT

will be

permanently active

and

Section 8.8

NXP Semiconductors

013aaa087

COUNTDOWN COUNTER

AF: ALARM

FLAG

CLEAR

SET

to interface: read AF

0 1

TF: TIMER

CLEAR

SET

PULSE

GENERATOR 2

CLEAR

TRIGGER

TIE

INT

from interface:

clear TF

from interface:

clear AF

set alarm

flag AF

to interface: read TF

TI_TP

AIE

e.g. AIE

0 1

PCF8563

Real-time clock/calendar

Table 6. Control_status_2 - control and status register 2 (address 01h) bit description …continued

Bit Symbol Value Description Reference

3AF 0

2TF 0

1AIE 0

0TIE 0

[2]

read: alarm flag inactive Section 8.3.2.1 write: alarm flag is cleared

1 read: alarm flag active

write: alarm flag remains unchanged

[2]

read: timer flag inactive write: timer flag is cleared

1 read: timer flag active

write: timer flag remains unchanged

[2]

alarm interrupt disabled

1 alarm interrupt enabled

[2]

timer interrupt disabled

1 timer interrupt enabled

[1] Bits labeled as N should always be written with logic 0. [2] Default value.

8.3.2.1 Interrupt output

Bits TF and AF: When an alarm occurs, AF is set to logic 1. Similarly, at the end of a

timer countdown, TF is set to logic 1. These bits maintain their value until overwritten using the interface. If both timer and alarm interrupts are required in the application, the source of the interrupt can be determined by reading these bit s. To prevent one flag being overwritten while clearing another, a logic AND is performed during a write access.

Fig 5. Interrupt scheme

Product data sheet Rev. 11 — 26 October 2015 8 of 45

When bits TIE and AIE are disabled, pin INT will remain high-impedance.

Bits TIE and AIE: These bits activate or deactivate the generation of an interrupt when

TF or AF is asserted, respectively. The interrupt is the logical OR of these two conditions when both AIE and TIE are set.

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Countdown timer interrupts: The pulse generator for the countdown timer interrupt uses

an internal clock and is dependent on the selected source clock for the countdown timer and on the countdown value n. As a consequence, the width of the interrupt pulse varies (see Table 7

Table 7. INT operation (bit TI_TP = 1)

Source clock (Hz) INT period (s)

4096 64 1

⁄

[1] TF and INT become active simultaneously. [2] n = loaded countdown value. Timer stops when n = 0.

8.4 Time and date registers

The majority of the registers are coded in the BCD form at to simp lify ap plic at ion use .

PCF8563

Real-time clock/calendar

[1]

n=1

⁄

8192

⁄

128

⁄

[2]

n>1

⁄

4096

⁄

[2]

8.4.1 Register VL_seconds

Table 8. VL_seconds - seconds and clock integrity status register (address 02h) bi t

description

Bit Symbol Value Place value Description

7 VL 0 - clock integrity is guaranteed

[1]

1 6 to 4 SECONDS 0 to 5 ten’s place actual seconds coded in BCD format, see Table 9 3 to 0 0 to 9 unit place

[1] Start-up value.

Table 9. Seconds coded in BCD format

Seconds value (decimal)

00 0000000 01 0000001 02 0000010 : ::::::: 09 0001001 10 0010000 : ::::::: 58 1011000 59 1011001

Upper-digit (ten’s place) Digit (unit place) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

- integrity of the clock information is not guaranteed

Product data sheet Rev. 11 — 26 October 2015 9 of 45

NXP Semiconductors

VL set

normal power operation

period of battery operation

low

mgr887

8.4.1.1 Voltage-low detector and clock monitor

PCF8563

Real-time clock/calendar

The PCF8563 has an on-chip voltage-low detector (see Figure 6 V

, bit VL in the VL_seconds register is set to indicate that the integrity of the clock

low

information is no longer guaranteed. The VL flag can only be cleared by using the interface.

Fig 6. Voltage-low detection

The VL flag is intended to detect the situation when VDD is decreasing slowly, for example under battery operation. Should the oscillator stop or V re-asserted, then the VL flag is set. This will indicate that the time may be corrupted.

8.4.2 Register Minutes

Table 10. Minutes - minutes register (address 03h) bit description

Bit Symbol Value Place value Description

7 - - - unused 6 to 4 MINUTES 0 to 5 ten’s place actual minutes coded in BCD format 3 to 0 0 to 9 unit place

reach V

). When VDD drops below

before power is

low

8.4.3 Register Hours

Table 11. Hours - hours register (address 04h) bit descrip tion

Bit Symbol Value Place value Description

7 to 6 - - - unused 5 to 4 HOURS 0 to 2 ten’s place actual hours coded in BCD format 3to0 0to9 unit place

8.4.4 Register Days

Table 12. Days - days register (address 05h) bit description

Bit Symbol Value Place value Description

7 to 6 - - - unused

[1]

5to4 DAYS

Product data sheet Rev. 11 — 26 October 2015 10 of 45

3to0 0to9 unit place

[1] The PCF8563 compensates for leap years by adding a 29th day to February if the year counter contains a

value which is exactly divisible by 4, including the year 00.

0 to 3 ten’s place actual day coded in BCD format

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8.4.5 Register Weekdays

Table 13. Weekdays - weekdays register (address 06h) bit descriptio n

Bit Symbol Value Description

7 to 3 - - unuse d 2 to 0 WEEKDAYS 0 to 6 actual weekday values, see Table 14

Table 14. Weekday assignments

Day

Sunday 0 0 0 Monday 0 0 1 Tuesday 0 1 0 Wednesday 0 1 1 Thursday 1 0 0 Friday 1 0 1 Saturday110

[1]

PCF8563

Real-time clock/calendar

Bit 2 1 0

[1] Definition may be re-assigned by the user.

8.4.6 Register Century_months

Table 15. Century_months - century flag and months register (addres s 07h) bit description

Bit Symbol Value Place value Description

[1]

6 to 5 - - - unused 4 MONTHS 0 to 1 ten’s place actual month coded in BCD format, see Table 16 3 to 0 0 to 9 unit place

[1] This bit may be re-assigned by the user. [2] This bit is toggled when the register Years overflows from 99 to 00.

Table 16. Month assignments in BCD format

Month Upper-digit

January 0 0 0 0 1 February 0 0 0 1 0 March 0 0 0 1 1 April00100 May00101 June00110 July00111 August01000 September 0 1 0 0 1

[2]

- indicates the century is x

1 - indicates the century is x + 1

Digit (unit place)

(ten’s place) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Product data sheet Rev. 11 — 26 October 2015 11 of 45

NXP Semiconductors

013aaa092

1 Hz tick

WEEKDAY

SECONDS

MINUTES

HOURS

DAYS

LEAP YEAR CALCULATION

MONTHS

YEARS

PCF8563

Real-time clock/calendar

Table 16. Month assignments

Month Upper-digit

…continuedin BCD format

Digit (unit place)

(ten’s place) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

October10000 November10001 December10010

8.4.7 Register Years

Table 17. Years - years register (08h) bit description

Bit Symbol Value Place value Description

7 to 4 YEARS 0 to 9 ten’s place actual year coded in BCD format 3to0 0to9 unit place

[1] When the register Years overflows from 99 to 00, the century bit C in the register Century_months is

toggled.

8.5 Setting and reading the time

Figure 7 shows the data flow and data dependencies starting from the 1 Hz clock tick.

[1]

Fig 7. Data flow for the time function

During read/write operations, the time counting circuits (memory locations 02h through 08h) are blocked.

This prevents

• Faulty reading of the clock and calendar during a carry condition

• Incrementing the time registers, during the read cycle

Product data sheet Rev. 11 — 26 October 2015 12 of 45

NXP Semiconductors

t < 1 s

013aaa215

SLAVE ADDRESS DATA STOPDATA

START

After this read/write access is completed, the time circuit is released again and any pending request to increment the time counters that occurred during the read access is serviced. A maximum of 1 request can be stored; therefore, all accesses must be completed within 1 second (see Figure 8

Fig 8. Access time for read/write operations

As a consequence of this method, it is very important to make a read or write access in one go, that is, setting or reading seconds through to years should be made in on e single access. Failing to comply with this method could result in the time becoming corrupted.

As an example, if the time (seconds through to hours) is set in one access and then in a second access the date is set, it is possible that the time may increment between the two accesses. A similar problem exists when reading. A roll over may occu r be twe e n read s thus giving the minutes from one moment and the hours from the next.

PCF8563

Real-time clock/calendar

Recommended method for reading the time:

1. Send a START condition and the slave address for write (A2h).

2. Set the address pointer to 2 (VL_seconds) by sending 02h.

3. Send a RESTART condition or STOP followed by START.

4. Send the slave address for read (A3h).

5. Read VL_seconds.

6. Read Minutes.

7. Read Hours.

8. Read Days.

9. Read Weekdays.

10. Read Century_months.

11. Read Years.

12. Send a STOP condition.

8.6 Alarm registers

8.6.1 Register Minute_alarm

Table 18. Minute_alarm - minute alarm register (address 09h ) bi t description

Bit Symbol Value Place value Description

7 AE_M 0 - minute alarm is enabled

6 to 4 MINUTE_ALARM 0 to 5 ten’s place minute alarm information coded in BCD 3 to 0 0 to 9 unit place

[1]

- minute alarm is disabled

format

Product data sheet Rev. 11 — 26 October 2015 13 of 45

NXP Semiconductors

[1] Default value.

8.6.2 Register Hour_alarm

Table 19. Hour_alarm - hour alarm register (address 0Ah) bit descri ption

Bit Symbol Value Place value Description

7 AE_H 0 - hour alarm is enabled

6 - - - unused 5 to 4 HOUR_ALARM 0 to 2 ten’s place hour alarm information coded in BCD 3 to 0 0 to 9 unit place

[1] Default value.

8.6.3 Register Day_alarm

Table 20. Day_alarm - day alarm register (address 0Bh) bit description

Bit Symbol Value Place value Description

7 AE_D 0 - day alarm is enabled

6 - - - unused 5 to 4 DAY_ALARM 0 to 3 ten’s place day alarm information coded in BCD 3 to 0 0 to 9 unit place

PCF8563

Real-time clock/calendar

[1]

- hour alarm is disabled

format

- day alarm is disabled

format

[1] Default value.

8.6.4 Register Weekday_alarm

Table 21. Weekday_alarm - weekday alarm register (address 0Ch) bit description

Bit Symbol Value Description

7 AE_W 0 weekday alarm is enabled

1 6 to 3 - - unused 2 to 0 WEEKDAY_ALARM 0 to 6 weekday alarm information

[1] Default value.

8.6.5 Alarm flag

By clearing the alarm enable bit (AE_x) of one or more of the alarm registers, the corresponding alarm condition(s) are active. When an alarm occurs, AF is set to logic 1. The asserted AF can be used to generate an interrupt (INT interface.

The registers at addresses 09h through 0Ch contain alarm information. When one or more of these registers is loaded with minute, hour, day or weekday, and its corresponding AE_x is logic 0, then that information is compared with the current minute, hour, day, and weekday. When all enabled comparisons first match, the alarm flag (AF in register Control_2) is set to logic 1.

[1]

weekday alarm is disabled

). The AF is cleared using the

Product data sheet Rev. 11 — 26 October 2015 14 of 45

NXP Semiconductors

The generation of interrupts from the alarm function is controlled via bit AIE. If bit AIE is enabled, the INT interface. Once AF has been cleared, it will only be set again when the time increments to match the alarm condition once more. Alarm re gisters wh ich have th eir AE_x bit at logic 1 are ignored.

PCF8563

Real-time clock/calendar

pin follows the condition of bit AF. AF will remain set until cleared by the

check now signal

MINUTE ALARM

MINUTE TIME

HOUR ALARM

HOUR TIME

DA Y ALARM

DA Y TIME

WEEKDA Y ALARM

WEEKDA Y TIME

(1) Only when all enabled alarm settings are matching.

It’s only on increment to a matched case that the alarm flag is set, see Section 8.6.5

Fig 9. Alarm function block diagram

AEN_M

AEN_H

AEN_D

AEN_W

example

AEN_M = 1

set alarm flag AF

013aaa088

1 0

(1)

8.7 Register CLKOUT_control and clock output

Frequencies of 32.768 kHz (default), 1.024 kHz, 32 Hz, and 1 Hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator.

Table 22. CLKOUT_control - CLKOUT control register (address 0Dh) bit description

Bit Symbol Value Description

7 FE 0 the CLKOUT output is inhibited and CLKOUT output is

set high-impedance

[1]

1 6 to 2 - - unused 1 to 0 FD[1:0] frequency output at pin CLKOUT

[1]

01 1.024 kHz

10 32 Hz

11 1 Hz

[1] Default value.

Product data sheet Rev. 11 — 26 October 2015 15 of 45

the CLKOUT output is activated

32.768 kHz

NXP Semiconductors

CountdownPeriod

SourceClockFrequency

-------------------------------------------------------------- -

8.8 Timer function

The 8-bit countdown timer at address 0Fh is controlled by the Timer_control register at address 0Eh. The Timer_control register determines one of 4 source clock frequencies for the timer (4096 Hz, 64 Hz, 1 Hz, or counts down from a software-loaded 8-bit binary value. At the end of every countdown, the timer sets the timer flag TF. The TF may only be cleared by using the interface. The asserted TF can be used to generate an interrupt on pin INT generated as a pulsed signal every countdown period or as a permanently active signal which follows the state of TF. Bit TI_TP is used to control this mode selection. When reading the timer, the current countdown value is returned.

8.8.1 Register Timer_control

Table 23. Timer_control - timer control register (address 0Eh) bit description

Bit Symbol Value Description

7TE 0

6 to 2 - - unused 1 to 0 TD[1:0] timer source clock frequency select

⁄60Hz), and enables or disables the timer. The timer

[1]

timer is disabled

1 timer is enabled

00 4.096 kHz

01 64 Hz

10 1 Hz

[2] 1

⁄60Hz

PCF8563

Real-time clock/calendar

. The interrupt may be

[2]

[1] Default value. [2] These bits determine the source clock for the countdown timer; when not in use, TD[1:0] should be set to

⁄60Hz for power saving.

8.8.2 Register Timer

Table 24. Timer - timer value register (address 0Fh) bit description

Bit Symbol Value Description

7 to 0 TIMER[7:0] 00h to FFh countdown period in seconds:

Table 25. Timer register bits value range

Bit 7 6 5 4 3 2 1 0

1286432168421

The register Timer is an 8-bit binary countdown timer. It is enabled and disabled via the Timer_control register bit TE. The source clock for the timer is also selected by the Timer_control register. Other timer properties such as interrupt generation are controlled via the register Control_status_2.

where n is the countdown value

Product data sheet Rev. 11 — 26 October 2015 16 of 45

For accurate read back of the count down value, it is recommended to read the register twice and check for consistent results, since it is not possible to freeze the countdown timer counter during read back.

NXP Semiconductors

8.9 EXT_CLK test mode

A test mode is available which allows for on-board testing. In such a mode it is possible to set up test conditions and control the operation of the RTC.

The test mode is entered by setting bit TEST1 in register Control_status_1. Then pin CLKOUT becomes an input. The test mode replaces the internal 64 Hz signal with the signal applied to pin CLKOUT. Every 64 positive edges applied to pin CLKOUT will then generate an increment of one second.

The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a maximum period of 1000 ns. The internal 64 Hz clock, now sourced from CLKOUT, is divided down to 1 Hz by a 2 a known state by using bit STOP. When bit STOP is set, the prescaler is reset to 0 (STOP must be cleared before the prescaler can operate again).

From a STOP condition, the first 1 second increment will take place after 32 positive edges on CLKOUT. Thereafter, every 64 positive edges will cause a one-second increment.

Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock. When entering the test mode, no assumption as to the state of the prescaler can be made.

PCF8563

Real-time clock/calendar

divide chain called a prescaler . The prescaler ca n be set into

8.9.1 Operation example:

1. Set EXT_CLK test mode (Control_status_1, bit TEST1 = 1).

2. Set STOP (Control_status_1, bit STOP = 1).

3. Clear STOP (Control_status_1, bit STOP = 0).

4. Set time registers to desired value.

5. Apply 32 clock pulses to CLKOUT.

6. Read time registers to see the first cha nge.

7. Apply 64 clock pulses to CLKOUT.

8. Read time registers to see the second change.

Repeat steps 7 and 8 for additional increments.

Product data sheet Rev. 11 — 26 October 2015 17 of 45

NXP Semiconductors

013aaa089

OSCILLATOR

32768 Hz

16384 Hz

OSCILLATOR STOP DETECTOR

RESET

2 Hz

1024 Hz

32 Hz

1 Hz tick

STOP

CLKOUT source

reset

8192 Hz

4096 Hz

32768 Hz

1 Hz

001aaf912

8192 Hz

stop released

0 μs to 122 μs

8.10 STOP bit function

The function of the STOP bit is to allow for accurate starting of the time circuits. The ST OP bit function will cause the upper part of the prescaler (F thus no 1 Hz ticks will be generated (see Figure 10 will not increment until the STOP bit is released (see Figure 11

PCF8563

Real-time clock/calendar

to F14) to be held in reset and

). The time circuits can then be set and

and Table 26).

Fig 10. STOP bit functional diagram

The STOP bit function will not affect the output of 32.768 kHz on CLKOUT, but will stop the generation of 1.024 kHz, 32 Hz, and 1 Hz.

The lower two stages of the prescaler (F is asynchronous to the crystal oscillator, the accuracy of re-starting the time circuit s will be between zero and one 8.192 kHz cycle (see Figure 11

Fig 11. STOP bit release timing

and F1) are not reset; and because the I2C-bus

Product data sheet Rev. 11 — 26 October 2015 18 of 45

NXP Semiconductors

013aaa076

0.507813 to 0.507935 s

1.000000 s

PCF8563

Real-time clock/calendar

Table 26. First increment of time circuits after STOP bit release

Bit Prescaler bits STOP F0F1-F2 to F

[1]

1Hz tick Time Comment

hh:mm:ss

Clock is running normally

01-0 0001 1101 0100

STOP bit is activated by user. F

XX-0 0000 0000 0000

are not reset and values cannot be predicted externally

0F1

12:45:12 prescaler counting normally

12:45:12 prescaler is reset; time circuits are frozen

New time is set by user

XX-0 0000 0000 0000

08:00:00 prescaler is reset; time circuits are frozen

STOP bit is released by user

XX-0 0000 0000 0000 XX-1 0000 0000 0000 XX-0 1000 0000 0000 XX-1 1000 0000 0000 : 11-1 1111 1111 1110 00-0 0000 0000 0001 10-0 0000 0000 0001 : 11-1 1111 1111 1111 00-0 0000 0000 0000 10-0 0000 0000 0000 : 11-1 1111 1111 1110 00-0 0000 0000 0001

08:00:00 prescaler is now running 08:00:00 08:00:00 08:00:00 :: 08:00:00 08:00:01 0 to 1 transition of F14 increments the time circuits 08:00:01 :: 08:00:01 08:00:01 08:00:01 :: 08:00:01 08:00:02 0 to 1 transition of F14 increments the time circuits

Product data sheet Rev. 11 — 26 October 2015 19 of 45

[1] F0 is clocked at 32.768 kHz.

The first increment of the time circuits is between 0.507813 s and 0.507935 s after STOP bit is released. The uncertainty is caused by the prescaler bits F (see Table 26

8.11 Reset

The PCF8563 includes an internal reset circuit which is active whenever the oscillator is stopped. In the reset state the I all registers are set according to Table 27 reset.

) and the unknown state of the 32 kHz clock.

C-bus logic is initialized including the address pointer and

. I2C-bus communication is not possible during

and F1 not being reset

NXP Semiconductors

mgm664

SCL

500 ns 2000 ns

SDA

8 ms

override active

power-on

PCF8563

Real-time clock/calendar

Table 27. Register reset value

[1]

Address Register name Bit

7 6 5 4 3 2 1 0

00h Control_status_100001000 01h Control_status_200000000 02hVL_seconds 1xxxxxxx 03hMinutes xxxxxxxx 04hHours xxxxxxxx 05hDays xxxxxxxx 06hWeekdays xxxxxxxx 07hCentury_monthsxxxxxxxx 08hYears xxxxxxxx 09hMinute_alarm 1xxxxxxx 0AhHour_alarm 1xxxxxxx 0BhDay_alarm 1xxxxxxx 0ChWeekday_alarm1xxxxxxx 0DhCLKOUT_control1xxxxx00 0EhTimer_control0xxxxx11 0FhTimer xxxxxxxx

[1] Registers marked x are undefined at power-up and unchanged by subsequent resets.

8.11.1 Power-On Reset (POR) override

The POR duration is directly related to the crystal oscillator start-up time. Due to the long start-up times experienced by these types of circuits, a mechanism has been built in to disable the POR and hence speed up on-board test of the device. The setting of this mode requires that the I shown in Figure 12

Once the override mode has been entered, the device immediately stops, being reset, and normal operation may commence i.e. entry into the EXT_CLK test mode via I access. The override mode may be cleared by writing logic 0 to TESTC. TESTC must be set to logic 1 before re-entry into the override mode is possible. Setting TESTC to logic 0 during normal operation has no effect except to prevent entry into the POR override mode.

C-bus pins, SDA and SCL, are toggled in a specific order as

. All timings are required minimums.

C-bus

Fig 12. POR override sequence

Product data sheet Rev. 11 — 26 October 2015 20 of 45

NXP Semiconductors

mbc621

data line

stable;

data valid

change

of data

allowed

SDA

SCL

mbc622

SDA

SCL

STOP condition

SDA

SCL

START condition

9. Characteristics of the I2C-bus

The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy.

9.1 Bit transfer

One data bit is transferred during each clock pulse. The d ata on the SDA line must re main stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Figure 13

PCF8563

Real-time clock/calendar

Fig 13. Bit transfer

9.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START

condition - S. A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition - P (see Figure 14

Fig 14. Definition of START and STOP conditions

9.3 System configuration

A device generating a message is a transmitter; a device receiving a message is a receiver. The device that controls the message is the master; and the devices which are controlled by the master are the slaves (see Figure 15

Product data sheet Rev. 11 — 26 October 2015 21 of 45

NXP Semiconductors

mba605

MASTER

TRANSMITTER

RECEIVER

SLAVE

RECEIVER

SLAVE

TRANSMITTER

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER

RECEIVER

SDA SCL

mbc602

START

condition

9821

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from

master

Fig 15. System configuration

9.4 Acknowledge

The number of data bytes transferred between th e START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle.

• A slave receiver, which is addressed, must generate an acknowledge after the

• Also a master receiver must generate an acknowledge after the reception of each

• The device that acknowledges must pull-down the SDA line during the acknowledge

• A master receiver must signal an end of data to the transmitter by not generating an

PCF8563

Real-time clock/calendar

reception of each byte.

byte that has been clocked out of the slave transmitter.

clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration).

acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.

Acknowledgement on the I

C-bus is illustrated in Figure 16.

Fig 16. Acknowledgement on the I2C-bus

Product data sheet Rev. 11 — 26 October 2015 22 of 45

NXP Semiconductors

mce189

1 0 1 0 0 0 1 R/W

group 1

group 2

0ASLAVE ADDRESS REGISTER ADDRESS A ADATA

acknowledgement

from slave

acknowledgement

from slave

acknowledgement

from slave

R/W

auto increment

memory register address

013aaa346

n bytes

9.5 I2C-bus protocol

9.5.1 Addressing

Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure.

The PCF8563 acts as a slave receiver or slave transmitter. Therefore the clock signal SCL is only an input signal, but the data signal SDA is a bidirectional line.

Two slave addresses are reserved for the PCF8563:

Read: A3h (10100011) Write: A2h (10100010)

PCF8563

Real-time clock/calendar

The PCF8563 slave address is illustrated in Figure 17

Fig 17. Slave address

9.5.2 Clock and calendar READ or WRITE cycles

The I2C-bus configuration for the different PCF 8563 READ and WRITE cycles is shown in

Figure 18

which register is to be accessed next. The upper four bits of the register address are not used.

, Figure 19 and Figure 20. The register address is a 4-bit value that defines

Product data sheet Rev. 11 — 26 October 2015 23 of 45

Fig 18. Master transmits to slave receiver (WRITE mode)

NXP Semiconductors

SLAVE ADDRESS

R/W

DATA

013aaa041

auto increment

memory register address

last byte

R/W

n bytes

(1)

acknowledgement

from slave

acknowledgement

from slave

acknowledgement

from slave

acknowledgement

from master

no acknowledgement

from master

auto increment

memory register address

SLAVE ADDRESS

DATA

SLAVE ADDRESS DATA

A1DATA

acknowledgement

from slave

acknowledgement

from master

no acknowledgement

from master

R/W

auto increment

013aaa347

auto increment

n bytes last byte

PCF8563

Real-time clock/calendar

(1) At this moment master transmitter becomes master receiver and PCF8563 slave receiver becomes slave transmitter.

Fig 19. Master reads after setting register address (write register address; READ data)

Fig 20. Master reads slave immediately after first byte (READ mode)

Product data sheet Rev. 11 — 26 October 2015 24 of 45

NXP Semiconductors

013aaa421

SLAVE ADDRESS

running

time

counters

WD timer

data

WD timer tracking

time counters frozen running

DATA

1 s < t < 2 s

DATA

START

data transfer fail

WD trips

9.6 Interface watchdog timer

PCF8563

Real-time clock/calendar

t < 1 s

data

WD timer

time

counters

START

SLAVE ADDRESS

running

DATA

WD timer tracking

time counters frozen running

STOP

013aaa420

a. Correct data transfer: read or write

b. Incorrect data transfer; read or write

Fig 21. Interface watchdog timer

During read/write operations, the time cou n tin g circ uits are froze n . To prevent a situation where the accessing device becomes locked and do es not cle ar the int er fa ce , the PCF8563 has a built in watchdog timer. Should the interface be active for more than 1 s from the time a valid slave address is transmitted, then the PCF8563 will automatically clear the interface and allow the time counting circuit s to continue counting . The watchdog will trigger between 1 s and 2 s after receiving a valid slave address. Each time the watchdog period is exceeded, 1 s will be lost from the time counters.

The watchdog is implemented to prevent the excessive loss of time due to interface access failure e.g. if main power is removed from a battery backed-up system during an interface access.

Product data sheet Rev. 11 — 26 October 2015 25 of 45

NXP Semiconductors

013aaa348

SDA

SCL

INT

CLKOUT

OSCO

OSCI

PCF8563

10. Internal circuitry

Fig 22. Device diode protection diagram

PCF8563

Real-time clock/calendar

Product data sheet Rev. 11 — 26 October 2015 26 of 45

NXP Semiconductors

11. Limiting values

PCF8563

Real-time clock/calendar

Table 28. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

supply voltage 0.5 +6.5 V supply current 50 +50 mA input voltage on pins SCL, SDA,

0.5 +6.5 V

and OSCI V I I P V

I T T

O I O

tot

ESD

stg

amb

output voltage on pins CLKOUT and INT 0.5 +6.5 V input current at any input 10 +10 mA output current at any output 10 +10 mA total power dissipation - 300 mW electrostatic discharge voltage HBM

[1]

HVSON10 (PCF8563BS/4) SO8 (PCF8563T/F4) TSSOP8 (PCF8563TS/4) SO8 (PCF8563T/5) TSSOP8 (PCF8563TS/5)

CDM

HVSON10 (PCF8563BS/4) SO8 (PCF8563T/F4) SO8 (PCF8563T/5) TSSOP8 (PCF8563TS/4)

TSSOP8 (PCF8563TS/5) latch-up current storage temperature

- 3500 V

[1] [1] [1]

[1]

2000 V

[2]

[2] [2] [2] [3]

-200mA

[4]

65 +150 C

2000 V 1000 V 1500 V 1500 V 1750 V

ambient temperature operating device 40 +85 C

[1] Pass level; Human Body Model (HBM), according to Ref. 5 “JESD22-A114”. [2] Pass level; Charged-Device Model (CDM), according to Ref. 6 “ [3] Pass level; latch-up testing according to Ref. 7 “ [4] According to the NXP store and transport requirements (see Ref. 9 “

to +45 C and a humidity of 25 % to 75 %. For long term storage products deviant conditions are described in that document.

Product data sheet Rev. 11 — 26 October 2015 27 of 45

JESD78” at maximum ambient temperature (T

JESD22-C101”.

amb(max)

UM10569”) the devices should be stored at a temperature of +8 C

NXP Semiconductors

12. Static characteristics

PCF8563

Real-time clock/calendar

Table 29. Static characteristics

VDD= 1.8 V to 5.5 V; VSS=0V; T

=40C to +85C; f

amb

= 32.768 kHz; quartz Rs=40k; CL= 8 pF; unless otherwise

osc

specified.

Symbol Parameter Conditions Min Typ Max Unit

Supplies

supply voltage interface inactive;

=0Hz;

SCL

=25C

amb

interface active;

= 400 kHz

SCL

clock data integrity; T

=25C

amb

supply current interface active

=400kHz --800A

SCL

=100kHz --200A

SCL

interface inactive (f disabled; T

amb

SCL

=25C

= 0 Hz); CLKOUT

[1]

1.0 - 5.5 V

1.8 - 5.5 V

low

[2]

-5.5V

VDD= 5.0 V - 275 550 nA

= 3.0 V - 250 500 nA

= 2.0 V - 225 450 nA

interface inactive (f disabled; T

= 40 Cto +85C

amb

= 0 Hz); CLKOUT

SCL

[2]

VDD= 5.0 V - 500 750 nA

= 3.0 V - 400 650 nA

= 2.0 V - 400 600 nA

interface inactive (f enabled at 32 kHz; T

= 0 Hz); CLKOUT

SCL

=25C

amb

[2]

VDD= 5.0 V - 825 1600 nA

= 3.0 V - 550 1000 nA

= 2.0 V - 425 800 nA

interface inactive (f enabled at 32 kHz; T

= 0 Hz); CLKOUT

SCL

= 40 Cto +85C

amb

[2]

VDD= 5.0 V - 950 1700 nA

= 3.0 V - 650 1100 nA

= 2.0 V - 500 900 nA

Inputs

LOW-level input

0.5 - +0.3VDDV

voltage

HIGH-level

0.7V

-5.5V

input voltage

input leakage

VI=VDD or V

10 +1A

current

input

[3]

--7pF

capacitance

Product data sheet Rev. 11 — 26 October 2015 28 of 45

NXP Semiconductors

02 6

mgr888

(V)

0.4

0.2

0.8

0.6

(μA)

02 6

mgr889

(V)

0.4

0.2

0.8

0.6

(μA)

PCF8563

Real-time clock/calendar

Table 29. Static characteristics

VDD= 1.8 V to 5.5 V; VSS=0V; T

…continued

=40C to +85C; f

amb

= 32.768 kHz; quartz Rs=40k; CL= 8 pF; unless otherwise

osc

specified.

Symbol Parameter Conditions Min Typ Max Unit

Outputs

LOW-level output current

output sink current; VOL=0.4V; VDD=5V

on pin SDA 3 - - mA on pin INT

1- - mA

on pin CLKOUT 1 - - mA

output leakage

VO=VDD or V

10 +1A

current

Voltage de tector

low

[1] For reliable oscillator start-up at power on use VDD greater than 1.3 V. If powered up at 1.0 V the oscillator will start but it might be a bit

slow, especially if at high temperature. Normally the power supply is not 1.0 V at start up and only comes at the end of battery discharge. V

of 1.3 V or greater is needed to ensure speedy oscillator start-up time. [2] Timer source clock= [3] Tested on sample basis.

low voltage T

=25C; sets bit VL; see Figure 6 -0.91.0V

amb

min of 1.0 V is specified so that the customer can calculate how large a battery or capacitor they need for their application. VDD min

⁄60Hz, level of pins SCL and SDA is VDD or VSS.

=25C; Timer = 1 minute. T

amb

Fig 23. Supply current IDD as a function of supply

voltage VDD; CLKOUT disabled

Product data sheet Rev. 11 — 26 October 2015 29 of 45

=25C; Timer = 1 minute.

amb

Fig 24. Supply current IDD as a function of supply

voltage VDD; CLKOUT = 32 kHz

NXP Semiconductors

−40 0 40 120

mgr890

T (°C)

0.4

0.2

0.8

0.6

(μA)

02 6

−4

−2

mgr891

(V)

frequency

deviation

(ppm)

PCF8563

Real-time clock/calendar

VDD= 3 V; Timer = 1 minute. T

Fig 25. Supply current IDD as a function of

temperature T; CLKOUT = 32 kHz

13. Dynamic characteristics

Table 30. Dynamic characteristics

VDD= 1.8 V to 5.5 V; VSS=0V; T specified.

Symbol Parameter Conditions Min Typ Max Unit

Oscillator

OSCO

f

osc/fosc

Quartz crystal parameters (f = 32.768 kHz)

trim

CLKOUT output



CLKOUT

C-bus timing characteristics (see Figure 27)

SCL

HD;STA

SU;STA

LOW

HIGH

Product data sheet Rev. 11 — 26 October 2015 30 of 45

capacitance on pin O SCO 15 25 35 pF relative oscillator frequency variation VDD=200mV;

series resistance - - 100 k load capacitance parallel trimmer capacitance external;

duty cycle on pin CLKOUT

SCL clock frequency hold time (repeated) START condition 0.6 - - s set-up time for a repeated START condition 0.6 - - s LOW period of the SCL clock 1.3 - - s HIGH period of the SCL clock 0.6 - - s rise time of both SDA and SCL signals

=25C; normalized to VDD=3V.

amb

Fig 26. Frequency deviation as a function of supply

voltage V

=40C to +85C; f

amb

= 32.768 kHz; quartz Rs=40k; CL= 8 pF; unless otherwise

osc

-0.2-ppm

=25C

amb

[1]

7 - 12.5 pF 5- 25pF

on pin OSCI

[2]

-50-%

[3][4]

[5]

- - 400 kHz

standard-mode - - 1 s fast-mode - - 0.3 s

NXP Semiconductors

trimCOSCO



trimCOSCO

+

-----------------------------------------

SDA

mga728

SDA

SCL

SU;STA

SU;STO

HD;STA

BUF

LOW

HD;DAT

HIGH

SU;DAT

PCF8563

Real-time clock/calendar

Table 30. Dynamic characteristics …continued

VDD= 1.8 V to 5.5 V; VSS=0V; T specified.

Symbol Parameter Conditions Min Typ Max Unit

BUF

fall time of both SDA and SCL signals - - 0.3 s bus free time between a STOP and START

condition

SU;DAT

HD;DAT

SU;STO

w(spike)

capacitive load for each bus line - - 400 pF data set-up time 100 - - ns data hold time 0 - - ns set-up time for STOP condition 0.6 - - s spike pulse width on bus - - 50 ns

=40C to +85C; f

amb

= 32.768 kHz; quartz Rs=40k; CL= 8 pF; unless otherwise

osc

1.3 - - s

[1] CL is a calculation of C

[2] Unspecified for f

CLKOUT

[3] All timing values are valid within the operating supply voltage at ambient temperature and referenced to V

swing of V

to VDD.

[4] A detailed description of the I

[5] I

C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.

trim

and C

in series: .

OSCO

= 32.768 kHz.

C-bus specification is given in Ref. 11 “UM10204”.

and VIH with an input voltage

Fig 27. I2C-bus timing waveforms

Product data sheet Rev. 11 — 26 October 2015 31 of 45

NXP Semiconductors

mgm665

SCL

SDA

OSCI

OSCO

CLOCK CALENDAR

PCF8563

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

SDA SCL

(I2C-bus)

R: pull-up resistor R =

1 F

100 nF

14. Application information

PCF8563

Real-time clock/calendar

Fig 28. Application diagram

14.1 Quartz frequency adjustment

14.1.1 Method 1: fixed OSCI capacitor

By evaluating the average capacitance necessary for the application layout, a fixed capacitor can be used. The frequency is best measured via the 32.768 kHz signal available after power-on at pin CLKOUT. The frequency tolerance depends on the quartz crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average 5 ppm). Average deviations of 5 minutes per year can be easily achieved.

14.1.2 Method 2: OSCI trimmer

Using the 32.768 kHz signal available after power-on at pin CLKOUT, fast setting of a trimmer is possible.

14.1.3 Method 3: OSCO output

Direct measurement of OSCO out (accounting for test probe capacitance).

Product data sheet Rev. 11 — 26 October 2015 32 of 45

NXP Semiconductors

0.50.21

0.05

0.00

UNIT

(1)

ye2e

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

3.1

2.9

1.75

1.45

3.1

2.9

2.55

2.15

0.30

0.18

0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT650-1 MO-229 - - -- - -

(1)

0.55

0.30

0.1v0.05

0 2 mm1

scale

SOT650-1

HVSON10: plastic thermal enhanced very thin small outline package; no leads; 10 terminals; body 3 x 3 x 0.85 mm

(1)

max.

detail X

01-01-22 02-02-08

terminal 1 index area

ACCB

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

15. Package outline

PCF8563

Real-time clock/calendar

Fig 29. Package outline SOT650-1 (HVSON10) of PCF8563BS

Product data sheet Rev. 11 — 26 October 2015 33 of 45

NXP Semiconductors

UNIT

max.

A1A2A3b

(1)E(2)

(1)

eHELLpQZywv θ

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

inches

1.75

0.25

0.10

1.45

1.25

0.25

0.49

0.36

0.25

0.19

5.0

4.8

4.0

3.8

1.27

6.2

5.8

1.05

0.7

0.6

0.7

0.3

8 0

o o

0.25 0.10.25

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

1.0

0.4

SOT96-1

w M

detail X

v M

(A )

pin 1 index

076E03 MS-012

0.069

0.010

0.004

0.057

0.049

0.01

0.019

0.014

0.0100

0.0075

0.20

0.19

0.16

0.15

0.05

0.244

0.228

0.028

0.024

0.028

0.012

0.010.010.041 0.004

0.039

0.016

0 2.5 5 mm

scale

SO8: plastic small outline package; 8 leads; body width 3.9 mm

SOT96-1

99-12-27 03-02-18

PCF8563

Real-time clock/calendar

Fig 30. Package outline SOT96-1 (SO8) of PCF8563T

Product data sheet Rev. 11 — 26 October 2015 34 of 45

NXP Semiconductors

UNIT

max.

A2A3b

wyv

ceD

(1)E(2)

(1)

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

0.15

0.05

0.95

0.80

0.45

0.25

0.28

0.15

3.1

2.9

3.1

2.9

0.65

5.1

4.7

0.70

0.35

6° 0°

0.1 0.10.10.94

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.7

0.4

SOT505-1

99-04-09 03-02-18

w M

0.25

(A3)

detail X

v M

2.5 5 mm0

scale

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm

SOT505-1

1.1

pin 1 index

PCF8563

Real-time clock/calendar

Fig 31. Package outline SOT505-1 (TSSOP8) of PCF8563TS

Product data sheet Rev. 11 — 26 October 2015 35 of 45

NXP Semiconductors

16. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC61340-5 or equivalent standards.

17. Soldering of SMD packages

This text provides a very brief insight into a complex technology . A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”.

17.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.

PCF8563

Real-time clock/calendar

17.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by so lder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leade d packages, packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

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NXP Semiconductors

17.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board

• Solder bath specifications, including temperature and impurities

17.4 Reflow soldering

Key characteristics in reflow soldering are:

• L ead-free versus SnPb sold ering; note that a lea d-free reflow process usually leads to

• Solder paste printing issues including smearing, release, and adjusting the process

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

Table 31. SnPb eutectic process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

< 2.5 235 220  2.5 220 220

PCF8563

Real-time clock/calendar

transport, the solder wave parameters, and the time during which components are exposed to the wave

higher minimum peak temperatures (see Figure 32 reducing the process window

window for a mix of large and small components on one board

heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joint s (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with

Table 31

and 32

Volume (mm3) < 350  350

) than a SnPb process, thus

Table 32. Lead-free process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3) < 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245 > 2.5 250 245 245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all times.

Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 32

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NXP Semiconductors

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Fig 32. Temperature profiles for large and small components

PCF8563

Real-time clock/calendar

MSL: Moisture Sensitivity Level

For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”.

18. Abbreviations

Table 33. Abbreviations

Acronym Description

BCD Binary Coded Decimal CDM Charged-Device Model CMOS Complementary Metal Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model

C Inter-Integrated Circuit

I IC Integrated Circuit LSB Least Significant Bit MSB Most Significant Bit MSL Moisture Sensitivity Level PCB Printed-Circuit Board POR Power-On Reset RTC Real-Time Clock SCL Serial CLock line SDA Serial DAta line SMD Surface Mount Device

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19. References

[1] AN10365 — Surface mount reflow soldering description [2] IEC 60134 — Rating syst ems for electronic tubes and valves and analogous

[3] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena [4] IPC/JEDEC J-STD-020 — Moisture/Reflow Sensitivity Classification for

[5] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body

[6] JESD22-C101 — Field-Induced Charged-Device Model Test Method for

[7] JESD78 — IC Latch-Up Test [8] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive

[9] UM10569 — NXP store and transport requirements [10] SNV-FA-01-02 — Marking Formats Integrated Circuits [11] UM10204 — I

PCF8563

Real-time clock/calendar

semiconductor devices

Nonhermetic Solid State Surface Mount Devices

Model (HBM)

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components

(ESDS) Devices

C-bus specification and user manual

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Real-time clock/calendar

20. Revision history

Table 34. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PCF8563 v.11 20151026 Prod uct data sheet - PCF8563 v.10 Modifications:

PCF8563 v.10 20120403 Product data sheet - PCF8563 v.9 Modifications:

PCF8563 v.9 20110616 Product data sheet - PCF8563 v.8 PCF8563 v.8 20101118 Product data sheet - PCF8563 v.7 PCF8563 v.7 20100723 Product data sheet - PCF8563_6 PCF8563_6 20080221 Prod uct data sheet - PCF8563_5 PCF8563_5 20070717 Prod uct data sheet - PCF8563-04 PCF8563-04

(9397 750 12999) PCF8563-03

(9397 750 11158) PCF8563-02

(9397 750 04855) PCF8563_N_1

(9397 750 03282)

• Removed DIP8 package

• Table 3: Corrected Table note 1

• Table 28, Table note 4: Corrected “the devices have to be stored” to “the devices should be

stored”

• Table 29:

– Deleted Table note 1 – V

: Corrected VSS to 0.5

– V

: Corrected VDD to 5.5

– Corrected Table note 1

from VDD f

= 400 kHz

SCL

• Adjusted marking codes

• Adjusted text for FE = 0 in Table 22

20040312 Product data - PCF8563-03

20030414 Product data - PCF8563-02

19990416 Product data - PCF8563_N_1

19980325 Objective specification - -

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Real-time clock/calendar

21. Legal information

21.1 Data sheet status

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) d escribed i n this docume nt may have changed since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

[1][2]

Product status

[3]

Definition

21.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied u pon to cont ain det ailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

21.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semi conductors’ aggregat e and cumulative liabil ity towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonabl y be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the cu stomer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.

NXP Semiconductors does not accept any liability related to any default , damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third part y customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell product s that is ope n for accept ance or the gr ant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

, unless otherwise

Product data sheet Rev. 11 — 26 October 2015 41 of 45

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PCF8563

Real-time clock/calendar

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It i s neither qua lif ied nor test ed in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equ ipment or applications.

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, da mages or failed produ ct cl aims resulting from custome r design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (t ranslated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.

21.4 Trademarks

Notice: All referenced brands, prod uct names, service names and trad emarks are the property of their respective owners.

C-bus — logo is a trademark of NXP Semiconductors N.V.

22. Contact information

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

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23. Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2

Table 2. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 4. Formatted registers overview . . . . . . . . . . . . . .6

Table 5. Control_status_1 - control and status register 1

(address 00h) bit description . . . . . . . . . . . . . . .7

Table 6. Control_status_2 - control and status register 2

(address 01h) bit description . . . . . . . . . . . . . . .7

Table 7. INT Table 8. VL_seconds - seconds and clock integrity status

Table 9. Seconds coded in BCD format . . . . . . . . . . . . .9

Table 10. Minutes - minutes register (address 03h) Table 11. Hours - hours register (address 04h) Table 12. Days - days register (address 05h) Table 13. Weekdays - weekdays register (address 06h)

Table 14. Weekday assignments . . . . . . . . . . . . . . . . . . .11

Table 15. Century_months - century flag and months

Table 16. Month assignments in BCD format. . . . . . . . . .11

Table 17. Years - years register (08h) bit description. . . .1 2

Table 18. Minute_alarm - minute alarm register Table 19. Hour_alarm - hour alarm register (address 0Ah) Table 20. Day_alarm - day alarm register (address 0Bh) Table 21. Weekday_alarm - weekday alarm register Table 22. CLKOUT_control - CLKOUT control register Table 23. Timer_control - timer control register Table 24. Timer - timer value register (address 0Fh)

Table 25. Timer register bits value range. . . . . . . . . . . . .16

Table 26. First increment of time circuits after STOP Table 27. Register reset value

Table 28. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 29. Static characte ristics . . . . . . . . . . . . . . . . . . . .28

Table 30. Dynamic characteristics . . . . . . . . . . . . . . . . . . 30

Table 31. SnPb eutectic process (from J-STD-020D) . . .37

Table 32. Lead-free process (from J-STD-020D) . . . . . .37

Table 33. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 34. Revision history . . . . . . . . . . . . . . . . . . . . . . . .40

operation (bit TI_TP = 1)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .10

bit description . . . . . . . . . . . . . . . . . . . . . . . . .11

(address 09h) bit description . . . . . . . . . . . . . .13

bit description . . . . . . . . . . . . . . . . . . . . . . . . . .14

(address 0Ch) bit description . . . . . . . . . . . . . .14

(address 0Dh) bit description . . . . . . . . . . . . . .15

(address 0Eh) bit description . . . . . . . . . . . . . .16

bit description . . . . . . . . . . . . . . . . . . . . . . . . .16

bit release . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

[1]

. . . . . . . . . . . . . .9

. . . . . . . . . . . . . . . . . . .20

PCF8563

Real-time clock/calendar

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NXP Semiconductors

24. Figures

Fig 1. Block diagram of PCF8563 . . . . . . . . . . . . . . . . . .3

Fig 2. Pin configuration for HVSON10 (PCF8563BS) . . .4

Fig 3. Pin configuration for SO8 (PCF8563T) . . . . . . . . .4

Fig 4. Pin configuration for TSSOP8 (PCF8563TS). . . . .4

Fig 5. Interrupt scheme . . . . . . . . . . . . . . . . . . . . . . . . . .8

Fig 6. Voltage-low detection. . . . . . . . . . . . . . . . . . . . . .1 0

Fig 7. Data flow for the time function . . . . . . . . . . . . . . .12

Fig 8. Access time for read/write operations . . . . . . . . .13

Fig 9. Alarm function block diagram. . . . . . . . . . . . . . . .15

Fig 10. STOP bit functional diagram . . . . . . . . . . . . . . . .18

Fig 11. STOP bit release timing. . . . . . . . . . . . . . . . . . . .18

Fig 12. POR override sequence . . . . . . . . . . . . . . . . . . .20

Fig 13. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Fig 14. Definition of START and STOP conditions. . . . . .21

Fig 15. System configuration. . . . . . . . . . . . . . . . . . . . . .22

Fig 16. Acknowledgement on the I

Fig 17. Slave address . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Fig 18. Master transmits to slave receiver

(WRITE mode). . . . . . . . . . . . . . . . . . . . . . . . . . .23

Fig 19. Master reads after setting register address (write

Fig 20. Master reads slave immediately after first byte

(READ mode) . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Fig 21. Interface watchdog timer . . . . . . . . . . . . . . . . . . .25

Fig 22. Device diode protection di agram. . . . . . . . . . . . .26

Fig 23. Supply current I

; CLKOUT disabled . . . . . . . . . . . . . . . . . . . .29

V Fig 24. Supply current IDD as a function of supply voltage

Fig 25. Supply current I Fig 26. Frequency deviation as a function of supply voltage Fig 27. I

Fig 28. Application diagram . . . . . . . . . . . . . . . . . . . . . . .32

Fig 29. Package outline SOT650-1 (HVSON10) of Fig 30. Package outline SOT96-1 (SO8) of PCF8563T. .34

Fig 31. Package outline SOT505-1 (TSSOP8) of Fig 32. Temperature profiles for large and small

VDD; CLKOUT = 32 kHz. . . . . . . . . . . . . . . . . . . .29

T; CLKOUT = 32 kHz. . . . . . . . . . . . . . . . . . . . . .30

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

C-bus timing waveforms . . . . . . . . . . . . . . . . . .31

PCF8563BS. . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

PCF8563TS. . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

as a function of supply voltage

as a function of temperature

C-bus . . . . . . . . . . . .22

PCF8563

Real-time clock/calendar

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25. Contents

PCF8563

Real-time clock/calendar

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

5 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4

7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

8 Functional description . . . . . . . . . . . . . . . . . . . 6

8.1 CLKOUT output . . . . . . . . . . . . . . . . . . . . . . . . 6

8.2 Register organization . . . . . . . . . . . . . . . . . . . . 6

8.3 Control registers . . . . . . . . . . . . . . . . . . . . . . . . 7

8.3.1 Register Control_status_1 . . . . . . . . . . . . . . . . 7

8.3.2 Register Control_status_2 . . . . . . . . . . . . . . . . 7

8.3.2.1 Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 8

8.4 Time and date registers . . . . . . . . . . . . . . . . . . 9

8.4.1 Register VL_seconds . . . . . . . . . . . . . . . . . . . . 9

8.4.1.1 Voltage-low detector and clock monitor . . . . . 10

8.4.2 Register Minutes. . . . . . . . . . . . . . . . . . . . . . . 10

8.4.3 Register Hours . . . . . . . . . . . . . . . . . . . . . . . . 10

8.4.4 Register Days. . . . . . . . . . . . . . . . . . . . . . . . . 10

8.4.5 Register Weekdays. . . . . . . . . . . . . . . . . . . . . 11

8.4.6 Register Century_months. . . . . . . . . . . . . . . . 11

8.4.7 Register Years . . . . . . . . . . . . . . . . . . . . . . . . 12

8.5 Setting and reading the time. . . . . . . . . . . . . . 12

8.6 Alarm registers . . . . . . . . . . . . . . . . . . . . . . . . 13

8.6.1 Register Minute_alarm . . . . . . . . . . . . . . . . . . 13

8.6.2 Register Hour_alarm . . . . . . . . . . . . . . . . . . . 14

8.6.3 Register Day_alarm . . . . . . . . . . . . . . . . . . . . 14

8.6.4 Register Weekday_alarm . . . . . . . . . . . . . . . . 14

8.6.5 Alarm flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

8.7 Register CLKOUT_control and clock outpu t. . 15

8.8 Timer function. . . . . . . . . . . . . . . . . . . . . . . . . 16

8.8.1 Register Timer_control . . . . . . . . . . . . . . . . . . 16

8.8.2 Register Timer . . . . . . . . . . . . . . . . . . . . . . . . 16

8.9 EXT_CLK test mode. . . . . . . . . . . . . . . . . . . . 17

8.9.1 Operation example: . . . . . . . . . . . . . . . . . . . . 17

8.10 STOP bit function . . . . . . . . . . . . . . . . . . . . . . 18

8.11 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8.11.1 Power-On Reset (POR) override . . . . . . . . . . 20

9 Characteristics of the I

C-bus . . . . . . . . . . . . 21

9.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

9.2 START and STOP conditions . . . . . . . . . . . . . 21

9.3 System configuration . . . . . . . . . . . . . . . . . . . 21

9.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 22

9.5 I

C-bus protocol. . . . . . . . . . . . . . . . . . . . . . . 23

9.5.1 Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9.5.2 Clock and calendar READ or WRITE cycles. 23

9.6 Interface watchdog timer . . . . . . . . . . . . . . . . 25

10 Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 26

11 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 27

12 Static characteristics . . . . . . . . . . . . . . . . . . . 28

13 Dynamic characteristics. . . . . . . . . . . . . . . . . 30

14 Application information . . . . . . . . . . . . . . . . . 32

14.1 Quartz frequency adjustment. . . . . . . . . . . . . 32

14.1.1 Method 1: fixed OSCI capacitor. . . . . . . . . . . 32

14.1.2 Method 2: OSCI trimmer . . . . . . . . . . . . . . . . 32

14.1.3 Method 3: OSCO output . . . . . . . . . . . . . . . . 32

15 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 33

16 Handling information . . . . . . . . . . . . . . . . . . . 36

17 Soldering of SMD packages. . . . . . . . . . . . . . 36

17.1 Introduction to soldering. . . . . . . . . . . . . . . . . 36

17.2 Wave and reflow soldering. . . . . . . . . . . . . . . 36

17.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 37

17.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 37

18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 38

19 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

20 Revision history . . . . . . . . . . . . . . . . . . . . . . . 40

21 Legal information . . . . . . . . . . . . . . . . . . . . . . 41

21.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 41

21.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

21.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 41

21.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 42

22 Contact information . . . . . . . . . . . . . . . . . . . . 42

23 Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

24 Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

25 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 26 October 2015

Document identifier: PCF8563

NXP PCF8563T/5 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1. General description

2. Features and benefits

3. Applications

4. Ordering information

5. Marking

6. Block diagram

7. Pinning information

7.1 Pinning

7.2 Pin description

8. Functional description

8.1 CLKOUT output

8.2 Register organization

8.3 Control registers

8.3.1 Register Control_status_1

8.3.2 Register Control_status_2

8.3.2.1 Interrupt output

8.4 Time and date registers

8.4.1 Register VL_seconds

8.4.1.1 Voltage-low detector and clock monitor

8.4.2 Register Minutes

8.4.3 Register Hours

8.4.4 Register Days

8.4.5 Register Weekdays

8.4.6 Register Century_months

8.4.7 Register Years

8.5 Setting and reading the time

8.6 Alarm registers

8.6.1 Register Minute_alarm

8.6.2 Register Hour_alarm

8.6.3 Register Day_alarm

8.6.4 Register Weekday_alarm

8.6.5 Alarm flag

8.7 Register CLKOUT_control and clock output

8.8 Timer function

8.8.1 Register Timer_control

8.8.2 Register Timer

8.9 EXT_CLK test mode

8.9.1 Operation example:

8.10 STOP bit function

8.11 Reset

8.11.1 Power-On Reset (POR) override

9. Characteristics of the I2C-bus

9.1 Bit transfer

9.2 START and STOP conditions

9.3 System configuration

9.4 Acknowledge

9.5 I2C-bus protocol

9.5.1 Addressing

9.5.2 Clock and calendar READ or WRITE cycles

9.6 Interface watchdog timer

10. Internal circuitry

11. Limiting values

12. Static characteristics

13. Dynamic characteristics

14. Application information

14.1 Quartz frequency adjustment

14.1.1 Method 1: fixed OSCI capacitor

14.1.2 Method 2: OSCI trimmer

14.1.3 Method 3: OSCO output

15. Package outline

16. Handling information

17. Soldering of SMD packages

17.1 Introduction to soldering

17.2 Wave and reflow soldering

17.3 Wave soldering

17.4 Reflow soldering

18. Abbreviations

19. References

20. Revision history

21. Legal information

21.1 Data sheet status

21.2 Definitions

21.3 Disclaimers

21.4 Trademarks

22. Contact information

23. Tables