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MC56F8
Reference Manual
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NXP MC56F8 Reference Manual

NXP Semiconductors Document identifier: DRM172
Reference Manual Rev. 1, 10/2020
LLC Resonant Converter Design Using MC56F8xxxx
NXP Semiconductors

Contents

Chapter 1 Introduction........................................................................................... 3
1.1 Application outline..................................................................................................................... 3
1.2 Resonant converter topologies and features.............................................................................3
1.3 MC56F8xxxx controller advantages and features..................................................................... 6
Chapter 2 System description................................................................................9
2.1 Structure....................................................................................................................................9
2.2 Modulation mode.....................................................................................................................10
2.3 Control loop introduction..........................................................................................................13
Chapter 3 Hardware design................................................................................. 15
3.1 Specifications.......................................................................................................................... 15
3.2 Resonant network design........................................................................................................15
3.3 Transformer design................................................................................................................. 16
3.4 Power circuits and drivers....................................................................................................... 17
3.5 PCB layout considerations...................................................................................................... 19
Chapter 4 Software design.................................................................................. 23
4.1 Parameter normalization......................................................................................................... 23
4.2 State machine..........................................................................................................................23
4.3 Control timing.......................................................................................................................... 26
4.4 Drive signal generation logic................................................................................................... 28
4.5 Fault protection........................................................................................................................29
4.6 Use of peripherals................................................................................................................... 29
4.7 Code runs in RAM................................................................................................................... 30
4.8 Bootloader............................................................................................................................... 32
Chapter 5 Testing................................................................................................ 35
5.1 System efficiency.....................................................................................................................35
5.2 Dynamic performance............................................................................................................. 37
5.3 Current limitation function........................................................................................................38
5.4 Output voltage ripple............................................................................................................... 39
Chapter 6 Revision history...................................................................................41
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Chapter 1 Introduction

1.1 Application outline

This reference design describes an LLC resonant converter design using MC56F8xxxx DSC.
This document focuses on the key part design of the LLC resonant converter.
• The system description includes:
— system structure
— modulation modes
— control loop
• The hardware design includes:
— resonant network design
— transformer design
— PCB layout consideration
• The software design includes:
— system state machine
— control timing
— drive signal generation logic
— fault protection
— bootloader

1.2 Resonant converter topologies and features

The demand for increasing power density of switched-mode power supplies pushes designers to use a higher switching frequency. But a high switching frequency significantly increases switching losses at Pulse Width Modulated (PWM) converters. It decreases the efficiency. Besides, with larger heatsink or forced cooling, it wastes the spaces saved by using smaller passive components. Therefore, the SMPS designers are looking for solutions to decrease switching losses.
One of the possible solutions is to use the resonant converter topologies. The resonant converter uses a resonant circuit in the conversion path. Figure 1 shows the typical structure of the resonant converter. The switching network generates a square wave voltage output. This voltage pattern feeds the resonant tank. The resonant tank consists of a serial or a parallel combination of L and C passive components. There are several combinations of two or three L and C passive components used in the resonant tank. The type of resonant tank and its connection to the load defines the resonant converter behaviors. Due to the resonant tank, the semiconductor switches can operate at zero voltage or current switching condition. This phenomenon significantly reduces switching losses and allows the converter operation at high switching frequencies.
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Introduction
Figure 1. Resonant converter principle
The most common known resonant topologies are a Serial Resonant Converter (SRC) and Parallel Resonant Converter (PRC).
• Figure 2 shows the SRC. The resonant tank consists of a serial connected inductor Lr and capacitor Cr. The load RL is also connected in series with the resonant tank. In the serial resonant converter, the resonant tank and load creates a voltage divider. Because the resonant tank impedance is frequency dependent, the output voltage of the SRC can be controlled by switching frequency. At the DC or low switching frequency the resonant tank has high impedance in comparison with the load impedance and the output voltage is low. Increasing the switch frequency also increases the output voltage. At the resonant frequency, the voltage drop on the resonant tank is equal to zero and thus the output voltages are equal to the input voltage. Continuing over the resonant frequency, the output voltage starts to decrease. This is because the resonant tank impedance increases against to the load impedance. The operation over the resonant frequency is preferred, even if the output voltage regulation is possible over or below resonant frequency. The inductive character of the resonant frequency allows to achieve Zero Voltage Switching (ZVS), which is preferred for MOSFET transistors.
The output voltage regulation is also limited by the load value. If the load is very low, the load impedance is high in comparison with the resonant tank. Keeping the desired voltage at the output becomes difficult. Theoretically the switching frequency can be infinite, but practically there is some maximal frequency limit. Therefore, the output voltage regulation at light or no load condition is very limited.
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Introduction
Figure 2. SRC topology
• Figure 3 shows another well-known topology - PRC. The parallel converter uses the same resonant tank as the serial resonant converter, the serial connection of inductor Lr and capacitor Cr. The PRC differs in load connection to the resonant tank. In this case, the load is connected in parallel with the capacitor Cr. In this configuration, the voltage divider consists of impedance of the inductor Lr and impedance of parallel combination of the capacitor Cr and the load RL. This means that both parts top and bottom impedance of the voltage divider are frequency dependent. At the DC or low switching frequency, the output voltage of the PRC is equal to input voltages. With the increase of the switching frequency, the output voltage also increases due to the characteristic of the resonant tank. The maximal output voltage is achieved at a resonant frequency, where the output voltage is Q times higher than the input voltage. The Q is a quality factor of the resonant tank. Over the resonant frequency, the output voltage falls, because the inductor impedance becomes more dominant against the capacitor impedance.
The PRC can control the output voltage even at no load conditions. In this case, the PRC is comprised of a resonant tank only. On the other hand, the permanent connection of the resonant tank to the switch network brings some drawbacks at nominal operation. At nominal load the parallel converter operates close to the resonant frequency and thus the resonant tanks have the lowest impedance. This also means a high circulating current through the resonant tank. The parallel converter is also suggested to operate over the resonant frequency due to ZVS conditions.
Figure 3. PRC topology
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Besides the two part resonant tanks, there are almost 40 possibilities of three part resonant tanks. The most popular member of three part tanks is the LLC resonant converter. The resonant tank consists of two inductors Lr, Lm and one capacitor Cr (see
Figure 4). The load is connected in parallel to the inductor Lm. The LLC resonant converter solves all drawbacks mentioned
above. At no load conditions the output voltage can still be controlled by a voltage drop over inductor Lm. Also at resonant frequency, the current is limited by the Lm inductor; therefore, the circulating current through the resonant circuit can be kept on an acceptable level. Another advantage of the LLC resonant converter is that it can operate under ZVS condition over the whole load range. Table 1 lists the summary of the key features of all mentioned resonant converters.
Introduction
Figure 4. LLC resonant converter topology
Table 1. Resonant converters comparison
— SRC PRC LLC
ZVS operation Above fr (resonant frequency)only Above fr only Yes
Operation without load No Yes, but high losses Yes
Operation at fr No No Yes
Operation at wide input range High losses High losses Yes

1.3 MC56F8xxxx controller advantages and features

The 56F8xxxx microcontroller is a member of the 32-bit 56800EX core-based Digital Signal Controllers (DSCs). Each device in the family combines, on a single chip, the processing power of a 32-bit DSP and the functionality of a microcontroller with a flexible set of peripherals. Due to its cost-effectiveness, configuration flexibility, and compact program code, 56F8xxxx is well-suited for many consumer and industrial applications.
With numerous, highly-integrated peripherals and powerful processing capabilities, the 56F8xxxx is a low-cost family especially useful for Switched Mode Power Supplies (SMPSs), advanced motor control (including dual motor control), smart appliances, Uninterruptible Power Supplies (UPSs), photovoltaic systems, power distribution systems, wireless charging, and medical monitoring applications.
The following list summarizes the superset of features across the entire 56F8xxxx family.
• 56800EX 32-bit DSC core
• Up to 100MIPS at 100 MHz core frequency
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Introduction
• Protects supervisor programs and resources from user programs
• One/Two 8-channel eFlexPWM module(s) with NanoEdge™ placement and enhanced capture
• Two 8-channel 12-bit cyclic ADC
• One windowed watchdog timer, power Supervisor;
• On-chip 8 MHz/400 kHz relaxation oscillator, 200 kHz Relaxation Oscillator and 4 MHz to 16 MHz Crystal Oscillator (XOSC)
• Inter-Module Crossbar with AND-OR-INVERT function
• Programmable Interrupt Controller (INTC)
• One/Two Quad Timer(s), two Periodic Interval Timers
• Two 12-bit DAC modules
• Four High Speed Comparators with integrated DAC references
The switched-mode power supply applications benefit greatly from the flexible eFlexPWM module, fast ADC module, on-chip analog comparator module, and inter-module crossbar with AOI function.
This PWM module can generate various switching patterns, including highly sophisticated waveforms. It can be used to control all known motor types and is ideal for controlling different SMPS topologies as well, it has the following features:
• 16 bits of resolution for center, edge aligned, and asymmetrical PWMs;
• Fractional delay for enhanced resolution of the PWM period and edge placement;
• PWM outputs that can operate as complementary pairs or independent channels;
• Support for synchronization to external hardware or other PWM, half cycle reload capability;
• Multiple output trigger events can be generated per PWM cycle via hardware;
• Fault inputs can be assigned to control multiple PWM outputs, programmable filters for fault inputs;
• Independently programmable PWM output polarity, independent top and bottom dead time insertion;
• Each complementary pair can operate with its own PWM frequency and dead time values;
• All outputs can be programmed to change simultaneously via a FORCE_OUT event.
The eFlexPWM offers flexibility in its configuration, enabling efficient control of any SMPS topology. The eFlexPWM module is capable of free control of rising and falling edges for each PWM output and includes automatic complementary signal generation and dead time insertion. Due to NanoEdge placement the eFlexPWM can generate duty cycles and frequencies with high a resolution of up to 312 ps. The eFlexPWM module can also generate up to six synchronization events per sub-module to provide synchronization with other modules (ADC, Quad-timer).
This LLC resonant converter application uses the eFlexPWM module for generating two PWM signals for primary side power MOSFETs and two PWM signals for secondary side synchronous rectifier, and provide the trigger signal for ADC sample.
The Analog-to-Digital Converter (ADC) function consists of two 12-bit resolution separate ADC, each with eight analog inputs and its own sample and hold circuit. A common digital control module configures and controls the functioning of the converters. ADC features include:
• Two independent 12-bit ADCs:
— Two 8-channel external inputs
— Built-in × 1, × 2, × 4 programmable gain pre-amplifier
• Support of analog inputs for single-ended and differential, including unipolar differential, conversions.
• Sequential, parallel, and independent scan mode.
• First eight samples have offset, limit and zero-crossing calculation supported.
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Introduction
• ADC conversions can be synchronized by any module connected to the internal crossbar module, such as PWM, timer, GPIO, and comparator modules.
• Support for simultaneous triggering and software-triggering conversions.
• Support for a multi-triggering mode with a programmable number of conversions on each trigger.
• Each ADC has ability to scan and store up to eight conversion results.
This LLC resonant converter application uses the ADC module in triggered parallel mode, it is synchronized at the center of PWM signal. ADCA sampled the output current and primary current, ADCB sampled output voltage and input voltage.
The Inter-Module Crossbar and AND-OR-INVERT logic features:
• Provides generalized connections between and among on-chip peripherals: ADCs, 12-bit DAC, comparators, quad-timers, eFlexPWMs, EWM, and select I/O pins.
• User-defined input/output pins for all modules connected to the crossbar.
• DMA request and interrupt generation from the crossbar.
• Write-once protection for all registers.
• AND-OR-INVERT function provides a universal Boolean function generator that uses a four- term sum-of-products expression, with each product term containing true or complement values of the four selected inputs (A, B, C, D).
This LLC resonant converter application uses the Inter-Module Crossbar and AND-OR-INVERT logic to provide interconnection between the eFlexPWM module and ADC module, interconnection between fault signal and on-chip comparator, generate the synchronization rectifier PWM by multiple signals from eFlexPWM and on-chip comparator.
The application also uses other peripherals like on-chip comparator for hardware protection and secondary side voltage zero-cross detection, a PIT module for the software timer, 2xSCI module for communication with the primary side and remote control via PC and several GPIOs for LED indication.
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Chapter 2 System description

2.1 Structure

LLC is an isolated buck-boost converter, and the isolation between the primary and secondary side is formed by transformer.
The primary side incorporates the pulse-wave voltage generator, resonant network, isolated drivers, and isolated UART port to communicate with other devices, such as, the front stage PFC converter.
The secondary side incorporates the synchronous rectifier, voltage/current sensing circuitry, output controller, drivers, PM Bus communication, and the DSC controller board.
The auxiliary power supply takes the power directly from the DC Bus, and then generates the desired voltages with the Flyback converter.
Figure 5 shows the overall system structure.
Figure 5. System block diagram
The sensing circuitries are used for sensing DC Bus voltage, resonant current, output voltage, output current and accommodating them to the MCU acceptable voltage level.
The drivers are used for amplification of MCU PWM signals. Isolated drivers are between the primary and secondary side for the driving of the resonant converter’s MOSFET on the primary side, which is implemented by pulse transformer. Non-isolated drivers are used for synchronous rectifier’s MOSFET on the secondary side.
The synchronous rectifier rectifies the output voltage to 12 V level and can reduce the conduction losses. The output controller determines the load on or off by software.
The DSC MC56F8xxxx controller is situated on the control daughter card and connected to the power board via the PCI slot. The control card is powered from the secondary side and it works as the master for the whole application.
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System description
The controller is also used to communicate with outside devices. One isolated UART is applied to communicating with the front PFC stage. Another UART to USB conversion is applied to communicating with the host PC for FreeMASTER or firmware updating. One IIC is reserved for the PM Bus network.

2.2 Modulation mode

Most conventional LLC resonant converter applies the Pulse Frequency Modulation (PFM), namely complementary pulse signals with 50% duty cycle drive the upper and lower arm switch and regulate the output voltage by adjusting the switching frequency. Assuming that the power is transferred mainly by the fundamental component, the First Harmonic Approximation (FHA) method can be used to analyze the LLC resonant converter. Figure 6 shows the equivalent circuit of LLC resonant converter.
Figure 6. Equivalent circuit of LLC resonant converter
V
is the fundamental component of the output of pulse-wave generator.
in(FHA)
Voe is the fundamental component of the output voltage in the primary side, where:
• φ is the phase angle between Voe and V
in(FHA)
• n is the transformer turn ratio
Fundamental component of current Ioe.
Re is the AC equivalent load on the primary side.
Then, the input-to-output voltage gain can be obtained.
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Where:
•
•
•
•
System description
• fsw is the operating frequency
For a more intuitive understanding of the modulation principles, it is necessary to know how voltage gain behaves as a function of fn, m, and Qe. The value of m is fixed after the physical parameters are determined and the quality factor Qe is now only load-dependent which is also fixed in certain condition. Therefore, it is wise to plot M with respect to fn for different values of Qe. As seen in Figure 7, the value of M varies with fn under certain m and Qe.
Figure 7. Plots of PFM voltage gain function
However, it is also obvious that the variation range of M is limited when fn > 1. To meet the requirements of a wide input voltage, improving the switching frequency unlimitedly is not desirable, because of the restriction of component availability, the effect of the transformer parasitic parameters, and so on.
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System description
Considering the above contradictions, the additional symmetric Pulse Width Modulation (PWM) mode, namely adjusting duty cycle of fixed frequency drive signals to regulate the output voltage, is desired.
When using symmetric PWM, V
expresses as:
in(FHA)
Where:
• d represents the duty cycle of the drive signal.
Then the voltage gain can be obtained.
Assuming a fixed working frequency which is larger than the resonant frequency, Figure 8 shows the voltage gain function for different values of Qeunder PWM mode. The voltage gain can be any value between 0 and 1 when the duty cycle varies from 0 to 0.5.
NOTE
In order to ensure ZVS, the duty cycle can’t be too small. This reference chooses 0.3 as the minimum duty cycle.
Figure 8. Plots of PFM voltage gain function
When the input voltage is too high or the load is too light, the symmetric PWM mode may still not meet requirements. So the burst mode, namely blocking switching drive signals periodically, is taken. The burst mode control can also improve the light load efficiency of the LLC converter. Figure 9 shows the burst operation processes. When the drive signals are not blocked, the output voltage rises, and conversely declines.
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System description
Figure 9. Waveforms of Burst operation
As seen in Figure 7, the voltage gain decreases as the switching frequency increases in the inductive area, while in Figure 8, the voltage gain decreases as the duty cycle decreases. In PFM mode, when the maximum switching frequency can’t meet the gain requirement, transfer to PWM mode. If the minimum duty cycle still can’t meet requirements, transfer to burst mode. In the closed-loop control, we take the required duty cycle which reflect the current state of the system instead of output voltage as the judgement condition to smoothly switch between different modes. Figure 10 shows the condition of each mode and the transition between them, a hysteresis is taken in burst mode to avoid frequent switching. In Figure 10, T switching period, T
is the allowed minimum period, D
min
is minimum allowed duty cycle, Don and D
off
is the allowed maximum
max
is the upper and lower
off
limitation of hysteresis.
Figure 10. PFM, PWM and burst modes

2.3 Control loop introduction

In the server, the battery charger and many other industrial applications, the power supplies are required to have both constant voltage and overload current limiting control. So the dual outer loop control scheme is applied, it includes the inner primary current loop and outer output voltage or out current loop determined by the output current. The inner average current control loop is applied to eliminate the difference in small-signal characteristics among different static operation, which is equivalent to modify the object model, to adapt to the wide range requirement. Figure 11 shows the control scheme.
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