This document is the hardware user’s guide for the i.MX 8M Nano LPDDR4 Evaluation Kit (EVK) based on the NXP
Semiconductor’s i.MX 8M Nano Applications Processor. This board is fully supported by NXP Semiconductor. This manual
includes system setup and configurations, and provides detailed information on the overall design and usage of the EVK board
from a hardware system perspective.
1.1 Board overview
The LPDDR4 EVK board is a platform designed to show the most commonly used features of the i.MX 8M Nano Applications
Processor. The i.MX 8M Nano LPDDR4 EVK board helps developers get familiar with the processor before investing a large
amount of resources in more specific designs.
Table 1 lists the features of the i.MX 8M Nano LPDDR4 EVK board.
Type-C Port2 is the only power supply port, and it must be always supplied for system running.
i.MX 8M Nano EVK is not a typical use case of the PD device. It is supplied by the PD charger only, but with a
power switch. When the switch keeps OFF for more than 5.5 seconds after adapting the PD charger, the charger
(Source) will repower EVK (Sink) after the system initiates the PD software. See Section 6.5.7 in Universal Serial
Bus Specification Revision 2.0. There are two ways to avoid the repower:
• The power switch must always be in the ON position before attaching the PD charger.
• Change the software to disable the PD function, and make it Type-C supply only.
2.1 Processor
The i.MX 8M Nano applications processors represent NXP Semiconductor’s latest achievement in highly integrated multimediafocused products offering high performance processing. These applications processors can enable the growing market of smart,
secure, connected devices. The i.MX 8M Nano applications processors feature NXP’s advanced implementation of the Quad ARM
Cortex®-A53+ ARM Cortex®-M7 cores, which operate at speeds up to 1.5 GHz and 750 MHz respectively. Each i.MX 8M Nano
device provides a 16-bit DDR3L/DDR4/LPDDR4 memory interface and other interfaces for connecting peripherals, such as MIPI
LCD, MIPI Camera, WLAN, Bluetooth™, Ethernet, Digital Mic, and multi-sensors.
For more detailed information about the processor, see the datasheet and reference manual on i.MX 8M NANO.
2.2 Boot mode and boot device configurations
The i.MX 8M Nano implements a compressed boot mode decode with four BOOT_MODE pins. It can boot from the boot
configuration selected on SW1101 or from the boot configuration stored on the internal eFUSE. In addition, the i.MX 8M Nano
can download a program image from a USB connection when configured in the serial downloader mode. The method used to
determine where the processor finds its boot information is from four dedicated BOOT MODE pins.
On the i.MX 8M Nano LPDDR4 EVK board, the default boot mode is to boot from the eMMC device. There are two additional boot
devices: one QSPI Nor Flash on the CPU board and one MicroSD connector on the base board. If you set the boot device to QSPI
or MicroSD, the board will boot from the device accordingly.
Table 2 shows the values used for boot selection.
Figure 3. Boot selection
Table 2. Boot selection
BOOT_MODE3
(SW1101 pin4)
0000Boot from fuses
0001Serial downloader
0010eMMC/uSDHC3
0011MicroSD/uSDHC2
0100NAND Flash
0110QSPI 3B Read
0111QSPI Hyperflash 3.3 V
1000ecSPI Boot
Only SW1101[1-4] are used for boot selection. The left pins of SW1101 and SW1102 are useless for i.MX 8M Nano.
Either 0 or 1 is acceptable.
BOOT_MODE2
(SW1101 pin3)
BOOT_MODE1
(SW1101 pin2)
NOTE
BOOT_MODE0
(SW1101 pin1)
Boot device
2.3 Power tree
There is a Type-C power supply that needs to be connected to the i.MX 8M Nano LPDDR4 EVK board at connector J302. The
other powers on the EVK board are generated from PMIC and discrete devices to supply the whole system. Figure 4 shows the
power tree.
In Figure 4, the developer can get all the voltage supply rails used on the EVK board. When some modules are not enabled, the
power supplies might be shut down by software. Table 3 lists the power rails on the board.
1. PCA9450B BUCK1 default output voltage is 0.85 V. Software will change it to 0.95 V for overdrive mode in SPL before
DDR initialization.
2. BUCK2 default output voltage is 0.85 V. Software will change it to 0.95 V for 1.4 GHz and to 1.0 V for 1.5 GHz.
2.4 LPDDR4 DRAM memory
The i.MX 8M Nano LPDDR4 EVK board has one 16 bit LPDDR4 SDRAM chip (C1612PC2WDGTKR-U) for a total of 2 GB
RAM memory.
In the physical layout, the LPDDR4 chip is placed on the TOP side, the data traces are not necessarily connected to the LPDDR4
chips in sequential order, but for ease of routing, are connected as best determined by the layout and other critical traces.
The DRAM_VREF can be generated by i.MX 8M Nano internally, so it does not need to use external power supply and decoupling
capacitors. The calibration resistors used by the LPDDR4 chips and processor are 240 Ohm 1% resistors. The differential
termination resistors for DRAM Clock are one 150 ohm 1% resistor on EVK. Developers can change this value depending on
simulation and test result.
2.5 eMMC memory (U4)
The eMMC memory is connected to the uSDHC3 interface of i.MX 8M Nano, and it can support up to eMMC 5.1 device. The eMMC
memory is on the 8MNANOLPD4-CPU board, and the part number is SDINBDG4-32G-I1 . It is the default boot device of the EVK.
The boot settings are as shown in Table 2.
2.6 QSPI Nor Flash (U5)
The QSPI memory is connected to the FlexSPI interface of i.MX 8M Nano, and it can support up to 166 MHz DDR mode device.
The QSPI memory is on the 8MNANOPLPD4-CPU board, and the part number is MT25QU256ABA1EW7-0SIT. To select it as
the boot device of the EVK, developers can refer to the boot settings as shown in Table 2.
2.7 SD card slot (J701)
There is one MicroSD card slot (J701) on the 8MMINI-BB board, connecting to the uSDHC2 interface of i.MX 8M Nano. This
connector supports one 4-bit SD3.0 MicroSD card. To select it as the boot device of the EVK, developers can refer to the boot
settings as shown in Table 2.
2.8 MIPI-CSI and MIPI-DSI connectors (J802, J801)
The i.MX 8M Nano processor supports one 4-lane MIPI-CSI and one 4-lane MIPI-DSI. The MiniSAS connectors are designed to
support camera and LCD with dedicated pin definition. The connectors are as shown in Figure 2. Display and camera accessory
boards are available separately. The full list can be found at i.MX 8 Series Accessory Boards.
The Ethernet subsystem of the EVK board is provided by the Qualcomm AR8031 Ethernet Transceiver (U501). The Ethernet
Transceiver (or PHY) receives standard RGMII Ethernet signals from the MAC-NET core of the i.MX 8M Nano. The processor
handles all Ethernet protocols at the MAC layer and above. The PHY is only responsible for the Link Layer formatting. The Ethernet
connector (J501) integrates Magnetic transformer inside, so it cannot be directly connected to AR8031 (U501).
Each EVK board has a unique MAC address, which is burned into i.MX 8M Nano by Fuse. A label with the unique MAC address
is placed on the connector for reference.
2.10 USB connector (J301, J302)
The i.MX 8M Nano Applications Processors contain one USB 2.0 OTG controller, with one integrated USB PHY. There are two
USB Type-C connectors on the EVK board, but only Port1 can support Host and Device Mode.
J301 is connected to USB1 interface of i.MX 8M Nano, which can act as the download port of the EVK.
J302 is the power supply port of the EVK.
2.11 Wi-Fi/Bluetooth (U9)
The EVK board has a Wi-Fi/Bluetooth module AW-CM358SM on the 8MNANOLPD4-CPU board. The module is NXP 88W8987
based, contains SDIO3.0, UART, PCM interface, and can support 802.11a/b/g/n/ac, BT5.0. The 2.4G/5G antenna is stuck to the
edge of the Base Board with a coaxial cable connected to the CPU Board.
2.12 Audio line output (J401)
The EVK board uses a high-quality Stereo DAC WM8524 (U401), which can support 24 bit I2S data and 192 KHz sampling rate.
The Line output of WM8524 is 2Vrms, not like common headphone output 1 Vrms. Developers must be very careful about this
interface. The Line output connector (J401) is a 3.5 mm 4-pole (or TRRS) phone jack.
NOTE
The Audio Line output connector is designed for active speaker with a power amplifier. To connect it with a
headphone, make sure that the headphone has volume control functionality and set the headphone’s volume
properly before wearing it. Do not plug in the non-volume-control headphone directly. The audio output volume may
be too high for non-volume-control headphone and may damage it.
2.13 Audio card connector (J1001)
One 60-pin FPC connector (J1001) is provided on the EVK board to support audio card connection, and the developers can use
the audio card to perform audio features development.
NOTE
There is no SAI1 from the i.MX 8M Nano process, so AK4458/AK4497 can’t be enabled on audio card.
2.14 JTAG connector (J902)
The i.MX 8M Nano Applications Processor has four JATG signals on dedicated pins, and one HW reset input signal POR_B. Those
signals are directly connected to the 10-pin 1.27 mm JTAG connector J902. The four JTAG signals used by the processor are:
The i.MX 8M Nano Applications Processor has four independent UART ports, UART1 - UART4. On the EVK board, UART2 is
used for Cortex-A53 core and UART4 is used for Cortex-M7 core. We use a single-chip USB to dual-channel UART IC for system
debugging, and the part number is FT2232D. The developers can download the driver from FTDI. After the driver for FT2232D is
installed, the PC will enumerate two COM ports when the USB cable is plugged into J901. Developers can use Putty, Tera Term,
Xshell, or other terminal tools. The required settings are as listed in Table 4.
Table 4. Terminal setting parameters
Data rate115,200 baud
Data bits8
ParityNone
Stop bits1
2.16 Expansion connector (J1003)
One 40-pin dual-row Pin Header connector, J1003, is provided on the EVK board to support I2S, UART, I2C, and GPIO
connection. The developers can use the port for some specific application development.
Table 5. J1003 pin definition
No.Net nameDescriptionNo.Net nameDescription
1VEXT_3V3Power Output, 3.3 V2VDD_5VPower Output, 5 V
3I2C3_SDA_3V3I2C3 data signal4VDD_5VPower Output, 5 V
5I2C3_SCL_3V3I2C3 clock signal6GNDGround
7UART3_CTSUART3 clear to send signal8UART3_TXDUART3 transmit signal
9GNDGround10UART3_RXDUART3 transmit signal
11UART3_RTSUART3 request to send signal12EXP_IO8Expansion IO signal
13EXP_IO9Expansion IO signal14GNDGround
15EXP_IO10Expansion IO signal16EXP_IO11Expansion IO signal
17VEXT_3V3Power Output, 3.3 V18—NC
19ECSPI2_MOSISPI2 data signal, master output
slave input
21ECSPI2_MISOSPI2 data signal, master input
slave output
20GNDGround
22—NC
23ECSPI2_SCLKSPI2 clock signal24ECSPI2_SS0SPI2 chip select signal
31EXP_IO14Expansion IO signal32EXP_IO12Expansion IO signal
33EXP_IO13Expansion IO signal34GNDGround
35SAI5_RXD3SAI5 receive data signal36SAI5_RXD2SAI5 receive data signal
37SAI5_RXD1SAI5 receive data signal38SAI5_RXD0SAI5 receive data signal
39GNDGround40SAI5_RXCSAI5 receive clock signal
2.17 I2C connector (J1004)
One 8-pin dual-row Pin Header connector (J1004) is provided on the EVK board to support I2C connection. The developers can
use the port for some specific application development.
Table 6. J1004 pin definition
No.Net nameDescription
1/2VDD_3V3Power Output, 3.3 V
3/4I2C3_SCL_3V3I2C clock signal
5/6I2C3_SDA_3V3I2C data signal
7/8GNDGround
2.18 User interface buttons
There are two user interface buttons on the EVK board.
2.18.1 Power button (SW901)
The i.MX 8M Nano Applications Processor supports the use of a button input signal to request main SoC power state changes,
such as, ON or OFF, from the PMU.
The ON/OFF button can be used for debounce, OFF-to-ON time, and max timeout. Debounce is used to generate the power-off
interrupt. In the ON state, if ON/OFF button is held longer than the debounce time, the power-off interrupt is generated. In the OFF
state, if the ON/OFF button is held longer than the OFF-to-ON time, the state will transit from OFF to ON. Max timeout can also
be the time for requesting physical power down after the ON/OFF button has been held for the defined time.
2.18.2 Reset button (SW902)
The RESET button, SW902, is directly connected to the PMIC PCA9450B. Holding the RESET button will force to reset the PMIC
power outputs except NVCC_SNVS_1V8 and VDD_SNVS_0V8 on the EVK board. The i.MX 8M Nano applications processor will be
immediately turned off and reinitiate a boot cycle from the OFF state.
The i.MX 8M Nano LPDDR4 EVK is composed by 8MNANOLPD4-CPU and 8MMINI-BB. Table 1 lists the dimensions of the two
boards. Both boards are made with standard 8-layer technology and the material is FR-4. The PCB stack-up information is shown
in Table 7 and Table 8.
Table 7. 8MNANOLPD4-CPU Board stack up information