NXP LPC55S69JBD100, LPC55S69JEV98, LPC55S66JBD100, LPC55S66JEV98, LPC55S66JBD64 Errata sheet

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LPC55S6x

Errata sheet LPC55S6x

Rev. 2.0 — February 25, 2021 Errata sheet

Document information

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Keywords LPC55S69JBD100, LPC55S69JEV98, LPC55S66JBD100,

LPC55S66JEV98,LPC55S66JBD64, LPC55S69JBD64

Abstract LPC55S6x errata

NXP Semiconductors

LPC55S6x

Errata sheet LPC55S6x

Revision history

Rev Date Description

2.0 20210225 Added USB.5 errata.,

extra byte(s) to the buffer if the NBytes is not multiple of 8 for OUT transfer”.

Updated date code in

1.9 20201214 Includes

handshaking fails when certain full-speed hubs are connected”.

1.8 20201027 Adds

1.7 20200825 Adds

mode”.

1.6 20191204 Updates ROM.5 workaround.

1.5 20191101 Describes ROM failure to respond to debug session request.

1.4 20191021 Add new product identification for LPC55S6x HTQFP64 package and USB.3 errata.

1.3 20190912 Describes ROM failure to enter ISP mode when an image is corrupted with flash pages in an erased or unprogrammed state.

1.2 20190710 Added USB.1, USB.2, ADC.1, ADC.2, ADC.3, GPIO.1, I2S.1, AES.1, Powerquad.1, Powerquad.2

Section 3.12 “USB.4: For the USB high-speed device controller, the detection

Section 3.21 “WAKEIO.1: Wake-up I/O register reports incorrect wake-up source”.

Section 5.1 “ROM bootloader updated to provide API functionality for entry to ISP

Section 3.22 “USB.5: In USB high-speed device mode, device writes

Section 5 “Errata notes detail”

1.1 20190221 Updated device markings

1.0 20181204 Initial version

Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Errata sheet Rev. 2.0 — February 25, 2021 2 of 20

NXP Semiconductors

1. Product identification

The LPC55S6x VFBGA98 package has the following top-side marking:

• First line: LPC55S6x

• Second line: JEV98

• Third line: xxxxxxxx

• Fourth line: zzzyywwxR

– yyww: Date code with yy = year and ww = week.

– xR: Device revision 1B

The LPC55S6x HLQFP100 package has the following top-side marking:

• First line: LPC55S6x

• Second line: xxxxxxxx

• Third line: zzzyywwxR

– yyww: Date code with yy = year and ww = week.

– xR: Device revision 0A or Device revision 1B

LPC55S6x

Errata sheet LPC55S6x

The LPC55S6x HTQFP64 package has the following top-side :

• First line: LPC55S6x marking

• Second line: JBD64

• Third line: xxxx

• Fourth line: xxxx

• Fifth line: zzzyywwxR

– yyww: Date code with yy = year and ww = week.

– xR: Device revision 1B

2. Errata overview

Table 1. Functional problems table

Functional problems

ROM.1 For PRINCE encrypted region, partial erase cannot be

ROM.2 For PUF based key provisioning, a reset must be

ROM.3 Unprotected sub regions in PRINCE defined regions

ROM.4 Last page of image is erased when simultaneously

ROM.5 ROM fails to enter ISP mode when image is corrupted

ROM.6 ROM fails to respond to debug session request. 0A Section 3.6

VDD.1 The minimum operating voltage is 1.85 V. 0A Section 3.7

Short description Revision identifier Detailed description

performed.

0A Section 3.2

performed.

0A Section 3.3

cannot be used.

0A Section 3.4

programming the signed image and CFPA region.

0A, 1B Section 3.5

with flash pages in an erased or unprogrammed state.

Section 3.1

Errata sheet Rev. 2.0 — February 25, 2021 3 of 20

NXP Semiconductors

LPC55S6x

Errata sheet LPC55S6x

Table 1. Functional problems table

Functional problems

CMP.1 The hysteresis on the comparator cannot be enabled. 0A Section 3.8

USB.1 USB HS host fails when connecting to an LS device

USB.2 USB PHY does not auto-power down in suspend

USB.3 Automatic USB rate adjustment not functional when

USB.4 For the USB high-speed device controller, the detection

ADC.1 Async interrupts with resume not supported. 0A, 1B Section 3.13

ADC.2 Request for offset calibration function bit (CALOFS) is

ADC.3 Sign-extend calibration results for averaging is not

GPIO.1 During power-up, an unexpected glitch (low pulse) can

I2S.1 I2S signal sharing is not functional. 0A Section 3.17

AES.1 AES keys are not available when Cortex-M33 is

Powerquad.1 Format issue in matrix scale function. 0A Section 3.19

Powerquad.2 Floating Point to integer converter scaling issue. 0A Section 3.20

WAKEIO.1 Wake-up I/O cause register identifies the wake-up I/O

USB.5 In USB high-speed device mode, device writes extra

Short description Revision identifier Detailed description

(mouse).

mode.

using multiple hubs.

handshaking fails when certain full-speed hubs are connected.

not cleared after completion of offset calibration function.

supported.

occur on port pins (PIO0_28, PIO1_1, PIO1_18, PIO1_30).

running a security level less than 3.

(WAKEUP pins) source from deep power-down mode.

byte(s) to the buffer if the NBytes is not multiple of 8 for OUT transfer

…continued

0A, 1B Section 3.9

0A Section 3.10

0A, 1B Section 3.11

0A, 1B Section 3.12

0A Section 3.14

0A Section 3.15

0A Section 3.16

0A Section 3.18

0A, 1B Section 3.21

0A, 1B Section 3.22

Table 2. AC/DC deviations table

AC/DC deviations

n/a n/a n/a n/a

Table 3. Errata notes

Errata notes Short description Revision identifier Detailed description

ISP.1 Devices with date code 2113 (yyww) and ROM patch

Errata sheet Rev. 2.0 — February 25, 2021 4 of 20

Short description Product version(s) Detailed description

0A, 1B

version (T1.1.5) will have runBootloader API function.

Section 5 “Errata notes detail”

NXP Semiconductors

3. Functional problems detail

3.1 ROM.1: For PRINCE encrypted region, partial erase cannot be performed

Introduction

The LPC55S6x devices supports real-time encryption and decryption for on-chip flash using the PRINCE encryption algorithm. The PRINCE module supports three flash memory regions for real-time encryption and decryption, referred to as crypto regions. Each crypto region resides at a 256 kB address boundary within the flash and are divided into 8 kB sub-regions which can be individually enabled.

Problem

For the LPC55S6x, when an erase operation is performed with a size less then 8 kB for a PRINCE encrypted region, a return error is returned and subsequent ISP commands do not respond.

Work-around

LPC55S6x

Errata sheet LPC55S6x

When a region is marked as a PRINCE encrypted region, a full erase of the PRINCE encrypted region must be performed.

This issue is fixed on device revision 1B.

3.2 ROM.2: For PUF based key provisioning, a reset must be

performed

Introduction

On the LPC55S6x, the Key Management module supports storing three 128-bit PRINCE Keys (KEY1, KEY2, and KEY3) used for the decryption process.

Problem

After PUF based key provisioning, the PRINCE module cannot perform the decryption process without performing a reset.

Work-around

Perform a reset via the external reset pin or power cycle the device for a successful decryption process when using a PUF key.

This issue is fixed on device revision 1B.

3.3 ROM.3: Unprotected sub regions in PRINCE defined

regions cannot be used.

Introduction

The LPC55S6x devices support real-time encryption and decryption for on-chip flash using the PRINCE encryption algorithm. The PRINCE module supports three flash memory regions for real-time encryption and decryption, referred to as crypto regions. Each crypto region resides at a 256 kB address boundary within the flash and is divided into 8 kB sub-regions which can be individually enabled.

Errata sheet Rev. 2.0 — February 25, 2021 5 of 20

NXP Semiconductors

Problem

Unprotected (non PRINCE encrypted) sub flash in PRINCE defined regions cannot be written after an erase operation. Any non PRINCE encrypted sub regions in the PRINCE defined regions cannot be used.

Work-around

There is no work-around.

This issue is fixed on device revision 1B.

3.4 ROM.4: Last page of image is erased when simultaneously programming the signed image and CFPA region

Introduction

On the LPC55S6x, the protected flash region (PFR) supports a Customer Field Programmable Area (CFPA) which can be used for Monotonic counters, Key revocation, and PRINCE IV codes. Also, the ROM supports secure boot using a signed image.

Problem

LPC55S6x

Errata sheet LPC55S6x

When simultaneously programming the signed image and the CFPA via the Secure Binary (SB2 file) image format, the last page of the image is erased.

Work-around

The signed image and the CFPA need to be programmed one a time to prevent the last page of the image from being erased.

This issue is fixed on device revision 1B.

3.5 ROM.5: ROM fails to enter ISP mode when image is corrupted with flash pages in an erased or unprogrammed state

Introduction

On the LPC55S6x, if the image is corrupted with flash pages in an erased or unprogrammed state, the ROM may fail to automatically enter ISP mode.

Problem

When secure boot is enabled in CMPA and the flash memory contains an erased or unprogrammed memory page inside the memory region specified by the image size field in the image header, the device does not automatically enter into ISP mode using the fallback mechanism, as in the case of a failed boot for an invalid image. This problem occurs when the application image is only partially written or erased but a valid image header is still present in memory.

Work-around

Perform a mass-erase to remove the incomplete and corrupted image using one of the following methods:

• Execute the erase command using Debug Mailbox. The device will enter directly into

ISP mode after exiting the mailbox.

Errata sheet Rev. 2.0 — February 25, 2021 6 of 20

NXP Semiconductors

• Enter into ISP mode using the Debug Mailbox command and use the flash-erase

• Reset the device and enter into ISP mode using the ISP pin. Use the flash-erase

This issue occurs on device revisions 0A and 1B.

3.6 ROM.6: ROM fails to respond to debug session request on version 0A parts

Introduction

Debugging is supported through Arm's Serial wire Debug (SWD) interface, enabling debug with a range of debug probes and tools from NXP and other ecosystem partners. Debug access by a remote host is controlled by the LPC55S6x ROM and is only enabled when permitted through the device configuration and when the correct protocol is followed to initiate a debug session.The Boot ROM implements a debug mailbox protocol to interact with host debug systems over the SWD interface. For LPC55S6x, if the device has been configured for debug authentication, then a debug session must be initiated following the correct authentication sequence.

LPC55S6x

Errata sheet LPC55S6x

command.

command to erase the corrupted (incomplete) image.

Problem

For the LPC55S6x, a new method of initiating a debug session was introduced, as documented in the current user manual. However, when used on 0A parts, a debug system attempting to connect could become stuck in an endless loop because the ROM in that silicon revision fails to issue a corresponding response to the new debug session request.

Work-around

It is possible to determine whether the cause of the hang during a debug session request is related to the part revision by detecting whether an overrun condition is reported via the debug mailbox, which is only generated by the newer parts and not by the older 0A version. The pseudo code below is a modified version to replace that shown in Chapter

51.6.1 of the user manual, implementing a check for silicon revision when connecting to LPC55S6x parts:

// Read AP ID register to identify DM AP at index 2 WriteDP 2 0x020000F0 // The returned AP ID should be 0x002A0000 value = ReadAP 3 print "AP ID: ", value

// Select DM AP index 2 // Select CSW register [BJS] WriteDP 2 0x02000000 // Write DM RESYNC_REQ + CHIP_RESET_REQ WriteAP 0 0x21 // Poll CSW register (0) a offset 0x00 for zero return, indicating success value = -1 while value != 0 {

Errata sheet Rev. 2.0 — February 25, 2021 7 of 20

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