NXP LPC55S69JBD100, LPC55S69JEV98, LPC55S66JBD100, LPC55S66JEV98, LPC55S66JBD64 Errata sheet
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LPC55S6x
Errata sheet LPC55S6x
Rev. 2.0 — February 25, 2021 Errata sheet
Document information
Info |
Content |
Keywords |
LPC55S69JBD100, LPC55S69JEV98, LPC55S66JBD100, |
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LPC55S66JEV98,LPC55S66JBD64, LPC55S69JBD64 |
Abstract |
LPC55S6x errata |
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NXP Semiconductors |
LPC55S6x |
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Errata sheet LPC55S6x |
Revision history |
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Rev |
Date |
Description |
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2.0 |
20210225 |
Added USB.5 errata., Section 3.22 “USB.5: In USB high-speed device mode, device writes |
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extra byte(s) to the buffer if the NBytes is not multiple of 8 for OUT transfer”. |
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Updated date code in Section 5 “Errata notes detail” |
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1.9 |
20201214 |
Includes Section 3.12 “USB.4: For the USB high-speed device controller, the detection |
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handshaking fails when certain full-speed hubs are connected”. |
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1.8 |
20201027 |
Adds Section 3.21 “WAKEIO.1: Wake-up I/O register reports incorrect wake-up source”. |
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1.7 |
20200825 |
Adds Section 5.1 “ROM bootloader updated to provide API functionality for entry to ISP |
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mode”. |
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1.6 |
20191204 |
Updates ROM.5 workaround. |
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1.5 |
20191101 |
Describes ROM failure to respond to debug session request. |
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1.4 |
20191021 |
Add new product identification for LPC55S6x HTQFP64 package and USB.3 errata. |
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1.3 |
20190912 |
Describes ROM failure to enter ISP mode when an image is corrupted with flash pages in an |
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erased or unprogrammed state. |
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1.2 |
20190710 |
Added USB.1, USB.2, ADC.1, ADC.2, ADC.3, GPIO.1, I2S.1, AES.1, Powerquad.1, |
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Powerquad.2 |
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1.1 |
20190221 |
Updated device markings |
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1.0 |
20181204 |
Initial version |
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Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
LPC55S6x |
All information provided in this document is subject to legal disclaimers. |
© NXP B.V. 2021. All rights reserved. |
Errata sheet |
Rev. 2.0 — February 25, 2021 |
2 of 20 |
NXP Semiconductors |
LPC55S6x |
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Errata sheet LPC55S6x |
1. Product identification
The LPC55S6x VFBGA98 package has the following top-side marking:
•First line: LPC55S6x
•Second line: JEV98
•Third line: xxxxxxxx
•Fourth line: zzzyywwxR
–yyww: Date code with yy = year and ww = week.
–xR: Device revision 1B
The LPC55S6x HLQFP100 package has the following top-side marking:
•First line: LPC55S6x
•Second line: xxxxxxxx
•Third line: zzzyywwxR
–yyww: Date code with yy = year and ww = week.
–xR: Device revision 0A or Device revision 1B
The LPC55S6x HTQFP64 package has the following top-side :
•First line: LPC55S6x marking
•Second line: JBD64
•Third line: xxxx
•Fourth line: xxxx
•Fifth line: zzzyywwxR
–yyww: Date code with yy = year and ww = week.
–xR: Device revision 1B
2.Errata overview
Table 1. |
Functional problems table |
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Functional |
Short description |
Revision identifier |
Detailed description |
problems |
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ROM.1 |
For PRINCE encrypted region, partial erase cannot be |
0A |
Section 3.1 |
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performed. |
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ROM.2 |
For PUF based key provisioning, a reset must be |
0A |
Section 3.2 |
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performed. |
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ROM.3 |
Unprotected sub regions in PRINCE defined regions |
0A |
Section 3.3 |
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cannot be used. |
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ROM.4 |
Last page of image is erased when simultaneously |
0A |
Section 3.4 |
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programming the signed image and CFPA region. |
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ROM.5 |
ROM fails to enter ISP mode when image is corrupted |
0A, 1B |
Section 3.5 |
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with flash pages in an erased or unprogrammed state. |
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ROM.6 |
ROM fails to respond to debug session request. |
0A |
Section 3.6 |
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VDD.1 |
The minimum operating voltage is 1.85 V. |
0A |
Section 3.7 |
LPC55S6x |
All information provided in this document is subject to legal disclaimers. |
© NXP B.V. 2021. All rights reserved. |
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Errata sheet |
Rev. 2.0 — February 25, 2021 |
3 of 20 |
NXP Semiconductors |
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LPC55S6x |
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Errata sheet LPC55S6x |
Table 1. |
Functional problems table …continued |
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Functional |
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Short description |
Revision identifier |
Detailed description |
problems |
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CMP.1 |
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The hysteresis on the comparator cannot be enabled. |
0A |
Section 3.8 |
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USB.1 |
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USB HS host fails when connecting to an LS device |
0A, 1B |
Section 3.9 |
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(mouse). |
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USB.2 |
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USB PHY does not auto-power down in suspend |
0A |
Section 3.10 |
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mode. |
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USB.3 |
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Automatic USB rate adjustment not functional when |
0A, 1B |
Section 3.11 |
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using multiple hubs. |
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USB.4 |
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For the USB high-speed device controller, the detection |
0A, 1B |
Section 3.12 |
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handshaking fails when certain full-speed hubs are |
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connected. |
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ADC.1 |
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Async interrupts with resume not supported. |
0A, 1B |
Section 3.13 |
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ADC.2 |
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Request for offset calibration function bit (CALOFS) is |
0A |
Section 3.14 |
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not cleared after completion of offset calibration |
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function. |
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ADC.3 |
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Sign-extend calibration results for averaging is not |
0A |
Section 3.15 |
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supported. |
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GPIO.1 |
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During power-up, an unexpected glitch (low pulse) can |
0A |
Section 3.16 |
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occur on port pins (PIO0_28, PIO1_1, PIO1_18, |
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PIO1_30). |
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I2S.1 |
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I2S signal sharing is not functional. |
0A |
Section 3.17 |
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AES.1 |
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AES keys are not available when Cortex-M33 is |
0A |
Section 3.18 |
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running a security level less than 3. |
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Powerquad.1 |
Format issue in matrix scale function. |
0A |
Section 3.19 |
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Powerquad.2 |
Floating Point to integer converter scaling issue. |
0A |
Section 3.20 |
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WAKEIO.1 |
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Wake-up I/O cause register identifies the wake-up I/O |
0A, 1B |
Section 3.21 |
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(WAKEUP pins) source from deep power-down mode. |
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USB.5 |
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In USB high-speed device mode, device writes extra |
0A, 1B |
Section 3.22 |
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byte(s) to the buffer if the NBytes is not multiple of 8 for |
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OUT transfer |
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Table 2. |
AC/DC deviations table |
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AC/DC |
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Short description |
Product version(s) |
Detailed description |
deviations |
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n/a |
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n/a |
n/a |
n/a |
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Table 3. |
Errata notes |
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Errata notes |
Short description |
Revision identifier |
Detailed description |
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ISP.1 |
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Devices with date code 2113 (yyww) and ROM patch |
0A, 1B |
Section 5 “Errata notes |
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version (T1.1.5) will have runBootloader API function. |
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detail” |
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LPC55S6x |
All information provided in this document is subject to legal disclaimers. |
© NXP B.V. 2021. All rights reserved. |
Errata sheet |
Rev. 2.0 — February 25, 2021 |
4 of 20 |
NXP Semiconductors |
LPC55S6x |
|
Errata sheet LPC55S6x |
3. Functional problems detail
3.1ROM.1: For PRINCE encrypted region, partial erase cannot be performed
Introduction
The LPC55S6x devices supports real-time encryption and decryption for on-chip flash using the PRINCE encryption algorithm. The PRINCE module supports three flash memory regions for real-time encryption and decryption, referred to as crypto regions. Each crypto region resides at a 256 kB address boundary within the flash and are divided into 8 kB sub-regions which can be individually enabled.
Problem
For the LPC55S6x, when an erase operation is performed with a size less then 8 kB for a PRINCE encrypted region, a return error is returned and subsequent ISP commands do not respond.
Work-around
When a region is marked as a PRINCE encrypted region, a full erase of the PRINCE encrypted region must be performed.
This issue is fixed on device revision 1B.
3.2ROM.2: For PUF based key provisioning, a reset must be performed
Introduction
On the LPC55S6x, the Key Management module supports storing three 128-bit PRINCE Keys (KEY1, KEY2, and KEY3) used for the decryption process.
Problem
After PUF based key provisioning, the PRINCE module cannot perform the decryption process without performing a reset.
Work-around
Perform a reset via the external reset pin or power cycle the device for a successful decryption process when using a PUF key.
This issue is fixed on device revision 1B.
3.3ROM.3: Unprotected sub regions in PRINCE defined regions cannot be used.
Introduction
The LPC55S6x devices support real-time encryption and decryption for on-chip flash using the PRINCE encryption algorithm. The PRINCE module supports three flash memory regions for real-time encryption and decryption, referred to as crypto regions. Each crypto region resides at a 256 kB address boundary within the flash and is divided into 8 kB sub-regions which can be individually enabled.
LPC55S6x |
All information provided in this document is subject to legal disclaimers. |
© NXP B.V. 2021. All rights reserved. |
Errata sheet |
Rev. 2.0 — February 25, 2021 |
5 of 20 |
NXP Semiconductors |
LPC55S6x |
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Errata sheet LPC55S6x |
Problem
Unprotected (non PRINCE encrypted) sub flash in PRINCE defined regions cannot be written after an erase operation. Any non PRINCE encrypted sub regions in the PRINCE defined regions cannot be used.
Work-around
There is no work-around.
This issue is fixed on device revision 1B.
3.4ROM.4: Last page of image is erased when simultaneously programming the signed image and CFPA region
Introduction
On the LPC55S6x, the protected flash region (PFR) supports a Customer Field Programmable Area (CFPA) which can be used for Monotonic counters, Key revocation, and PRINCE IV codes. Also, the ROM supports secure boot using a signed image.
Problem
When simultaneously programming the signed image and the CFPA via the Secure Binary (SB2 file) image format, the last page of the image is erased.
Work-around
The signed image and the CFPA need to be programmed one a time to prevent the last page of the image from being erased.
This issue is fixed on device revision 1B.
3.5ROM.5: ROM fails to enter ISP mode when image is corrupted with flash pages in an erased or unprogrammed state
Introduction
On the LPC55S6x, if the image is corrupted with flash pages in an erased or unprogrammed state, the ROM may fail to automatically enter ISP mode.
Problem
When secure boot is enabled in CMPA and the flash memory contains an erased or unprogrammed memory page inside the memory region specified by the image size field in the image header, the device does not automatically enter into ISP mode using the fallback mechanism, as in the case of a failed boot for an invalid image. This problem occurs when the application image is only partially written or erased but a valid image header is still present in memory.
Work-around
Perform a mass-erase to remove the incomplete and corrupted image using one of the following methods:
•Execute the erase command using Debug Mailbox. The device will enter directly into ISP mode after exiting the mailbox.
LPC55S6x |
All information provided in this document is subject to legal disclaimers. |
© NXP B.V. 2021. All rights reserved. |
Errata sheet |
Rev. 2.0 — February 25, 2021 |
6 of 20 |
NXP Semiconductors |
LPC55S6x |
|
Errata sheet LPC55S6x |
•Enter into ISP mode using the Debug Mailbox command and use the flash-erase command.
•Reset the device and enter into ISP mode using the ISP pin. Use the flash-erase command to erase the corrupted (incomplete) image.
This issue occurs on device revisions 0A and 1B.
3.6ROM.6: ROM fails to respond to debug session request on version 0A parts
Introduction
Debugging is supported through Arm's Serial wire Debug (SWD) interface, enabling debug with a range of debug probes and tools from NXP and other ecosystem partners. Debug access by a remote host is controlled by the LPC55S6x ROM and is only enabled when permitted through the device configuration and when the correct protocol is followed to initiate a debug session.The Boot ROM implements a debug mailbox protocol to interact with host debug systems over the SWD interface. For LPC55S6x, if the device has been configured for debug authentication, then a debug session must be initiated following the correct authentication sequence.
Problem
For the LPC55S6x, a new method of initiating a debug session was introduced, as documented in the current user manual. However, when used on 0A parts, a debug system attempting to connect could become stuck in an endless loop because the ROM in that silicon revision fails to issue a corresponding response to the new debug session request.
Work-around
It is possible to determine whether the cause of the hang during a debug session request is related to the part revision by detecting whether an overrun condition is reported via the debug mailbox, which is only generated by the newer parts and not by the older 0A version. The pseudo code below is a modified version to replace that shown in Chapter 51.6.1 of the user manual, implementing a check for silicon revision when connecting to LPC55S6x parts:
//Read AP ID register to identify DM AP at index 2 WriteDP 2 0x020000F0
//The returned AP ID should be 0x002A0000
value = ReadAP 3 print "AP ID: ", value
//Select DM AP index 2
//Select CSW register [BJS] WriteDP 2 0x02000000
//Write DM RESYNC_REQ + CHIP_RESET_REQ WriteAP 0 0x21
//Poll CSW register (0) a offset 0x00 for zero return, indicating success value = -1
while value != 0 {
LPC55S6x |
All information provided in this document is subject to legal disclaimers. |
© NXP B.V. 2021. All rights reserved. |
Errata sheet |
Rev. 2.0 — February 25, 2021 |
7 of 20 |
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