NXP LPC2458 data sheet

LPC2458

Single-chip 16-bit/32-bit micro; 512 kB flash, Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interface

Rev. 4.2 — 15 October 2020 Product data sheet

1. General description

NXP Semiconductors designed the LPC2458 microcontroller around a 16-bit/32-bit ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and embedded trace. The LPC2458 has 512 kB of on-chip high-speed flash memory. This flash memory includes a special 128-bit wide memory interface and accelerator architecture that enables the CPU to execute sequential instructions from flash memory at the maximum 72 MHz system clock rate. This feature is available only on the LPC2000 ARM microcontroller family of products. The LPC2458 can execute both 32-bit ARM and 16-bit Thumb instructions. Support for the two instruction sets means engineers can choose to optimize their application for either performance or code size at the sub-routine level. When the core executes instructions in Thumb state it can reduce code size by more than 30 % with only a small loss in performance while executing instructions in ARM state maximizes core performance.

The LPC2458 microcontroller is ideal for multi-purpose communication applications. It incorporates a 10/100 Ethernet Media Access Controller (MAC), a USB full-speed Device/Host/OTG Controller with 4 kB of endpoint RAM, four UARTs, two Controller Area Network (CAN) channels, an SPI interface, two Synchronous Serial Ports (SSP), three I interfaces, and an I interfaces are the following feature components; an on-chip 4 MHz internal precision oscillator, 98 kB of total RAM consisting of 64 kB of local SRAM, 16 kB SRAM for Ethernet, 16 kB SRAM for general purpose DMA, 2 kB of battery powered SRAM, and an External Memory Controller (EMC). These features make this device optimally suited for communication gateways and protocol converters. Complementing the many serial communication controllers, versatile clocking capabilities, and memory features are various 32-bit timers, an improved 10-bit ADC, 10-bit DAC, two PWM units, four external interrupt pins, and up to 136 fast GPIO lines. The LPC2458 connects 64 of the GPIO pins to the hardware based Vector Interrupt Controller (VIC) that means these external inputs can generate edge-triggered interrupts. All of these features make the LPC2458 particularly suitable for industrial control and medical systems.

2. Features and benefits

 ARM7TDMI-S processor, running at up to 72 MHz.  512 kB on-chip flash program memory with In-System Programming (ISP) and

In-Application Programming (IAP) capabilities. Flash program memory is on the ARM local bus for high performance CPU access.

 98 kB on-chip SRAM includes:

 64 kB of SRAM on the ARM local bus for high performance CPU access.  16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.

S interface. Supporting this collection of serial communications

NXP Semiconductors

Single-chip 16-bit/32-bit micro

 16 kB SRAM for general purpose DMA use also accessible by the USB.  2 kB SRAM data storage powered from the Real-Time Clock (RTC) power domain.

 Dual Advanced High-performance Bus (AHB) system allows simultaneous Ethernet

DMA, USB DMA, and program execution from on-chip flash with no contention.

 EMC provides support for asynchronous static memory devices such as RAM, ROM

and flash, as well as dynamic memories such as Single Data Rate SDRAM.

 Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.  General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP,

S, and SD/MM interface as well as for memory-to-memory transfers.

 Serial Interfaces:

 Ethernet MAC with MII/RMII interface and associated DMA controller. These

functions reside on an independent AHB.

 USB 2.0 full-speed dual port Device/Host/OTG Controller with on-chip PHY and

associated DMA controller.

 Four UARTs with fractional baud rate generation, one with modem control I/O, one

with IrDA support, all with FIFO.

 CAN controller with two channels.  SPI controller.  Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate

for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA controller.

 Three I2C-bus interfaces (one with open-drain and two with standard port pins).  I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with

the GPDMA.

 Other peripherals:

 SD/MMC memory card interface.  136 General purpose I/O pins with configurable pull-up/down resistors.  10-bit ADC with input multiplexing among 8 pins.  10-bit DAC.  Four general purpose timers/counters with 8 capture inputs and 10 compare

outputs. Each timer block has an external count input.

 Two PWM/timer blocks with support for three-phase motor control. Each PWM has

an external count inputs.

 RTC with separate power domain, clock source can be the RTC oscillator or the

APB clock.

 2 kB SRAM powered from the RTC power pin, allowing data to be stored when the

rest of the chip is powered off.

 WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,

the RTC oscillator, or the APB clock.

 Standard ARM test/debug interface for compatibility with existing tools.  Emulation trace module supports real-time trace.  Single 3.3 V power supply (3.0 V to 3.6 V).  Four reduced power modes: idle, sleep, power-down, and deep power-down.  Four external interrupt inputs configurable as edge/level sensitive. All pins on port 0

and port 2 can be used as edge sensitive interrupt sources.

 Processor wake-up from Power-down mode via any interrupt able to operate during

Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt, CAN bus activity, port 0/2 pin interrupt).

Product data sheet Rev. 4.2 — 15 October 2020 2 of 81

LPC2458

NXP Semiconductors

 Two independent power domains allow fine tuning of power consumption based on

 Each peripheral has its own clock divider for further power saving. These dividers help

 Brownout detect with separate thresholds for interrupt and forced reset.  On-chip power-on reset.  On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.  4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as

 On-chip PLL allows CPU operation up to the maximum CPU rate without the need for

 Boundary scan for simplified board testing.  Versatile pin function selections allow more possibilities for using on-chip peripheral

3. Applications

LPC2458

Single-chip 16-bit/32-bit micro

needed features.

reduce active power by 20 % to 30 %.

the system clock. When used as the CPU clock, does not allow CAN and USB to run.

a high frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator.

functions.

 Industrial control  Medical systems  Protocol converter  Communications

4. Ordering information

Table 1. Ordering information

Typ e n u mber Package

LPC2458FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12  12  0.8 mm SOT570-3

Table 2. Ordering options

Typ e n u mber Flash

LPC2458FET180 512 64 16 16 2 98 16-bit MII/

Name Description Version

4.1 Ordering options

(kB)

SRAM (kB) External

bus

Local bus

Ethernet buffer

GP/USB

RTC

Tot al

Ethernet USB

OTG/ OHC/ DEV +4kB FIFO

yes 2 yes yes 8 1 40 C to

RMII

CAN channels

SD/ MMC

GP DMA

Tem p range

ADC channels

DAC channels

+85 C

Product data sheet Rev. 4.2 — 15 October 2020 3 of 81

NXP Semiconductors

power domain 2

LPC2458

A[19:0]

D[15:0]

EXTERNAL

MEMORY

CONTROLLER

ALARM

002aad093

PWM0, PWM1

ARM7TDMI-S

PLL

EINT3 to EINT0

FLASH

P3, P4

P0, P1, P2,

LEGACY GPI/O 64 PINS TOTAL

P0, P1

SCK, SCK0 MOSI, MOSI0

SSEL, SSEL0 SCK1

MOSI1 MISO1

SSEL1

SCL0, SCL1, SCL2

I2SRX_CLK I2STX_CLK I2SRX_WS I2STX_WS

8 × AD0

RTCX1 RTCX2

MCICLK, MCIPWR

RXD0, RXD2, RXD3

TXD1 RXD1

RD1, RD2 TD1, TD2

CAN1, CAN2

port 1

XTAL1

TCK TDO

EXTIN0

XTAL2

RESET

TRST

TDITMS

HIGH-SPEED

GPIO

136 PINS

TOTAL

port 2

64 kB

SRAM

512 kB

FLASH

INTERNAL

CONTROLLERS

TEST/DEBUG

INTERFACE

EMULATION

TRACE MODULE

trace signals

AHB

BRIDGE

AHB

BRIDGE

ETHERNET

MAC WITH

DMA

16 kB

SRAM

MASTER

PORT

AHB TO

AHB BRIDGE

SLAVE

PORT

system

clock

SYSTEM

FUNCTIONS

INTERNAL RC

OSCILLATOR

DDA

DD(3V3)

DD(DCDC)(3V3)

VREF V

SSA

, V

SSIO, VSSCORE

VIC

16 kB

SRAM

USB DEVICE/

HOST/OTG WITH

4 kB RAM AND DMA

GPDMA

CONTROLLER

I2S INTERFACE

SPI, SSP0 INTERFACE

I2SRX_SDA I2STX_SDA

MISO, MISO0

SSP1 INTERFACE

SD/MMC CARD

INTERFACE

MCICMD, MCIDAT[3:0]

TXD0, TXD2, TXD3

UART0, UART2, UART3

UART1

DTR1, RTS1 DSR1, CTS1, DCD1,

RI1

C0, I2C1, I2C2

SDA0, SDA1, SDA2

EXTERNAL INTERRUPTS

CAPTURE/COMPARE

TIMER0/TIMER1/

TIMER2/TIMER3

A/D CONVERTER

D/A CONVERTER

2 kB BATTERY RAM

RTC

OSCILLATOR

REAL-

TIME

CLOCK

WATCHDOG TIMER

SYSTEM CONTROL

2 × CAP0/CAP1/

CAP2/CAP3

4 × MAT2,

2 × MAT3,

2 × MAT1/MAT0

6 × PWM0, PWM1

1 × PCAP0,

2 × PCAP1

AOUT

VBAT

AHB TO

APB BRIDGE

SRAM

MII/RMII

BUS

DBGEN

P0, P2

AHB2

AHB1

control lines

5. Block diagram

LPC2458

Single-chip 16-bit/32-bit micro

Product data sheet Rev. 4.2 — 15 October 2020 4 of 81

Fig 1. LPC2458 block diagram

NXP Semiconductors

002aad094

LPC2458

2 4 6 8 10 12 13141357911

ball A1 index area

Transparent top view

6. Pinning information

6.1 Pinning

LPC2458

Single-chip 16-bit/32-bit micro

Fig 2. LPC2458 pinning TFBGA180 package

Table 3. Pin allocation table

Pin Symbol Pin Symbol Pin Symbol Pin Symbol

Row A

1 P3[12]/D12 2 P3[2]/D2 3 P0[3]/RXD0 4 P3[9]/D9

5 P1[1]/ENET_TXD1 6 P3[8]/D8 7 P1[10]/ENET_RXD1 8 P1[15]/

ENET_REF_CLK/ ENET_RX_CLK

9 P1[3]/ENET_TXD3/

MCICMD/PWM0[2]

13 P0[9]/I2STX_SDA/

MOSI1/MAT2[3]

10 V

SSCORE

14 P1[12]/ENET_RXD3/

MCIDAT3/PCAP0[0]

11 P0[4]/I2SRX_CLK/RD2/

CAP2[0]

15 - 16 -

12 P1[11]/ENET_RXD2/

MCIDAT2/PWM0[6]

Row B

1 TDO 2 P3[11]/D11 3 P3[10]/D10 4 V

5 P1[0]/ENET_TXD0 6 P1[8]/ENET_CRS_DV/

ENET_CRS

9 P4[29]/

13 P1[5]/ENET_TX_ER/

MAT2[1]/RXD3

10 P1[6]/ENET_TX_CLK/

MCIDAT0/PWM0[4]

14 P4[13]/A13 15 - 16 -

7 P1[2]/ENET_TXD2/

MCICLK/PWM0[1]

11 P0[5]/I2SRX_WS/TD2/

CAP2[1]

SSIO

8 P1[16]/ENET_MDC

12 P0[7]/I2STX_CLK/SCK1

/MAT2[1]

MCIPWR/PWM0[3]

Row C

1 P3[13]/D13 2 TMS 3 TDI 4 RTCK

DD(3V3)

9 P1[17]/ENET_MDIO 10 P4[15]/A15 11 V

6 P1[4]/ENET_TX_EN 7 P4[30]/CS0 8 P4[24]/OE

SSIO

12 P0[8]/I2STX_WS/

MISO1/MAT2[2]

Product data sheet Rev. 4.2 — 15 October 2020 5 of 81

NXP Semiconductors

LPC2458

Single-chip 16-bit/32-bit micro

Table 3. Pin allocation table …continued

Pin Symbol Pin Symbol Pin Symbol Pin Symbol

13 P1[7]/ENET_COL/

MCIDAT1/PWM0[5]

Row D

1 P0[26]/AD0[3]/

AOUT/RXD3

5 P0[2]/TXD0 6 P3[0]/D0 7 P1[9]/ENET_RXD0 8 P1[14]/ENET_RX_ER

9 P4[25]/WE

13 V

SSIO

Row E

1 P0[24]/AD0[1]/

I2SRX_WS/CAP3[1]

5 DBGEN 6 P3[1]/D1 7 P4[31]/CS1

DD(DCDC)(3V3)

13 P2[3]/PWM1[4]/

DCD1/PIPESTAT2

Row F

1 P3[14]/D14 2 V

5 P0[23]/AD0[0]/

I2SRX_CLK/CAP3[0]

9 10 P4[12]/A12 11 P4[11]/A11 12 P2[5]/PWM1[6]/

13 P2[6]/PCAP1[0]/

RI1/TRACEPKT1

Row G

DD(DCDC)(3V3)

5 P3[3]/D3 6 7 8

9 10 n.c. 11 P2[7]/RD2/

13 V

SSIO

Row H

1 n.c. 2 RSTOUT 3V

5ALARM 6 7 8

9 10 P4[5]/A5 11 P2[9]/

13 P0[15]/TXD1/

SCK0/SCK

Row J

1 RESET 2 RTCX1 3 RTCX2 4 P0[12]/USB_PPWR2/

5 P0[13]/USB_UP_LED2/

MOSI1/AD0[7]

14 P2[1]/PWM1[2]/RXD1/

15 - 16 -

PIPESTAT0

2 TCK 3 P3[4]/D4 4 TRST

10 P4[28]/

MAT2[0]/TXD3

11 P0[6]/I2SRX_SDA/

SSEL1/MAT2[0]

12 P2[0]/PWM1[1]/TXD1/

TRACECLK

14 P1[13]/ENET_RX_DV 15 - 16 -

DD(3V3)

3 P3[5]/D5 4 P0[25]/AD0[2]/

I2SRX_SDA/TXD3

8 P4[14]/A14

10 V

DD(3V3)

11 P2[2]/PWM1[3]/

12 V

DD(3V3)

CTS1/PIPESTAT1

14 P2[4]/PWM1[5]/

15 - 16 -

DSR1/TRACESYNC

DDA

SSA

4 P3[6]/D6

678

DTR1/TRACEPKT0

14 P4[27]/BLS1

15 - 16 -

2 VREF 3 P3[7]/D7 4 P3[15]/D15

12 P4[10]/A10

RTS1/TRACEPKT2

14 P2[8]/TD2/

15 - 16 -

TXD2/TRACEPKT3

SSCORE

SSIO

12 P4[9]/A9 USB_CONNECT1/ RXD2/EXTIN0

14 P0[16]/RXD1/

15 - 16 -

SSEL0/SSEL

MISO1/AD0[6]

678

Product data sheet Rev. 4.2 — 15 October 2020 6 of 81

NXP Semiconductors

LPC2458

Single-chip 16-bit/32-bit micro

Table 3. Pin allocation table …continued

Pin Symbol Pin Symbol Pin Symbol Pin Symbol

9 10 P0[19]/DSR1/

MCICLK/SDA1

13 P0[18]/DCD1/

14 V

DD(3V3)

MOSI0/MOSI

Row K

1 VBAT 2 P1[31]/USB_OVRCR2/

SCK1/AD0[5]

5 P0[29]/USB_D+1 6 P1[20]/USB_TX_DP1/

PWM1[2]/SCK0

9 P4[3]/A3 10 P4[6]/A6 11 P0[21]/RI1/

13 P4[26]/BLS0

14 P0[20]/DTR1/

MCICMD/SCL1

Row L

1 P2[29]/DQMOUT1 2 XTAL1 3 P0[27]/SDA0 4 V

5 P1[18]/USB_UP_LED1/

6 P4[0]/A0 7 P1[25]/USB_LS1/

PWM1[1]/CAP1[0]

SSIO

10 P0[10]/TXD2/SDA2/

MAT3[0]

13 V

SSIO

14 P0[22]/RTS1/

MCIDAT0/TD1

Row M

1 P0[28]/SCL0 2 P2[28]/DQMOUT0 3 P3[25]/MAT0[0]/

5 P0[14]/USB_HSTEN2

USB_CONNECT2/

6 P1[22]/USB_RCV1/

USB_PWRD1/MAT1[0]

SSEL1

9 P1[27]/USB_INT1

10 P0[0]/RD1/TXD3/SDA1 11 P2[13]/EINT3/

USB_OVRCR1/CAP0[1]

13 P2[10]/EINT0

14 P4[19]/A19 15 - 16 -

Row N

1 P0[31]/USB_D+2 2 USB_D2 3 P3[24]/CAP0[1]/

5 P2[19]/CLKOUT1 6 P1[21]/USB_TX_DM1/

PWM1[3]/SSEL0

DD(DCDC)(3V3)

10 P1[29]/USB_SDA1/

PCAP1[1]/MAT0[1]

13 P4[17]/A17 14 P2[12]/EINT2

MCIDAT2/I2STX_WS

Row P

1 P2[24]/CKEOUT0 2 P2[25]/CKEOUT1 3 P2[18]/CLKOUT0 4 V

5 P1[19]/USB_TX_E1/

USB_PPWR1

/CAP1[1]

9 P2[16]/CAS

6 P2[20]/DYCS0

10 P1[28]/USB_SCL1/

PCAP1[0]/MAT0[0]

13 P4[4]/A4 14 P4[18]/A18 15 - 16 -

11 P4[8]/A8 12 P0[17]/CTS1/

MISO0/MISO

15 - 16 -

3 P1[30]/USB_PWRD2/

/AD0[4]

BUS

7 P3[26]/MAT0[1]/

4XTAL2

DD(3V3)

PWM1[3]

12 P4[7]/A7 MCIPWR/RD1

15 - 16 -

DD(3V3)

8V USB_HSTEN1

11 V

DD(3V3)

/MAT1[1]

SSCORE

12 n.c.

15 - 16 -

4 P3[23]/CAP0[0]/ PWM1[2]

PCAP1[0]

7 P4[1]/A1 8 P4[2]/A2

12 P2[11]/EINT1/ MCIDAT3/I2STX_SDA

MCIDAT1/I2STX_CLK

4 P0[30]/USB_D1 PWM1[1]

7 P1[23]/USB_RX_DP1/

8 P2[21]/DYCS1 PWM1[4]/MISO0

11 P0[1]/TD1/RXD3/SCL1 12 P4[16]/A16

15 - 16 -

SSIO

7 P1[24]/USB_RX_DM1/

PWM1[5]/MOSI0

8 P1[26]/USB_SSPND1/

PWM1[6]/CAP0[0]

11 P2[17]/RAS 12 P0[11]/RXD2/SCL2/

MAT3[1]

Product data sheet Rev. 4.2 — 15 October 2020 7 of 81

NXP Semiconductors

LPC2458

Single-chip 16-bit/32-bit micro

6.2 Pin description

M10

N11

A11

B11

D11

B12

C12

operation of port 0 pins depends upon the pin function selected via the Pin Connect block.

[1]

I/O P0[0] — General purpose digital input/output pin.

I RD1 — CAN1 receiver input.

O TXD3 — Transmitter output for UART3.

I/O SDA1 — I

[1]

I/O P0[1] — General purpose digital input/output pin.

C1 data input/output (this is not an open-drain pin).

O TD1 — CAN1 transmitter output.

I RXD3 — Receiver input for UART3.

I/O SCL1 — I

[1]

I/O P0[2] — General purpose digital input/output pin.

C1 clock input/output (this is not an open-drain pin).

O TXD0 — Transmitter output for UART0.

[1]

I/O P0[3] — General purpose digital input/output pin.

I RXD0 — Receiver input for UART0.

[1]

I/O P0[4] — General purpose digital input/output pin.

I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the

slave. Corresponds to the signal SCK in the I

S-bus specification.

I RD2 — CAN2 receiver input.

I CAP2[0] — Capture input for Timer 2, channel 0.

[1]

I/O P0[5] — General purpose digital input/output pin.

I/O I2SRX_WS — Receive Word Select. It is driven by the master and received by

the slave. Corresponds to the signal WS in the I

S-bus specification.

O TD2 — CAN2 transmitter output.

I CAP2[1] — Capture input for Timer 2, channel 1.

[1]

I/O P0[6] — General purpose digital input/output pin.

I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the

receiver. Corresponds to the signal SD in the I

S-bus specification.

I/O SSEL1 — Slave Select for SSP1.

O MAT2[0] — Match output for Timer 2, channel 0.

[1]

I/O P0[7] — General purpose digital input/output pin.

I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the

slave. Corresponds to the signal SCK in the I

S-bus specification.

I/O SCK1 — Serial Clock for SSP1.

O MAT2[1] — Match output for Timer 2, channel 1.

[1]

I/O P0[8] — General purpose digital input/output pin.

I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by

the slave. Corresponds to the signal WS in the I

S-bus specification.

I/O MISO1 — Master In Slave Out for SSP1.

O MAT2[2] — Match output for Timer 2, channel 2.

Table 4. Pin description

Symbol Ball Type Description

P0[0] to P0[31] I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The

P0[0]/RD1/ TXD3/SDA1

P0[1]/TD1/RXD3/ SCL1

P0[2]/TXD0 D5

P0[3]/RXD0 A3

P0[4]/ I2SRX_CLK/ RD2/CAP2[0]

P0[5]/ I2SRX_WS/ TD2/CAP2[1]

P0[6]/ I2SRX_SDA/ SSEL1/MAT2[0]

P0[7]/ I2STX_CLK/ SCK1/MAT2[1]

P0[8]/ I2STX_WS/ MISO1/MAT2[2]

Product data sheet Rev. 4.2 — 15 October 2020 8 of 81

NXP Semiconductors

Table 4. Pin description …continued

Symbol Ball Type Description

P0[9]/ I2STX_SDA/ MOSI1/MAT2[3]

P0[10]/TXD2/ SDA2/MAT3[0]

P0[11]/RXD2/ SCL2/MAT3[1]

P0[12]/ USB_PPWR2

MISO1/AD0[6]

P0[13]/ USB_UP_LED2/ MOSI1/AD0[7]

P0[14]/ USB_HSTEN2

/ USB_CONNECT2/ SSEL1

P0[15]/TXD1/ SCK0/SCK

P0[16]/RXD1/ SSEL0/SSEL

A13

L10

P12

H13

H14

[1]

I/O P0[9] — General purpose digital input/output pin.

I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the

receiver. Corresponds to the signal SD in the I

I/O MOSI1 — Master Out Slave In for SSP1.

O MAT2[3] — Match output for Timer 2, channel 3.

[1]

I/O P0[10] — General purpose digital input/output pin.

O TXD2 — Transmitter output for UART2.

I/O SDA2 — I

O MAT3[0] — Match output for Timer 3, channel 0.

[1]

I/O P0[11] — General purpose digital input/output pin.

I RXD2 — Receiver input for UART2.

I/O SCL2 — I

O MAT3[1] — Match output for Timer 3, channel 1.

[2]

I/O P0[12] — General purpose digital input/output pin.

O USB_PPWR2

I/O MISO1 — Master In Slave Out for SSP1.

I AD0[6] — A/D converter 0, input 6.

[2]

I/O P0[13] — General purpose digital input/output pin.

O USB_UP_LED2 — USB port 2 GoodLink LED indicator. It is LOW when device is

configured (non-control endpoints enabled), or when host is enabled and has detected a device on the bus. It is HIGH when the device is not configured, or when host is enabled and has not detected a device on the bus, or during global suspend. It transitions between LOW and HIGH (flashes) when host is enabled and detects activity on the bus.

I/O MOSI1 — Master Out Slave In for SSP1.

I AD0[7] — A/D converter 0, input 7.

[1]

I/O P0[14] — General purpose digital input/output pin.

O USB_HSTEN2

O USB_CONNECT2 — SoftConnect control for USB port 2. Signal used to switch

an external 1.5 k resistor under software control. Used with the SoftConnect USB feature.

I/O SSEL1 — Slave Select for SSP1.

[1]

I/O P0[15] — General purpose digital input/output pin.

O TXD1 — Transmitter output for UART1.

I/O SCK0 — Serial clock for SSP0.

I/O SCK — Serial clock for SPI.

[1]

I/O P0[16] — General purpose digital input/output pin.

I RXD1 — Receiver input for UART1.

I/O SSEL0 — Slave Select for SSP0.

I/O SSEL — Slave Select for SPI.

Single-chip 16-bit/32-bit micro

S-bus specification.

C2 data input/output (this is not an open-drain pin).

C2 clock input/output (this is not an open-drain pin).

— Port Power enable signal for USB port 2.

— Host Enabled status for USB port 2.

LPC2458

Product data sheet Rev. 4.2 — 15 October 2020 9 of 81

NXP Semiconductors

Table 4. Pin description …continued

Symbol Ball Type Description

P0[17]/CTS1/ MISO0/MISO

P0[18]/DCD1/ MOSI0/MOSI

P0[19]/DSR1/ MCICLK/SDA1

P0[20]/DTR1/ MCICMD/SCL1

P0[21]/RI1/ MCIPWR/RD1

P0[22]/RTS1/ MCIDAT0/TD1

P0[23]/AD0[0]/ I2SRX_CLK/ CAP3[0]

P0[24]/AD0[1]/ I2SRX_WS/ CAP3[1]

P0[25]/AD0[2]/ I2SRX_SDA/ TXD3

J12

J13

J10

K14

K11

L14

[1]

I/O P0[17] — General purpose digital input/output pin.

I CTS1 — Clear to Send input for UART1.

I/O MISO0 — Master In Slave Out for SSP0.

I/O MISO — Master In Slave Out for SPI.

[1]

I/O P0[18] — General purpose digital input/output pin.

I DCD1 — Data Carrier Detect input for UART1.

I/O MOSI0 — Master Out Slave In for SSP0.

I/O MOSI — Master Out Slave In for SPI.

[1]

I/O P0[19] — General purpose digital input/output pin.

I DSR1 — Data Set Ready input for UART1.

O MCICLK — Clock output line for SD/MMC interface.

I/O SDA1 — I

[1]

I/O P0[20] — General purpose digital input/output pin.

O DTR1 — Data Terminal Ready output for UART1.

I/O MCICMD — Command line for SD/MMC interface.

I/O SCL1 — I

[1]

I/O P0[21] — General purpose digital input/output pin.

I RI1 — Ring Indicator input for UART1.

O MCIPWR — Power Supply Enable for external SD/MMC power supply.

I RD1 — CAN1 receiver input.

[1]

I/O P0[22] — General purpose digital input/output pin.

O RTS1 — Request to Send output for UART1.

I/O MCIDAT0 — Data line 0 for SD/MMC interface.

O TD1 — CAN1 transmitter output.

[2]

I/O P0[23] — General purpose digital input/output pin.

I AD0[0] — A/D converter 0, input 0.

I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the

slave. Corresponds to the signal SCK in the I

I CAP3[0] — Capture input for Timer 3, channel 0.

[2]

I/O P0[24] — General purpose digital input/output pin.

I AD0[1] — A/D converter 0, input 1.

I/O I2SRX_WS — Receive Word Select. It is driven by the master and received by

the slave. Corresponds to the signal WS in the I

I CAP3[1] — Capture input for Timer 3, channel 1.

[2]

I/O P0[25] — General purpose digital input/output pin.

I AD0[2] — A/D converter 0, input 2.

I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the

receiver. Corresponds to the signal SD in the I

O TXD3 — Transmitter output for UART3.

Single-chip 16-bit/32-bit micro

C1 data input/output (this is not an open-drain pin).

C1 clock input/output (this is not an open-drain pin).

S-bus specification.

LPC2458

Product data sheet Rev. 4.2 — 15 October 2020 10 of 81

NXP Semiconductors

LPC2458

Single-chip 16-bit/32-bit micro

Table 4. Pin description …continued

Symbol Ball Type Description

P0[26]/AD0[3]/ AOUT/RXD3

P0[27]/SDA0 L3

P0[28]/SCL0 M1

P0[29]/USB_D+1 K5

P0[30]/USB_D1N4

P0[31]/USB_D+2 N1

P1[0] to P1[31] I/O Port 1: Port 1 is a 32 bit I/O port with individual direction controls for each bit. The

P1[0]/ ENET_TXD0

P1[1]/ ENET_TXD1

P1[2]/ ENET_TXD2/ MCICLK/ PWM0[1]

P1[3]/ ENET_TXD3/ MCICMD/ PWM0[2]

P1[4]/ ENET_TX_EN

P1[5]/ ENET_TX_ER/ MCIPWR/ PWM0[3]

P1[6]/ ENET_TX_CLK/ MCIDAT0/ PWM0[4]

B13

B10

[2][3]

[4]

[5]

[1]

I/O P0[26] — General purpose digital input/output pin.

I AD0[3] — A/D converter 0, input 3.

O AOUT — D/A converter output.

I RXD3 — Receiver input for UART3.

I/O P0[27] — General purpose digital input/output pin. Output is open-drain.

I/O SDA0 — I

C0 data input/output. Open-drain output (for I2C-bus compliance).

I/O P0[28] — General purpose digital input/output pin. Output is open-drain.

I/O SCL0 — I

C0 clock input/output. Open-drain output (for I2C-bus compliance).

I/O P0[29] — General purpose digital input/output pin.

I/O USB_D+1 — USB port 1 bidirectional D+ line.

I/O P0[30] — General purpose digital input/output pin.

I/O USB_D1 — USB port 1 bidirectional D line.

I/O P0[31] — General purpose digital input/output pin.

I/O USB_D+2 — USB port 2 bidirectional D+ line.

operation of port 1 pins depends upon the pin function selected via the Pin Connect block.

I/O P1[0] — General purpose digital input/output pin.

O ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface).

I/O P1[1] — General purpose digital input/output pin.

O ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface).

I/O P1[2] — General purpose digital input/output pin.

O ENET_TXD2 — Ethernet transmit data 2 (MII interface).

O MCICLK — Clock output line for SD/MMC interface.

O PWM0[1] — Pulse Width Modulator 0, output 1.

I/O P1[3] — General purpose digital input/output pin.

O ENET_TXD3 — Ethernet transmit data 3 (MII interface).

I/O MCICMD — Command line for SD/MMC interface.

O PWM0[2] — Pulse Width Modulator 0, output 2.

I/O P1[4] — General purpose digital input/output pin.

O ENET_TX_EN — Ethernet transmit data enable (RMII/MII interface).

[1]

I/O P1[5] — General purpose digital input/output pin.

O ENET_TX_ER — Ethernet Transmit Error (MII interface).

O MCIPWR — Power Supply Enable for external SD/MMC power supply.

O PWM0[3] — Pulse Width Modulator 0, output 3.

[1]

I/O P1[6] — General purpose digital input/output pin.

I ENET_TX_CLK — Ethernet Transmit Clock (MII interface).

I/O MCIDAT0 — Data line 0 for SD/MMC interface.

O PWM0[4] — Pulse Width Modulator 0, output 4.

Product data sheet Rev. 4.2 — 15 October 2020 11 of 81

NXP Semiconductors

Table 4. Pin description …continued

Symbol Ball Type Description

P1[7]/ ENET_COL/ MCIDAT1/ PWM0[5]

P1[8]/ ENET_CRS_DV/ ENET_CRS

P1[9]/ ENET_RXD0

P1[10]/ ENET_RXD1

P1[11]/ ENET_RXD2/ MCIDAT2/ PWM0[6]

P1[12]/ ENET_RXD3/ MCIDAT3/ PCAP0[0]

P1[13]/ ENET_RX_DV

P1[14]/ ENET_RX_ER

P1[15]/ ENET_REF_CLK/ ENET_RX_CLK

P1[16]/ ENET_MDC

P1[17]/ ENET_MDIO

P1[18]/ USB_UP_LED1/ PWM1[1]/ CAP1[0]

P1[19]/ USB_TX_E1 USB_PPWR1

CAP1[1]

C13

A12

A14

D14

[1]

I/O P1[7] — General purpose digital input/output pin.

I ENET_COL — Ethernet Collision detect (MII interface).

I/O MCIDAT1 — Data line 1 for SD/MMC interface.

O PWM0[5] — Pulse Width Modulator 0, output 5.

[1]

I/O P1[8] — General purpose digital input/output pin.

I ENET_CRS_DV/ENET_CRS — Ethernet Carrier Sense/Data Valid (RMII

interface)/ Ethernet Carrier Sense (MII interface).

[1]

I/O P1[9] — General purpose digital input/output pin.

I ENET_RXD0 — Ethernet receive data 0 (RMII/MII interface).

[1]

I/O P1[10] — General purpose digital input/output pin.

I ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface).

[1]

I/O P1[11] — General purpose digital input/output pin.

I ENET_RXD2 — Ethernet Receive Data 2 (MII interface).

I/O MCIDAT2 — Data line 2 for SD/MMC interface.

O PWM0[6] — Pulse Width Modulator 0, output 6.

[1]

I/O P1[12] — General purpose digital input/output pin.

I ENET_RXD3 — Ethernet Receive Data (MII interface).

I/O MCIDAT3 — Data line 3 for SD/MMC interface.

I PCAP0[0] — Capture input for PWM0, channel 0.

[1]

I/O P1[13] — General purpose digital input/output pin.

I ENET_RX_DV — Ethernet Receive Data Valid (MII interface).

[1]

I/O P1[14] — General purpose digital input/output pin.

I ENET_RX_ER — Ethernet receive error (RMII/MII interface).

[1]

I/O P1[15] — General purpose digital input/output pin.

I ENET_REF_CLK/ENET_RX_CLK — Ethernet Reference Clock (RMII interface)/

Ethernet Receive Clock (MII interface).

[1]

I/O P1[16] — General purpose digital input/output pin.

O ENET_MDC — Ethernet MIIM clock.

[1]

I/O P1[17] — General purpose digital input/output pin.

I/O ENET_MDIO — Ethernet MI data input and output.

[1]

I/O P1[18] — General purpose digital input/output pin.

O USB_UP_LED1 — USB port 1 GoodLink LED indicator. It is LOW when device is

O PWM1[1] — Pulse Width Modulator 1, channel 1 output.

I CAP1[0] — Capture input for Timer 1, channel 0.

[1]

I/O P1[19] — General purpose digital input/output pin.

O USB_TX_E1

O USB_PPWR1

I CAP1[1] — Capture input for Timer 1, channel 1.

LPC2458

Single-chip 16-bit/32-bit micro

— Transmit Enable signal for USB port 1 (OTG transceiver).

— Port Power enable signal for USB port 1.

Product data sheet Rev. 4.2 — 15 October 2020 12 of 81

NXP Semiconductors

Table 4. Pin description …continued

Symbol Ball Type Description

P1[20]/ USB_TX_DP1/ PWM1[2]/SCK0

P1[21]/ USB_TX_DM1/ PWM1[3]/SSEL0

P1[22]/ USB_RCV1/ USB_PWRD1/ MAT1[0]

P1[23]/ USB_RX_DP1/ PWM1[4]/MISO0

P1[24]/ USB_RX_DM1/ PWM1[5]/MOSI0

P1[25]/ USB_LS1

/ USB_HSTEN1/ MAT1[1]

P1[26]/ USB_SSPND1

/ PWM1[6]/ CAP0[0]

P1[27]/ USB_INT1

/ USB_OVRCR1/ CAP0[1]

P1[28]/ USB_SCL1/ PCAP1[0]/ MAT0[0]

P1[29]/ USB_SDA1/ PCAP1[1]/ MAT0[1]

P10

N10

[1]

I/O P1[20] — General purpose digital input/output pin.

O USB_TX_DP1 — D+ transmit data for USB port 1 (OTG transceiver).

O PWM1[2] — Pulse Width Modulator 1, channel 2 output.

I/O SCK0 — Serial clock for SSP0.

[1]

I/O P1[21] — General purpose digital input/output pin.

O USB_TX_DM1 — D transmit data for USB port 1 (OTG transceiver).

O PWM1[3] — Pulse Width Modulator 1, channel 3 output.

I/O SSEL0 — Slave Select for SSP0.

[1]

I/O P1[22] — General purpose digital input/output pin.

I USB_RCV1 — Differential receive data for USB port 1 (OTG transceiver).

I USB_PWRD1 — Power Status for USB port 1 (host power switch).

O MAT1[0] — Match output for Timer 1, channel 0.

[1]

I/O P1[23] — General purpose digital input/output pin.

I USB_RX_DP1 — D+ receive data for USB port 1 (OTG transceiver).

O PWM1[4] — Pulse Width Modulator 1, channel 4 output.

I/O MISO0 — Master In Slave Out for SSP0.

[1]

I/O P1[24] — General purpose digital input/output pin.

I USB_RX_DM1 — D receive data for USB port 1 (OTG transceiver).

O PWM1[5] — Pulse Width Modulator 1, channel 5 output.

I/O MOSI0 — Master Out Slave in for SSP0.

[1]

I/O P1[25] — General purpose digital input/output pin.

O USB_LS1

O USB_HSTEN1

O MAT1[1] — Match output for Timer 1, channel 1.

[1]

I/O P1[26] — General purpose digital input/output pin.

O USB_SSPND1

O PWM1[6] — Pulse Width Modulator 1, channel 6 output.

I CAP0[0] — Capture input for Timer 0, channel 0.

[1]

I/O P1[27] — General purpose digital input/output pin.

I USB_INT1

I USB_OVRCR1

I CAP0[1] — Capture input for Timer 0, channel 1.

[1]

I/O P1[28] — General purpose digital input/output pin.

I/O USB_SCL1 — USB port 1 I

I PCAP1[0] — Capture input for PWM1, channel 0.

O MAT0[0] — Match output for Timer 0, channel 0.

[1]

I/O P1[29] — General purpose digital input/output pin.

I/O USB_SDA1 — USB port 1 I

I PCAP1[1] — Capture input for PWM1, channel 1.

O MAT0[1] — Match output for Timer 0, channel 0.

LPC2458

Single-chip 16-bit/32-bit micro

— Low-speed status for USB port 1 (OTG transceiver).

— Host Enabled status for USB port 1.

— USB port 1 Bus Suspend status (OTG transceiver).

— USB port 1 OTG transceiver interrupt.

— USB port 1 Over-Current status.

C serial clock (OTG transceiver).

C serial data (OTG transceiver).

Product data sheet Rev. 4.2 — 15 October 2020 13 of 81

NXP Semiconductors

LPC2458

Single-chip 16-bit/32-bit micro

Table 4. Pin description …continued

Symbol Ball Type Description

[2]

P1[30]/ USB_PWRD2/

/AD0[4]

BUS

P1[31]/ USB_OVRCR2 SCK1/AD0[5]

P2[0] to P2[31] I/O Port 2: Port 2 is a 32-bit I/O port with individual direction controls for each bit. The

P2[0]/PWM1[1]/ TXD1/ TRACECLK

P2[1]/PWM1[2]/ RXD1/ PIPESTAT0

P2[2]/PWM1[3]/ CTS1/ PIPESTAT1

P2[3]/PWM1[4]/ DCD1/ PIPESTAT2

P2[4]/PWM1[5]/ DSR1/ TRACESYNC

P2[5]/PWM1[6]/ DTR1/ TRACEPKT0

P2[6]/PCAP1[0]/RI1/ TRACEPKT1

I/O P1[30] — General purpose digital input/output pin.

I USB_PWRD2 — Power Status for USB port 2.

I V

— Monitors the presence of USB bus power.

BUS

Note: This signal must be HIGH for USB reset to occur.

I AD0[4] — A/D converter 0, input 4.

[2]

I/O P1[31] — General purpose digital input/output pin.

I USB_OVRCR2

— Over-Current status for USB port 2.

I/O SCK1 — Serial Clock for SSP1.

I AD0[5] — A/D converter 0, input 5.

operation of port 2 pins depends upon the pin function selected via the Pin Connect block.

Pins P2[14:15], P2[22:23], P[26:27] and P2[30:31] are not available.

[1]

D12

I/O P2[0] — General purpose digital input/output pin.

O PWM1[1] — Pulse Width Modulator 1, channel 1 output.

O TXD1 — Transmitter output for UART1.

O TRACECLK — Trace Clock.

[1]

C14

I/O P2[1] — General purpose digital input/output pin.

O PWM1[2] — Pulse Width Modulator 1, channel 2 output.

I RXD1 — Receiver input for UART1.

O PIPESTAT0 — Pipeline Status, bit 0.

[1]

E11

I/O P2[2] — General purpose digital input/output pin.

O PWM1[3] — Pulse Width Modulator 1, channel 3 output.

I CTS1 — Clear to Send input for UART1.

O PIPESTAT1 — Pipeline Status, bit 1.

[1]

E13

I/O P2[3] — General purpose digital input/output pin.

O PWM1[4] — Pulse Width Modulator 1, channel 4 output.

I DCD1 — Data Carrier Detect input for UART1.

O PIPESTAT2 — Pipeline Status, bit 2.

[1]

E14

I/O P2[4] — General purpose digital input/output pin.

O PWM1[5] — Pulse Width Modulator 1, channel 5 output.

I DSR1 — Data Set Ready input for UART1.

O TRACESYNC — Trace Synchronization.

[1]

F12

I/O P2[5] — General purpose digital input/output pin.

O PWM1[6] — Pulse Width Modulator 1, channel 6 output.

O DTR1 — Data Terminal Ready output for UART1.

O TRACEPKT0 — Trace Packet, bit 0.

[1]

F13

I/O P2[6] — General purpose digital input/output pin.

I PCAP1[0] — Capture input for PWM1, channel 0.

I RI1 — Ring Indicator input for UART1.

O TRACEPKT1 — Trace Packet, bit 1.

Product data sheet Rev. 4.2 — 15 October 2020 14 of 81

NXP Semiconductors

Table 4. Pin description …continued

Symbol Ball Type Description

P2[7]/RD2/ RTS1/ TRACEPKT2

P2[8]/TD2/ TXD2/ TRACEPKT3

P2[9]/ USB_CONNECT1/ RXD2/ EXTIN0

P2[10]/EINT0

P2[11]/EINT1

/ MCIDAT1/ I2STX_CLK

P2[12]/EINT2

/ MCIDAT2/ I2STX_WS

P2[13]/EINT3

/ MCIDAT3/ I2STX_SDA

P2[16]/CAS

P2[17]/RAS

P2[18]/ CLKOUT0

P2[19]/ CLKOUT1

G11

G14

H11

M13

M12

N14

M11

P11

[1]

I/O P2[7] — General purpose digital input/output pin.

I RD2 — CAN2 receiver input.

O RTS1 — Request to Send output for UART1.

O TRACEPKT2 — Trace Packet, bit 2.

[1]

I/O P2[8] — General purpose digital input/output pin.

O TD2 — CAN2 transmitter output.

O TXD2 — Transmitter output for UART2.

O TRACEPKT3 — Trace Packet, bit 3.

[1]

I/O P2[9] — General purpose digital input/output pin.

O USB_CONNECT1 — USB1 SoftConnect control. Signal used to switch an

external 1.5 k resistor under the software control. Used with the SoftConnect USB feature.

I RXD2 — Receiver input for UART2.

I EXTIN0 — External Trigger Input.

[6]

I/O P2[10] — General purpose digital input/output pin.

Note: LOW on this pin while RESET over control of the part after a reset.

I EINT0

[6]

I/O P2[11] — General purpose digital input/output pin.

I EINT1

— External interrupt 0 input.

— External interrupt 1 input.

I/O MCIDAT1 — Data line 1 for SD/MMC interface.

I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the

slave. Corresponds to the signal SCK in the I

[6]

I/O P2[12] — General purpose digital input/output pin.

I EINT2

— External interrupt 2 input.

I/O MCIDAT2 — Data line 2 for SD/MMC interface.

I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by

the slave. Corresponds to the signal WS in the I

[6]

I/O P2[13] — General purpose digital input/output pin.

I EINT3

— External interrupt 3 input.

I/O MCIDAT3 — Data line 3 for SD/MMC interface.

I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the

receiver. Corresponds to the signal SD in the I

[1]

I/O P2[16] — General purpose digital input/output pin.

O CAS

[1]

I/O P2[17] — General purpose digital input/output pin.

O RAS

— LOW active SDRAM Column Address Strobe.

— LOW active SDRAM Row Address Strobe.

I/O P2[18] — General purpose digital input/output pin.

O CLKOUT0 — SDRAM clock 0.

[1]

I/O P2[19] — General purpose digital input/output pin.

O CLKOUT1 — SDRAM clock 1.

LPC2458

Single-chip 16-bit/32-bit micro

is LOW forces on-chip bootloader to take

S-bus specification.

Product data sheet Rev. 4.2 — 15 October 2020 15 of 81

NXP Semiconductors

LPC2458

Single-chip 16-bit/32-bit micro

Table 4. Pin description …continued

Symbol Ball Type Description

[1]

I/O P2[20] — General purpose digital input/output pin.

O DYCS0

— SDRAM chip select 0.

I/O P2[21] — General purpose digital input/output pin.

O DYCS1

— SDRAM chip select 1.

I/O P2[24] — General purpose digital input/output pin.

O CKEOUT0 — SDRAM clock enable 0.

[1]

I/O P2[25] — General purpose digital input/output pin.

O CKEOUT1 — SDRAM clock enable 1.

[1]

I/O P2[28] — General purpose digital input/output pin.

O DQMOUT0 — Data mask 0 used with SDRAM and static devices.

[1]

I/O P2[29] — General purpose digital input/output pin.

O DQMOUT1 — Data mask 1 used with SDRAM and static devices.

operation of port 3 pins depends upon the pin function selected via the Pin Connect block.

Pins P3[16:22] and P3[27:31] are not available.

[1]

I/O P3[0] — General purpose digital input/output pin.

I/O D0 — External memory data line 0.

[1]

I/O P3[1] — General purpose digital input/output pin.

I/O D1 — External memory data line 1.

[1]

I/O P3[2] — General purpose digital input/output pin.

I/O D2 — External memory data line 2.

[1]

I/O P3[3] — General purpose digital input/output pin.

I/O D3 — External memory data line 3.

[1]

I/O P3[4] — General purpose digital input/output pin.

I/O D4 — External memory data line 4.

[1]

I/O P3[5] — General purpose digital input/output pin.

I/O D5 — External memory data line 5.

[1]

I/O P3[6] — General purpose digital input/output pin.

I/O D6 — External memory data line 6.

[1]

I/O P3[7] — General purpose digital input/output pin.

I/O D7 — External memory data line 7.

[1]

I/O P3[8] — General purpose digital input/output pin.

I/O D8 — External memory data line 8.

[1]

I/O P3[9] — General purpose digital input/output pin.

I/O D9 — External memory data line 9.

[1]

I/O P3[10] — General purpose digital input/output pin.

I/O D10 — External memory data line 10.

[1]

I/O P3[11] — General purpose digital input/output pin.

I/O D11 — External memory data line 11.

P2[20]/DYCS0 P6

P2[21]/DYCS1

P2[24]/ CKEOUT0

P2[25]/ CKEOUT1

P2[28]/ DQMOUT0

P2[29]/ DQMOUT1

P3[0] to P3[31] I/O Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each bit. The

P3[0]/D0 D6

P3[1]/D1 E6

P3[2]/D2 A2

P3[3]/D3 G5

P3[4]/D4 D3

P3[5]/D5 E3

P3[6]/D6 F4

P3[7]/D7 G3

P3[8]/D8 A6

P3[9]/D9 A4

P3[10]/D10 B3

P3[11]/D11 B2

Product data sheet Rev. 4.2 — 15 October 2020 16 of 81

NXP Semiconductors

LPC2458

Single-chip 16-bit/32-bit micro

Table 4. Pin description …continued

Symbol Ball Type Description

[1]

I/O P3[12] — General purpose digital input/output pin.

I/O D12 — External memory data line 12.

[1]

I/O P3[13] — General purpose digital input/output pin.

I/O D13 — External memory data line 13.

[1]

I/O P3[14] — General purpose digital input/output pin.

I/O D14 — External memory data line 14.

[1]

I/O P3[15] — General purpose digital input/output pin.

I/O D15 — External memory data line 15.

[1]

I/O P3[23] — General purpose digital input/output pin.

I CAP0[0] — Capture input for Timer 0, channel 0.

I PCAP1[0] — Capture input for PWM1, channel 0.

[1]

I/O P3[24] — General purpose digital input/output pin.

I CAP0[1] — Capture input for Timer 0, channel 1.

O PWM1[1] — Pulse Width Modulator 1, output 1.

[1]

I/O P3[25] — General purpose digital input/output pin.

O MAT0[0] — Match output for Timer 0, channel 0.

O PWM1[2] — Pulse Width Modulator 1, output 2.

[1]

I/O P3[26] — General purpose digital input/output pin.

O MAT0[1] — Match output for Timer 0, channel 1.

O PWM1[3] — Pulse Width Modulator 1, output 3.

operation of port 4 pins depends upon the pin function selected via the Pin Connect block.

Pins P4[20:23] are not available.

[1]

I/O P4[0] — General purpose digital input/output pin.

I/O A0 — External memory address line 0.

[1]

I/O P4[1] — General purpose digital input/output pin.

I/O A1 — External memory address line 1.

[1]

I/O P4[2] — General purpose digital input/output pin.

I/O A2 — External memory address line 2.

[1]

I/O P4[3] — General purpose digital input/output pin.

I/O A3 — External memory address line 3.

[1]

I/O P4[4] — General purpose digital input/output pin.

I/O A4 — External memory address line 4.

[1]

I/O P4[5] — General purpose digital input/output pin.

I/O A5 — External memory address line 5.

[1]

I/O P4[6] — General purpose digital input/output pin.

I/O A6 — External memory address line 6.

[1]

I/O P4[7] — General purpose digital input/output pin.

I/O A7 — External memory address line 7.

P3[12]/D12 A1

P3[13]/D13 C1

P3[14]/D14 F1

P3[15]/D15 G4

P3[23]/CAP0[0]/ PCAP1[0]

P3[24]/CAP0[1]/ PWM1[1]

P3[25]/MAT0[0]/ PWM1[2]

P3[26]/MAT0[1]/ PWM1[3]

P4[0] to P4[31] I/O Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. The

P4[0]/A0 L6

P4[1]/A1 M7

P4[2]/A2 M8

P4[3]/A3 K9

P4[4]/A4 P13

P4[5]/A5 H10

P4[6]/A6 K10

P4[7]/A7 K12

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NXP Semiconductors

Table 4. Pin description …continued

Symbol Ball Type Description

K13

F14

D10

[1]

I/O P4[8] — General purpose digital input/output pin.

I/O A8 — External memory address line 8.

[1]

I/O P4[9] — General purpose digital input/output pin.

I/O A9 — External memory address line 9.

[1]

I/O P4[10] — General purpose digital input/output pin.

I/O A10 — External memory address line 10.

[1]

I/O P4[11] — General purpose digital input/output pin.

I/O A11 — External memory address line 11.

[1]

I/O P4[12] — General purpose digital input/output pin.

I/O A12 — External memory address line 12.

[1]

I/O P4[13] — General purpose digital input/output pin.

I/O A13 — External memory address line 13.

[1]

I/O P4[14] — General purpose digital input/output pin.

I/O A14 — External memory address line 14.

[1]

I/O P4[15] — General purpose digital input/output pin.

I/O A15 — External memory address line 15.

[1]

I/O P4[16] — General purpose digital input/output pin.

I/O A16 — External memory address line 16.

[1]

I/O P4[17] — General purpose digital input/output pin.

I/O A17 — External memory address line 17.

[1]

I/O P4[18] — General purpose digital input/output pin.

I/O A18 — External memory address line 18.

[1]

I/O P4[19] — General purpose digital input/output pin.

I/O A19 — External memory address line 19.

[1]

I/O P4[24] — General purpose digital input/output pin.

O OE

— LOW active Output Enable signal.

I/O P4[25] — General purpose digital input/output pin.

O WE

[1]

I/O P4[26] — General purpose digital input/output pin.

O BLS0

[1]

I/O P4[27] — General purpose digital input/output pin.

O BLS1

[1]

I/O P4[28] — General purpose digital input/output pin.

— LOW active Write Enable signal.

— LOW active Byte Lane select signal 0.

— LOW active Byte Lane select signal 1.

O MAT2[0] — Match output for Timer 2, channel 0.

O TXD3 — Transmitter output for UART3.

[1]

I/O P4[29] — General purpose digital input/output pin.

O MAT2[1] — Match output for Timer 2, channel 1.

I RXD3 — Receiver input for UART3.

[1]

I/O P4[30] — General purpose digital input/output pin.

O CS0

— LOW active Chip Select 0 signal.

P4[8]/A8 J11

P4[9]/A9 H12

P4[10]/A10 G12

P4[11]/A11 F11

P4[12]/A12 F10

P4[13]/A13 B14

P4[14]/A14 E8

P4[15]/A15 C10

P4[16]/A16 N12

P4[17]/A17 N13

P4[18]/A18 P14

P4[19]/A19 M14

P4[24]/OE

P4[25]/WE

P4[26]/BLS0

P4[27]/BLS1

P4[28]/MAT2[0]/ TXD3

P4[29]/MAT2[1]/ RXD3

P4[30]/CS0

LPC2458

Single-chip 16-bit/32-bit micro

Product data sheet Rev. 4.2 — 15 October 2020 18 of 81

NXP Semiconductors

Table 4. Pin description …continued

Symbol Ball Type Description

P4[31]/CS1 E7

ALARM H5

USB_D2N2I/OUSB_D2 — USB port 2 bidirectional D line.

DBGEN E5

TDO B1

TDI C3

TMS C2

TRST

TCK D2

RTCK C4

RSTOUT

RESET

XTAL1 L2

XTAL2 K4

RTCX1 J2

RTCX2 J3

SSIO

SSCORE

SSA

DD(3V3)

n.c. H1, L12,

DD(DCDC)(3V3)

[1]

[7]

I/O P4[31] — General purpose digital input/output pin.

O CS1

— LOW active Chip Select 1 signal.

O ALARM — RTC controlled output. This is a 1.8 V pin. It goes HIGH when a RTC

alarm is generated.

[1][8]

[1][9]

[1][8]

[1][9]

I DBGEN — JTAG interface control signal. Also used for boundary scan.

O TDO — Test Data Out for JTAG interface.

I TDI — Test Data In for JTAG interface.

I TMS — Test Mode Select for JTAG interface.

I TRST — Test Reset for JTAG interface.

I TCK — Test Clock for JTAG interface. This clock must be slower than 1⁄6 of the

CPU clock (CCLK) for the JTAG interface to operate.

[1][8]

I/O RTCK — JTAG interface control signal.

Note: LOW on this pin while RESET

is LOW enables ETM pins (P2[9:0]) to

operate as Trace port after reset.

H2 O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC2458 being in

Reset state.

[10]

I external reset input: A LOW on this pin resets the device, causing I/O ports and

peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant.

[7][11]

[7][12]

H4, P4,

I Input to the oscillator circuit and internal clock generator circuits.

O Output from the oscillator amplifier.

I Input to the RTC oscillator circuit.

O Output from the RTC oscillator circuit.

I ground: 0 V reference for the digital IO pins.

L9, L13, G13, D13, C11,

[13]

H3, L8, A10

[14]

E2, L4,

I ground: 0 V reference for the core.

[13]

I analog ground: 0 V reference. This should nominally be the same voltage as

SSIO/VSSCORE

, but should be isolated to minimize noise and error.

I 3.3 V supply voltage: This is the power supply voltage for the I/O ports.

K8, L11, J14, E12, E10,

[15]

I not connected pins: These pins must be left unconnected (floating).

[16]

G10

G1, N9,

[17]

I 3.3 V DC-to-DC converter supply voltage: This is the power supply for the

on-chip DC-to-DC converter.

LPC2458

Single-chip 16-bit/32-bit micro

Product data sheet Rev. 4.2 — 15 October 2020 19 of 81

NXP Semiconductors

LPC2458

Single-chip 16-bit/32-bit micro

Table 4. Pin description …continued

Symbol Ball Type Description

DDA

VREF G2

VBAT K1

[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.

[2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input,

digital section of the pad is disabled.

[3] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,

digital section of the pad is disabled.

[4] Open-drain 5 V tolerant digital I/O pad, compatible with I

functionality. When power is switched off, this pin connected to the I configuration applies to all functions on this pin.

[5] Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and

Low-speed mode only).

[6] 5 V tolerant pad with 10 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.

[7] Pad provides special analog functionality.

[8] This pin has a built-in pull-up resistor.

[9] This pin has no built-in pull-up and no built-in pull-down resistor.

[10] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.

[11] When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding

is preferred to reduce susceptibility to noise). XTAL2 should be left floating.

[12] If the RTC is not used, these pins can be left floating.

[13] Pad provides special analog functionality.

[14] Pad provides special analog functionality.

[15] Pad provides special analog functionality.

[16] Pad provides special analog functionality.

[17] Pad provides special analog functionality.

[18] Pad provides special analog functionality.

[18]

I analog 3.3 V pad supply voltage: This should be nominally the same voltage as

but should be isolated to minimize noise and error. This voltage is used

DD(3V3)

to power the ADC and DAC.

I ADC reference: This should be nominally the same voltage as V

DD(3V3)

but should be isolated to minimize noise and error. The level on this pin is used as a reference for ADC and DAC.

I RTC power supply: 3.3 V on this pin supplies the power to the RTC peripheral.

C-bus 400 kHz specification. It requires an external pull-up to provide output

C-bus is floating and does not disturb the I2C lines. Open-drain

7. Functional description

7.1 Architectural overview

The LPC2458 microcontroller consists of an ARM7TDMI-S CPU with emulation support, the ARM7 local bus for closely coupled, high-speed access to the majority of on-chip memory, the AMBA AHB interfacing to high-speed on-chip peripherals and external memory, and the AMBA APB for connection to other on-chip peripheral functions. The microcontroller permanently configures the ARM7TDMI-S processor for little-endian byte order.

The LPC2458 implements two AHB in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, includes the VIC, GPDMA controller, and EMC.

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The second AHB, referred to as AHB2, includes only the Ethernet block and an associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into off-chip memory or unused space in memory residing on AHB1.

In summary, bus masters with access to AHB1 are the ARM7 itself, the GPDMA function, and the Ethernet block (via the bus bridge from AHB2). Bus masters with access to AHB2 are the ARM7 and the Ethernet block.

AHB peripherals are allocated a 2 MB range of addresses at the very top of the 4 GB ARM memory space. Each AHB peripheral is allocated a 16 kB address space within the AHB address space. Lower speed peripheral functions are connected to the APB. The AHB to APB bridge interfaces the APB to the AHB. APB peripherals are also allocated a 2 MB range of addresses, beginning at the 3.5 GB address point. Each APB peripheral is allocated a 16 kB address space within the APB address space.

The ARM7TDMI-S processor is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed complex instruction set computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core.

LPC2458

Single-chip 16-bit/32-bit micro

Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue.

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets:

• the standard 32-bit ARM set

• a 16-bit Thumb set

The Thumb set’s 16-bit instruction length allows it to approach higher density compared to standard ARM code while retaining most of the ARM’s performance.

7.2 On-chip flash programming memory

The LPC2458 incorporates 512 kB flash memory system. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It may be programmed In System via the serial port (UART0). The application program may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field and firmware upgrades.

The flash memory is 128 bits wide and includes pre-fetching and buffering techniques to allow it to operate at speeds of 72 MHz.

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7.3 On-chip SRAM

The LPC2458 includes a SRAM memory of 64 kB reserved for the ARM processor exclusive use. This RAM may be used for code and/or data storage and may be accessed as 8 bits, 16 bits, and 32 bits.

A 16 kB SRAM block serving as a buffer for the Ethernet controller and a 16 kB SRAM associated with the second AHB can be used both for data and code storage. The 2 kB RTC SRAM can be used for data storage only. The RTC SRAM is battery powered and retains the content in the absence of the main power supply.

7.4 Memory map

The LPC2458 memory map incorporates several distinct regions as shown in Tab le 5 and

Figure 3.

In addition, the CPU interrupt vectors may be remapped to allow them to reside in either flash memory (default), boot ROM, or SRAM (see

Table 5. LPC2458 memory usage and details

Address range General use Address range details and description

0x0000 0000 to 0x3FFF FFFF

0x4000 0000 to 0x7FFF FFFF

0x8000 0000 to 0xBFFF FFFF

0xE000 0000 to 0xEFFF FFFF

0xF000 0000 to 0xFFFF FFFF

LPC2458

Single-chip 16-bit/32-bit micro

Section 7.26.6).

on-chip non-volatile memory and fast I/O

on-chip RAM 0x4000 0000 to 0x4000 FFFF RAM (64 kB)

off-chip memory two static memory banks, 1 MB each

APB peripherals 36 peripheral blocks, 16 kB each

AHB peripherals

0x0000 0000 to 0x0007 FFFF flash memory (512 kB)

0x3FFF C000 to 0x3FFF FFFF fast GPIO registers

0x7FE0 0000 to 0x7FE0 3FFF Ethernet RAM (16 kB)

0x7FD0 0000 to 0x7FD0 3FFF USB RAM (16 kB)

0x8000 0000 to 0x800F FFFF static memory bank 0

0x8100 0000 to 0x810F FFFF static memory bank 1

two dynamic memory banks, 256 MB each

0xA000 0000 to 0xAFFF FFFF dynamic memory bank 0

0xB000 0000 to 0xBFFF FFFF dynamic memory bank 1

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NXP Semiconductors

0.0 GB

1.0 GB

ON-CHIP NON-VOLATILE MEMORY

0x0000 0000

RESERVED ADDRESS SPACE

SPECIAL REGISTERS

ON-CHIP STATIC RAM

RESERVED ADDRESS SPACE

0x4000 0000

0x3FFF 8000

0x3FFF FFFF

2.0 GB 0x8000 0000 0x7FFF FFFF

BOOT ROM AND BOOT FLASH

(BOOT FLASH REMAPPED FROM ON-CHIP FLASH)

0xDFFF FFFF

0xC000 0000 0xBFFF FFFF

RESERVED ADDRESS SPACE

EXTERNAL STATIC AND DYNAMIC MEMORY

3.75 GB

4.0 GB

3.5 GB

AHB PERIPHERALS

APB PERIPHERALS

0xE000 0000

0xF000 0000

0xFFFF FFFF

002aad657

LPC2458

Single-chip 16-bit/32-bit micro

Fig 3. LPC2458 memory map

7.5 Interrupt controller

The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be programmed as FIQ or vectored IRQ types. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted.

FIQs have the highest priority. If more than one request is assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ

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NXP Semiconductors

service routine can simply start dealing with that device. But if more than one request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt.

Vectored IRQs, which include all interrupt requests that are not classified as FIQs, have a programmable interrupt priority. When more than one interrupt is assigned the same priority and occur simultaneously, the one connected to the lowest numbered VIC channel will be serviced first.

The VIC ORs the requests from all of the vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping to the address supplied by that register.

7.5.1 Interrupt sources

Each peripheral device has one interrupt line connected to the VIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source.

Any pin on port 0 and port 2 (total of 64 pins) regardless of the selected function, can be programmed to generate an interrupt on a rising edge, a falling edge, or both. Such interrupt request coming from port 0 and/or port 2 will be combined with the EINT3 interrupt requests.

LPC2458

Single-chip 16-bit/32-bit micro

7.6 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals.

Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined.

7.7 External memory controller

The LPC2458 EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM, and flash. In addition, it can be used as an interface with off-chip memory-mapped devices and peripherals. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant peripheral.

7.7.1 Features

• Dynamic memory interface support including single data rate SDRAM.

• Asynchronous static memory device support including RAM, ROM, and flash, with or

without asynchronous page mode.

• Low transaction latency.

• Read and write buffers to reduce latency and to improve performance.

• 8/16 data and 20 address lines wide static memory support.

• 16 bit wide chip select SDRAM memory support.

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NXP Semiconductors

• Static memory features include:

• Two chip selects for synchronous memory and two chip selects for static memory

• Power-saving modes dynamically control CKE and CLKOUT to SDRAMs.

• Dynamic memory self-refresh mode controlled by software.

• Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row

• Separate reset domains allow auto-refresh through a chip reset if desired.

Note: Synchronous static memory devices (synchronous burst mode) are not supported.

LPC2458

Single-chip 16-bit/32-bit micro

– Asynchronous page mode read

– Programmable Wait States

– Bus turnaround delay

– Output enable and write enable delays

– Extended wait

devices.

address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB parts, with 4, 8, and 16 data bits per device.

7.8 General purpose DMA controller

The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2458 peripherals to have DMA support.

The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For example, a bidirectional port requires one stream for transmit and one for receive. The source and destination areas can each be either a memory region or a peripheral, and can be accessed through the AHB master.

7.8.1 Features

• Two DMA channels. Each channel can support a unidirectional transfer.

• The GPDMA can transfer data between the 16 kB SRAM, external memory, and

peripherals such as the SD/MMC, two SSPs, and the I

• Single DMA and burst DMA request signals. Each peripheral connected to the

GPDMA can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the GPDMA.

• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and

peripheral-to-peripheral transfers.

• Scatter or gather DMA is supported through the use of linked lists. This means that

the source and destination areas do not have to occupy contiguous areas of memory.

• Hardware DMA channel priority. Each DMA channel has a specific hardware priority.

DMA channel 0 has the highest priority and channel 1 has the lowest priority. If requests from two channels become active at the same time, the channel with the highest priority is serviced first.

• AHB slave DMA programming interface. The GPDMA is programmed by writing to the

DMA control registers over the AHB slave interface.

S interface.

Product data sheet Rev. 4.2 — 15 October 2020 25 of 81

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