NXP LPC2458 data sheet

LPC2458

Single-chip 16-bit/32-bit micro; 512 kB flash, Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interface

Rev. 4.2 — 15 October 2020 Product data sheet

1. General description

NXP Semiconductors designed the LPC2458 microcontroller around a 16-bit/32-bit ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and embedded trace. The LPC2458 has 512 kB of on-chip high-speed flash memory. This flash memory includes a special 128-bit wide memory interface and accelerator architecture that enables the CPU to execute sequential instructions from flash memory at the maximum 72 MHz system clock rate. This feature is available only on the LPC2000 ARM microcontroller family of products. The LPC2458 can execute both 32-bit ARM and 16-bit Thumb instructions. Support for the two instruction sets means engineers can choose to optimize their application for either performance or code size at the sub-routine level. When the core executes instructions in Thumb state it can reduce code size by more than 30 % with only a small loss in performance while executing instructions in ARM state maximizes core performance.

The LPC2458 microcontroller is ideal for multi-purpose communication applications. It incorporates a 10/100 Ethernet Media Access Controller (MAC), a USB full-speed Device/Host/OTG Controller with 4 kB of endpoint RAM, four UARTs, two Controller Area Network (CAN) channels, an SPI interface, two Synchronous Serial Ports (SSP), three I interfaces, and an I interfaces are the following feature components; an on-chip 4 MHz internal precision oscillator, 98 kB of total RAM consisting of 64 kB of local SRAM, 16 kB SRAM for Ethernet, 16 kB SRAM for general purpose DMA, 2 kB of battery powered SRAM, and an External Memory Controller (EMC). These features make this device optimally suited for communication gateways and protocol converters. Complementing the many serial communication controllers, versatile clocking capabilities, and memory features are various 32-bit timers, an improved 10-bit ADC, 10-bit DAC, two PWM units, four external interrupt pins, and up to 136 fast GPIO lines. The LPC2458 connects 64 of the GPIO pins to the hardware based Vector Interrupt Controller (VIC) that means these external inputs can generate edge-triggered interrupts. All of these features make the LPC2458 particularly suitable for industrial control and medical systems.

2. Features and benefits

 ARM7TDMI-S processor, running at up to 72 MHz.  512 kB on-chip flash program memory with In-System Programming (ISP) and

In-Application Programming (IAP) capabilities. Flash program memory is on the ARM local bus for high performance CPU access.

 98 kB on-chip SRAM includes:

 64 kB of SRAM on the ARM local bus for high performance CPU access.  16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.

S interface. Supporting this collection of serial communications

NXP Semiconductors

Single-chip 16-bit/32-bit micro

 16 kB SRAM for general purpose DMA use also accessible by the USB.  2 kB SRAM data storage powered from the Real-Time Clock (RTC) power domain.

 Dual Advanced High-performance Bus (AHB) system allows simultaneous Ethernet

DMA, USB DMA, and program execution from on-chip flash with no contention.

 EMC provides support for asynchronous static memory devices such as RAM, ROM

and flash, as well as dynamic memories such as Single Data Rate SDRAM.

 Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.  General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP,

S, and SD/MM interface as well as for memory-to-memory transfers.

 Serial Interfaces:

 Ethernet MAC with MII/RMII interface and associated DMA controller. These

functions reside on an independent AHB.

 USB 2.0 full-speed dual port Device/Host/OTG Controller with on-chip PHY and

associated DMA controller.

 Four UARTs with fractional baud rate generation, one with modem control I/O, one

with IrDA support, all with FIFO.

 CAN controller with two channels.  SPI controller.  Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate

for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA controller.

 Three I2C-bus interfaces (one with open-drain and two with standard port pins).  I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with

the GPDMA.

 Other peripherals:

 SD/MMC memory card interface.  136 General purpose I/O pins with configurable pull-up/down resistors.  10-bit ADC with input multiplexing among 8 pins.  10-bit DAC.  Four general purpose timers/counters with 8 capture inputs and 10 compare

outputs. Each timer block has an external count input.

 Two PWM/timer blocks with support for three-phase motor control. Each PWM has

an external count inputs.

 RTC with separate power domain, clock source can be the RTC oscillator or the

APB clock.

 2 kB SRAM powered from the RTC power pin, allowing data to be stored when the

rest of the chip is powered off.

 WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,

the RTC oscillator, or the APB clock.

 Standard ARM test/debug interface for compatibility with existing tools.  Emulation trace module supports real-time trace.  Single 3.3 V power supply (3.0 V to 3.6 V).  Four reduced power modes: idle, sleep, power-down, and deep power-down.  Four external interrupt inputs configurable as edge/level sensitive. All pins on port 0

and port 2 can be used as edge sensitive interrupt sources.

 Processor wake-up from Power-down mode via any interrupt able to operate during

Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt, CAN bus activity, port 0/2 pin interrupt).

Product data sheet Rev. 4.2 — 15 October 2020 2 of 81

LPC2458

NXP Semiconductors

 Two independent power domains allow fine tuning of power consumption based on

 Each peripheral has its own clock divider for further power saving. These dividers help

 Brownout detect with separate thresholds for interrupt and forced reset.  On-chip power-on reset.  On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.  4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as

 On-chip PLL allows CPU operation up to the maximum CPU rate without the need for

 Boundary scan for simplified board testing.  Versatile pin function selections allow more possibilities for using on-chip peripheral

3. Applications

LPC2458

Single-chip 16-bit/32-bit micro

needed features.

reduce active power by 20 % to 30 %.

the system clock. When used as the CPU clock, does not allow CAN and USB to run.

a high frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator.

functions.

 Industrial control  Medical systems  Protocol converter  Communications

4. Ordering information

Table 1. Ordering information

Typ e n u mber Package

LPC2458FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12  12  0.8 mm SOT570-3

Table 2. Ordering options

Typ e n u mber Flash

LPC2458FET180 512 64 16 16 2 98 16-bit MII/

Name Description Version

4.1 Ordering options

(kB)

SRAM (kB) External

bus

Local bus

Ethernet buffer

GP/USB

RTC

Tot al

Ethernet USB

OTG/ OHC/ DEV +4kB FIFO

yes 2 yes yes 8 1 40 C to

RMII

CAN channels

SD/ MMC

GP DMA

Tem p range

ADC channels

DAC channels

+85 C

Product data sheet Rev. 4.2 — 15 October 2020 3 of 81

NXP Semiconductors

power domain 2

LPC2458

A[19:0]

D[15:0]

EXTERNAL

MEMORY

CONTROLLER

ALARM

002aad093

PWM0, PWM1

ARM7TDMI-S

PLL

EINT3 to EINT0

FLASH

P3, P4

P0, P1, P2,

LEGACY GPI/O 64 PINS TOTAL

P0, P1

SCK, SCK0 MOSI, MOSI0

SSEL, SSEL0 SCK1

MOSI1 MISO1

SSEL1

SCL0, SCL1, SCL2

I2SRX_CLK I2STX_CLK I2SRX_WS I2STX_WS

8 × AD0

RTCX1 RTCX2

MCICLK, MCIPWR

RXD0, RXD2, RXD3

TXD1 RXD1

RD1, RD2 TD1, TD2

CAN1, CAN2

port 1

XTAL1

TCK TDO

EXTIN0

XTAL2

RESET

TRST

TDITMS

HIGH-SPEED

GPIO

136 PINS

TOTAL

port 2

64 kB

SRAM

512 kB

FLASH

INTERNAL

CONTROLLERS

TEST/DEBUG

INTERFACE

EMULATION

TRACE MODULE

trace signals

AHB

BRIDGE

AHB

BRIDGE

ETHERNET

MAC WITH

DMA

16 kB

SRAM

MASTER

PORT

AHB TO

AHB BRIDGE

SLAVE

PORT

system

clock

SYSTEM

FUNCTIONS

INTERNAL RC

OSCILLATOR

DDA

DD(3V3)

DD(DCDC)(3V3)

VREF V

SSA

, V

SSIO, VSSCORE

VIC

16 kB

SRAM

USB DEVICE/

HOST/OTG WITH

4 kB RAM AND DMA

GPDMA

CONTROLLER

I2S INTERFACE

SPI, SSP0 INTERFACE

I2SRX_SDA I2STX_SDA

MISO, MISO0

SSP1 INTERFACE

SD/MMC CARD

INTERFACE

MCICMD, MCIDAT[3:0]

TXD0, TXD2, TXD3

UART0, UART2, UART3

UART1

DTR1, RTS1 DSR1, CTS1, DCD1,

RI1

C0, I2C1, I2C2

SDA0, SDA1, SDA2

EXTERNAL INTERRUPTS

CAPTURE/COMPARE

TIMER0/TIMER1/

TIMER2/TIMER3

A/D CONVERTER

D/A CONVERTER

2 kB BATTERY RAM

RTC

OSCILLATOR

REAL-

TIME

CLOCK

WATCHDOG TIMER

SYSTEM CONTROL

2 × CAP0/CAP1/

CAP2/CAP3

4 × MAT2,

2 × MAT3,

2 × MAT1/MAT0

6 × PWM0, PWM1

1 × PCAP0,

2 × PCAP1

AOUT

VBAT

AHB TO

APB BRIDGE

SRAM

MII/RMII

BUS

DBGEN

P0, P2

AHB2

AHB1

control lines

5. Block diagram

LPC2458

Single-chip 16-bit/32-bit micro

Product data sheet Rev. 4.2 — 15 October 2020 4 of 81

Fig 1. LPC2458 block diagram

NXP Semiconductors

002aad094

LPC2458

2 4 6 8 10 12 13141357911

ball A1 index area

Transparent top view

6. Pinning information

6.1 Pinning

LPC2458

Single-chip 16-bit/32-bit micro

Fig 2. LPC2458 pinning TFBGA180 package

Table 3. Pin allocation table

Pin Symbol Pin Symbol Pin Symbol Pin Symbol

Row A

1 P3[12]/D12 2 P3[2]/D2 3 P0[3]/RXD0 4 P3[9]/D9

5 P1[1]/ENET_TXD1 6 P3[8]/D8 7 P1[10]/ENET_RXD1 8 P1[15]/

ENET_REF_CLK/ ENET_RX_CLK

9 P1[3]/ENET_TXD3/

MCICMD/PWM0[2]

13 P0[9]/I2STX_SDA/

MOSI1/MAT2[3]

10 V

SSCORE

14 P1[12]/ENET_RXD3/

MCIDAT3/PCAP0[0]

11 P0[4]/I2SRX_CLK/RD2/

CAP2[0]

15 - 16 -

12 P1[11]/ENET_RXD2/

MCIDAT2/PWM0[6]

Row B

1 TDO 2 P3[11]/D11 3 P3[10]/D10 4 V

5 P1[0]/ENET_TXD0 6 P1[8]/ENET_CRS_DV/

ENET_CRS

9 P4[29]/

13 P1[5]/ENET_TX_ER/

MAT2[1]/RXD3

10 P1[6]/ENET_TX_CLK/

MCIDAT0/PWM0[4]

14 P4[13]/A13 15 - 16 -

7 P1[2]/ENET_TXD2/

MCICLK/PWM0[1]

11 P0[5]/I2SRX_WS/TD2/

CAP2[1]

SSIO

8 P1[16]/ENET_MDC

12 P0[7]/I2STX_CLK/SCK1

/MAT2[1]

MCIPWR/PWM0[3]

Row C

1 P3[13]/D13 2 TMS 3 TDI 4 RTCK

DD(3V3)

9 P1[17]/ENET_MDIO 10 P4[15]/A15 11 V

6 P1[4]/ENET_TX_EN 7 P4[30]/CS0 8 P4[24]/OE

SSIO

12 P0[8]/I2STX_WS/

MISO1/MAT2[2]

Product data sheet Rev. 4.2 — 15 October 2020 5 of 81

NXP Semiconductors

LPC2458

Single-chip 16-bit/32-bit micro

Table 3. Pin allocation table …continued

Pin Symbol Pin Symbol Pin Symbol Pin Symbol

13 P1[7]/ENET_COL/

MCIDAT1/PWM0[5]

Row D

1 P0[26]/AD0[3]/

AOUT/RXD3

5 P0[2]/TXD0 6 P3[0]/D0 7 P1[9]/ENET_RXD0 8 P1[14]/ENET_RX_ER

9 P4[25]/WE

13 V

SSIO

Row E

1 P0[24]/AD0[1]/

I2SRX_WS/CAP3[1]

5 DBGEN 6 P3[1]/D1 7 P4[31]/CS1

DD(DCDC)(3V3)

13 P2[3]/PWM1[4]/

DCD1/PIPESTAT2

Row F

1 P3[14]/D14 2 V

5 P0[23]/AD0[0]/

I2SRX_CLK/CAP3[0]

9 10 P4[12]/A12 11 P4[11]/A11 12 P2[5]/PWM1[6]/

13 P2[6]/PCAP1[0]/

RI1/TRACEPKT1

Row G

DD(DCDC)(3V3)

5 P3[3]/D3 6 7 8

9 10 n.c. 11 P2[7]/RD2/

13 V

SSIO

Row H

1 n.c. 2 RSTOUT 3V

5ALARM 6 7 8

9 10 P4[5]/A5 11 P2[9]/

13 P0[15]/TXD1/

SCK0/SCK

Row J

1 RESET 2 RTCX1 3 RTCX2 4 P0[12]/USB_PPWR2/

5 P0[13]/USB_UP_LED2/

MOSI1/AD0[7]

14 P2[1]/PWM1[2]/RXD1/

15 - 16 -

PIPESTAT0

2 TCK 3 P3[4]/D4 4 TRST

10 P4[28]/

MAT2[0]/TXD3

11 P0[6]/I2SRX_SDA/

SSEL1/MAT2[0]

12 P2[0]/PWM1[1]/TXD1/

TRACECLK

14 P1[13]/ENET_RX_DV 15 - 16 -

DD(3V3)

3 P3[5]/D5 4 P0[25]/AD0[2]/

I2SRX_SDA/TXD3

8 P4[14]/A14

10 V

DD(3V3)

11 P2[2]/PWM1[3]/

12 V

DD(3V3)

CTS1/PIPESTAT1

14 P2[4]/PWM1[5]/

15 - 16 -

DSR1/TRACESYNC

DDA

SSA

4 P3[6]/D6

678

DTR1/TRACEPKT0

14 P4[27]/BLS1

15 - 16 -

2 VREF 3 P3[7]/D7 4 P3[15]/D15

12 P4[10]/A10

RTS1/TRACEPKT2

14 P2[8]/TD2/

15 - 16 -

TXD2/TRACEPKT3

SSCORE

SSIO

12 P4[9]/A9 USB_CONNECT1/ RXD2/EXTIN0

14 P0[16]/RXD1/

15 - 16 -

SSEL0/SSEL

MISO1/AD0[6]

678

Product data sheet Rev. 4.2 — 15 October 2020 6 of 81

NXP Semiconductors

LPC2458

Single-chip 16-bit/32-bit micro

Table 3. Pin allocation table …continued

Pin Symbol Pin Symbol Pin Symbol Pin Symbol

9 10 P0[19]/DSR1/

MCICLK/SDA1

13 P0[18]/DCD1/

14 V

DD(3V3)

MOSI0/MOSI

Row K

1 VBAT 2 P1[31]/USB_OVRCR2/

SCK1/AD0[5]

5 P0[29]/USB_D+1 6 P1[20]/USB_TX_DP1/

PWM1[2]/SCK0

9 P4[3]/A3 10 P4[6]/A6 11 P0[21]/RI1/

13 P4[26]/BLS0

14 P0[20]/DTR1/

MCICMD/SCL1

Row L

1 P2[29]/DQMOUT1 2 XTAL1 3 P0[27]/SDA0 4 V

5 P1[18]/USB_UP_LED1/

6 P4[0]/A0 7 P1[25]/USB_LS1/

PWM1[1]/CAP1[0]

SSIO

10 P0[10]/TXD2/SDA2/

MAT3[0]

13 V

SSIO

14 P0[22]/RTS1/

MCIDAT0/TD1

Row M

1 P0[28]/SCL0 2 P2[28]/DQMOUT0 3 P3[25]/MAT0[0]/

5 P0[14]/USB_HSTEN2

USB_CONNECT2/

6 P1[22]/USB_RCV1/

USB_PWRD1/MAT1[0]

SSEL1

9 P1[27]/USB_INT1

10 P0[0]/RD1/TXD3/SDA1 11 P2[13]/EINT3/

USB_OVRCR1/CAP0[1]

13 P2[10]/EINT0

14 P4[19]/A19 15 - 16 -

Row N

1 P0[31]/USB_D+2 2 USB_D2 3 P3[24]/CAP0[1]/

5 P2[19]/CLKOUT1 6 P1[21]/USB_TX_DM1/

PWM1[3]/SSEL0

DD(DCDC)(3V3)

10 P1[29]/USB_SDA1/

PCAP1[1]/MAT0[1]

13 P4[17]/A17 14 P2[12]/EINT2

MCIDAT2/I2STX_WS

Row P

1 P2[24]/CKEOUT0 2 P2[25]/CKEOUT1 3 P2[18]/CLKOUT0 4 V

5 P1[19]/USB_TX_E1/

USB_PPWR1

/CAP1[1]

9 P2[16]/CAS

6 P2[20]/DYCS0

10 P1[28]/USB_SCL1/

PCAP1[0]/MAT0[0]

13 P4[4]/A4 14 P4[18]/A18 15 - 16 -

11 P4[8]/A8 12 P0[17]/CTS1/

MISO0/MISO

15 - 16 -

3 P1[30]/USB_PWRD2/

/AD0[4]

BUS

7 P3[26]/MAT0[1]/

4XTAL2

DD(3V3)

PWM1[3]

12 P4[7]/A7 MCIPWR/RD1

15 - 16 -

DD(3V3)

8V USB_HSTEN1

11 V

DD(3V3)

/MAT1[1]

SSCORE

12 n.c.

15 - 16 -

4 P3[23]/CAP0[0]/ PWM1[2]

PCAP1[0]

7 P4[1]/A1 8 P4[2]/A2

12 P2[11]/EINT1/ MCIDAT3/I2STX_SDA

MCIDAT1/I2STX_CLK

4 P0[30]/USB_D1 PWM1[1]

7 P1[23]/USB_RX_DP1/

8 P2[21]/DYCS1 PWM1[4]/MISO0

11 P0[1]/TD1/RXD3/SCL1 12 P4[16]/A16

15 - 16 -

SSIO

7 P1[24]/USB_RX_DM1/

PWM1[5]/MOSI0

8 P1[26]/USB_SSPND1/

PWM1[6]/CAP0[0]

11 P2[17]/RAS 12 P0[11]/RXD2/SCL2/

MAT3[1]

Product data sheet Rev. 4.2 — 15 October 2020 7 of 81

NXP Semiconductors

LPC2458

Single-chip 16-bit/32-bit micro

6.2 Pin description

M10

N11

A11

B11

D11

B12

C12

operation of port 0 pins depends upon the pin function selected via the Pin Connect block.

[1]

I/O P0[0] — General purpose digital input/output pin.

I RD1 — CAN1 receiver input.

O TXD3 — Transmitter output for UART3.

I/O SDA1 — I

[1]

I/O P0[1] — General purpose digital input/output pin.

C1 data input/output (this is not an open-drain pin).

O TD1 — CAN1 transmitter output.

I RXD3 — Receiver input for UART3.

I/O SCL1 — I

[1]

I/O P0[2] — General purpose digital input/output pin.

C1 clock input/output (this is not an open-drain pin).

O TXD0 — Transmitter output for UART0.

[1]

I/O P0[3] — General purpose digital input/output pin.

I RXD0 — Receiver input for UART0.

[1]

I/O P0[4] — General purpose digital input/output pin.

I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the

slave. Corresponds to the signal SCK in the I

S-bus specification.

I RD2 — CAN2 receiver input.

I CAP2[0] — Capture input for Timer 2, channel 0.

[1]

I/O P0[5] — General purpose digital input/output pin.

I/O I2SRX_WS — Receive Word Select. It is driven by the master and received by

the slave. Corresponds to the signal WS in the I

S-bus specification.

O TD2 — CAN2 transmitter output.

I CAP2[1] — Capture input for Timer 2, channel 1.

[1]

I/O P0[6] — General purpose digital input/output pin.

I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the

receiver. Corresponds to the signal SD in the I

S-bus specification.

I/O SSEL1 — Slave Select for SSP1.

O MAT2[0] — Match output for Timer 2, channel 0.

[1]

I/O P0[7] — General purpose digital input/output pin.

I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the

slave. Corresponds to the signal SCK in the I

S-bus specification.

I/O SCK1 — Serial Clock for SSP1.

O MAT2[1] — Match output for Timer 2, channel 1.

[1]

I/O P0[8] — General purpose digital input/output pin.

I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by

the slave. Corresponds to the signal WS in the I

S-bus specification.

I/O MISO1 — Master In Slave Out for SSP1.

O MAT2[2] — Match output for Timer 2, channel 2.

Table 4. Pin description

Symbol Ball Type Description

P0[0] to P0[31] I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The

P0[0]/RD1/ TXD3/SDA1

P0[1]/TD1/RXD3/ SCL1

P0[2]/TXD0 D5

P0[3]/RXD0 A3

P0[4]/ I2SRX_CLK/ RD2/CAP2[0]

P0[5]/ I2SRX_WS/ TD2/CAP2[1]

P0[6]/ I2SRX_SDA/ SSEL1/MAT2[0]

P0[7]/ I2STX_CLK/ SCK1/MAT2[1]

P0[8]/ I2STX_WS/ MISO1/MAT2[2]

Product data sheet Rev. 4.2 — 15 October 2020 8 of 81

NXP Semiconductors

Table 4. Pin description …continued

Symbol Ball Type Description

P0[9]/ I2STX_SDA/ MOSI1/MAT2[3]

P0[10]/TXD2/ SDA2/MAT3[0]

P0[11]/RXD2/ SCL2/MAT3[1]

P0[12]/ USB_PPWR2

MISO1/AD0[6]

P0[13]/ USB_UP_LED2/ MOSI1/AD0[7]

P0[14]/ USB_HSTEN2

/ USB_CONNECT2/ SSEL1

P0[15]/TXD1/ SCK0/SCK

P0[16]/RXD1/ SSEL0/SSEL

A13

L10

P12

H13

H14

[1]

I/O P0[9] — General purpose digital input/output pin.

I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the

receiver. Corresponds to the signal SD in the I

I/O MOSI1 — Master Out Slave In for SSP1.

O MAT2[3] — Match output for Timer 2, channel 3.

[1]

I/O P0[10] — General purpose digital input/output pin.

O TXD2 — Transmitter output for UART2.

I/O SDA2 — I

O MAT3[0] — Match output for Timer 3, channel 0.

[1]

I/O P0[11] — General purpose digital input/output pin.

I RXD2 — Receiver input for UART2.

I/O SCL2 — I

O MAT3[1] — Match output for Timer 3, channel 1.

[2]

I/O P0[12] — General purpose digital input/output pin.

O USB_PPWR2

I/O MISO1 — Master In Slave Out for SSP1.

I AD0[6] — A/D converter 0, input 6.

[2]

I/O P0[13] — General purpose digital input/output pin.

O USB_UP_LED2 — USB port 2 GoodLink LED indicator. It is LOW when device is

configured (non-control endpoints enabled), or when host is enabled and has detected a device on the bus. It is HIGH when the device is not configured, or when host is enabled and has not detected a device on the bus, or during global suspend. It transitions between LOW and HIGH (flashes) when host is enabled and detects activity on the bus.

I/O MOSI1 — Master Out Slave In for SSP1.

I AD0[7] — A/D converter 0, input 7.

[1]

I/O P0[14] — General purpose digital input/output pin.

O USB_HSTEN2

O USB_CONNECT2 — SoftConnect control for USB port 2. Signal used to switch

an external 1.5 k resistor under software control. Used with the SoftConnect USB feature.

I/O SSEL1 — Slave Select for SSP1.

[1]

I/O P0[15] — General purpose digital input/output pin.

O TXD1 — Transmitter output for UART1.

I/O SCK0 — Serial clock for SSP0.

I/O SCK — Serial clock for SPI.

[1]

I/O P0[16] — General purpose digital input/output pin.

I RXD1 — Receiver input for UART1.

I/O SSEL0 — Slave Select for SSP0.

I/O SSEL — Slave Select for SPI.

Single-chip 16-bit/32-bit micro

S-bus specification.

C2 data input/output (this is not an open-drain pin).

C2 clock input/output (this is not an open-drain pin).

— Port Power enable signal for USB port 2.

— Host Enabled status for USB port 2.

LPC2458

Product data sheet Rev. 4.2 — 15 October 2020 9 of 81

NXP Semiconductors

Table 4. Pin description …continued

Symbol Ball Type Description

P0[17]/CTS1/ MISO0/MISO

P0[18]/DCD1/ MOSI0/MOSI

P0[19]/DSR1/ MCICLK/SDA1

P0[20]/DTR1/ MCICMD/SCL1

P0[21]/RI1/ MCIPWR/RD1

P0[22]/RTS1/ MCIDAT0/TD1

P0[23]/AD0[0]/ I2SRX_CLK/ CAP3[0]

P0[24]/AD0[1]/ I2SRX_WS/ CAP3[1]

P0[25]/AD0[2]/ I2SRX_SDA/ TXD3

J12

J13

J10

K14

K11

L14

[1]

I/O P0[17] — General purpose digital input/output pin.

I CTS1 — Clear to Send input for UART1.

I/O MISO0 — Master In Slave Out for SSP0.

I/O MISO — Master In Slave Out for SPI.

[1]

I/O P0[18] — General purpose digital input/output pin.

I DCD1 — Data Carrier Detect input for UART1.

I/O MOSI0 — Master Out Slave In for SSP0.

I/O MOSI — Master Out Slave In for SPI.

[1]

I/O P0[19] — General purpose digital input/output pin.

I DSR1 — Data Set Ready input for UART1.

O MCICLK — Clock output line for SD/MMC interface.

I/O SDA1 — I

[1]

I/O P0[20] — General purpose digital input/output pin.

O DTR1 — Data Terminal Ready output for UART1.

I/O MCICMD — Command line for SD/MMC interface.

I/O SCL1 — I

[1]

I/O P0[21] — General purpose digital input/output pin.

I RI1 — Ring Indicator input for UART1.

O MCIPWR — Power Supply Enable for external SD/MMC power supply.

I RD1 — CAN1 receiver input.

[1]

I/O P0[22] — General purpose digital input/output pin.

O RTS1 — Request to Send output for UART1.

I/O MCIDAT0 — Data line 0 for SD/MMC interface.

O TD1 — CAN1 transmitter output.

[2]

I/O P0[23] — General purpose digital input/output pin.

I AD0[0] — A/D converter 0, input 0.

I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the

slave. Corresponds to the signal SCK in the I

I CAP3[0] — Capture input for Timer 3, channel 0.

[2]

I/O P0[24] — General purpose digital input/output pin.

I AD0[1] — A/D converter 0, input 1.

I/O I2SRX_WS — Receive Word Select. It is driven by the master and received by

the slave. Corresponds to the signal WS in the I

I CAP3[1] — Capture input for Timer 3, channel 1.

[2]

I/O P0[25] — General purpose digital input/output pin.

I AD0[2] — A/D converter 0, input 2.

I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the

receiver. Corresponds to the signal SD in the I

O TXD3 — Transmitter output for UART3.

Single-chip 16-bit/32-bit micro

C1 data input/output (this is not an open-drain pin).

C1 clock input/output (this is not an open-drain pin).

S-bus specification.

LPC2458

Product data sheet Rev. 4.2 — 15 October 2020 10 of 81

NXP Semiconductors

LPC2458

Single-chip 16-bit/32-bit micro

Table 4. Pin description …continued

Symbol Ball Type Description

P0[26]/AD0[3]/ AOUT/RXD3

P0[27]/SDA0 L3

P0[28]/SCL0 M1

P0[29]/USB_D+1 K5

P0[30]/USB_D1N4

P0[31]/USB_D+2 N1

P1[0] to P1[31] I/O Port 1: Port 1 is a 32 bit I/O port with individual direction controls for each bit. The

P1[0]/ ENET_TXD0

P1[1]/ ENET_TXD1

P1[2]/ ENET_TXD2/ MCICLK/ PWM0[1]

P1[3]/ ENET_TXD3/ MCICMD/ PWM0[2]

P1[4]/ ENET_TX_EN

P1[5]/ ENET_TX_ER/ MCIPWR/ PWM0[3]

P1[6]/ ENET_TX_CLK/ MCIDAT0/ PWM0[4]

B13

B10

[2][3]

[4]

[5]

[1]

I/O P0[26] — General purpose digital input/output pin.

I AD0[3] — A/D converter 0, input 3.

O AOUT — D/A converter output.

I RXD3 — Receiver input for UART3.

I/O P0[27] — General purpose digital input/output pin. Output is open-drain.

I/O SDA0 — I

C0 data input/output. Open-drain output (for I2C-bus compliance).

I/O P0[28] — General purpose digital input/output pin. Output is open-drain.

I/O SCL0 — I

C0 clock input/output. Open-drain output (for I2C-bus compliance).

I/O P0[29] — General purpose digital input/output pin.

I/O USB_D+1 — USB port 1 bidirectional D+ line.

I/O P0[30] — General purpose digital input/output pin.

I/O USB_D1 — USB port 1 bidirectional D line.

I/O P0[31] — General purpose digital input/output pin.

I/O USB_D+2 — USB port 2 bidirectional D+ line.

operation of port 1 pins depends upon the pin function selected via the Pin Connect block.

I/O P1[0] — General purpose digital input/output pin.

O ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface).

I/O P1[1] — General purpose digital input/output pin.

O ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface).

I/O P1[2] — General purpose digital input/output pin.

O ENET_TXD2 — Ethernet transmit data 2 (MII interface).

O MCICLK — Clock output line for SD/MMC interface.

O PWM0[1] — Pulse Width Modulator 0, output 1.

I/O P1[3] — General purpose digital input/output pin.

O ENET_TXD3 — Ethernet transmit data 3 (MII interface).

I/O MCICMD — Command line for SD/MMC interface.

O PWM0[2] — Pulse Width Modulator 0, output 2.

I/O P1[4] — General purpose digital input/output pin.

O ENET_TX_EN — Ethernet transmit data enable (RMII/MII interface).

[1]

I/O P1[5] — General purpose digital input/output pin.

O ENET_TX_ER — Ethernet Transmit Error (MII interface).

O MCIPWR — Power Supply Enable for external SD/MMC power supply.

O PWM0[3] — Pulse Width Modulator 0, output 3.

[1]

I/O P1[6] — General purpose digital input/output pin.

I ENET_TX_CLK — Ethernet Transmit Clock (MII interface).

I/O MCIDAT0 — Data line 0 for SD/MMC interface.

O PWM0[4] — Pulse Width Modulator 0, output 4.

Product data sheet Rev. 4.2 — 15 October 2020 11 of 81

NXP Semiconductors

Table 4. Pin description …continued

Symbol Ball Type Description

P1[7]/ ENET_COL/ MCIDAT1/ PWM0[5]

P1[8]/ ENET_CRS_DV/ ENET_CRS

P1[9]/ ENET_RXD0

P1[10]/ ENET_RXD1

P1[11]/ ENET_RXD2/ MCIDAT2/ PWM0[6]

P1[12]/ ENET_RXD3/ MCIDAT3/ PCAP0[0]

P1[13]/ ENET_RX_DV

P1[14]/ ENET_RX_ER

P1[15]/ ENET_REF_CLK/ ENET_RX_CLK

P1[16]/ ENET_MDC

P1[17]/ ENET_MDIO

P1[18]/ USB_UP_LED1/ PWM1[1]/ CAP1[0]

P1[19]/ USB_TX_E1 USB_PPWR1

CAP1[1]

C13

A12

A14

D14

[1]

I/O P1[7] — General purpose digital input/output pin.

I ENET_COL — Ethernet Collision detect (MII interface).

I/O MCIDAT1 — Data line 1 for SD/MMC interface.

O PWM0[5] — Pulse Width Modulator 0, output 5.

[1]

I/O P1[8] — General purpose digital input/output pin.

I ENET_CRS_DV/ENET_CRS — Ethernet Carrier Sense/Data Valid (RMII

interface)/ Ethernet Carrier Sense (MII interface).

[1]

I/O P1[9] — General purpose digital input/output pin.

I ENET_RXD0 — Ethernet receive data 0 (RMII/MII interface).

[1]

I/O P1[10] — General purpose digital input/output pin.

I ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface).

[1]

I/O P1[11] — General purpose digital input/output pin.

I ENET_RXD2 — Ethernet Receive Data 2 (MII interface).

I/O MCIDAT2 — Data line 2 for SD/MMC interface.

O PWM0[6] — Pulse Width Modulator 0, output 6.

[1]

I/O P1[12] — General purpose digital input/output pin.

I ENET_RXD3 — Ethernet Receive Data (MII interface).

I/O MCIDAT3 — Data line 3 for SD/MMC interface.

I PCAP0[0] — Capture input for PWM0, channel 0.

[1]

I/O P1[13] — General purpose digital input/output pin.

I ENET_RX_DV — Ethernet Receive Data Valid (MII interface).

[1]

I/O P1[14] — General purpose digital input/output pin.

I ENET_RX_ER — Ethernet receive error (RMII/MII interface).

[1]

I/O P1[15] — General purpose digital input/output pin.

I ENET_REF_CLK/ENET_RX_CLK — Ethernet Reference Clock (RMII interface)/

Ethernet Receive Clock (MII interface).

[1]

I/O P1[16] — General purpose digital input/output pin.

O ENET_MDC — Ethernet MIIM clock.

[1]

I/O P1[17] — General purpose digital input/output pin.

I/O ENET_MDIO — Ethernet MI data input and output.

[1]

I/O P1[18] — General purpose digital input/output pin.

O USB_UP_LED1 — USB port 1 GoodLink LED indicator. It is LOW when device is

O PWM1[1] — Pulse Width Modulator 1, channel 1 output.

I CAP1[0] — Capture input for Timer 1, channel 0.

[1]

I/O P1[19] — General purpose digital input/output pin.

O USB_TX_E1

O USB_PPWR1

I CAP1[1] — Capture input for Timer 1, channel 1.

LPC2458

Single-chip 16-bit/32-bit micro

— Transmit Enable signal for USB port 1 (OTG transceiver).

— Port Power enable signal for USB port 1.

Product data sheet Rev. 4.2 — 15 October 2020 12 of 81

NXP Semiconductors

Table 4. Pin description …continued

Symbol Ball Type Description

P1[20]/ USB_TX_DP1/ PWM1[2]/SCK0

P1[21]/ USB_TX_DM1/ PWM1[3]/SSEL0

P1[22]/ USB_RCV1/ USB_PWRD1/ MAT1[0]

P1[23]/ USB_RX_DP1/ PWM1[4]/MISO0

P1[24]/ USB_RX_DM1/ PWM1[5]/MOSI0

P1[25]/ USB_LS1

/ USB_HSTEN1/ MAT1[1]

P1[26]/ USB_SSPND1

/ PWM1[6]/ CAP0[0]

P1[27]/ USB_INT1

/ USB_OVRCR1/ CAP0[1]

P1[28]/ USB_SCL1/ PCAP1[0]/ MAT0[0]

P1[29]/ USB_SDA1/ PCAP1[1]/ MAT0[1]

P10

N10

[1]

I/O P1[20] — General purpose digital input/output pin.

O USB_TX_DP1 — D+ transmit data for USB port 1 (OTG transceiver).

O PWM1[2] — Pulse Width Modulator 1, channel 2 output.

I/O SCK0 — Serial clock for SSP0.

[1]

I/O P1[21] — General purpose digital input/output pin.

O USB_TX_DM1 — D transmit data for USB port 1 (OTG transceiver).

O PWM1[3] — Pulse Width Modulator 1, channel 3 output.

I/O SSEL0 — Slave Select for SSP0.

[1]

I/O P1[22] — General purpose digital input/output pin.

I USB_RCV1 — Differential receive data for USB port 1 (OTG transceiver).

I USB_PWRD1 — Power Status for USB port 1 (host power switch).

O MAT1[0] — Match output for Timer 1, channel 0.

[1]

I/O P1[23] — General purpose digital input/output pin.

I USB_RX_DP1 — D+ receive data for USB port 1 (OTG transceiver).

O PWM1[4] — Pulse Width Modulator 1, channel 4 output.

I/O MISO0 — Master In Slave Out for SSP0.

[1]

I/O P1[24] — General purpose digital input/output pin.

I USB_RX_DM1 — D receive data for USB port 1 (OTG transceiver).

O PWM1[5] — Pulse Width Modulator 1, channel 5 output.

I/O MOSI0 — Master Out Slave in for SSP0.

[1]

I/O P1[25] — General purpose digital input/output pin.

O USB_LS1

O USB_HSTEN1

O MAT1[1] — Match output for Timer 1, channel 1.

[1]

I/O P1[26] — General purpose digital input/output pin.

O USB_SSPND1

O PWM1[6] — Pulse Width Modulator 1, channel 6 output.

I CAP0[0] — Capture input for Timer 0, channel 0.

[1]

I/O P1[27] — General purpose digital input/output pin.

I USB_INT1

I USB_OVRCR1

I CAP0[1] — Capture input for Timer 0, channel 1.

[1]

I/O P1[28] — General purpose digital input/output pin.

I/O USB_SCL1 — USB port 1 I

I PCAP1[0] — Capture input for PWM1, channel 0.

O MAT0[0] — Match output for Timer 0, channel 0.

[1]

I/O P1[29] — General purpose digital input/output pin.

I/O USB_SDA1 — USB port 1 I

I PCAP1[1] — Capture input for PWM1, channel 1.

O MAT0[1] — Match output for Timer 0, channel 0.

LPC2458

Single-chip 16-bit/32-bit micro

— Low-speed status for USB port 1 (OTG transceiver).

— Host Enabled status for USB port 1.

— USB port 1 Bus Suspend status (OTG transceiver).

— USB port 1 OTG transceiver interrupt.

— USB port 1 Over-Current status.

C serial clock (OTG transceiver).

C serial data (OTG transceiver).

Product data sheet Rev. 4.2 — 15 October 2020 13 of 81

NXP Semiconductors

LPC2458

Single-chip 16-bit/32-bit micro

Table 4. Pin description …continued

Symbol Ball Type Description

[2]

P1[30]/ USB_PWRD2/

/AD0[4]

BUS

P1[31]/ USB_OVRCR2 SCK1/AD0[5]

P2[0] to P2[31] I/O Port 2: Port 2 is a 32-bit I/O port with individual direction controls for each bit. The

P2[0]/PWM1[1]/ TXD1/ TRACECLK

P2[1]/PWM1[2]/ RXD1/ PIPESTAT0

P2[2]/PWM1[3]/ CTS1/ PIPESTAT1

P2[3]/PWM1[4]/ DCD1/ PIPESTAT2

P2[4]/PWM1[5]/ DSR1/ TRACESYNC

P2[5]/PWM1[6]/ DTR1/ TRACEPKT0

P2[6]/PCAP1[0]/RI1/ TRACEPKT1

I/O P1[30] — General purpose digital input/output pin.

I USB_PWRD2 — Power Status for USB port 2.

I V

— Monitors the presence of USB bus power.

BUS

Note: This signal must be HIGH for USB reset to occur.

I AD0[4] — A/D converter 0, input 4.

[2]

I/O P1[31] — General purpose digital input/output pin.

I USB_OVRCR2

— Over-Current status for USB port 2.

I/O SCK1 — Serial Clock for SSP1.

I AD0[5] — A/D converter 0, input 5.

operation of port 2 pins depends upon the pin function selected via the Pin Connect block.

Pins P2[14:15], P2[22:23], P[26:27] and P2[30:31] are not available.

[1]

D12

I/O P2[0] — General purpose digital input/output pin.

O PWM1[1] — Pulse Width Modulator 1, channel 1 output.

O TXD1 — Transmitter output for UART1.

O TRACECLK — Trace Clock.

[1]

C14

I/O P2[1] — General purpose digital input/output pin.

O PWM1[2] — Pulse Width Modulator 1, channel 2 output.

I RXD1 — Receiver input for UART1.

O PIPESTAT0 — Pipeline Status, bit 0.

[1]

E11

I/O P2[2] — General purpose digital input/output pin.

O PWM1[3] — Pulse Width Modulator 1, channel 3 output.

I CTS1 — Clear to Send input for UART1.

O PIPESTAT1 — Pipeline Status, bit 1.

[1]

E13

I/O P2[3] — General purpose digital input/output pin.

O PWM1[4] — Pulse Width Modulator 1, channel 4 output.

I DCD1 — Data Carrier Detect input for UART1.

O PIPESTAT2 — Pipeline Status, bit 2.

[1]

E14

I/O P2[4] — General purpose digital input/output pin.

O PWM1[5] — Pulse Width Modulator 1, channel 5 output.

I DSR1 — Data Set Ready input for UART1.

O TRACESYNC — Trace Synchronization.

[1]

F12

I/O P2[5] — General purpose digital input/output pin.

O PWM1[6] — Pulse Width Modulator 1, channel 6 output.

O DTR1 — Data Terminal Ready output for UART1.

O TRACEPKT0 — Trace Packet, bit 0.

[1]

F13

I/O P2[6] — General purpose digital input/output pin.

I PCAP1[0] — Capture input for PWM1, channel 0.

I RI1 — Ring Indicator input for UART1.

O TRACEPKT1 — Trace Packet, bit 1.

Product data sheet Rev. 4.2 — 15 October 2020 14 of 81

NXP Semiconductors

Table 4. Pin description …continued

Symbol Ball Type Description

P2[7]/RD2/ RTS1/ TRACEPKT2

P2[8]/TD2/ TXD2/ TRACEPKT3

P2[9]/ USB_CONNECT1/ RXD2/ EXTIN0

P2[10]/EINT0

P2[11]/EINT1

/ MCIDAT1/ I2STX_CLK

P2[12]/EINT2

/ MCIDAT2/ I2STX_WS

P2[13]/EINT3

/ MCIDAT3/ I2STX_SDA

P2[16]/CAS

P2[17]/RAS

P2[18]/ CLKOUT0

P2[19]/ CLKOUT1

G11

G14

H11

M13

M12

N14

M11

P11

[1]

I/O P2[7] — General purpose digital input/output pin.

I RD2 — CAN2 receiver input.

O RTS1 — Request to Send output for UART1.

O TRACEPKT2 — Trace Packet, bit 2.

[1]

I/O P2[8] — General purpose digital input/output pin.

O TD2 — CAN2 transmitter output.

O TXD2 — Transmitter output for UART2.

O TRACEPKT3 — Trace Packet, bit 3.

[1]

I/O P2[9] — General purpose digital input/output pin.

O USB_CONNECT1 — USB1 SoftConnect control. Signal used to switch an

external 1.5 k resistor under the software control. Used with the SoftConnect USB feature.

I RXD2 — Receiver input for UART2.

I EXTIN0 — External Trigger Input.

[6]

I/O P2[10] — General purpose digital input/output pin.

Note: LOW on this pin while RESET over control of the part after a reset.

I EINT0

[6]

I/O P2[11] — General purpose digital input/output pin.

I EINT1

— External interrupt 0 input.

— External interrupt 1 input.

I/O MCIDAT1 — Data line 1 for SD/MMC interface.

I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the

slave. Corresponds to the signal SCK in the I

[6]

I/O P2[12] — General purpose digital input/output pin.

I EINT2

— External interrupt 2 input.

I/O MCIDAT2 — Data line 2 for SD/MMC interface.

I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by

the slave. Corresponds to the signal WS in the I

[6]

I/O P2[13] — General purpose digital input/output pin.

I EINT3

— External interrupt 3 input.

I/O MCIDAT3 — Data line 3 for SD/MMC interface.

I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the

receiver. Corresponds to the signal SD in the I

[1]

I/O P2[16] — General purpose digital input/output pin.

O CAS

[1]

I/O P2[17] — General purpose digital input/output pin.

O RAS

— LOW active SDRAM Column Address Strobe.

— LOW active SDRAM Row Address Strobe.

I/O P2[18] — General purpose digital input/output pin.

O CLKOUT0 — SDRAM clock 0.

[1]

I/O P2[19] — General purpose digital input/output pin.

O CLKOUT1 — SDRAM clock 1.

LPC2458

Single-chip 16-bit/32-bit micro

is LOW forces on-chip bootloader to take

S-bus specification.

Product data sheet Rev. 4.2 — 15 October 2020 15 of 81

NXP Semiconductors

LPC2458

Single-chip 16-bit/32-bit micro

Table 4. Pin description …continued

Symbol Ball Type Description

[1]

I/O P2[20] — General purpose digital input/output pin.

O DYCS0

— SDRAM chip select 0.

I/O P2[21] — General purpose digital input/output pin.

O DYCS1

— SDRAM chip select 1.

I/O P2[24] — General purpose digital input/output pin.

O CKEOUT0 — SDRAM clock enable 0.

[1]

I/O P2[25] — General purpose digital input/output pin.

O CKEOUT1 — SDRAM clock enable 1.

[1]

I/O P2[28] — General purpose digital input/output pin.

O DQMOUT0 — Data mask 0 used with SDRAM and static devices.

[1]

I/O P2[29] — General purpose digital input/output pin.

O DQMOUT1 — Data mask 1 used with SDRAM and static devices.

operation of port 3 pins depends upon the pin function selected via the Pin Connect block.

Pins P3[16:22] and P3[27:31] are not available.

[1]

I/O P3[0] — General purpose digital input/output pin.

I/O D0 — External memory data line 0.

[1]

I/O P3[1] — General purpose digital input/output pin.

I/O D1 — External memory data line 1.

[1]

I/O P3[2] — General purpose digital input/output pin.

I/O D2 — External memory data line 2.

[1]

I/O P3[3] — General purpose digital input/output pin.

I/O D3 — External memory data line 3.

[1]

I/O P3[4] — General purpose digital input/output pin.

I/O D4 — External memory data line 4.

[1]

I/O P3[5] — General purpose digital input/output pin.

I/O D5 — External memory data line 5.

[1]

I/O P3[6] — General purpose digital input/output pin.

I/O D6 — External memory data line 6.

[1]

I/O P3[7] — General purpose digital input/output pin.

I/O D7 — External memory data line 7.

[1]

I/O P3[8] — General purpose digital input/output pin.

I/O D8 — External memory data line 8.

[1]

I/O P3[9] — General purpose digital input/output pin.

I/O D9 — External memory data line 9.

[1]

I/O P3[10] — General purpose digital input/output pin.

I/O D10 — External memory data line 10.

[1]

I/O P3[11] — General purpose digital input/output pin.

I/O D11 — External memory data line 11.

P2[20]/DYCS0 P6

P2[21]/DYCS1

P2[24]/ CKEOUT0

P2[25]/ CKEOUT1

P2[28]/ DQMOUT0

P2[29]/ DQMOUT1

P3[0] to P3[31] I/O Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each bit. The

P3[0]/D0 D6

P3[1]/D1 E6

P3[2]/D2 A2

P3[3]/D3 G5

P3[4]/D4 D3

P3[5]/D5 E3

P3[6]/D6 F4

P3[7]/D7 G3

P3[8]/D8 A6

P3[9]/D9 A4

P3[10]/D10 B3

P3[11]/D11 B2

Product data sheet Rev. 4.2 — 15 October 2020 16 of 81

NXP Semiconductors

LPC2458

Single-chip 16-bit/32-bit micro

Table 4. Pin description …continued

Symbol Ball Type Description

[1]

I/O P3[12] — General purpose digital input/output pin.

I/O D12 — External memory data line 12.

[1]

I/O P3[13] — General purpose digital input/output pin.

I/O D13 — External memory data line 13.

[1]

I/O P3[14] — General purpose digital input/output pin.

I/O D14 — External memory data line 14.

[1]

I/O P3[15] — General purpose digital input/output pin.

I/O D15 — External memory data line 15.

[1]

I/O P3[23] — General purpose digital input/output pin.

I CAP0[0] — Capture input for Timer 0, channel 0.

I PCAP1[0] — Capture input for PWM1, channel 0.

[1]

I/O P3[24] — General purpose digital input/output pin.

I CAP0[1] — Capture input for Timer 0, channel 1.

O PWM1[1] — Pulse Width Modulator 1, output 1.

[1]

I/O P3[25] — General purpose digital input/output pin.

O MAT0[0] — Match output for Timer 0, channel 0.

O PWM1[2] — Pulse Width Modulator 1, output 2.

[1]

I/O P3[26] — General purpose digital input/output pin.

O MAT0[1] — Match output for Timer 0, channel 1.

O PWM1[3] — Pulse Width Modulator 1, output 3.

operation of port 4 pins depends upon the pin function selected via the Pin Connect block.

Pins P4[20:23] are not available.

[1]

I/O P4[0] — General purpose digital input/output pin.

I/O A0 — External memory address line 0.

[1]

I/O P4[1] — General purpose digital input/output pin.

I/O A1 — External memory address line 1.

[1]

I/O P4[2] — General purpose digital input/output pin.

I/O A2 — External memory address line 2.

[1]

I/O P4[3] — General purpose digital input/output pin.

I/O A3 — External memory address line 3.

[1]

I/O P4[4] — General purpose digital input/output pin.

I/O A4 — External memory address line 4.

[1]

I/O P4[5] — General purpose digital input/output pin.

I/O A5 — External memory address line 5.

[1]

I/O P4[6] — General purpose digital input/output pin.

I/O A6 — External memory address line 6.

[1]

I/O P4[7] — General purpose digital input/output pin.

I/O A7 — External memory address line 7.

P3[12]/D12 A1

P3[13]/D13 C1

P3[14]/D14 F1

P3[15]/D15 G4

P3[23]/CAP0[0]/ PCAP1[0]

P3[24]/CAP0[1]/ PWM1[1]

P3[25]/MAT0[0]/ PWM1[2]

P3[26]/MAT0[1]/ PWM1[3]

P4[0] to P4[31] I/O Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. The

P4[0]/A0 L6

P4[1]/A1 M7

P4[2]/A2 M8

P4[3]/A3 K9

P4[4]/A4 P13

P4[5]/A5 H10

P4[6]/A6 K10

P4[7]/A7 K12

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NXP Semiconductors

Table 4. Pin description …continued

Symbol Ball Type Description

K13

F14

D10

[1]

I/O P4[8] — General purpose digital input/output pin.

I/O A8 — External memory address line 8.

[1]

I/O P4[9] — General purpose digital input/output pin.

I/O A9 — External memory address line 9.

[1]

I/O P4[10] — General purpose digital input/output pin.

I/O A10 — External memory address line 10.

[1]

I/O P4[11] — General purpose digital input/output pin.

I/O A11 — External memory address line 11.

[1]

I/O P4[12] — General purpose digital input/output pin.

I/O A12 — External memory address line 12.

[1]

I/O P4[13] — General purpose digital input/output pin.

I/O A13 — External memory address line 13.

[1]

I/O P4[14] — General purpose digital input/output pin.

I/O A14 — External memory address line 14.

[1]

I/O P4[15] — General purpose digital input/output pin.

I/O A15 — External memory address line 15.

[1]

I/O P4[16] — General purpose digital input/output pin.

I/O A16 — External memory address line 16.

[1]

I/O P4[17] — General purpose digital input/output pin.

I/O A17 — External memory address line 17.

[1]

I/O P4[18] — General purpose digital input/output pin.

I/O A18 — External memory address line 18.

[1]

I/O P4[19] — General purpose digital input/output pin.

I/O A19 — External memory address line 19.

[1]

I/O P4[24] — General purpose digital input/output pin.

O OE

— LOW active Output Enable signal.

I/O P4[25] — General purpose digital input/output pin.

O WE

[1]

I/O P4[26] — General purpose digital input/output pin.

O BLS0

[1]

I/O P4[27] — General purpose digital input/output pin.

O BLS1

[1]

I/O P4[28] — General purpose digital input/output pin.

— LOW active Write Enable signal.

— LOW active Byte Lane select signal 0.

— LOW active Byte Lane select signal 1.

O MAT2[0] — Match output for Timer 2, channel 0.

O TXD3 — Transmitter output for UART3.

[1]

I/O P4[29] — General purpose digital input/output pin.

O MAT2[1] — Match output for Timer 2, channel 1.

I RXD3 — Receiver input for UART3.

[1]

I/O P4[30] — General purpose digital input/output pin.

O CS0

— LOW active Chip Select 0 signal.

P4[8]/A8 J11

P4[9]/A9 H12

P4[10]/A10 G12

P4[11]/A11 F11

P4[12]/A12 F10

P4[13]/A13 B14

P4[14]/A14 E8

P4[15]/A15 C10

P4[16]/A16 N12

P4[17]/A17 N13

P4[18]/A18 P14

P4[19]/A19 M14

P4[24]/OE

P4[25]/WE

P4[26]/BLS0

P4[27]/BLS1

P4[28]/MAT2[0]/ TXD3

P4[29]/MAT2[1]/ RXD3

P4[30]/CS0

LPC2458

Single-chip 16-bit/32-bit micro

Product data sheet Rev. 4.2 — 15 October 2020 18 of 81

NXP Semiconductors

Table 4. Pin description …continued

Symbol Ball Type Description

P4[31]/CS1 E7

ALARM H5

USB_D2N2I/OUSB_D2 — USB port 2 bidirectional D line.

DBGEN E5

TDO B1

TDI C3

TMS C2

TRST

TCK D2

RTCK C4

RSTOUT

RESET

XTAL1 L2

XTAL2 K4

RTCX1 J2

RTCX2 J3

SSIO

SSCORE

SSA

DD(3V3)

n.c. H1, L12,

DD(DCDC)(3V3)

[1]

[7]

I/O P4[31] — General purpose digital input/output pin.

O CS1

— LOW active Chip Select 1 signal.

O ALARM — RTC controlled output. This is a 1.8 V pin. It goes HIGH when a RTC

alarm is generated.

[1][8]

[1][9]

[1][8]

[1][9]

I DBGEN — JTAG interface control signal. Also used for boundary scan.

O TDO — Test Data Out for JTAG interface.

I TDI — Test Data In for JTAG interface.

I TMS — Test Mode Select for JTAG interface.

I TRST — Test Reset for JTAG interface.

I TCK — Test Clock for JTAG interface. This clock must be slower than 1⁄6 of the

CPU clock (CCLK) for the JTAG interface to operate.

[1][8]

I/O RTCK — JTAG interface control signal.

Note: LOW on this pin while RESET

is LOW enables ETM pins (P2[9:0]) to

operate as Trace port after reset.

H2 O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC2458 being in

Reset state.

[10]

I external reset input: A LOW on this pin resets the device, causing I/O ports and

peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant.

[7][11]

[7][12]

H4, P4,

I Input to the oscillator circuit and internal clock generator circuits.

O Output from the oscillator amplifier.

I Input to the RTC oscillator circuit.

O Output from the RTC oscillator circuit.

I ground: 0 V reference for the digital IO pins.

L9, L13, G13, D13, C11,

[13]

H3, L8, A10

[14]

E2, L4,

I ground: 0 V reference for the core.

[13]

I analog ground: 0 V reference. This should nominally be the same voltage as

SSIO/VSSCORE

, but should be isolated to minimize noise and error.

I 3.3 V supply voltage: This is the power supply voltage for the I/O ports.

K8, L11, J14, E12, E10,

[15]

I not connected pins: These pins must be left unconnected (floating).

[16]

G10

G1, N9,

[17]

I 3.3 V DC-to-DC converter supply voltage: This is the power supply for the

on-chip DC-to-DC converter.

LPC2458

Single-chip 16-bit/32-bit micro

Product data sheet Rev. 4.2 — 15 October 2020 19 of 81

NXP Semiconductors

LPC2458

Single-chip 16-bit/32-bit micro

Table 4. Pin description …continued

Symbol Ball Type Description

DDA

VREF G2

VBAT K1

[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.

[2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input,

digital section of the pad is disabled.

[3] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,

digital section of the pad is disabled.

[4] Open-drain 5 V tolerant digital I/O pad, compatible with I

functionality. When power is switched off, this pin connected to the I configuration applies to all functions on this pin.

[5] Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and

Low-speed mode only).

[6] 5 V tolerant pad with 10 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.

[7] Pad provides special analog functionality.

[8] This pin has a built-in pull-up resistor.

[9] This pin has no built-in pull-up and no built-in pull-down resistor.

[10] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.

[11] When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding

is preferred to reduce susceptibility to noise). XTAL2 should be left floating.

[12] If the RTC is not used, these pins can be left floating.

[13] Pad provides special analog functionality.

[14] Pad provides special analog functionality.

[15] Pad provides special analog functionality.

[16] Pad provides special analog functionality.

[17] Pad provides special analog functionality.

[18] Pad provides special analog functionality.

[18]

I analog 3.3 V pad supply voltage: This should be nominally the same voltage as

but should be isolated to minimize noise and error. This voltage is used

DD(3V3)

to power the ADC and DAC.

I ADC reference: This should be nominally the same voltage as V

DD(3V3)

but should be isolated to minimize noise and error. The level on this pin is used as a reference for ADC and DAC.

I RTC power supply: 3.3 V on this pin supplies the power to the RTC peripheral.

C-bus 400 kHz specification. It requires an external pull-up to provide output

C-bus is floating and does not disturb the I2C lines. Open-drain

7. Functional description

7.1 Architectural overview

The LPC2458 microcontroller consists of an ARM7TDMI-S CPU with emulation support, the ARM7 local bus for closely coupled, high-speed access to the majority of on-chip memory, the AMBA AHB interfacing to high-speed on-chip peripherals and external memory, and the AMBA APB for connection to other on-chip peripheral functions. The microcontroller permanently configures the ARM7TDMI-S processor for little-endian byte order.

The LPC2458 implements two AHB in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, includes the VIC, GPDMA controller, and EMC.

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The second AHB, referred to as AHB2, includes only the Ethernet block and an associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into off-chip memory or unused space in memory residing on AHB1.

In summary, bus masters with access to AHB1 are the ARM7 itself, the GPDMA function, and the Ethernet block (via the bus bridge from AHB2). Bus masters with access to AHB2 are the ARM7 and the Ethernet block.

AHB peripherals are allocated a 2 MB range of addresses at the very top of the 4 GB ARM memory space. Each AHB peripheral is allocated a 16 kB address space within the AHB address space. Lower speed peripheral functions are connected to the APB. The AHB to APB bridge interfaces the APB to the AHB. APB peripherals are also allocated a 2 MB range of addresses, beginning at the 3.5 GB address point. Each APB peripheral is allocated a 16 kB address space within the APB address space.

The ARM7TDMI-S processor is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed complex instruction set computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core.

LPC2458

Single-chip 16-bit/32-bit micro

Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue.

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets:

• the standard 32-bit ARM set

• a 16-bit Thumb set

The Thumb set’s 16-bit instruction length allows it to approach higher density compared to standard ARM code while retaining most of the ARM’s performance.

7.2 On-chip flash programming memory

The LPC2458 incorporates 512 kB flash memory system. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It may be programmed In System via the serial port (UART0). The application program may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field and firmware upgrades.

The flash memory is 128 bits wide and includes pre-fetching and buffering techniques to allow it to operate at speeds of 72 MHz.

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7.3 On-chip SRAM

The LPC2458 includes a SRAM memory of 64 kB reserved for the ARM processor exclusive use. This RAM may be used for code and/or data storage and may be accessed as 8 bits, 16 bits, and 32 bits.

A 16 kB SRAM block serving as a buffer for the Ethernet controller and a 16 kB SRAM associated with the second AHB can be used both for data and code storage. The 2 kB RTC SRAM can be used for data storage only. The RTC SRAM is battery powered and retains the content in the absence of the main power supply.

7.4 Memory map

The LPC2458 memory map incorporates several distinct regions as shown in Tab le 5 and

Figure 3.

In addition, the CPU interrupt vectors may be remapped to allow them to reside in either flash memory (default), boot ROM, or SRAM (see

Table 5. LPC2458 memory usage and details

Address range General use Address range details and description

0x0000 0000 to 0x3FFF FFFF

0x4000 0000 to 0x7FFF FFFF

0x8000 0000 to 0xBFFF FFFF

0xE000 0000 to 0xEFFF FFFF

0xF000 0000 to 0xFFFF FFFF

LPC2458

Single-chip 16-bit/32-bit micro

Section 7.26.6).

on-chip non-volatile memory and fast I/O

on-chip RAM 0x4000 0000 to 0x4000 FFFF RAM (64 kB)

off-chip memory two static memory banks, 1 MB each

APB peripherals 36 peripheral blocks, 16 kB each

AHB peripherals

0x0000 0000 to 0x0007 FFFF flash memory (512 kB)

0x3FFF C000 to 0x3FFF FFFF fast GPIO registers

0x7FE0 0000 to 0x7FE0 3FFF Ethernet RAM (16 kB)

0x7FD0 0000 to 0x7FD0 3FFF USB RAM (16 kB)

0x8000 0000 to 0x800F FFFF static memory bank 0

0x8100 0000 to 0x810F FFFF static memory bank 1

two dynamic memory banks, 256 MB each

0xA000 0000 to 0xAFFF FFFF dynamic memory bank 0

0xB000 0000 to 0xBFFF FFFF dynamic memory bank 1

Product data sheet Rev. 4.2 — 15 October 2020 22 of 81

NXP Semiconductors

0.0 GB

1.0 GB

ON-CHIP NON-VOLATILE MEMORY

0x0000 0000

RESERVED ADDRESS SPACE

SPECIAL REGISTERS

ON-CHIP STATIC RAM

RESERVED ADDRESS SPACE

0x4000 0000

0x3FFF 8000

0x3FFF FFFF

2.0 GB 0x8000 0000 0x7FFF FFFF

BOOT ROM AND BOOT FLASH

(BOOT FLASH REMAPPED FROM ON-CHIP FLASH)

0xDFFF FFFF

0xC000 0000 0xBFFF FFFF

RESERVED ADDRESS SPACE

EXTERNAL STATIC AND DYNAMIC MEMORY

3.75 GB

4.0 GB

3.5 GB

AHB PERIPHERALS

APB PERIPHERALS

0xE000 0000

0xF000 0000

0xFFFF FFFF

002aad657

LPC2458

Single-chip 16-bit/32-bit micro

Fig 3. LPC2458 memory map

7.5 Interrupt controller

The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be programmed as FIQ or vectored IRQ types. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted.

FIQs have the highest priority. If more than one request is assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ

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NXP Semiconductors

service routine can simply start dealing with that device. But if more than one request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt.

Vectored IRQs, which include all interrupt requests that are not classified as FIQs, have a programmable interrupt priority. When more than one interrupt is assigned the same priority and occur simultaneously, the one connected to the lowest numbered VIC channel will be serviced first.

The VIC ORs the requests from all of the vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping to the address supplied by that register.

7.5.1 Interrupt sources

Each peripheral device has one interrupt line connected to the VIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source.

Any pin on port 0 and port 2 (total of 64 pins) regardless of the selected function, can be programmed to generate an interrupt on a rising edge, a falling edge, or both. Such interrupt request coming from port 0 and/or port 2 will be combined with the EINT3 interrupt requests.

LPC2458

Single-chip 16-bit/32-bit micro

7.6 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals.

Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined.

7.7 External memory controller

The LPC2458 EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM, and flash. In addition, it can be used as an interface with off-chip memory-mapped devices and peripherals. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant peripheral.

7.7.1 Features

• Dynamic memory interface support including single data rate SDRAM.

• Asynchronous static memory device support including RAM, ROM, and flash, with or

without asynchronous page mode.

• Low transaction latency.

• Read and write buffers to reduce latency and to improve performance.

• 8/16 data and 20 address lines wide static memory support.

• 16 bit wide chip select SDRAM memory support.

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NXP Semiconductors

• Static memory features include:

• Two chip selects for synchronous memory and two chip selects for static memory

• Power-saving modes dynamically control CKE and CLKOUT to SDRAMs.

• Dynamic memory self-refresh mode controlled by software.

• Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row

• Separate reset domains allow auto-refresh through a chip reset if desired.

Note: Synchronous static memory devices (synchronous burst mode) are not supported.

LPC2458

Single-chip 16-bit/32-bit micro

– Asynchronous page mode read

– Programmable Wait States

– Bus turnaround delay

– Output enable and write enable delays

– Extended wait

devices.

address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB parts, with 4, 8, and 16 data bits per device.

7.8 General purpose DMA controller

The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2458 peripherals to have DMA support.

The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For example, a bidirectional port requires one stream for transmit and one for receive. The source and destination areas can each be either a memory region or a peripheral, and can be accessed through the AHB master.

7.8.1 Features

• Two DMA channels. Each channel can support a unidirectional transfer.

• The GPDMA can transfer data between the 16 kB SRAM, external memory, and

peripherals such as the SD/MMC, two SSPs, and the I

• Single DMA and burst DMA request signals. Each peripheral connected to the

GPDMA can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the GPDMA.

• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and

peripheral-to-peripheral transfers.

• Scatter or gather DMA is supported through the use of linked lists. This means that

the source and destination areas do not have to occupy contiguous areas of memory.

• Hardware DMA channel priority. Each DMA channel has a specific hardware priority.

DMA channel 0 has the highest priority and channel 1 has the lowest priority. If requests from two channels become active at the same time, the channel with the highest priority is serviced first.

• AHB slave DMA programming interface. The GPDMA is programmed by writing to the

DMA control registers over the AHB slave interface.

S interface.

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NXP Semiconductors

• One AHB master for transferring data. This interface transfers data when a DMA

• 32-bit AHB master bus width.

• Incrementing or non-incrementing addressing for source and destination.

• Programmable DMA burst size. The DMA burst size can be programmed to more

• Internal four-word FIFO per channel.

• Supports 8-bit, 16-bit, and 32-bit wide transactions.

• An interrupt to the processor can be generated on a DMA completion or when a DMA

• Interrupt masking. The DMA error and DMA terminal count interrupt requests can be

• Raw interrupt status. The DMA error and DMA count raw interrupt status can be read

LPC2458

Single-chip 16-bit/32-bit micro

request goes active.

efficiently transfer data. Usually the burst size is set to half the size of the FIFO in the peripheral.

error has occurred.

masked.

prior to masking.

7.9 Fast general purpose parallel I/O

Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back as well as the current state of the port pins.

LPC2458 use accelerated GPIO functions:

• GPIO registers are relocated to the ARM local bus so that the fastest possible I/O

timing can be achieved.

• Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

• All GPIO registers are byte and half-word addressable.

• Entire port value can be written in one instruction.

Additionally, any pin on port 0 and port 2 (total of 64 pins) that is not configured as an analog input/output can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous, so it may operate when clocks are not present such as during Power-down mode. Each enabled interrupt can be used to wake the chip up from Power-down mode.

7.9.1 Features

• Bit level set and clear registers allow a single instruction to set or clear any number of

bits in one port.

• Direction control of individual bits.

• All I/O default to inputs after reset.

• Backward compatibility with other earlier devices is maintained with legacy port 0 and

port 1 registers appearing at the original addresses on the APB.

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NXP Semiconductors

7.10 Ethernet

The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with scatter-gather DMA off-loads many operations from the CPU.

The Ethernet block and the CPU share a dedicated AHB subsystem that is used to access the Ethernet SRAM for Ethernet data, control, and status information. All other AHB traffic in the LPC2458 takes place on a different AHB subsystem, effectively separating Ethernet activity from the rest of the system. The Ethernet DMA can also access off-chip memory via the EMC, as well as the SRAM located on another AHB. However, using memory other than the Ethernet SRAM, especially off-chip memory, will slow Ethernet access to memory and increase the loading of its AHB.

The Ethernet block interfaces between an off-chip Ethernet PHY using the Media Independent Interface (MII) or Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial bus.

LPC2458

Single-chip 16-bit/32-bit micro

7.10.1 Features

• Ethernet standards support:

– Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,

100 Base-FX, and 100 Base-T4.

– Fully compliant with IEEE standard 802.3.

– Fully compliant with 802.3x full duplex flow control and half duplex back pressure.

– Flexible transmit and receive frame options.

– Virtual Local Area Network (VLAN) frame support.

• Memory management:

– Independent transmit and receive buffers memory mapped to shared SRAM.

– DMA managers with scatter/gather DMA and arrays of frame descriptors.

– Memory traffic optimized by buffering and pre-fetching.

• Enhanced Ethernet features:

– Receive filtering.

– Multicast and broadcast frame support for both transmit and receive.

– Optional automatic Frame Check Sequence (FCS) insertion with Circular

Redundancy Check (CRC) for transmit.

– Selectable automatic transmit frame padding.

– Over-length frame support for both transmit and receive allows any length frames.

– Promiscuous receive mode.

– Automatic collision back-off and frame retransmission.

– Includes power management by clock switching.

– Wake-on-LAN power management support allows system wake-up: using the

receive filters or a magic frame detection filter.

Product data sheet Rev. 4.2 — 15 October 2020 27 of 81

NXP Semiconductors

• Physical interface:

7.11 USB interface

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The Host Controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot plugging and dynamic configuration of the devices. All transactions are initiated by the Host Controller.

The LPC2458 USB interface includes a device, Host, and OTG Controller. Details on typical USB interfacing solutions can be found in

solutions” on page 65

7.11.1 USB device controller

The device controller enables 12 Mbit/s data exchange with a USB Host Controller. It consists of a register interface, serial interface engine, endpoint buffer memory, and a DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. When enabled, the DMA controller transfers data between the endpoint buffer and the USB RAM.

LPC2458

Single-chip 16-bit/32-bit micro

– Attachment of external PHY chip through standard MII or RMII interface.

– PHY register access is available via the MIIM interface.

Section 14.1 “Suggested USB interface

7.11.1.1 Features

• Fully compliant with USB 2.0 specification (full speed).

• Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM.

• Supports Control, Bulk, Interrupt and Isochronous endpoints.

• Scalable realization of endpoints at run time.

• Endpoint Maximum packet size selection (up to USB maximum specification) by

software at run time.

• Supports SoftConnect and GoodLink features.

• While USB is in the Suspend mode, LPC2458 can enter one of the reduced power

modes and wake up on USB activity.

• Supports DMA transfers with the DMA RAM of 16 kB on all non-control endpoints.

• Allows dynamic switching between CPU-controlled and DMA modes.

• Double buffer implementation for Bulk and Isochronous endpoints.

7.11.2 USB Host Controller

The Host Controller enables full- and low-speed data exchange with USB devices attached to the bus. It consists of a register interface, a serial interface engine and a DMA controller. The register interface complies with the OHCI specification.

7.11.2.1 Features

• OHCI compliant.

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NXP Semiconductors

• Two downstream ports.

• Supports per-port power switching.

7.11.3 USB OTG Controller

USB OTG is a supplement to the USB 2.0 specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals.

The OTG Controller integrates the Host Controller, device controller, and a master-only

C interface to implement OTG dual-role device functionality. The dedicated I2C interface

controls an external OTG transceiver.

7.11.3.1 Features

• Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision

• Hardware support for Host Negotiation Protocol (HNP).

• Includes a programmable timer required for HNP and Session Request Protocol

• Supports any OTG transceiver compliant with the OTG Transceiver Specification

LPC2458

Single-chip 16-bit/32-bit micro

1.0a.

(SRP).

(CEA-2011), Rev. 1.0.

7.12 CAN controller and acceptance filters

The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security. Its domain of application ranges from high-speed networks to low cost multiplex wiring.

The CAN block is intended to support multiple CAN buses simultaneously, allowing the device to be used as a gateway, switch, or router between two of CAN buses in industrial or automotive applications.

Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN Library block, but the 8-bit registers of those devices have been combined in 32-bit words to allow simultaneous access in the ARM environment. The main operational difference is that the recognition of received Identifiers, known in CAN terminology as Acceptance Filtering, has been removed from the CAN controllers and centralized in a global Acceptance Filter.

7.12.1 Features

• Two CAN controllers and buses.

• Data rates to 1 Mbit/s on each bus.

• 32-bit register and RAM access.

• Compatible with CAN specification 2.0B, ISO 11898-1.

• Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN

buses.

• Acceptance Filter can provide FullCAN-style automatic reception for selected

Standard Identifiers.

• FullCAN messages can generate interrupts.

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7.13 10-bit ADC

The LPC2458 contains one ADC. It is a single 10-bit successive approximation ADC with eight channels.

7.13.1 Features

• 10-bit successive approximation ADC

• Input multiplexing among 8 pins

• Power-down mode

• Measurement range 0 V to V

• 10-bit conversion time  2.44 s

• Burst conversion mode for single or multiple inputs

• Optional conversion on transition of input pin or Timer Match signal

• Individual result registers for each ADC channel to reduce interrupt overhead

7.14 10-bit DAC

LPC2458

Single-chip 16-bit/32-bit micro

i(VREF)

The DAC allows the LPC2458 to generate a variable analog output. The maximum output value of the DAC is V

7.14.1 Features

• 10-bit DAC

• Resistor string architecture

• Buffered output

• Power-down mode

• Selectable output drive

7.15 UARTs

The LPC2458 contains four UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface.

The UARTs include a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz.

7.15.1 Features

• 16 B Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• Fractional divider for baud rate control, auto baud capabilities and FIFO control

mechanism that enables software flow control implementation.

• UART1 equipped with standard modem interface signals. This module also provides

full support for hardware flow control (auto-CTS/RTS).

i(VREF)

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NXP Semiconductors

• UART3 includes an IrDA mode to support infrared communication.

7.16 SPI serial I/O controller

The LPC2458 contains one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master.

7.16.1 Features

• Compliant with SPI specification

• Synchronous, Serial, Full Duplex Communication

• Combined SPI master and slave

• Maximum data bit rate of one eighth of the input clock rate

• 8 bits to 16 bits per transfer

LPC2458

Single-chip 16-bit/32-bit micro

7.17 SSP serial I/O controller

The LPC2458 contains two SSP controllers. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data.

7.17.1 Features

• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

• Synchronous serial communication

• Master or slave operation

• 8-frame FIFOs for both transmit and receive

• 4-bit to 16-bit frame

• Maximum SPI bus data bit rate of one half (Master mode) and one twelfth (Slave

mode) of the input clock rate

• DMA transfers supported by GPDMA

7.18 SD/MMC card interface

The Secure Digital and Multimedia Card Interface (MCI) allows access to external SD memory cards. The SD card interface conforms to the SD Multimedia Card Specification Version 2.11.

7.18.1 Features

• The MCI interface provides all functions specific to the SD/MMC memory card. These

include the clock generation unit, power management control, and command and data transfer.

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NXP Semiconductors

• Conforms to Multimedia Card Specification v2.11.

• Conforms to Secure Digital Memory Card Physical Layer Specification, v0.96.

• Can be used as a multimedia card bus or a secure digital memory card bus host. The

• DMA supported through the GPDMA controller.

7.19 I2C-bus serial I/O controller

The LPC2458 contains three I2C-bus controllers.

The I (SCL), and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I be controlled by more than one bus master connected to it.

LPC2458

Single-chip 16-bit/32-bit micro

SD/MMC can be connected to several multimedia cards or a single secure digital memory card.

C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line

C-bus is a multi-master bus and can

The I

C-bus implemented in LPC2458 supports bit rates up to 400 kbit/s (Fast I2C-bus).

7.19.1 Features

• I

C0 is a standard I2C compliant bus interface with open-drain pins.

• I

C1 and I2C2 use standard I/O pins and do not support powering off of individual

devices connected to the same bus lines.

• Easy to configure as master, slave, or master/slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I

C-bus can be used for test and diagnostic purposes.

7.20 I2S-bus serial I/O controllers

The I2S-bus provides a standard communication interface for digital audio applications.

The I

S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I master, and one slave. The I and receive channel, each of which can operate as either a master or a slave.

Product data sheet Rev. 4.2 — 15 October 2020 32 of 81

S interface on the LPC2458 provides a separate transmit

S connection has one master, which is always the

NXP Semiconductors

7.20.1 Features

• The interface has separate input/output channels each of which can operate in master

• Capable of handling 8-bit, 16-bit, and 32-bit word sizes.

• Mono and stereo audio data supported.

• The sampling frequency can range from 16 kHz to 48 kHz (16, 22.05, 32, 44.1,

• Configurable word select period in master mode (separately for I

• Two 8 word FIFO data buffers are provided, one for transmit and one for receive.

• Generates interrupt requests when buffer levels cross a programmable boundary.

• Two DMA requests, controlled by programmable buffer levels. These are connected

• Controls include reset, stop and mute options separately for I

7.21 General purpose 32-bit timers/external event counters

or slave mode.

48) kHz.

to the GPDMA block.

LPC2458

Single-chip 16-bit/32-bit micro

S input and output).

S input and I2S output.

The LPC2458 includes four 32-bit Timer/Counters. The Timer/Counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. The Timer/Counter also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt.

7.21.1 Features

• A 32-bit Timer/Counter with a programmable 32-bit prescaler.

• Counter or Timer operation.

• Up to four 32-bit capture channels per timer, that can take a snapshot of the timer

value when an input signal transitions. A capture event may also optionally generate an interrupt.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Up to four external outputs corresponding to match registers, with the following

capabilities:

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

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NXP Semiconductors

7.22 Pulse width modulator

The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2458. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers. The PWM function is in addition to these features and is based on match register events.

The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions.

Two match registers can be used to provide a single edge controlled PWM output. A dedicated match register controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs.

Three match registers can be used to provide a PWM output with both edges controlled. Again, a dedicated match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs.

LPC2458

Single-chip 16-bit/32-bit micro

With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge).

7.22.1 Features

• LPC2458 has two PWMs with the same operational features. These may be operated

in a synchronized fashion by setting them both up to run at the same rate, then enabling both simultaneously. PWM0 acts as the master and PWM1 as the slave for this use.

• Counter or Timer operation (may use the peripheral clock or one of the capture inputs

as the clock source).

• Seven match registers allow up to 6 single edge controlled or 3 double edge

controlled PWM outputs, or a mix of both types. The match registers also allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.

– Reset timer on match with optional interrupt generation.

• Supports single edge controlled and/or double edge controlled PWM outputs. Single

edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the output is a constant LOW. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses.

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NXP Semiconductors

• Pulse period and width can be any number of timer counts. This allows complete

• Double edge controlled PWM outputs can be programmed to be either positive going

• Match register updates are synchronized with pulse outputs to prevent generation of

• May be used as a standard timer if the PWM mode is not enabled.

• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

7.23 Watchdog timer (WDT)

The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined amount of time.

LPC2458

Single-chip 16-bit/32-bit micro

flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate.

or negative going pulses.

erroneous pulses. Software must ‘release’ new match values before they can become effective.

7.23.1 Features

• Internally resets chip if not periodically reloaded.

• Debug mode.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 32-bit timer with internal prescaler.

• Selectable time period from (T

multiples of T

cy(WDCLK)

• The Watchdog Clock (WDCLK) source can be selected from the RTC clock, the

Internal RC oscillator (IRC), or the APB peripheral clock. This gives a wide range of potential timing choices of Watchdog operation under different power reduction conditions. It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring, for increased reliability.

7.24 RTC and battery RAM

The RTC is a set of counters for measuring time when system power is on, and optionally when power is off. It uses little power in Power-down and Deep power-down modes. On the LPC2458, the RTC can be clocked by a separate 32.768 kHz oscillator or by a programmable prescale divider based on the APB clock. The RTC is powered by its own power supply pin, VBAT, which can be connected to a battery or to the same 3.3 V supply used by the rest of the device.

 4.

cy(WDCLK)

 256  4) to (T

cy(WDCLK)

 232 4) in

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NXP Semiconductors

The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions require a minimum of power to operate, which can be supplied by an external battery. When the CPU and the rest of chip functions are stopped and power is removed, the RTC can supply an alarm output that can be used by external hardware to restore chip power and resume operation.

7.24.1 Features

• Measures the passage of time to maintain a calendar and clock.

• Ultra low power design to support battery powered systems.

• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and

• Dedicated 32 kHz oscillator or programmable prescaler from APB clock.

• Dedicated power supply pin can be connected to a battery or to the main 3.3 V.

• An alarm output pin is included to assist in waking up when the chip has had power

• Periodic interrupts can be generated from increments of any field of the time registers,

• 2 kB data SRAM powered by VBAT.

• RTC and Battery RAM power supply is isolated from the rest of the chip.

LPC2458

Single-chip 16-bit/32-bit micro

Day of Year.

removed to all functions except the RTC and Battery RAM.

and selected fractional second values. This enhancement enables the RTC to be used as a System Timer.

7.25 Clocking and power control

7.25.1 Crystal oscillators

The LPC2458 includes three independent oscillators. These are the Main Oscillator, the Internal RC oscillator, and the RTC oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Any of the three clock sources can be chosen by software to drive the PLL and ultimately the CPU.

Following reset, the LPC2458 will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency.

7.25.1.1 Internal RC oscillator

The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed to 1 % accuracy.

Upon power-up or any chip reset, the LPC2458 uses the IRC as the clock source. Software may later switch to one of the other available clock sources.

7.25.1.2 Main oscillator

The main oscillator can be used as the clock source for the CPU, with or without using the PLL. The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock frequency is referred to as CCLK elsewhere in this document. The frequencies of

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NXP Semiconductors

PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The clock frequency for each peripheral can be selected individually and is referred to as PCLK. Refer to Section 7.25.2

7.25.1.3 RTC oscillator

The RTC oscillator can be used as the clock source for the RTC and/or the WDT. Also, the RTC oscillator can be used to drive the PLL and the CPU.

7.25.2 PLL

The PLL accepts an input clock frequency in the range of 32 kHz to 25 MHz. The input frequency is multiplied up to a high frequency, then divided down to provide the actual clock used by the CPU and the USB block.

The PLL input, in the range of 32 kHz to 25 MHz, may initially be divided down by a value ‘N’, which may be in the range of 1 to 256. This input division provides a wide range of output frequencies from the same input frequency.

Following the PLL input divider is the PLL multiplier. This can multiply the input divider output through the use of a Current Controlled Oscillator (CCO) by a value ‘M’, in the range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to 550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a phase-frequency detector to compare the divided CCO output to the multiplier input. The error value is used to adjust the CCO frequency.

LPC2458

Single-chip 16-bit/32-bit micro

for additional information.

The PLL is turned off and bypassed following a chip Reset and by entering Power-down mode. PLL is enabled by software only. The program must configure and activate the PLL, wait for the PLL to lock, then connect to the PLL as a clock source.

7.25.3 Wake-up timer

The LPC2458 begins operation at power-up and when awakened from Power-down and Deep power-down modes by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source.

When the main oscillator is initially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. This is important at power on, all types of Reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down and Deep power-down modes, any wake-up of the processor from Power-down modes makes use of the Wake-up Timer.

The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin code execution. When power is applied to the chip, or when some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of V electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions.

ramp (in the case of power on), the type of crystal and its

DD(3V3)

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NXP Semiconductors

7.25.4 Power control

The LPC2458 supports a variety of power control features. There are four special modes of processor power reduction: Idle mode, Sleep mode, Power-down mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, Peripheral power control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Each of the peripherals has its own clock divider which provides even better power control.

The LPC2458 also implements a separate power domain in order to allow turning off power to the bulk of the device while maintaining operation of the RTC and a small SRAM, referred to as the Battery RAM.

7.25.4.1 Idle mode

In Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses.

LPC2458

Single-chip 16-bit/32-bit micro

7.25.4.2 Sleep mode

In Sleep mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Sleep mode and the logic levels of chip pins remain static. The output of the IRC is disabled but the IRC is not powered down for a fast wake-up later. The 32 kHz RTC oscillator is not stopped because the RTC interrupts may be used as the wake-up source. The PLL is automatically turned off and disconnected. The CCLK and USB clock dividers automatically get reset to zero.

The Sleep mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Sleep mode reduces chip power consumption to a very low value. The flash memory is left on in Sleep mode, allowing a very quick wake-up.

On the wake-up from Sleep mode, if the IRC was used before entering Sleep mode, the code execution and peripherals activities will resume after 4 cycles expire. If the main external oscillator was used, the code execution will resume when 4096 cycles expire.

The customers need to reconfigure the PLL and clock dividers accordingly.

7.25.4.3 Power-down mode

Power-down mode does everything that Sleep mode does, but also turns off the IRC oscillator and the flash memory. This saves more power, but requires waiting for resumption of flash operation before execution of code or data access in the flash memory can be accomplished.

On the wake-up from Power-down mode, if the IRC was used before entering Power-down mode, it will take IRC 60 s to start-up. After this 4 IRC cycles will expire before the code execution can then be resumed if the code was running from SRAM. In

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NXP Semiconductors

the meantime, the flash wake-up timer then counts 4 MHz IRC clock cycles to make the 100 s flash start-up time. When it times out, access to the flash will be allowed. The customers need to reconfigure the PLL and clock dividers accordingly.

7.25.4.4 Deep power-down mode

Deep power-down mode is similar to the Power-down mode, but now the on-chip regulator that supplies power to the internal logic is also shut off. This produces the lowest possible power consumption without removing power from the entire chip. Since the Deep power-down mode shuts down the on-chip logic power supply, there is no register or memory retention, and resumption of operation involves the same activities as a full chip reset.

If power is supplied to the LPC2458 during Deep power-down mode, wake-up can be caused by the RTC Alarm interrupt or by external Reset.

While in Deep power-down mode, external device power may be removed. In this case, the LPC2458 will start up when external power is restored.

Essential data may be retained through Deep power-down mode (or through complete powering off of the chip) by storing data in the Battery RAM, as long as the external power to the VBAT pin is maintained.

LPC2458

Single-chip 16-bit/32-bit micro

7.25.4.5 Power domains

The LPC2458 provides two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the Battery RAM.

On the LPC2458, I/O pads are powered by the 3.3 V (V V

DD(DCDC)(3V3)

pins power the on-chip DC-to-DC converter which in turn provides power to

the CPU and most of the peripherals.

Although both the I/O pad ring and the core require a 3.3 V supply, different powering schemes can be used depending on the actual application requirements.

The first option assumes that power consumption is not a concern and the design ties the V

DD(3V3)

and V

DD(DCDC)(3V3)

supply for both pads, the CPU, and peripherals. While this solution is simple, it does not support powering down the I/O pad ring “on the fly” while keeping the CPU and peripherals alive.

The second option uses two power supplies; a 3.3 V supply for the I/O pads (V a dedicated 3.3 V supply for the CPU (V converter powered independently from the I/O pad ring enables shutting down of the I/O pad power supply “on the fly”, while the CPU and peripherals stay active.

The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions require a minimum of power to operate, which can be supplied by an external battery. When the CPU and the rest of chip functions are stopped and power removed, the RTC can supply an alarm output that may be used by external hardware to restore chip power and resume operation.

) pins, while the

DD(3V3)

pins together. This approach requires only one 3.3 V power

) and

DD(3V3)

DD(DCDC)(3V3)

). Having the on-chip DC-DC

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NXP Semiconductors

7.26 System control

7.26.1 Reset

Reset has four sources on the LPC2458: the RESET pin, the Watchdog reset, power-on reset, and the BrownOut Detection (BOD) circuit. The RESET pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, starts the Wake-up timer (see description in causing reset to remain asserted until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the flash controller has completed its initialization.

When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the Boot Block. At that point, all of the processor and peripheral registers have been initialized to predetermined values.

7.26.2 Brownout detection

LPC2458

Single-chip 16-bit/32-bit micro

pin is a Schmitt trigger input

Section 7.25.3 “Wake-up timer”),

The LPC2458 includes 2-stage monitoring of the voltage on the V voltage falls below 2.95 V, the BOD asserts an interrupt signal to the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the VIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register.

The second stage of low-voltage detection asserts Reset to inactivate the LPC2458 when the voltage on the V the flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point the power-on reset circuitry maintains the overall Reset.

Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly-executed event loop to sense the condition.

DD(DCDC)(3V3)

pins falls below 2.65 V. This Reset prevents alteration of

7.26.3 Code security (Code Read Protection - CRP)

This feature of the LPC2458 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP.

There are three levels of the Code Read Protection.

CRP1 disables access to chip via the JTAG and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased.

DD(DCDC)(3V3)

pins. If this

CRP2 disables access to chip via the JTAG and only allows full flash erase and update using a reduced set of the ISP commands.

Running an application with level CRP3 selected fully disables any access to chip via the JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too. It is up to the user’s application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UART0.

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NXP Semiconductors

CAUTION

7.26.4 AHB

In summary, bus masters with access to AHB1 are the ARM7 itself, the USB block, the GPDMA function, and the Ethernet block (via the bus bridge from AHB2). Bus masters with access to AHB2 are the ARM7 and the Ethernet block.

LPC2458

Single-chip 16-bit/32-bit micro

If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device.

7.26.5 External interrupt inputs

The LPC2458 includes up to 68 edge sensitive interrupt inputs combined with up to four level sensitive external interrupt inputs as selectable pin functions. The external interrupt inputs can optionally be used to wake up the processor from Power-down mode.

7.26.6 Memory mapping control

The memory mapping control alters the mapping of the interrupt vectors that appear at the beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the Boot ROM, the SRAM, or external memory. This allows code running in different memory spaces to have control of the interrupts.

7.27 Emulation and debugging

The LPC2458 support emulation and debugging via a JTAG serial port. A trace port allows tracing program execution. Debugging and trace functions are multiplexed only with GPIOs on P2[0] to P2[9]. This means that all communication, timer, and interface peripherals residing on other pins are available during the development and debugging phase as they are when the application is run in the embedded system itself.

7.27.1 EmbeddedICE

The EmbeddedICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an EmbeddedICE protocol convertor. The EmbeddedICE protocol convertor converts the Remote Debug Protocol commands to the JTAG data needed to access the ARM7TDMI-S core present on the target system.

The ARM core has a Debug Communication Channel (DCC) function built-in. The DCC allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or even entering the debug state. The

Product data sheet Rev. 4.2 — 15 October 2020 41 of 81

NXP Semiconductors

DCC is accessed as a coprocessor 14 by the program running on the ARM7TDMI-S core. The DCC allows the JTAG port to be used for sending and receiving data without affecting the normal program flow. The DCC data and control registers are mapped in to addresses in the EmbeddedICE logic.

LPC2458

Single-chip 16-bit/32-bit micro

The JTAG clock (TCK) must be slower than interface to operate.

7.27.2 Embedded trace

Since the LPC2458 have significant amounts of on-chip memories, it is not possible to determine how the processor core is operating simply by observing the external pins. The ETM provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to a trace port. A software debugger allows configuration of the ETM using a JTAG interface and displays the trace information that has been captured.

The ETM is connected directly to the ARM core and not to the main AMBA system bus. It compresses the trace information and exports it through a narrow trace port. An external Trace Port Analyzer captures the trace information under software debugger control. The trace port can broadcast the Instruction trace information. Instruction trace (or PC trace) shows the flow of execution of the processor and provides a list of all the instructions that were executed. Instruction trace is significantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. Trace information generation can be controlled by selecting the trigger resource. Trigger resources include address comparators, counters and sequencers. Since trace information is compressed the software debugger requires a static image of the code being executed. Self-modifying code can not be traced because of this restriction.

⁄6 of the CPU clock (CCLK) for the JTAG

7.27.3 RealMonitor

RealMonitor is a configurable software module, developed by ARM Inc., which enables real-time debug. It is a lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC, which is present in the EmbeddedICE logic. The LPC2458 contain a specific configuration of RealMonitor software programmed into the on-chip ROM memory.

Product data sheet Rev. 4.2 — 15 October 2020 42 of 81

NXP Semiconductors

8. Limiting values

LPC2458

Single-chip 16-bit/32-bit micro

Table 6. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

[1]

Symbol Parameter Conditions Min Max Unit

DD(3V3)

supply voltage (3.3 V) core and external

3.0 3.6 V

rail

DD(DCDC)(3V3)

DC-to-DC converter supply voltage

3.0 3.6 V

(3.3 V)

DDA

i(VBAT)

i(VREF)

analog 3.3 V pad supply voltage 0.5 +4.6 V

input voltage on pin VBAT for the RTC 0.5 +4.6 V

input voltage on pin VREF 0.5 +4.6 V

analog input voltage on ADC related

0.5 +5.1 V

pins

input voltage 5 V tolerant I/O

[2]

0.5 +6.0 V pins; only valid when the V

DD(3V3)

supply voltage is present

other I/O pins

[2][3]

0.5 V

DD(3V3)

0.5

stg

tot(pack)

supply current per supply pin

ground current per ground pin

storage temperature non-operating

total power dissipation (per package) based on package

[4]

- 100 mA

[4]

- 100 mA

[5]

65 +150 C

-1.5W heat transfer, not device power consumption

ESD

electrostatic discharge voltage human body

[6]

2500 +2500 V

model; all pins

[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V

unless otherwise noted.

[2] Including voltage on outputs in 3-state mode.

[3] Not to exceed 4.6 V.

[4] The peak current is limited to 25 times the corresponding maximum current.

[5] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined

based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details.

[6] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

Product data sheet Rev. 4.2 — 15 October 2020 43 of 81

SSIO/VSSCORE

NXP Semiconductors

TjT

amb

PDR

th j a–

+=

9. Thermal characteristics

The average chip junction temperature, Tj (C), can be calculated using the following equation:

LPC2458

Single-chip 16-bit/32-bit micro

(1)

• T

• R

• P

The internal power dissipation is the product of I

= ambient temperature (C),

amb

= the package junction-to-ambient thermal resistance (C/W)

th(j-a)

= sum of internal and I/O power dissipation

and VDD. The I/O power dissipation of

the I/O pins is often small and many times can be negligible. However it can be significant in some applications.

Table 7. Thermal characteristics

VDD= 3.0 V to 3.6 V; T

Symbol Parameter Conditions Min Typ Max Unit

j(max)

maximum junction temperature

=40C to +85C unless otherwise specified

amb

Table 8. Thermal resistance value (C/W): ±15 %

VDD= 3.0 V to 3.6 V; T

TFBGA180

ja

JEDEC (4.5 in  4 in)

0 m/s 45.5

1 m/s 38.3

2.5 m/s 33.8

8-layer (4.5 in  3 in)

0 m/s 38

1 m/s 33.5

2.5 m/s 29.8

jc 8.9

jb 12

=40C to +85C unless otherwise specified

amb

--125 C

Product data sheet Rev. 4.2 — 15 October 2020 44 of 81

NXP Semiconductors

10. Static characteristics

LPC2458

Single-chip 16-bit/32-bit micro

Table 9. Static characteristics

=40C to +85C for commercial applications, unless otherwise specified.

amb

Symbol Parameter Conditions Min Typ

DD(3V3)

DD(DCDC)(3V3)

supply voltage (3.3 V) core and external rail 3.0 3.3 3.6 V

DC-to-DC converter

3.0 3.3 3.6 V

supply voltage (3.3 V)

DDA

analog 3.3 V pad

3.0 3.3 3.6 V

supply voltage

i(VBAT)

input voltage on pin

[2]

2.0 3.3 3.6 V

VBAT

i(VREF)

input voltage on pin

2.5 3.3 V

VREF

DD(DCDC)act(3V3)

active mode DC-to-DC converter supply current (3.3 V)

DD(DCDC)(3V3)

=25C; code

amb

while(1){}

=3.3V;

executed from flash; no peripherals enabled; PCLK = CCLK

CCLK = 10 MHz - 15 - mA

CCLK = 72 MHz - 63 - mA

all peripherals enabled; PCLK = CCLK / 8

CCLK = 10 MHz - 21 - mA

CCLK = 72 MHz - 92 - mA

all peripherals enabled; PCLK = CCLK

CCLK = 10 MHz - 27 - mA

CCLK = 72 MHz - 125 - mA

DD(DCDC)pd(3V3)

DD(DCDC)dpd(3V3)

Power-down mode DC-to-DC converter supply current (3.3 V)

Deep power-down

DD(DCDC)(3V3)

=25C

amb

= 3.3 V;

[3]

-113-A

[3]

mode DC-to-DC converter supply

-20-A

[4]

-20-A

[3]

-20-A

BATact

BAT

current (3.3 V)

active mode battery supply current

battery supply current Deep power-down mode

[1]

Max Unit

DDA

Product data sheet Rev. 4.2 — 15 October 2020 45 of 81

NXP Semiconductors

Single-chip 16-bit/32-bit micro

Table 9. Static characteristics …continued

=40C to +85C for commercial applications, unless otherwise specified.

amb

Symbol Parameter Conditions Min Typ

Standard port pins, RESET, RTCK

latch

hys

OHS

OLS

I2C-bus pins (P0[27] and P0[28])

hys

LOW-level input

VI= 0 V; no pull-up - - 3 A

current

HIGH-level input

VI=V

; no pull-down - - 3 A

DD(3V3)

current

OFF-state output current

I/O latch-up current (0.5V

input voltage pin configured to provide a

VO=0V; VO=V no pull-up/down

) < VI <

DD(3V3)

(1.5V

< 125 C

DD(3V3)

);

digital function

DD(3V3)

;

-- 3A

- - 100 mA

[5][6][7]

0- 5.5V

[8]

output voltage output active 0 - V

HIGH-level input

2.0 - - V

voltage

LOW-level input

-- 0.8V

voltage

hysteresis voltage 0.4 - - V

HIGH-level output voltage

LOW-level output

IOH= 4 mA

IOL= 4 mA

[9]

DD(3V3)



--V

0.4

[9]

-- 0.4V

voltage

HIGH-level output

VOH=V

DD(3V3)

 0.4 V

[9]

4- - mA

current

LOW-level output

VOL=0.4V

[9]

4- - mA

current

HIGH-level

VOH=0V

[10]

-- 45 mA short-circuit output current

LOW-level short-circuit

VOL=V

DDA

[10]

-- 50mA output current

pull-down current VI=5V

[11]

10 50 150 A

pull-up current VI=0V 15 50 85 A

[11]

00 0A

0.7V

DD(3V3)

--V

HIGH-level input

DD(3V3)<VI

<5V

voltage

LOW-level input

- - 0.3V voltage

hysteresis voltage - 0.05V

LOW-level output

OLS

=3 mA

[9]

-- 0.4V voltage

input leakage current VI=V

=5V - 10 22 A

DD(3V3)

[12]

-2 4A

[1]

DD(3V3)

LPC2458

Max Unit

DD(3V3)

-V

Product data sheet Rev. 4.2 — 15 October 2020 46 of 81

NXP Semiconductors

Single-chip 16-bit/32-bit micro

Table 9. Static characteristics …continued

=40C to +85C for commercial applications, unless otherwise specified.

amb

Symbol Parameter Conditions Min Typ

Oscillator pins

i(XTAL1)

o(XTAL2)

i(RTCX1)

o(RTCX2)

USB pins

BUS

th(rs)se

trans

DRV

input voltage on pin

0.5 1.8 1.95 V

XTAL1

output voltage on pin

0.5 1.8 1.95 V

XTAL2

input voltage on pin

0.5 1.8 1.95 V

RTCX1

output voltage on pin

0.5 1.8 1.95 V

RTCX2

OFF-state output

0V<VI<3.3V - - 10 A

current

bus supply voltage - - 5.25 V

differential input

(D+)  (D) 0.2 - - V

sensitivity voltage

differential common

includes VDI range 0.8 - 2.5 V

mode voltage range

single-ended receiver

0.8 - 2.0 V switching threshold voltage

LOW-level output

RL of 1.5 k to 3.6 V - - 0.18 V voltage for low-/full-speed

HIGH-level output

RL of 15 k to GND 2.8 - 3.5 V voltage (driven) for low-/full-speed

transceiver

pin to GND - - 20 pF capacitance

driver output impedance for driver

with 33  series resistor;

steady state drive

[13]

36 - 44.1 

which is not high-speed capable

[1]

LPC2458

Max Unit

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages

[2] The RTC typically fails when V

[3] V

DD(DCDC)(3V3)

[4] On pin VBAT.

[5] Including voltage on outputs in 3-state mode.

[6] V

DD(3V3)

[7] 3-state outputs go into 3-state mode when V

[8] Please also see the errata note mentioned in errata sheet.

[9] Accounts for 100 mV voltage drop in all supply lines.

[10] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[11] Minimum condition for V

[12] To V

[13] Includes external resistors of 33 1 % on D+ and D.

Product data sheet Rev. 4.2 — 15 October 2020 47 of 81

SSIO

= 3.3 V; V

supply voltages must be present.

DD(3V3)

= 4.5 V, maximum condition for VI=5.5V.

drops below 1.6 V.

i(VBAT)

= 3.3 V; V

i(VBAT)

DD(3V3)

= 3.3 V; T

is grounded.

amb

=25C.

NXP Semiconductors

002aae049

−2

DD(IO)

(μA)

−4 temperature (°C)

−40 853510 60−15

DD(3V3)

= 3.3 V

DD(3V3)

= 3.0 V

002aae050

i(VBAT)

= 3.3 V

i(VBAT)

= 3.0 V

BAT

(μA)

temperature (°C)

−40 853510 60−15

10.1 Power-down mode

LPC2458

Single-chip 16-bit/32-bit micro

= V

i(VBAT)

DD(DCDC)(3V3)

Fig 4. I/O maximum supply current I

Fig 5. RTC battery maximum supply current I

mode

DD(3V3)

= V

DD(DCDC)(3V3)

= 3.3 V; T

=25C.

amb

versus temperature in Power-down mode

DD(IO)

=25C.

amb

versus temperature in Power-down

BAT

Product data sheet Rev. 4.2 — 15 October 2020 48 of 81

NXP Semiconductors

002aae051

200

600

400

800

temperature (°C)

−40 853510 60−15

DD(DCDC)(3V3)

= 3.3 V

DD(DCDC)(3V3)

= 3.0 V

DD(DCDC)pd(3v3)

(μA)

temperature (°C)

−40 853510 60−15

002aae046

100

200

300

DD(IO)

(μA)

DD(3V3)

= 3.3 V

DD(3V3)

= 3.0 V

Fig 6. Total DC-to-DC converter supply current I

DD(3V3)

= V

i(VBAT)

= 3.3 V; T

in Power-down mode

amb

=25C.

Single-chip 16-bit/32-bit micro

DD(DCDC)pd(3V3)

LPC2458

at different temperatures

10.2 Deep power-down mode

Fig 7. I/O maximum supply current I

mode

DD(3V3)

= V

DD(DCDC)(3V3)

= 3.3 V; T

=25C.

amb

versus temperature in Deep power-down

DD(IO)

Product data sheet Rev. 4.2 — 15 October 2020 49 of 81

NXP Semiconductors

002aae047

BAT

(μA)

temperature (°C)

−40 853510 60−15

i(VBAT)

= 3.3 V

i(VBAT)

= 3.0 V

002aae048

temperature (°C)

−40 853510 60−15

DD(DCDC)dpd(3v3)

(μA)

100

DD(DCDC)(3V3)

= 3.3 V

DD(DCDC)(3V3)

= 3.0 V

LPC2458

Single-chip 16-bit/32-bit micro

Fig 8. RTC battery maximum supply current I

DD(3V3)

= V

DD(DCDC)(3V3)

= 3.3 V; T

amb

=25C

versus temperature in Deep

BAT

power-down mode

DD(3V3)

= V

i(VBAT)

= 3.3 V; T

amb

=25C.

Fig 9. Total DC-to-DC converter maximum supply current I

temperature in Deep power-down mode

DD(DCDC)dpd(3V3)

versus

Product data sheet Rev. 4.2 — 15 October 2020 50 of 81

NXP Semiconductors

IOH (mA)

0 24168

002aaf112

2.8

2.4

3.2

3.6

(V)

2.0

T = 85 °C

25 °C

−40 °C

VOL (V)

0 0.60.40.2

002aaf111

(mA)

T = 85 °C

25 °C

−40 °C

10.3 Electrical pin characteristics

LPC2458

Single-chip 16-bit/32-bit micro

Conditions: V

= 3.3 V; standard port pins.

DD(3V3)

Fig 10. Typical HIGH-level output voltage VOH versus HIGH-level output source current

Conditions: V

Fig 11. Typical LOW-level output current IOL versus LOW-level output voltage V

= 3.3 V; standard port pins.

DD(3V3)

Product data sheet Rev. 4.2 — 15 October 2020 51 of 81

NXP Semiconductors

CHCL

CLCX

CHCX

cy(clk)

CLCH

002aaa907

11. Dynamic characteristics

LPC2458

Single-chip 16-bit/32-bit micro

Table 10. Dynamic characteristics

=40C to +85C for commercial applications; V

amb

Symbol Parameter Conditions Min Ty p

over specified ranges.

DD(3V3)

[1]

[2]

External clock

osc

cy(clk)

CHCX

CLCX

CLCH

CHCL

oscillator frequency 1 - 25 MHz

clock cycle time 40 - 1000 ns

clock HIGH time T

clock LOW time T

 0.4 - - ns

cy(clk)

 0.4 - - ns

cy(clk)

clock rise time - - 5 ns

clock fall time - - 5 ns

I2C-bus pins (P0[27] and P0[28])

f(o)

output fall time VIH to V

20 + 0.1  C

[3]

--ns

SSP interface

su(SPI_MISO)

SPI_MISO set-up time T

amb

= 25 C;

-11-ns measured in SPI Master mode; see

Figure 16

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.

[3] Bus capacitance C

in pF, from 10 pF to 400 pF.

Max Unit

Fig 12. External clock timing (with an amplitude of at least V

i(RMS)

= 200 mV)

Product data sheet Rev. 4.2 — 15 October 2020 52 of 81

NXP Semiconductors

LPC2458

Single-chip 16-bit/32-bit micro

11.1 Internal oscillators

Table 11. Dynamic characteristic: Internal oscillators

=40C to +85C; 3.0 V  V

amb

Symbol Parameter Conditions Min Ty p

osc(RC)

i(RTC)

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.

DD(3V3)

 3.6 V.

[1]

[2]

Max Unit

internal RC oscillator frequency - 3.96 4.02 4.04 MHz

RTC input frequency - - 32.768 - kHz

11.2 I/O pins

Table 12. Dynamic characteristic: I/O pins

=40C to +85C; V

amb

DD(3V3)

over specified ranges.

Symbol Parameter Conditions Min Typ Max Unit

rise time pin configured as output 3.0 - 5.0 ns

fall time pin configured as output 2.5 - 5.0 ns

[1]

[1] Applies to standard I/O pins and RESET pin.

11.3 USB interface

Table 13. Dynamic characteristics of USB pins

CL = 50 pF; Rpu = 1.5 k on D+ to V

Symbol Parameter Conditions Min Typ Max Unit

FRFM

CRS

FEOPT

FDEOP

JR1

JR2

EOPR1

EOPR2

,unless otherwise specified.

DD(3V3)

rise time 10 % to 90 % 8.5 - 13.8 ns

fall time 10 % to 90 % 7.7 - 13.7 ns

differential rise and fall time

tr/t

--109%

matching

output signal crossover voltage 1.3 - 2.0 V

source SE0 interval of EOP see Figure 15 160 - 175 ns

source jitter for differential transition

see Figure 15 2-+5ns

to SE0 transition

receiver jitter to next transition 18.5 - +18.5 ns

receiver jitter for paired transitions 10 % to 90 % 9-+9ns

EOP width at receiver must reject as

[1]

40 - - ns EOP; see

Figure 15

EOP width at receiver must accept as

[1]

82 - - ns EOP; see

Figure 15

[1] Characterized but not implemented as production test. Guaranteed by design.

Product data sheet Rev. 4.2 — 15 October 2020 53 of 81

NXP Semiconductors

LPC2458

Single-chip 16-bit/32-bit micro

11.4 Flash memory

Table 14. Dynamic characteristics of flash

=40C to +85C, unless otherwise specified; V

amb

ground.

Symbol Parameter Conditions Min Typ Max Unit

endu

ret

prog

[1] Number of program/erase cycles.

[2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes.

= 3.0 V to 3.6 V; all voltages are measured with respect to

DD(3V3)

endurance

retention time powered; < 100 cycles

unpowered; < 100 cycles 20 - - years

erase time sector or multiple

consecutive sectors

programming time

[1]

10000 100000 - cycles

[2]

10 - - years

95 100 105 ms

[2]

0.95 1 1.05 ms

Product data sheet Rev. 4.2 — 15 October 2020 54 of 81

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

Product data sheet Rev. 4.2 — 15 October 2020 55 of 81

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

11.5 Static external memory interface

Table 15. Dynamic characteristics: Static external memory interface

CL=30pF, T

=40C to 85C, V

amb

Symbol Parameter Conditions Min Typ Max Unit

Common to read and write cycles

CSLAV

CS LOW to address valid time

Read cycle parameters

OELAV

OE LOW to address valid time

CSLOEL

h(D)

CSHOEH

OEHANV

CS LOW to OE LOW time 0.78 + T

memory access time

data input hold time

CS HIGH to OE HIGH time 0.49 0 0.20 ns

OE HIGH to address invalid time

OELOEH

BLSLAV

OE LOW to OE HIGH time 0.59 + (WAITRD 

BLS LOW to address valid time

CSHBLSH

CS HIGH to BLS HIGH time 0.88 0.49 0.68 ns

Write cycle parameters

CSLWEL

CSLBLSL

WELDV

CSLDV

WELWEH

BLSLBLSH

CS LOW to WE LOW time 0.88 + T

CS LOW to BLS LOW time 0.88 0.49 0.98 ns

WE LOW to data valid time 0.68 2.54 5.86 ns

CS LOW to data valid time 0 2.64 4.79 ns

WE LOW to WE HIGH time

BLS LOW to BLS HIGH time

WEHANV

WE HIGH to address invalid time

[1][2]

[1][6]

DD(DCDC)(3V3)

[1]

= V

= 3.0 V to 3.6 V

DD(3V3)

[3][4]

[5]

[3]

0.29 0.20 2.54 ns

cy(CCLK)

 WAITOEN 0 + T

(WAITRD  WAITOEN + 1)  T

cy(CCLK)

 12.70

cy(CCLK)

(WAITRD  WAITOEN + 1)  T

cy(CCLK)

 WAITOEN 0.49 + T

 9.57

cy(CCLK)

 WAITOEN ns

(WAITRD  WAITOEN + 1)  T

cy(CCLK)

 8.11

0--ns

0.20 0.20 2.44 ns

WAITOEN + 1)  T

cy(CCLK)

0 + (WAITRD  WAITOEN +

1)  T

cy(CCLK)

0.10 + (WAITRD  WAITOEN + 1)  T

cy(CCLK)

0.39 0 2.54 ns

 (1 +

cy(CCLK)

WAITWEN)

0.78 + T

cy(CCLK)



(WAITWR  WAITWEN + 1)

0.88 + T

cy(CCLK)



(WAITWR  WAITWEN + 3)

0 + T

cy(CCLK)

0.10 + T

cy(CCLK)

WAITWEN)

0 + T

cy(CCLK)

 (WAITWR 

WAITWEN + 1)

0 + T

cy(CCLK)

 (WAITWR 

WAITWEN + 3)

0.20 + T

cy(CCLK)

 (1 +

0.20 + T

cy(CCLK)

 (1 +

WAITWEN)

0.10 + T

cy(CCLK)



(WAITWR  WAITWEN + 1)

0.59 + T

cy(CCLK)



(WAITWR  WAITWEN + 3)

2.74 + T

cy(CCLK)

NXP Semiconductors

Single-chip 16-bit/32-bit micro

LPC2458

Product data sheet Rev. 4.2 — 15 October 2020 56 of 81

Table 15. Dynamic characteristics: Static external memory interface …continued

CL=30pF, T

Symbol Parameter Conditions Min Typ Max Unit

WEHDNV

BLSHANV

BLSHDNV

[1] VOH = 2.5 V, VOL = 0.2 V.

[2] V

[3] T

[4] Latest of address valid, CS

[5] Earliest of CS

[6] Byte lane state bit (PB) = 1.

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

=40C to 85C, V

amb

WE HIGH to data invalid time

BLS HIGH to address invalid time

BLS HIGH to data invalid time

= 2.5 V, VIL = 0.5 V.

cy(CCLK)

= 1⁄

CCLK

HIGH, OE HIGH, address change to data invalid.

DD(DCDC)(3V3)

LOW, OE LOW to data valid.

= V

DD(3V3)

[3]

= 3.0 V to 3.6 V

0.78 + T

2.54 + T

cy(CCLK)

5.96 + T

cy(CCLK)

0.29 0.20 2.54 ns

02.545.37ns

NXP Semiconductors

Single-chip 16-bit/32-bit micro

LPC2458

NXP Semiconductors

LPC2458

Single-chip 16-bit/32-bit micro

11.6 Dynamic external memory interface

Table 16. Dynamic characteristics: Dynamic external memory interface

CL=30pF, T

=40C to 85C, V

amb

(RD = 00)

Symbol Parameter Conditions Min Ty p Max Unit

Common

d(SV)

h(S)

d(RASV)

h(RAS)

d(CASV)

h(CAS)

d(WV)

h(W)

d(GV)

h(G)

d(AV)

h(A)

chip select valid delay time

chip select hold time

row address strobe valid delay time

row address strobe hold time

column address strobe valid delay time

column address strobe hold time

write valid delay time

write hold time

output enable valid delay time

output enable hold time

address valid delay time

address hold time

Read cycle parameters

su(D)

h(D)

data input set-up time

data input hold time

Write cycle parameters

d(QV)

h(Q)

data output valid delay time

data output hold time

DD(DCDC)(3V3)

= V

= 3.0 V to 3.6 V, EMC Dynamic Read Config Register = 0x0

DD(3V3)

[1]

- 1.05 1.76 ns

[1]

0.1 1.02 - ns

[1]

- 1.51 1.95 ns

[1]

0.5 1.51 - ns

[1]

- 0.98 1.27 ns

[1]

0.1 0.97 - ns

[1]

- 0.84 1.95 ns

[1]

0.1 0.84 - ns

[1]

- 0.95 1.86 ns

[1]

0.1 1 - ns

[1]

- 0.87 1.95 ns

[1]

0.1 0.81 - ns

[1]

0.51 2.24 - ns

[1]

0.57 2.41 - ns

[1]

- 2.65 4.36 ns

[1]

0.49 2.61 - ns

[1] See Figure 17.

Product data sheet Rev. 4.2 — 15 October 2020 57 of 81

NXP Semiconductors

LPC2458

Single-chip 16-bit/32-bit micro

Table 17. Dynamic characteristics: Dynamic external memory interface

CL= 30 pF on all pins, T (RD = 01), T

cy(CCLK)

=40C to 85C, V

amb

= 1/CCLK

DD(DCDC)(3V3)

= V

= 3.3 V, EMC Dynamic Read Config Register = 0x1

DD(3V3)

Symbol Parameter Conditions Min Typ Max Unit

Common

d(SV)

chip select valid delay

[1]

- 3 + T

cy(CCLK)

/2 1.5 + T

cy(CCLK)

/2 ns

time

h(S)

d(RASV)

chip select hold time

row address strobe valid

[1]

4 + T

[1]

- 3 + T

cy(CCLK)

/2 3 + T

/2 - ns

cy(CCLK)

/2 1.5 + T

cy(CCLK)

/2 ns

delay time

h(RAS)

row address strobe hold

[1]

3 + T

cy(CCLK)

/2 2.3 + T

/2 - ns

cy(CCLK)

time

d(CASV)

column address strobe

[1]

- 3.4 + T

cy(CCLK)

/2 2.1 + T

cy(CCLK)

/2 ns

valid delay time

h(CAS)

column address strobe

[1]

4 + T

cy(CCLK)

/2 3 + T

/2 - ns

cy(CCLK)

hold time

d(WV)

h(W)

d(GV)

write valid delay time

write hold time

output enable valid delay

[1]

- 3.4 + T

[1]

4 + T

[1]

- 3 + T

cy(CCLK)

/2 3 + T

/2 2.1 + T

cy(CCLK)

/2 - ns

cy(CCLK)

/2 1.3 + T

cy(CCLK)

/2 ns

time

h(G)

d(AV)

h(A)

output enable hold time

address valid delay time

address hold time

[1]

4 + T

[1]

- 2.6 + T

[1]

4 + T

cy(CCLK)

/2 2.1 + T

/2 2.3 + T

/2 - ns

cy(CCLK)

/2 1.4 + T

cy(CCLK)

/2 - ns

cy(CCLK)

/2 ns

Read cycle parameters

su(D)

h(D)

data input set-up time

data input hold time

[1]

2.6 1.5 - ns

[1]

2.6 1.3 - ns

Write cycle parameters

d(QV)

data output valid delay

[1]

- 2.6 + T

cy(CCLK)

/2 4.8 + T

cy(CCLK)

/2 ns

time

h(Q)

data output hold time

[1]

3.8 + T

cy(CCLK)

/2 3.4 + T

/2 - ns

cy(CCLK)

[1] See Figure 17.

Product data sheet Rev. 4.2 — 15 October 2020 58 of 81

NXP Semiconductors

addr

data

BLS

CSLAV

OELAV

OELOEH

CSLOEL

h(D)

CSHOEH

OEHANV

002aad955

BLSLAV

CSHBLSH

addr

data

BLS/WE

CSLWEL

CSLBLSL

WELDV

CSLDV

WELWEH

BLSLBLSH

WEHANV

BLSHANV

WEHDNV

BLSHDNV

002aad956

CSLAV

11.7 Timing

LPC2458

Single-chip 16-bit/32-bit micro

Fig 13. External memory read access

Fig 14. External memory write access

Product data sheet Rev. 4.2 — 15 October 2020 59 of 81

NXP Semiconductors

002aab561

PERIOD

differential data lines

crossover point

source EOP width: t

FEOPT

receiver EOP width: t

EOPR1

, t

EOPR2

crossover point

extended

differential data to

SE0/EOP skew

n × T

PERIOD

+ t

FDEOP

su(SPI_MISO)

SCK

shifting edges

MOSI

MISO

002aad326

sampling edges

002aad636

reference

clock

output signal (O)

input signal (I)

d(XXX)

h(XXX)

h(D)

su(D)

Fig 15. Differential data-to-EOP transition skew and EOP width

LPC2458

Single-chip 16-bit/32-bit micro

Fig 16. MISO line set-up time in SSP Master mode

Fig 17. Signal timing

Product data sheet Rev. 4.2 — 15 October 2020 60 of 81

NXP Semiconductors

12. ADC electrical characteristics

LPC2458

Single-chip 16-bit/32-bit micro

Table 18. ADC static characteristics

= 2.5 V to 3.6 V; T

DDA

=40C to +85C unless otherwise specified; ADC frequency 4.5 MHz.

amb

Symbol Parameter Conditions Min Typ Max Unit

L(adj)

vsi

analog input voltage 0 - V

DDA

analog input capacitance - - 1 pF

differential linearity error

integral non-linearity

offset error

gain error

absolute error

voltage source interface

[1][2][3]

--1LSB

[1][4]

--2LSB

[1][5]

--3LSB

[1][6]

--0.5 %

[1][7]

--4LSB

[8]

--40k

resistance

[1] Conditions: V

[2] The ADC is monotonic, there are no missing codes.

[3] The differential linearity error (E

[4] The integral non-linearity (E

appropriate adjustment of gain and offset errors. See

[5] The offset error (E

ideal curve. See

[6] The gain error (E

error, and the straight line which fits the ideal transfer curve. See

[7] The absolute error (E

ADC and the ideal transfer curve. See

[8] See

Figure 19.

=0V, V

SSA

) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the

Figure 18.

) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset

=3.3V.

DDA

) is the difference between the actual step width and the ideal step width. See Figure 18.

) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

L(adj)

) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated

Figure 18.

Product data sheet Rev. 4.2 — 15 October 2020 61 of 81

NXP Semiconductors

1023

1022

1021

1020

1019

(2)

(1)

10241018 1019 1020 1021 1022 1023

7123456

1018

(5)

(4)

(3)

1 LSB (ideal)

code

out

offset

error

gain

error

offset error

VIA (LSB

ideal

)

002aae604

i(VREF)

− V

SSA

1024

1 LSB =

LPC2458

Single-chip 16-bit/32-bit micro

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

L(adj)

(3) Differential linearity error (E

(4) Integral non-linearity (E

(5) Center of a step of the actual transfer curve.

Fig 18. ADC characteristics

Product data sheet Rev. 4.2 — 15 October 2020 62 of 81

NXP Semiconductors

LPC2XXX

AD0[y]

SAMPLE

AD0[y]

20 kΩ

3 pF

5 pF

vsi

SSIO, VSSCORE

EXT

002aad586

Fig 19. Suggested ADC interface - LPC2458 AD0[y] pin

LPC2458

Single-chip 16-bit/32-bit micro

Product data sheet Rev. 4.2 — 15 October 2020 63 of 81

NXP Semiconductors

13. DAC electrical characteristics

LPC2458

Single-chip 16-bit/32-bit micro

Table 19. DAC electrical characteristics

= 3.0 V to 3.6 V; T

DDA

=40C to +85C unless otherwise specified

amb

Symbol Parameter Conditions Min Typ Max Unit

L(adj)

differential linearity error - 1- LSB

integral non-linearity - 1.5 - LSB

offset error - 0.6 - %

gain error - 0.6 - %

load capacitance - 200 - pF

load resistance 1 - - k

Product data sheet Rev. 4.2 — 15 October 2020 64 of 81

NXP Semiconductors

LPC24XX

USB-B connector

USB_D+

USB_CONNECT

soft-connect switch

USB_D−

BUS

SSIO, VSSCORE

DD(3V3)

1.5 kΩ

RS = 33 Ω

002aad587

RS = 33 Ω

USB_UP_LED

LPC24XX

DD(3V3)

1.5 kΩ

USB_UP_LED

002aad588

USB-B connector

USB_D+ USB_D−

BUS

SSIO, VSSCORE

RS = 33 Ω RS = 33 Ω

14. Application information

14.1 Suggested USB interface solutions

LPC2458

Single-chip 16-bit/32-bit micro

Fig 20. LPC2458 USB interface on a self-powered device

Fig 21. LPC2458 USB interface on a bus-powered device

Product data sheet Rev. 4.2 — 15 October 2020 65 of 81

NXP Semiconductors

USB_UP_LED1

USB_D+1 USB_D−1

USB_PWRD2

USB_SDA1

USB_SCL1

RSTOUT

15 kΩ 15 kΩ

LPC24XX

USB-A connector

Mini-AB connector

33 Ω

USB_UP_LED2

USB_OVRCR2

LM3526-L

ENA

5 V

OUTA FLAGA

D+ D−

BUS

USB_PPWR2

USB_D+2

USB_D−2

002aad589

R4 R5 R6

R1 R2 R3 R4

USB_INT1

RESET_N ADR/PSW

SPEED

SUSPEND

OE_N/INT_N

SCL

SDA

INT_N

BUS

ID DP

ISP1302

SSIO,

SSCORE

SSIO,

SSCORE

LPC2458

Single-chip 16-bit/32-bit micro

Fig 22. LPC2458 USB OTG port configuration: USB port 1 OTG dual-role device, USB port 2 host

Product data sheet Rev. 4.2 — 15 October 2020 66 of 81

NXP Semiconductors

USB_TX_DP1 USB_TX_DM1

USB_RCV1 USB_RX_DP1 USB_RX_DM1

USB_SCL1 USB_SDA1

SPEED

ADR/PSW

SDA

SCL

RESET_N

INT_N

SUSPEND

OE_N/INT_N

SE0_VM

DAT_VP

RCV

BUS

ID DP DM

LPC24XX

ISP1302

USB MINI-AB connector

33 Ω

002aad590

USB_TX_E1

RSTOUT

USB_INT1

USB_UP_LED1

SSIO,

SSCORE

LPC2458

Single-chip 16-bit/32-bit micro

Fig 23. LPC2458 USB OTG port configuration: VP_VM mode

Product data sheet Rev. 4.2 — 15 October 2020 67 of 81

NXP Semiconductors

USB_UP_LED1

USB_D+1 USB_D−1

USB_PWRD1

15 kΩ 15 kΩ

LPC24XX

USB-A connector

USB-B connector

33 Ω

002aad595

USB_UP_LED2

USB_CONNECT2

USB_OVRCR1 USB_PPWR1

LM3526-L

ENA

5 V

FLAGA OUTA

D+ D−

BUS

USB_D+2

USB_D−2

BUS

SSIO,

SSCORE

SSIO,

SSCORE

LPC2458

Single-chip 16-bit/32-bit micro

Fig 24. LPC2458 USB OTG port configuration: USB port 2 device, USB port 1 host

Product data sheet Rev. 4.2 — 15 October 2020 68 of 81

NXP Semiconductors

USB_UP_LED1

USB_D+1 USB_D−1

USB_PWRD1

USB_PWRD2

15 kΩ

15 kΩ 15 kΩ

15 kΩ

LPC24XX

USB-A connector

33 Ω

002aad596

USB_UP_LED2

USB_OVRCR1

USB_OVRCR2

USB_PPWR1

LM3526-L

ENA

ENB

5 V

FLAGA OUTA

OUTB FLAGB

D+ D−

BUS

USB_PPWR2

USB_D+2

USB_D−2

SSIO,

SSCORE

SSIO,

SSCORE

LPC2xxx

XTAL1

100 pF

002aae718

LPC2458

Single-chip 16-bit/32-bit micro

which attenuates the input voltage by a factor Ci / (Ci + Cg). In

Fig 25. LPC2458 USB OTG port configuration: USB port 1 host, USB port 2 host

14.2 Crystal oscillator XTAL input and component selection

Product data sheet Rev. 4.2 — 15 October 2020 69 of 81

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with C

= 100 pF. To limit the input voltage to the specified range, choose an additional

capacitor to ground C slave mode, a minimum of 200 mV (RMS) is needed.

Fig 26. Slave mode operation of the on-chip oscillator

NXP Semiconductors

In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure 26 corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTAL2 pin in this configuration can be left unconnected.

LPC2458

Single-chip 16-bit/32-bit micro

), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This

External components and models used in oscillation mode are shown in

Figure 27 and in Ta bl e 2 0 and Tab l e 2 1. Since the feedback resistance is integrated on chip, only a crystal

and the capacitances C fundamental mode oscillation (the fundamental frequency is represented by L, C R

). Capacitance CP in Figure 27 represents the parallel package capacitance and should

not be larger than 7 pF. Parameters F

and CX2 need to be connected externally in case of

, CL, RS and CP are supplied by the crystal

OSC

and

manufacturer.

LPC2xxx

XTAL1 XTAL2

XTAL

Fig 27. Oscillator modes and models: oscillation mode of operation and external crystal

model used for CX1/CX2 evaluation

002aag46

Table 20. Recommended values for C

in oscillation mode (crystal and external

X1/CX2

components parameters): low frequency mode

Fundamental oscillation frequency F

OSC

Crystal load capacitance C

Maximum crystal series resistance R

External load capacitors C

X1/CX2

1 MHz to 5 MHz 10 pF < 300  18 pF, 18 pF

20 pF < 300  39 pF, 39 pF

30 pF < 300  57 pF, 57 pF

5 MHz to 10 MHz 10 pF < 300  18 pF, 18 pF

20 pF < 200  39 pF, 39 pF

30 pF < 100  57 pF, 57 pF

10 MHz to 15 MHz 10 pF < 160  18 pF, 18 pF

20 pF < 60  39 pF, 39 pF

15 MHz to 20 MHz 10 pF < 80  18 pF, 18 pF

Product data sheet Rev. 4.2 — 15 October 2020 70 of 81

NXP Semiconductors

002aaf495

LPC2xxx

RTCX1 RTCX2

32 kHz XTAL

Table 21. Recommended values for CX1/C

Fundamental oscillation frequency F

15 MHz to 20 MHz 10 pF < 180  18 pF, 18 pF

20 MHz to 25 MHz 10 pF < 160  18 pF, 18 pF

14.3 RTC 32 kHz oscillator component selection

in oscillation mode (crystal and external

components parameters): high frequency mode

OSC

Crystal load capacitance C

Maximum crystal series resistance R

20 pF < 100  39 pF, 39 pF

20 pF < 80  39 pF, 39 pF

LPC2458

Single-chip 16-bit/32-bit micro

External load capacitors CX1,

CX2

Fig 28. RTC oscillator modes and models: oscillation mode of operation and external

crystal model used for CX1/CX2 evaluation

The RTC external oscillator circuit is shown in Figure 28. Since the feedback resistance is integrated on chip, only a crystal, the capacitances C

and CX2 need to be connected

externally to the microcontroller.

Ta bl e 2 2 gives the crystal parameters that should be used. CL is the typical load

capacitance of the crystal and is usually specified by the crystal manufacturer. The actual C

influences oscillation frequency. When using a crystal that is manufactured for a

different load capacitance, the circuit will oscillate at a slightly different frequency (depending on the quality of the crystal) compared to the specified one. Therefore for an accurate time reference it is advised to use the load capacitors as specified in that belong to a specific C

. The value of external capacitances CX1 and CX2 specified in

this table are calculated from the internal parasitic capacitances and the C

Ta bl e 2 2

. Parasitics

from PCB and package are not taken into account.

Table 22. Recommended values for the RTC external 32 kHz oscillator C

Crystal load capacitance C

11 pF < 100 k 18 pF, 18 pF

Maximum crystal series resistance R

External load capacitors CX1/C

13 pF < 100 k 22 pF, 22 pF

15 pF < 100 k 27 pF, 27 pF

X1/CX2

components

Product data sheet Rev. 4.2 — 15 October 2020 71 of 81

NXP Semiconductors

ESD

weak pull-up

weak pull-down

output enable

output

pull-up enable

pull-down enable

data input

analog input

select analog input

002aaf496

pin configured

as digital output

driver

pin configured

as digital input

pin configured

as analog input

14.4 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines

The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors C third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plain. Loops must be made as small as possible in order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of C accordingly to the increase in parasitics of the PCB layout.

14.5 Standard I/O pin configuration

Figure 29 shows the possible pin modes for standard I/O pins with analog input function:

• Digital output driver

• Digital input: Pull-up enabled/disabled

• Digital input: Pull-down enabled/disabled

• Analog input (for ADC input channels)

The default configuration for standard I/O pins is input with pull-up enabled. The weak MOS devices provide a drive capability equivalent to pull-up and pull-down resistors.

LPC2458

Single-chip 16-bit/32-bit micro

, Cx2, and Cx3 in case of

and Cx2 should be chosen smaller

Fig 29. Standard I/O pin configuration with analog input

Product data sheet Rev. 4.2 — 15 October 2020 72 of 81

NXP Semiconductors

reset

002aaf274

ESD

20 ns RC

GLITCH FILTER

14.6 Reset pin configuration

Fig 30. Reset pin configuration

LPC2458

Single-chip 16-bit/32-bit micro

Product data sheet Rev. 4.2 — 15 October 2020 73 of 81

NXP Semiconductors

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

SOT570-3

08-07-09 10-04-15

UNIT

max nom

min

1.20

1.06

0.95

0.40

0.35

0.30

0.50

0.45

0.40

12.1

12.0

11.9

12.1

12.0

11.9

0.8 10.4 0.15 0.12

DIMENSIONS (mm are the original dimensions)

TFBGA180: thin fine-pitch ball grid array package; 180 balls

0 5 10 mm

scale

A1A

0.80

0.71

0.65

b D E e e

10.4

v w

0.05

y y

0.1

ball A1 index area

2468101214

135791113

1/2 e

∅ v

C∅ w

ball A1 index area

detail X

15. Package outline

LPC2458

Single-chip 16-bit/32-bit micro

Fig 31. Package outline SOT570-3 (TFBGA180)

Product data sheet Rev. 4.2 — 15 October 2020 74 of 81

NXP Semiconductors

DIMENSIONS in mm

PSLSPSRHxHy

SOT570-3

solder land plus solder paste

occupied area

Footprint information for reflow soldering of TFBGA180 package

solder land

solder paste deposit

solder resist

SL SP SR

Generic footprint pattern

Refer to the package outline drawing for actual layout

detail X

see detail X

sot570-3_fr

0.80 0.400 0.400 0.550 12.575 12.575

16. Soldering

LPC2458

Single-chip 16-bit/32-bit micro

Fig 32. Reflow soldering of the TFBGA180 package

Product data sheet Rev. 4.2 — 15 October 2020 75 of 81

NXP Semiconductors

17. Abbreviations

Table 23. Acronym list

Acronym Description

ADC Analog-to-Digital Converter

AHB Advanced High-performance Bus

AMBA Advanced Microcontroller Bus Architecture

APB Advanced Peripheral Bus

BOD BrownOut Detection

CAN Controller Area Network

DAC Digital-to-Analog Converter

DCC Debug Communication Channel

DMA Direct Memory Access

EOP End Of Packet

ETM Embedded Trace Macrocell

GPIO General Purpose Input/Output

IrDA Infrared Data Association

JTAG Joint Test Action Group

MII Media Independent Interface

OHC Open Host Controller

OHCI Open Host Controller Interface

OTG On-The-Go

PHY PHYsical Layer

PLL Phase-Locked Loop

PWM Pulse Width Modulator

RMII Reduced Media Independent Interface

SD/MMC Secure Digital/MultiMediaCard

SE0 Single Ended Zero

SPI Serial Peripheral Interface

SSI Synchronous Serial Interface

SSP Synchronous Serial Port

TTL Transistor-Transistor Logic

UART Universal Asynchronous Receiver/Transmitter

USB Universal Serial Bus

LPC2458

Single-chip 16-bit/32-bit micro

Product data sheet Rev. 4.2 — 15 October 2020 76 of 81

NXP Semiconductors

LPC2458

Single-chip 16-bit/32-bit micro

18. Revision history

Table 24. Revision history

Document ID Release date Data sheet status Change notice Supersedes

LPC2458 v.4.2 20201009 Product data sheet LPC2458 v.4.1

Modifications:

LPC2458 v.4.1 <tbd> Product data sheet - LPC2458 v.4

Modifications:

LPC2458 v.4 20110901 Product data sheet - LPC2458 v.3

Modifications:

LPC2458 v.3 20101005 Product data sheet - LPC2458 v.2

LPC2458 v.2 20081125 Product data sheet - LPC2458 v.1

LPC2458 v.1 20080623 Product data sheet - -

Table 17 “Dynamic characteristics: Dynamic external memory interface”: Updated T

/2 for most parameters.

cy(CCLK)

• Table 4 “Pin description”, Table note 6: Changed glitch filter spec from 5 ns to 10 ns.

• Table 10 “Dynamic characteristics”: Changed min clock cycle time from 42 to 40.

• Table 17 “Dynamic characteristics: Dynamic external memory interface”: Changed t

and max.

• SOT570-2 obsolete; replaced with SOT570-3.

• Table 4 “Pin description”: Updated description for USB_UP_LED1 and USB_UP_LED2.

• Table 6 “Limiting values”: Added “non-operating” to conditions column of T

stg

• Table 6 “Limiting values”: Updated Table note [5].

• Table 8 “Thermal resistance value (C/W): ±15 %”: Added new table.

• Table 9 “Static characteristics”: Changed V

typ value from 0.5V

hys

DD(3V3)

to 0.05V

• Table 14 “Dynamic characteristics of flash”: Updated table.

• Table 15 “Dynamic characteristics: Static external memory interface”: Removed “AHB clock

= 1 MHz”.

• Table 15 “Dynamic characteristics: Static external memory interface”: Swapped min/max

values for tam.

• Table 15 “Dynamic characteristics: Static external memory interface”: Updated t

spec.

• Table 16 “Dynamic characteristics: Dynamic external memory interface”: Removed “AHB

clock = 1 MHz”.

• Table 17 “Dynamic characteristics: Dynamic external memory interface”: Added new table.

• Section 14.5 “Standard I/O pin configuration” Updated bullets.

cy(CCLK)

d(QV)

DD(3V3)

WEHDNV

typ

Product data sheet Rev. 4.2 — 15 October 2020 77 of 81

NXP Semiconductors

LPC2458

Single-chip 16-bit/32-bit micro

19. Legal information

19.1 Data sheet status

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

[1][2]

Product status

[3]

Definition

19.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

19.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.

NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.

http://www.nxp.com/profile/terms, unless otherwise

Product data sheet Rev. 4.2 — 15 October 2020 78 of 81

NXP Semiconductors

LPC2458

Single-chip 16-bit/32-bit micro

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

19.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

C-bus — logo is a trademark of NXP B.V.

20. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Product data sheet Rev. 4.2 — 15 October 2020 79 of 81

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21. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3

4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8

7 Functional description . . . . . . . . . . . . . . . . . . 20

7.1 Architectural overview . . . . . . . . . . . . . . . . . . 20

7.2 On-chip flash programming memory . . . . . . . 21

7.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 22

7.4 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.5 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 23

7.5.1 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 24

7.6 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 24

7.7 External memory controller. . . . . . . . . . . . . . . 24

7.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.8 General purpose DMA controller . . . . . . . . . . 25

7.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.9 Fast general purpose parallel I/O . . . . . . . . . . 26

7.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.10 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.11 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.11.1 USB device controller . . . . . . . . . . . . . . . . . . . 28

7.11.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.11.2 USB Host Controller . . . . . . . . . . . . . . . . . . . . 28

7.11.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.11.3 USB OTG Controller . . . . . . . . . . . . . . . . . . . . 29

7.11.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.12 CAN controller and acceptance filters . . . . . . 29

7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.13 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.14 10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.15 UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.16 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 31

7.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.17 SSP serial I/O controller . . . . . . . . . . . . . . . . . 31

7.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.18 SD/MMC card interface . . . . . . . . . . . . . . . . . 31

7.18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.19 I

C-bus serial I/O controller . . . . . . . . . . . . . . 32

LPC2458

Single-chip 16-bit/32-bit micro

7.19.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.20 I

7.20.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.21 General purpose 32-bit timers/external event

7.21.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.22 Pulse width modulator . . . . . . . . . . . . . . . . . . 34

7.22.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.23 Watchdog timer (WDT) . . . . . . . . . . . . . . . . . 35

7.23.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.24 RTC and battery RAM . . . . . . . . . . . . . . . . . . 35

7.24.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.25 Clocking and power control . . . . . . . . . . . . . . 36

7.25.1 Crystal oscillators. . . . . . . . . . . . . . . . . . . . . . 36

7.25.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 36

7.25.1.2 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . 36

7.25.1.3 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 37

7.25.2 PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.25.3 Wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . 37

7.25.4 Power control. . . . . . . . . . . . . . . . . . . . . . . . . 38

7.25.4.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.25.4.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.25.4.3 Power-down mode . . . . . . . . . . . . . . . . . . . . . 38

7.25.4.4 Deep power-down mode . . . . . . . . . . . . . . . . 39

7.25.4.5 Power domains . . . . . . . . . . . . . . . . . . . . . . . 39

7.26 System control . . . . . . . . . . . . . . . . . . . . . . . . 40

7.26.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.26.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 40

7.26.3 Code security (Code Read Protection - CRP) 40

7.26.4 AHB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.26.5 External interrupt inputs. . . . . . . . . . . . . . . . . 41

7.26.6 Memory mapping control . . . . . . . . . . . . . . . . 41

7.27 Emulation and debugging . . . . . . . . . . . . . . . 41

7.27.1 EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 41

7.27.2 Embedded trace. . . . . . . . . . . . . . . . . . . . . . . 42

7.27.3 RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 43

9 Thermal characteristics . . . . . . . . . . . . . . . . . 44

10 Static characteristics . . . . . . . . . . . . . . . . . . . 45

10.1 Power-down mode . . . . . . . . . . . . . . . . . . . . . 48

10.2 Deep power-down mode . . . . . . . . . . . . . . . . 49

10.3 Electrical pin characteristics. . . . . . . . . . . . . . 51

11 Dynamic characteristics. . . . . . . . . . . . . . . . . 52

11.1 Internal oscillators . . . . . . . . . . . . . . . . . . . . . 53

11.2 I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

11.3 USB interface. . . . . . . . . . . . . . . . . . . . . . . . . 53

11.4 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 54

S-bus serial I/O controllers . . . . . . . . . . . . . 32

counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

T D

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continued >>

Product data sheet Rev. 4.2 — 15 October 2020 80 of 81

NXP Semiconductors

11.5 Static external memory interface . . . . . . . . . . 55

11.6 Dynamic external memory interface . . . . . . . . 57

11.7 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

12 ADC electrical characteristics . . . . . . . . . . . . 61

13 DAC electrical characteristics . . . . . . . . . . . . 64

14 Application information. . . . . . . . . . . . . . . . . . 65

14.1 Suggested USB interface solutions . . . . . . . . 65

14.2 Crystal oscillator XTAL input and component

selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

14.3 RTC 32 kHz oscillator component selection . . 71

14.4 XTAL and RTCX Printed Circuit Board (PCB)

layout guidelines. . . . . . . . . . . . . . . . . . . . . . . 72

14.5 Standard I/O pin configuration . . . . . . . . . . . . 72

14.6 Reset pin configuration. . . . . . . . . . . . . . . . . . 73

15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 74

16 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

17 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 76

18 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 77

19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 78

19.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 78

19.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

19.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

19.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 79

20 Contact information. . . . . . . . . . . . . . . . . . . . . 79

21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

LPC2458

Single-chip 16-bit/32-bit micro

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 15 October 2020

Document identifier: LPC2458

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

NXP: LPC2458FET180,551

NXP LPC2458 data sheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1. General description

2. Features and benefits

3. Applications

4. Ordering information

4.1 Ordering options

5. Block diagram

6. Pinning information

6.1 Pinning

6.2 Pin description

7. Functional description

7.1 Architectural overview

7.2 On-chip flash programming memory

7.3 On-chip SRAM

7.4 Memory map

7.5 Interrupt controller

7.5.1 Interrupt sources

7.6 Pin connect block

7.7 External memory controller

7.7.1 Features

7.8 General purpose DMA controller

7.8.1 Features

7.9 Fast general purpose parallel I/O

7.9.1 Features

7.10 Ethernet

7.10.1 Features

7.11 USB interface

7.11.1 USB device controller

7.11.1.1 Features

7.11.2 USB Host Controller

7.11.2.1 Features

7.11.3 USB OTG Controller

7.11.3.1 Features

7.12 CAN controller and acceptance filters

7.12.1 Features

7.13 10-bit ADC

7.13.1 Features

7.14 10-bit DAC

7.14.1 Features

7.15 UARTs

7.15.1 Features

7.16 SPI serial I/O controller

7.16.1 Features

7.17 SSP serial I/O controller

7.17.1 Features

7.18 SD/MMC card interface

7.18.1 Features

7.19 I2C-bus serial I/O controller

7.19.1 Features

7.20 I2S-bus serial I/O controllers

7.20.1 Features

7.21 General purpose 32-bit timers/external event counters

7.21.1 Features

7.22 Pulse width modulator

7.22.1 Features

7.23 Watchdog timer (WDT)

7.23.1 Features

7.24 RTC and battery RAM

7.24.1 Features

7.25 Clocking and power control

7.25.1 Crystal oscillators

7.25.1.1 Internal RC oscillator

7.25.1.2 Main oscillator

7.25.1.3 RTC oscillator

7.25.2 PLL

7.25.3 Wake-up timer

7.25.4 Power control

7.25.4.1 Idle mode

7.25.4.2 Sleep mode

7.25.4.3 Power-down mode

7.25.4.4 Deep power-down mode

7.25.4.5 Power domains

7.26 System control

7.26.1 Reset

7.26.2 Brownout detection

7.26.3 Code security (Code Read Protection - CRP)

7.26.4 AHB