NXP LPC 2194 HBD64 Datasheet

LPC2194

Single-chip 16/32-bit microcontroller; 256 kB ISP/IAP flash
with 10-bit ADC and CAN

Rev. 05 — 10 December 2007 Product data sheet

1. General description

The LPC2194 is based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and
embedded trace support, together with 256 kB of embedded high-speed flash memory. A
128-bit wide memory interface and a unique accelerator architecture enable 32-bit code
execution at maximum clock rate. For critical code size applications, the alternative 16-bit
Thumb mode reduces code by more than 30 % with minimal performance penalty.

With its compact 64-pin package, low power consumption, various 32-bit timers,
4-channel 10-bit ADC, four advanced CAN channels, PWM channels and 46 fast GPIO
lines with up to nine external interrupt pins this microcontroller is particularly suitable for
automotive applications such as a CAN gateway that connects several CAN busses or a
CAN bridge between sub networks at different speeds. Sensors with CAN interface or
debugging via CANare additional applications that need more than two CAN interfaces. It
is also an adequate solution for industrial control, medical systems and fault-tolerant
maintenance buses. With a wide range of additional serial communications interfaces, it is
also suited for communication gateways and protocol converters as well as many other
general-purpose applications.

2. Features

2.1 Key features brought by LPC2194/01 devices

Remark: Throughout the data sheet, the term LPC2194 will apply to devices with and

without the /00 or /01 suffixes. The /00 or the /01 suffix will be used to differentiate from
other devices only when necessary.

n FastGPIO ports enable port pin toggling up to 3.5 times faster than the original device.

They also allow for a port pin to be read at any time regardless of its function.

n Dedicated result registers for ADC(s) reduce interrupt overhead. The ADC pads are

5 V tolerant when configured for digital I/O function(s).

n UART0/1 include fractional baud rate generator, auto-bauding capabilities and

handshake flow-control fully implemented in hardware.

n Buffered SSP serial controller supporting SPI, 4-wire SSI, and Microwire formats.
n SPI programmable data length and master mode enhancement.
n Diversified Code Read Protection (CRP) enables different security levels to be

implemented. This feature is available in LPC2194/00 devices as well.

n General purpose timers can operate as external event counters.

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2.2 Key features common for all devices

n 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.
n 16 kB on-chip SRAM and 256 kB on-chip flash program memory. 128-bit wide

n In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

n EmbeddedICE-RT and Embedded Trace interfaces offer real-time debugging with

n Fourinterconnected CAN interfaceswith advanced acceptance filters. Additional serial

n Four channel 10-bit ADC with conversion time as low as 2.44 µs.
n Two 32-bit timers (with four capture and four compare channels), PWM unit (six

n Vectored Interrupt Controller with configurable priorities and vector addresses.
n Up to forty-six 5 V tolerant general purpose I/O pins. Up to nine edge or level sensitive

n Operating temperature range from −40 °C to +125 °C.
n 60 MHz maximum CPU clock available from programmable on-chip Phase-Locked

n On-chip crystal oscillator with an operating range of 1 MHz to 30 MHz.
n Two low power modes, Idle and Power-down.
n Processor wake-up from Power-down mode via external interrupt.
n Individual enable/disable of peripheral functions for power optimization.
n Dual power supply:

LPC2194

Single-chip 16/32-bit microcontroller

interface/accelerator enables high speed 60 MHz operation.

bootloader software. Flash programming takes 1 ms per 512 B line. Single sector or
full chip erase takes 400 ms.

on-chip RealMonitor software as well as high speed real-time tracing of instruction
execution.

interfaces are two UARTs (16C550), Fast I2C-bus (400 kbit/s) and two SPIs.

outputs), Real-Time Clock and Watchdog.

external interrupt pins available.

Loop with settling time of 100 µs.

u CPU operating voltage range of 1.65 V to 1.95 V (1.8 V ± 0.15 V).
u I/O power supply range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O pads.

3. Ordering information

Table 1. Ordering information

Type number Package

Name Description Version

LPC2194HBD64 LQFP64 plastic low profile quad flat package; 64 leads;

body 10 × 10 × 1.4 mm

LPC2194HBD64/00 LQFP64 plastic low profile quad flat package; 64 leads;

body 10 × 10 × 1.4 mm

LPC2194HBD64/01 LQFP64 plastic low profile quad flat package; 64 leads;

body 10 × 10 × 1.4 mm

LPC2194_5 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 05 — 10 December 2007 2 of 40

SOT314-2

SOT314-2

SOT314-2

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4. Block diagram

TRST

TMS

(2)

(2)

TCK

TDI

(2)

(2)

TDO

RTCK

(2)

LPC2194

Single-chip 16/32-bit microcontroller

XTAL2

XTAL1

RESET

P0[30:27],

P0[25:0]

P1[31:16]

EINT[3:0]

4 × CAP0
4 × CAP1
4 × MAT0
4 × MAT1

LPC2194

HIGH-SPEED

GPI/O

46 PINS TOTAL

ARM7 LOCAL BUS

INTERNAL

SRAM

CONTROLLER

16 kB

SRAM

(3)

INTERNAL

FLASH

CONTROLLER

256 kB
FLASH

INTERFACE

ARM7TDMI-S

AHB BRIDGE

AHB TO APB

BRIDGE

system

EMULATION

clock

TRACE MODULE

PLL

FUNCTIONS

VECTORED

INTERRUPT

CONTROLLER

AMBA Advanced High-performance

Bus (AHB)

APB

DIVIDER

2

I

C-BUS SERIAL

DECODER

SYSTEM

AHB

INTERFACE

TEST/DEBUG

(1)

(1)
(1)
(1)
(1)

EXTERNAL

INTERRUPTS

CAPTURE/
COMPARE

TIMER 0/TIMER 1

SPI1/SSP

(3)

SERIAL

INTERFACE

SPI0 SERIAL

INTERFACE

V

DD(3V3)

V

DD(1V8)

V

SS

SCL

SDA
SCK1

MOSI1
MISO1
SSEL1

SCK0
MOSI0
MISO0
SSEL0

(1)

(1)

(1)

(1)
(1)
(1)

(1)

(1)
(1)
(1)

AIN[3:0]

P0[30:27],

P0[25:0]

P1[31:16]

PWM[6:1]

RD[4:1]

TD[4:1]

(1)

A/D CONVERTER

UART0/UART1

GENERAL

PURPOSE I/O

(1)

(1)
(1)

CAN INTERFACE 1, 2, 3 AND 4

PWM0

ACCEPTANCE FILTERS

WATCHDOG

TIMER

SYSTEM

CONTROL

REAL-TIME CLOCK

002aad178

TXD[1:0]
RXD[1:0]

(1)

DSR1

(1)

RTS1

(1)

DCD1

(1)

(1)

, CTS1

, DTR1

, RI1

(1)

,

(1)

,

(1)

(1) Shared with GPIO.
(2) When test/debug interface is used, GPIO/other functions sharing these pins are not available.
(3) SSP interface and high-speed GPIO are available on LPC2194/01 only.

Fig 1. Block diagram

LPC2194_5 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 05 — 10 December 2007 3 of 40

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5. Pinning information

5.1 Pinning

LPC2194

Single-chip 16/32-bit microcontroller

DDA(1V8)

P1[27]/TDO

V

646362616059585756555453525150

P0[21]/PWM5/RD3/CAP1[3] P1[20]/TRACESYNC

P0[22]/TD3/CAP0[0]/MAT0[0] P0[17]/CAP1[2]/SCK1/MAT1[2]

P0[23]/RD2 P0[16]/EINT0/MAT0[2]/CAP0[2]

P1[19]/TRACEPKT3 P0[15]/RI1/EINT2

P0[24]/TD2 P1[21]/PIPESTAT0

V

DDA(3V3)

P1[18]/TRACEPKT2 P0[14]/DCD1/EINT1

P0[25]/RD1 P1[22]/PIPESTAT1

P0[27]/AIN0/CAP0[1]/MAT0[1] P0[12]/DSR1/MAT1[0]/RD4

P1[17]/TRACEPKT1 P0[11]/CTS1/CAP1[1]
P0[28]/AIN1/CAP0[2]/MAT0[2] P1[23]/PIPESTAT2
P0[29]/AIN2/CAP0[3]/MAT0[3] P0[10]/RTS1/CAP1[0]

P0[30]/AIN3/EINT3/CAP0[0] P0[9]/RXD1/PWM6/EINT3

P1[16]/TRACEPKT0 P0[8]/TXD1/PWM4

1
2
3
4
5
6

V

SS

7
8
9

10

TD1 P0[13]/DTR1/MAT1[1]/TD4

11
12
13
14
15
16

171819202122232425262728293031

SS

V

DD(1V8)

V

P0[0]/TXD0/PWM1 XTAL1

P1[31]/TRST XTAL2

P0[1]/RXD0/PWM3/EINT0 P1[28]/TDI

SSA

SSA(PLL)

V

LPC2194
LPC2194/00
LPC2194/01

DD(3V3)

V

P1[26]/RTCK RESET

P0[2]/SCL/CAP0[0] V

DD(3V3)

P1[29]/TCK

SS

V

P1[25]/EXTIN0 P0[18]/CAP1[3]/MISO1/MAT1[3]

P0[4]/SCK0/CAP0[1] P0[19]/MAT1[2]/MOSI1/CAP1[2]

P0[3]/SDA/MAT0[0]/EINT1 P0[20]/MAT1[3]/SSEL1/EINT3

SS

P0[6]/MOSI0/CAP0[2] V

P0[5]/MISO0/MAT0[1] P1[30]/TMS

P0[7]/SSEL0/PWM2/EINT2 V

DD(1V8)

49

32

P1[24]/TRACECLK V

48
47
46
45
44
43

V

DD(3V3)

42

V

SS

41
40
39
38
37
36
35
34
33

002aad179

Fig 2. Pin configuration

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Product data sheet Rev. 05 — 10 December 2007 4 of 40

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LPC2194

Single-chip 16/32-bit microcontroller

5.2 Pin description

Table 2. Pin description

Symbol Pin Type Description

P0[0] to P0[31] I/O Port 0 is a 32-bit bidirectional I/O port with individual direction controls for each bit.

The operation of port 0 pins depends upon the pin function selected via the Pin
Connect Block. Pins 26 and 31 of port 0 are not available.

P0[0]/TXD0/
PWM1

P0[1]/RXD0/
PWM3/EINT0

P0[2]/SCL/
CAP0[0]

P0[3]/SDA/
MAT0[0]/EINT1

P0[4]/SCK0/
CAP0[1]

P0[5]/MISO0/
MAT0[1]

P0[6]/MOSI0/
CAP0[2]

P0[7]/SSEL0/
PWM2/EINT2

P0[8]/TXD1/
PWM4

P0[9]/RXD1/
PWM6/EINT3

P0[10]/RTS1/
CAP1[0]

P0[11]/CTS1/
CAP1[1]

P0[12]/DSR1/
MAT1[0]/RD4

P0[13]/DTR1/
MAT1[1]/TD4

19 O TXD0 — Transmitter output for UART0.

O PWM1 — Pulse Width Modulator output 1.

21 I RXD0 — Receiver input for UART0.

O PWM3 — Pulse Width Modulator output 3.
I EINT0 — External interrupt 0 input.

2

22 I/O SCL — I

I CAP0[0] — Capture input for Timer 0, channel 0.

26 I/O SDA — I

O MAT0[0] — Match output for Timer 0, channel 0.
I EINT1 — External interrupt 1 input.

27 I/O SCK0 — Serial clock for SPI0. SPI clock output from master or input to slave.

I CAP0[1] — Capture input for Timer 0, channel 1.

29 I/O MISO0 — Master In Slave Out for SPI0. Data input to SPI master or data output

from SPI slave.

O MAT0[1] — Match output for Timer 0, channel 1.

30 I/O MOSI0 — Master Out Slave In for SPI0. Data output from SPI master or data input

to SPI slave.

I CAP0[2] — Capture input for Timer 0, channel 2.

31 I SSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave.

O PWM2 — Pulse Width Modulator output 2.
I EINT2 — External interrupt 2 input.

33 O TXD1 — Transmitter output for UART1.

O PWM4 — Pulse Width Modulator output 4.

34 I RXD1 — Receiver input for UART1.

O PWM6 — Pulse Width Modulator output 6.
I EINT3 — External interrupt 3 input.

35 O RTS1 — Request to Send output for UART1.

I CAP1[0] — Capture input for Timer 1, channel 0.

37 I CTS1 — Clear to Send input for UART1.

I CAP1[1] — Capture input for Timer 1, channel 1.

38 I DSR1 — Data Set Ready input for UART1.

O MAT1[0] — Match output for Timer 1, channel 0.
O RD4 — CAN4 receiver input.

39 O DTR1 — Data Terminal Ready output for UART1.

O MAT1[1] — Match output for Timer 1, channel 1.
O TD4 — CAN4 transmitter output.

C-bus clock input/output. Open-drain output (for I2C-bus compliance).

2

C-bus data input/output. Open-drain output (for I2C-bus compliance).

LPC2194_5 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 05 — 10 December 2007 5 of 40

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LPC2194

Single-chip 16/32-bit microcontroller

Table 2. Pin description

Symbol Pin Type Description

P0[14]/DCD1/
EINT1

P0[15]/RI1/EINT2 45 I RI1 — Ring Indicator input for UART1.

P0[16]/EINT0/
MAT0[2]/CAP0[2]

P0[17]/CAP1[2]/
SCK1/MAT1[2]

P0[18]/CAP1[3]/
MISO1/MAT1[3]

P0[19]/MAT1[2]/
MOSI1/CAP1[2]

P0[20]/MAT1[3]/
SSEL1/EINT3

P0[21]/PWM5/
RD3/CAP1[3]

P0[22]/TD3/
CAP0[0]/MAT0[0]

P0[23]/RD2 3 I CAN2 receiver input.
P0[24]/TD2 5 O CAN2 transmitter output.
P0[25]/RD1 9 O CAN1 receiver input.
P0[27]/AIN0/

CAP0[1]/MAT0[1]

P0[28]/AIN1/
CAP0[2]/MAT0[2]

P0[29]/AIN2/
CAP0[3]/MAT0[3]

…continued

41 I DCD1 — Data Carrier Detect input for UART1.

I EINT1 — External interrupt 1 input.

Note: LOW on this pin while
control of the part after reset.

I EINT2 — External interrupt 2 input.

46 I EINT0 — External interrupt 0 input.

O MAT0[2] — Match output for Timer 0, channel 2.
I CAP0[2] — Capture input for Timer 0, channel 2.

47 I CAP1[2] — Capture input for Timer 1, channel 2.

I/O SCK1 — Serial Clock for SPI1/SSP

slave.

O MAT1[2] — Match output for Timer 1, channel 2.

53 I CAP1[3] — Capture input for Timer 1, channel 3.

I/O MISO1 — Master In Slave Out for SPI1/SSP

output from SPI slave.

O MAT1[3] — Match output for Timer 1, channel 3.

54 O MAT1[2] — Match output for Timer 1, channel 2.

I/O MOSI1 — Master Out Slave In for SPI1/SSP

input to SPI slave.

I CAP1[2] — Capture input for Timer 1, channel 2.

55 O MAT1[3] — Match output for Timer 1, channel 3.

I SSEL1 — Slave Select for SPI1/SSP
I EINT3 — External interrupt 3 input.

1OPWM5 — Pulse Width Modulator output 5.

I RD3 — CAN3 receiver input.
I CAP1[3] — Capture input for Timer 1, channel 3.

2OTD3 — CAN3 transmitter output.

I CAP0[0] — Capture input for Timer 0, channel 0.
O MAT0[0] — Match output for Timer 0, channel 0.

11 I AIN0 — A/D converter, input 0. This analog input is always connected to its pin.

I CAP0[1] — Capture input for Timer 0, channel 1.
O MAT0[1] — Match output for Timer 0, channel 1.

13 I AIN1 — A/D converter, input 1. This analog input is always connected to its pin.

I CAP0[2] — Capture input for Timer 0, channel 2.
O MAT0[2] — Match output for Timer 0, channel 2.

14 I AIN2 — A/D converter, input 2. This analog input is always connected to its pin.

I CAP0[3] — Capture input for Timer 0, Channel 3.
O MAT0[3] — Match output for Timer 0, channel 3.

RESET is LOW forces on-chip bootloader to take

[1]

. SPI clock output from master or input to

[1]

. Data input to SPI master or data

[1]

. Data output from SPI master or data

[1]

. Selects the SPI interface as a slave.

LPC2194_5 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 05 — 10 December 2007 6 of 40

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LPC2194

Single-chip 16/32-bit microcontroller

Table 2. Pin description

Symbol Pin Type Description

P0[30]/AIN3/
EINT3/CAP0[0]

P1[0] to P1[31] I/O Port 1 is a 32-bit bidirectional I/O port with individual direction controls for each bit.

P1[16]/
TRACEPKT0

P1[17]/
TRACEPKT1

P1[18]/
TRACEPKT2

P1[19]/
TRACEPKT3

P1[20]/
TRACESYNC

P1[21]/
PIPESTAT0

P1[22]/
PIPESTAT1

P1[23]/
PIPESTAT2

P1[24]/
TRACECLK

P1[25]/EXTIN0 28 I External Trigger Input. Standard I/O with internal pull-up.
P1[26]/RTCK 24 I/O Returned TestClock output. Extra signal added to the JTAG port. Assists debugger

P1[27]/TDO 64 O Test Data out for JTAG interface.
P1[28]/TDI 60 I Test Data in for JTAG interface.
P1[29]/TCK 56 I Test Clock for JTAG interface. This clock must be slower than

P1[30]/TMS 52 I Test Mode Select for JTAG interface.

TRST 20 I Test Reset for JTAG interface.

P1[31]/
TD1 10 O CAN1 transmitter output.
RESET 57 I external reset input; a LOW on this pin resets the device, causing I/O ports and

XTAL1 62 I input to the oscillator circuit and internal clock generator circuits.
XTAL2 61 O output from the oscillator amplifier.
V

SS

…continued

15 I AIN3 — A/D converter, input 3. This analog input is always connected to its pin.

I EINT3 — External interrupt 3 input.
I CAP0[0] — Capture input for Timer 0, channel 0.

The operation of port 1 pins depends upon the pin function selected via the Pin
Connect Block. Pins 0 through 15 of port 1 are not available.

16 O Trace Packet, bit 0. Standard I/O port with internal pull-up.

12 O Trace Packet, bit 1. Standard I/O port with internal pull-up.

8 O Trace Packet, bit 2. Standard I/O port with internal pull-up.

4 O Trace Packet, bit 3. Standard I/O port with internal pull-up.

48 O Trace Synchronization. Standard I/O port with internal pull-up.

Note: LOW on this pin while
Trace port after reset.

44 O Pipeline Status, bit 0. Standard I/O port with internal pull-up.

40 O Pipeline Status, bit 1. Standard I/O port with internal pull-up.

36 O Pipeline Status, bit 2. Standard I/O port with internal pull-up.

32 O Trace Clock. Standard I/O port with internal pull-up.

synchronization when processor frequency varies. Bidirectional pin with internal
pull-up.

Note: LOW on this pin while
Debug port after reset.

(CCLK) for the JTAG interface to operate.

peripherals to take on their default states, and processor execution to begin at
address 0. TTL with hysteresis, 5 V tolerant.

6, 18, 25,
42, 50

I ground: 0 V reference.

RESET is LOW, enables pins P1[25:16] to operate as

RESET is LOW, enables pins P1[31:26] to operate as

1

⁄6 of the CPU clock

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Product data sheet Rev. 05 — 10 December 2007 7 of 40

NXP Semiconductors

LPC2194

Single-chip 16/32-bit microcontroller

Table 2. Pin description

…continued

Symbol Pin Type Description

V

SSA

59 I analog ground; 0 V reference. This should nominally be the same voltage as VSS,

but should be isolated to minimize noise and error.

V

SSA(PLL)

V

DD(1V8)

V

DDA(1V8)

58 I PLL analog ground; 0 V reference. This should nominally be the same voltage as

V

, but should be isolated to minimize noise and error.

SS

17, 49 I 1.8 V core power supply; this is the power supply voltage for internal circuitry.
63 I analog 1.8 V core power supply; this is the power supply voltage for internal

circuitry. This should be nominally the same voltage as V
isolated to minimize noise and error.

V

DD(3V3)

V

DDA(3V3)

[1] SSP interface available on LPC2194/01 only.

23, 43, 51 I 3.3 V pad power supply; this is the power supply voltage for the I/O ports.
7 I analog 3.3 V pad power supply; this should be nominally the same voltage as

V

but should be isolated to minimize noise and error.

DD(3V3)

DD(1V8)

but should be

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Product data sheet Rev. 05 — 10 December 2007 8 of 40

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6. Functional description

Details of the LPC2194 systems and peripheral functions are described in the following
sections.

6.1 Architectural overview

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers. This simplicity results in a high instruction throughput and
impressive real-time interrupt response from a small and cost-effective processor core.

Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.

LPC2194

Single-chip 16/32-bit microcontroller

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:

• The standard 32-bit ARM set.

• A 16-bit Thumb set.

The Thumb set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because Thumb code
operates on the same 32-bit register set as ARM code.

Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the
performance of an equivalent ARM processor connected to a 16-bit memory system.

6.2 On-chip flash program memory

The LPC2194 incorporates a 256 kB flash memory system. This memory may be used for
both code and data storage. Programming of the flash memory may be accomplished in
several ways. It may be programmed In System via the serial port. The application
program may also erase and/or program the flash while the application is running,
allowing a great degree of flexibility for data storage field firmware upgrades, etc. When
on-chip bootloader is used, 248 kB of flash memory is available for user code.

The LPC2194 flash memory provides a minimum of 100000 erase/write cycles and 20
years of data retention.

On-chip bootloader (as of revision 1.60) provides Code Read Protection (CRP) for the
LPC2194 on-chip flash memory. When the CRP is enabled, the JTAG debug port and ISP
commands accessing either the on-chip RAM or flash memory are disabled. However, the

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Product data sheet Rev. 05 — 10 December 2007 9 of 40

NXP Semiconductors

ISP flash erase command can be executed at any time (no matter whether the CRP is on
or off). Removal of CRP is achievedby erasure of full on-chip user flash. With the CRP off,
full access to the chip via the JTAG and/or ISP is restored.

6.3 On-chip SRAM

On-chip SRAM may be used for code and/or data storage. The SRAM may be accessed
as 8 bit, 16 bit, and 32 bit. The LPC2194 provides 16 kB of SRAM.

6.4 Memory map

The LPC2194 memory maps incorporate several distinct regions, as shown in Figure 3.
In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either

flash memory (the default) or on-chip SRAM. This is described in Section 6.18 “System

control”.

LPC2194

Single-chip 16/32-bit microcontroller

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Product data sheet Rev. 05 — 10 December 2007 10 of 40

NXP Semiconductors

LPC2194

Single-chip 16/32-bit microcontroller

4.0 GB

3.75 GB

3.5 GB

3.0 GB

2.0 GB

1.0 GB

AHB PERIPHERALS

APB PERIPHERALS

RESERVED ADDRESS SPACE

BOOT BLOCK (RE-MAPPED FROM

ON-CHIP FLASH MEMORY)

RESERVED ADDRESS SPACE

16 kB ON-CHIP STATIC RAM

0xFFFF FFFF
0xF000 0000

0xEFFF FFFF
0xE000 0000

0xDFFF FFFF

0xC000 0000

0x8000 0000
0x7FFF FFFF

0x7FFF E000
0x7FFF DFFF

0x4000 4000
0x4000 3FFF

0x4000 0000
0x3FFF FFFF

RESERVED ADDRESS SPACE

0x0004 0000
0x0003 FFFF

256 kB ON-CHIP FLASH MEMORY

0.0 GB

0x0000 0000

002aad180

Fig 3. LPC2194 memory map

6.5 Interrupt controller

The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and
categorizes them as Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), and
non-vectored IRQ as defined by programmable settings. The programmable assignment
scheme means that priorities of interrupts from the various peripherals can be dynamically
assigned and adjusted.

FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC
combines the requests to produce the FIQ signal to the ARM processor. The fastest
possible FIQ latency is achieved when only one request is classified as FIQ, because then
the FIQ service routine can simply start dealing with that device. But if more than one
request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC
that identifies which FIQ source(s) is (are) requesting an interrupt.

LPC2194_5 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 05 — 10 December 2007 11 of 40

NXP Semiconductors

Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned
to this category. Any of the interrupt requests can be assigned to any of the 16 vectored
IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.

Non-vectored IRQs have the lowest priority.
The VIC combines the requests from all the vectored and non-vectored IRQs to produce

the IRQ signal to the ARM processor. The IRQ service routine can start by reading a
register from the VIC and jumping there. If any of the vectored IRQs are requesting, the
VIC provides the address of the highest-priority requesting IRQs service routine,
otherwise it provides the address of a default routine that is shared by all the non-vectored
IRQs. The default routine can read another VIC register to see what IRQs are active.

6.5.1 Interrupt sources

Table 3 lists the interrupt sources for each peripheral function. Each peripheral device has

one interrupt line connected to the Vectored Interrupt Controller, but may have several
internal interrupt flags. Individual interrupt flags may also represent more than one
interrupt source.

Table 3. Interrupt sources

Block Flag(s) VIC channel #

WDT Watchdog Interrupt (WDINT) 0

- Reserved for software interrupts only 1
ARM Core EmbeddedICE, DbgCommRx 2
ARM Core EmbeddedICE, DbgCommTx 3
Timer 0 Match 0 to 3 (MR0, MR1, MR2, MR3)

Timer 1 Match 0 to 3 (MR0, MR1, MR2, MR3)

UART0 Rx Line Status (RLS)

UART1 Rx Line Status (RLS)

PWM0 Match 0 to 3 (MR0, MR1, MR2, MR3, MR4, MR5, MR6) 8

2

C-bus SI (state change) 9

I
SPI0 SPIF, MODF 10
SPI1 and SSP
PLL PLL Lock (PLOCK) 12
RTC RTCCIF (Counter Increment), RTCALF (Alarm) 13

Single-chip 16/32-bit microcontroller

Capture 0 to 3 (CR0, CR1, CR2, CR3)

Capture 0 to 3 (CR0, CR1, CR2, CR3)

Transmit Holding Register empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)

Transmit Holding Register empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
Modem Status Interrupt (MSI)

[1]

SPIF, MODF and TXRIS, RXRIS, RTRIS, RORRIS 11

LPC2194

4

5

6

7

LPC2194_5 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 05 — 10 December 2007 12 of 40