NXP LPC 2138 FBD64 Datasheet

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers; 32/64/128/256/512 kB
ISP/IAP flash with 10-bit ADC and DAC

Rev. 04 — 16 October 2007 Product data sheet

1. General description

The LPC2131/32/34/36/38 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU
with real-time emulation and embedded trace support, that combine the microcontroller
with 32 kB, 64 kB, 128 kB, 256 kB and 512 kB of embedded high-speed flash memory. A
128-bit wide memory interface and a unique accelerator architecture enable 32-bit code
execution at maximum clock rate. For critical code size applications, the alternative 16-bit
Thumb mode reduces code by more than 30 % with minimal performance penalty.

Due to their tiny size and low power consumption, these microcontrollers are ideal for
applications where miniaturization is a key requirement, such as access control and
point-of-sale. With a wide range of serial communications interfaces and on-chip SRAM
options of 8 kB, 16 kB, and 32 kB, they are very well suited for communication gateways
and protocol converters, soft modems, voice recognition and low-end imaging, providing
both large buffer size and high processing power. Various 32-bit timers, single or dual
10-bit 8-channel ADC(s), 10-bit DAC, PWM channels and 47 GPIO lines with up to nine
edge or level sensitive external interrupt pins make these microcontrollers particularly
suitable for industrial control and medical systems.

2. Features

2.1 Enhancements brought by LPC213x/01 devices

2.2 Key features common for LPC213x and LPC213x/01

n Fast GPIO ports enable port pin toggling up to 3.5 times faster than the original

LPC213x. They also allow for a port pin to be read at any time regardless of its
function.

n Dedicated result registers for ADC(s) reduce interrupt overhead.
n UART0/1 include fractional baud rate generator, auto-bauding capabilities and

handshake flow-control fully implemented in hardware.

n Additional BOD control enables further reduction of power consumption.

n 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 or HVQFN package.
n 8/16/32 kB of on-chip static RAM and 32/64/128/256/512 kB of on-chip flash program

memory. 128-bit wide interface/accelerator enables high-speed 60 MHz operation.

n In-System Programming/In-ApplicationProgramming (ISP/IAP) via on-chip bootloader

software. Single flash sector or full chip erase in 400 ms and programming of 256 B in
1 ms.

n EmbeddedICE RT and Embedded Trace interfaces offer real-time debugging with the

on-chip RealMonitor software and high-speed tracing of instruction execution.

NXP Semiconductors

n One (LPC2131/32) or two (LPC2134/36/38) 8-channel 10-bit ADCs provide a total of

n Single 10-bit DAC provides variable analog output (LPC2132/34/36/38).
n Two 32-bit timers/external event counters (with four capture and four compare

n Low power Real-time clock with independent power and dedicated 32 kHz clock input.
n Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus (400 kbit/s),

n Vectored interrupt controller with configurable priorities and vector addresses.
n Up to forty-seven 5 V tolerant general purpose I/O pins in tiny LQFP64 or HVQFN

n Up to nine edge or level sensitive external interrupt pins available.
n 60 MHz maximum CPU clock available from programmable on-chip PLL with settling

n On-chip integrated oscillator operates with external crystal in range of 1 MHz to

n Power saving modes include Idle and Power-down.
n Individual enable/disable of peripheral functions as well as peripheral clock scaling

n Processor wake-up from Power-down mode via external interrupt or BOD.
n Single power supply chip with POR and BOD circuits:

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

up to 16 analog inputs, with conversion times as low as 2.44 µs per channel.

channels each), PWM unit (six outputs) and watchdog.

SPI and SSP with buffering and variable data length capabilities.

package.

time of 100 µs.

30 MHz and with external oscillator up to 50 MHz.

down for additional power optimization.

u CPU operating voltage range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O

pads.

3. Ordering information

Table 1. Ordering information

Type number Package

LPC2131FBD64 LQFP64 plastic low profile quad flat package; 64 leads;

LPC2131FBD64/01 LQFP64 plastic low profile quad flat package; 64 leads;

LPC2132FBD64 LQFP64 plastic low profile quad flat package; 64 leads;

LPC2132FBD64/01 LQFP64 plastic low profile quad flat package; 64 leads;

LPC2132FHN64 HVQFN64 plastic thermal enhanced very thin quad flat

LPC2132FHN64/01 HVQFN64 plastic thermal enhanced very thin quad flat

LPC2134FBD64 LQFP64 plastic low profile quad flat package; 64 leads;

LPC2134FBD64/01 LQFP64 plastic low profile quad flat package; 64 leads;

Name Description Version

SOT314-2

body 10 × 10 × 1.4 mm

SOT314-2

body 10 × 10 × 1.4 mm

SOT314-2

body 10 × 10 × 1.4 mm

SOT314-2

body 10 × 10 × 1.4 mm

SOT804-2
package; no leads; 64 terminals; body
9 × 9 × 0.85 mm

SOT804-2
package; no leads; 64 terminals; body
9 × 9 × 0.85 mm

SOT314-2
body 10 × 10 × 1.4 mm

SOT314-2
body 10 × 10 × 1.4 mm

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 2 of 39

NXP Semiconductors

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

Table 1. Ordering information

Type number Package

Name Description Version

LPC2136FBD64 LQFP64 plastic low profile quad flat package; 64 leads;

LPC2136FBD64/01 LQFP64 plastic low profile quad flat package; 64 leads;

LPC2138FBD64 LQFP64 plastic low profile quad flat package; 64 leads;

LPC2138FBD64/01 LQFP64 plastic low profile quad flat package; 64 leads;

LPC2138FHN64 HVQFN64 plastic thermal enhanced very thin quad flat

LPC2138FHN64/01 HVQFN64 plastic thermal enhanced very thin quad flat

…continued

body 10 × 10 × 1.4 mm

body 10 × 10 × 1.4 mm

body 10 × 10 × 1.4 mm

body 10 × 10 × 1.4 mm

package; no leads; 64 terminals; body
9 × 9 × 0.85 mm

package; no leads; 64 terminals; body
9 × 9 × 0.85 mm

3.1 Ordering options

Table 2. Ordering options

Type number Flash

memory

LPC2131FBD64 32 kB 8 kB 1 - no −40 °C to +85 °C
LPC2131FBD64/01 32 kB 8 kB 1 - yes −40 °C to +85 °C
LPC2132FBD64 64 kB 16 kB 1 1 no −40 °C to +85 °C
LPC2132FBD64/01 64 kB 16 kB 1 1 yes −40 °C to +85 °C
LPC2132FHN64 64 kB 16 kB 1 1 no −40 °C to +85 °C
LPC2132FHN64/01 64 kB 16 kB 1 1 yes −40 °C to +85 °C
LPC2134FBD64 128 kB 16 kB 2 1 no −40 °C to +85 °C
LPC2134FBD64/01 128 kB 16 kB 2 1 yes −40 °C to +85 °C
LPC2136FBD64 256 kB 32 kB 2 1 no −40 °C to +85 °C
LPC2136FBD64/01 256 kB 32 kB 2 1 yes −40 °C to +85 °C
LPC2138FBD64 512 kB 32 kB 2 1 no −40 °C to +85 °C
LPC2138FBD64/01 512 kB 32 kB 2 1 yes −40 °C to +85 °C
LPC2138FHN64 512 kB 32 kB 2 1 no −40 °C to +85 °C
LPC2138FHN64/01 512 kB 32 kB 2 1 yes −40 °C to +85 °C

RAM ADC DAC Enhanced UARTs,

ADC, Fast I/Os, and
BOD

Temperature
range

SOT314-2

SOT314-2

SOT314-2

SOT314-2

SOT804-2

SOT804-2

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 3 of 39

NXP Semiconductors

4. Block diagram

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

P0[31:0]

P1[31:16]

EINT[3:0]

8 × CAP

8 × MAT

AD0[7:0]

AD1[7:0]

AOUT

P0[31:0]

P1[31:16]

PWM[6:1]

TRST

(3)

TMS

(3)

TCK

(3)

TDI

(3)

TDO

(3)

trace

signals

XTAL1

XTAL2

RESET

LPC2131, LPC2131/01
LPC2132, LPC2132/01
LPC2134, LPC2134/01
LPC2136, LPC2136/01
LPC2138, LPC2138/01

FAST GENERAL

PURPOSE I/O

ARM7 local bus

INTERNAL

SRAM

CONTROLLER

8/16/32 kB

SRAM

TIMER 0/TIMER 1

A/D CONVERTERS

(1)

(2)

D/A CONVERTER

INTERNAL

FLASH

CONTROLLER

32/64/128/

256/512 kB

FLASH

EXTERNAL

INTERRUPTS

CAPTURE/
COMPARE

(1)

0 AND 1

GENERAL

PURPOSE I/O

PWM0

(2)

TEST/DEBUG

INTERFACE

ARM7TDMI-S

AHB BRIDGE

AHB TO APB

BRIDGE

PLL

system

EMULATION

clock

TRACE MODULE

(Advanced High-performance Bus)

APB (ARM

peripheral bus)

AMBA AHB

APB

DIVIDER

2

C SERIAL

I

INTERFACES 0 AND 1

SPI AND SSP

SERIAL INTERFACES

UART0/UART1

REAL TIME CLOCK

WATCHDOG

TIMER

SYSTEM

FUNCTIONS

VECTORED
INTERRUPT

CONTROLLER

AHB

DECODER

SCL0,1

SDA0,1

SCK0,1
MOSI0,1
MISO0,1
SSEL0,1

TXD0,1
RXD0,1

DSR1
RTS1
DCD1

RTCX1
RTCX2
VBAT

(1)

(1)

(1)

,CTS1

, DTR1

, RI1

(1)

(1)

(1)

SYSTEM

CONTROL

002aab067

(1) LPC2134/36/38 only.
(2) LPC2132/34/36/38 only.
(3) Pins shared with GPIO.

Fig 1. Block diagram

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 4 of 39

NXP Semiconductors

5. Pinning information

5.1 Pinning

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

VREF

646362616059585756555453525150

V

V

DDA

SS

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

171819202122232425262728293031

SS

V

P0.31 P1.27/TDO

P0.21/PWM5/CAP1.3 P1.20/TRACESYNC

P0.22/CAP0.0/MAT0.0 P0.17/CAP1.2/SCK1/MAT1.2

RTCX1 P0.16/EINT0/MAT0.2/CAP0.2

P1.19/TRACEPKT3 P0.15/EINT2

RTCX2 P1.21/PIPESTAT0

P1.18/TRACEPKT2 P0.14/EINT1/SDA1

P0.25/AD0.4 P1.22/PIPESTAT1
P0.26/AD0.5 P0.13/MAT1.1

P0.27/AD0.0/CAP0.1/MAT0.1 P0.12/MAT1.0

P1.17/TRACEPKT1 P0.11/CAP1.1/SCL1
P0.28/AD0.1/CAP0.2/MAT0.2 P1.23/PIPESTAT2
P0.29/AD0.2/CAP0.3/MAT0.3 P0.10/CAP1.0

P0.30/AD0.3/EINT3/CAP0.0 P0.9/RXD1/PWM6/EINT3

P1.16/TRACEPKT0 P0.8/TXD1/PWM4

SSA

P0.23

LPC2131

LPC2131/01

DD

V

P1.29/TCK

SS

V

DD

SS

49

32

48
47
46
45
44
43

V

DD

42

V

SS

41
40
39
38
37
36
35
34
33

002aab068

P1.31/TRST XTAL2

P0.0/TXD0/PWM1 XTAL1

P0.1/RXD0/PWM3/EINT0 P1.28/TDI

P1.26/RTCK RESET

P0.2/SCL0/CAP0.0 V

P1.25/EXTIN0 P0.18/CAP1.3/MISO1/MAT1.3

P1.24/TRACECLK VBAT

P0.6/MOSI0/CAP0.2 V

P0.4/SCK0/CAP0.1/AD0.6 P0.19/MAT1.2/MOSI1/CAP1.2

P0.3/SDA0/MAT0.0/EINT1 P0.20/MAT1.3/SSEL1/EINT3

P0.7/SSEL0/PWM2/EINT2 V

P0.5/MISO0/MAT0.1/AD0.7 P1.30/TMS

Fig 2. LPC2131 LQFP64 pinning

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 5 of 39

NXP Semiconductors

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

VREF

646362616059585756555453525150

V

V

DDA

SS

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

171819202122232425262728293031

SS

V

P0.31 P1.27/TDO

P0.21/PWM5/CAP1.3 P1.20/TRACESYNC

P0.22/CAP0.0/MAT0.0 P0.17/CAP1.2/SCK1/MAT1.2

RTCX1 P0.16/EINT0/MAT0.2/CAP0.2

P1.19/TRACEPKT3 P0.15/EINT2

RTCX2 P1.21/PIPESTAT0

P1.18/TRACEPKT2 P0.14/EINT1/SDA1
P0.25/AD0.4/AOUT P1.22/PIPESTAT1

P0.26/AD0.5 P0.13/MAT1.1

P0.27/AD0.0/CAP0.1/MAT0.1 P0.12/MAT1.0

P1.17/TRACEPKT1 P0.11/CAP1.1/SCL1
P0.28/AD0.1/CAP0.2/MAT0.2 P1.23/PIPESTAT2
P0.29/AD0.2/CAP0.3/MAT0.3 P0.10/CAP1.0

P0.30/AD0.3/EINT3/CAP0.0 P0.9/RXD1/PWM6/EINT3

P1.16/TRACEPKT0 P0.8/TXD1/PWM4

SSA

P0.23

LPC2132

LPC2132/01

DD

V

P1.29/TCK

SS

V

DD

SS

49

32

48
47
46
45
44
43

V

DD

42

V

SS

41
40
39
38
37
36
35
34
33

002aab406

P1.31/TRST XTAL2

P0.0/TXD0/PWM1 XTAL1

P0.1/RXD0/PWM3/EINT0 P1.28/TDI

P1.26/RTCK RESET

P0.2/SCL0/CAP0.0 V

P1.25/EXTIN0 P0.18/CAP1.3/MISO1/MAT1.3

P1.24/TRACECLK VBAT

P0.6/MOSI0/CAP0.2 V

P0.4/SCK0/CAP0.1/AD0.6 P0.19/MAT1.2/MOSI1/CAP1.2

P0.3/SDA0/MAT0.0/EINT1 P0.20/MAT1.3/SSEL1/EINT3

P0.7/SSEL0/PWM2/EINT2 V

P0.5/MISO0/MAT0.1/AD0.7 P1.30/TMS

Fig 3. LPC2132 LQFP64 pin configuration

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 6 of 39

NXP Semiconductors

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

VREF

646362616059585756555453525150

V

V

DDA

SS

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

171819202122232425262728293031

SS

V

P0.31 P1.27/TDO

P0.21/PWM5/AD1.6/CAP1.3 P1.20/TRACESYNC

P0.22/AD1.7/CAP0.0/MAT0.0 P0.17/CAP1.2/SCK1/MAT1.2

RTCX1 P0.16/EINT0/MAT0.2/CAP0.2

P1.19/TRACEPKT3 P0.15/RI1/EINT2/AD1.5

RTCX2 P1.21/PIPESTAT0

P1.18/TRACEPKT2 P0.14/DCD1/EINT1/SDA1
P0.25/AD0.4/AOUT P1.22/PIPESTAT1

P0.26/AD0.5 P0.13/DTR1/MAT1.1/AD1.4

P0.27/AD0.0/CAP0.1/MAT0.1 P0.12/DSR1/MAT1.0/AD1.3

P1.17/TRACEPKT1 P0.11/CTS1/CAP1.1/SCL1
P0.28/AD0.1/CAP0.2/MAT0.2 P1.23/PIPESTAT2
P0.29/AD0.2/CAP0.3/MAT0.3 P0.10/RTS1/CAP1.0/AD1.2

P0.30/AD0.3/EINT3/CAP0.0 P0.9/RXD1/PWM6/EINT3

P1.16/TRACEPKT0 P0.8/TXD1/PWM4/AD1.1

SSA

P0.23

P1.29/TCK

LPC2134, LPC2134/01
LPC2136, LPC2136/01
LPC2138, LPC2138/01

SS

DD

V

V

DD

SS

49

32

48
47
46
45
44
43

V

DD

42

V

SS

41
40
39
38
37
36
35
34
33

002aab407

P1.31/TRST XTAL2

P0.0/TXD0/PWM1 XTAL1

P0.1/RXD0/PWM3/EINT0 P1.28/TDI

P1.26/RTCK RESET

P0.2/SCL0/CAP0.0 V

P1.25/EXTIN0 P0.18/CAP1.3/MISO1/MAT1.3

P1.24/TRACECLK VBAT

P0.4/SCK0/CAP0.1/AD0.6 P0.19/MAT1.2/MOSI1/CAP1.2

P0.3/SDA0/MAT0.0/EINT1 P0.20/MAT1.3/SSEL1/EINT3

P0.7/SSEL0/PWM2/EINT2 V

P0.6/MOSI0/CAP0.2/AD1.0 V

P0.5/MISO0/MAT0.1/AD0.7 P1.30/TMS

Fig 4. LPC2134/36/38 LQFP64 pin configuration

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 7 of 39

NXP Semiconductors

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

terminal 1

index area

P0.21/PWM5/AD1.6/CAP1.3

P0.22/AD1.7/CAP0.0/MAT0.0

RTCX1

P1.19/TRACEPKT3

RTCX2

V

SS

V

DDA

P1.18/TRACEPKT2

P0.25/AD0.4/AOUT

P0.26/AD0.5

P0.27/AD0.0/CAP0.1/MAT0.1

P1.17/TRACEPKT1
P0.28/AD0.1/CAP0.2/MAT0.2
P0.29/AD0.2/CAP0.3/MAT0.3

P0.30/AD0.3/EINT3/CAP0.0

P1.16/TRACEPKT0

P1.27/TDO

VREF

XTAL1

646362616059585756555453525150
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40

10 39
11 38
12 37
13 36
14 35
15 34
16 33

171819202122232425262728293031

SS

V

P0.31

P0.0/TXD0/PWM1

SSA

XTAL2

P1.28/TDI

V

LPC2132/2138

P1.31/TRST

P0.2/SCL0/CAP0.0

P0.23

RESET

DD

V

P1.26/RTCK

P1.29/TCK

P0.20/MAT1.3/SSEL1/EINT3

P0.19/MAT1.2/MOSI1/CAP1.2

P0.18/CAP1.3/MISO1/MAT1.3

P1.30/TMS

VDDVSSVBAT

SS

V

P1.25/EXTIN0

49

32

P1.24/TRACECLK

P1.20/TRACESYNC
P0.17/CAP1.2/SCK1/MAT1.2
P0.16/EINT0/MAT0.2/CAP0.2
P0.15/RI1/EINT2/AD1.5
P1.21/PIPESTAT0
V

DD

V

SS

P0.14/DCD1/EINT1/SDA1
P1.22/PIPESTAT1
P0.13/DTR1/MAT1.1/AD1.4
P0.12/DSR1/MAT1.0/AD1.3
P0.11/CTS1/CAP1.1/SCL1
P1.23/PIPESTAT2
P0.10/RTS1/CAP1.0/AD1.2
P0.9/RXD1/PWM6/EINT3
P0.8/TXD1/PWM4/AD1.1

P0.1/RXD0/PWM3/EINT0

Transparent top view

P0.4/SCK0/CAP0.1/AD0.6

P0.3/SDA0/MAT0.0/EINT1

P0.7/SSEL0/PWM2/EINT2

P0.6/MOSI0/CAP0.2/AD1.0

P0.5/MISO0/MAT0.1/AD0.7

002aab943

AD1.7 to AD1.0 only available on LPC2134/36/38.

Fig 5. LPC2132/38 HVQFN64 pin configuration

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 8 of 39

NXP Semiconductors

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

5.2 Pin description

Table 3. Pin description

Symbol Pin Type Description

P0.0 to P0.31 I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit.

Total of 31 pins of the Port 0 can be used as a general purpose bidirectional
digital I/Os while P0.31 is output only pin. The operation of port 0 pins
depends upon the pin function selected via the pin connect block.

Pin P0.24 is not available.

P0.0/TXD0/
PWM1

P0.1/RXD0/
PWM3/EINT0

P0.2/SCL0/
CAP0.0

P0.3/SDA0/
MAT0.0/EINT1

P0.4/SCK0/
CAP0.1/AD0.6

P0.5/MISO0/
MAT0.1/AD0.7

P0.6/MOSI0/
CAP0.2/AD1.0

P0.7/SSEL0/
PWM2/EINT2

P0.8/TXD1/
PWM4/AD1.1

P0.9/RXD1/
PWM6/EINT3

P0.10/RTS1/
CAP1.0/AD1.2

19

21

22

26

27

29

30

31

33

34

35

[1]

[2]

[3]

[3]

[4]

[4]

[4]

[2]

[4]

[2]

[4]

O TXD0 — Transmitter output for UART0.
O PWM1 — Pulse Width Modulator output 1.
I RXD0 — Receiver input for UART0.
O PWM3 — Pulse Width Modulator output 3.
I EINT0 — External interrupt 0 input.
I/O SCL0 — I2C0 clock input/output. Open drain output (for I2C-bus compliance).
I CAP0.0 — Capture input for Timer 0, channel 0.
I/O SDA0 — I2C0 data input/output. Open drain output (for I2C-bus compliance).
O MAT0.0 — Match output for Timer 0, channel 0.
I EINT1 — External interrupt 1 input.
I/O SCK0 — Serial clock for SPI0. SPI clock output from master or input to slave.
I CAP0.1 — Capture input for Timer 0, channel 1.
I AD0.6 — ADC 0, input 6. This analog input is always connected to its pin.
I/O MISO0 — Master In Slave VDD = 3.6 V for SPI0. Data input to SPI master or

data output from SPI slave.
O MAT0.1 — Match output for Timer 0, channel 1.
I AD0.7 — ADC 0, input 7. This analog input is always connected to its pin.
I/O MOSI0 — Master Out Slave In for SPI0. Data output from SPI master or data

input to SPI slave.
I CAP0.2 — Capture input for Timer 0, channel 2.
I AD1.0 — ADC 1, input 0. This analog input is always connected to its pin.

Available in LPC2134/36/38 only.
I SSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave.
O PWM2 — Pulse Width Modulator output 2.
I EINT2 — External interrupt 2 input.
O TXD1 — Transmitter output for UART1.
O PWM4 — Pulse Width Modulator output 4.
I AD1.1 — ADC 1, input 1. This analog input is always connected to its pin.

Available in LPC2134/36/38 only.
I RXD1 — Receiver input for UART1.
O PWM6 — Pulse Width Modulator output 6.
I EINT3 — External interrupt 3 input.
O RTS1 — Request to Send output for UART1. Available in LPC2134/36/38.
I CAP1.0 — Capture input for Timer 1, channel 0.
I AD1.2 — ADC 1, input 2. This analog input is always connected to its pin.

Available in LPC2134/36/38 only.

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 9 of 39

NXP Semiconductors

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

Table 3. Pin description

…continued

Symbol Pin Type Description

P0.11/CTS1/
CAP1.1/SCL1

37

[3]

I CTS1 — Clear to Send input for UART1. Available in LPC2134/36/38.
I CAP1.1 — Capture input for Timer 1, channel 1.
I/O SCL1 — I

P0.12/DSR1/
MAT1.0/AD1.3

38

[4]

I DSR1 — Data Set Ready input for UART1. Available in LPC2134/36/38.
O MAT1.0 — Match output for Timer 1, channel 0.
I AD1.3 — ADC 1, input 3. This analog input is always connected to its pin.

Available in LPC2134/36/38 only.

P0.13/DTR1/
MAT1.1/AD1.4

39

[4]

O DTR1 — Data Terminal Ready output for UART1. Available in

LPC2134/36/38.
O MAT1.1 — Match output for Timer 1, channel 1.
I AD1.4 — ADC 1, input 4. This analog input is always connected to its pin.

Available in LPC2134/36/38 only.

P0.14/DCD1/
EINT1/SDA1

41

[3]

I DCD1 — Data Carrier Detect input for UART1. Available in LPC2134/36/38.
I EINT1 — External interrupt 1 input.
I/O SDA1 — I

P0.15/RI1/
EINT2/AD1.5

45

[4]

I RI1 — Ring Indicator input for UART1. Available in LPC2134/36/38.
I EINT2 — External interrupt 2 input.
I AD1.5 — ADC 1, input 5. This analog input is always connected to its pin.

Available in LPC2134/36/38 only.

P0.16/EINT0/
MAT0.2/CAP0.2

46

[2]

I EINT0 — External interrupt 0 input.
O MAT0.2 — Match output for Timer 0, channel 2.
I CAP0.2 — Capture input for Timer 0, channel 2.

P0.17/CAP1.2/
SCK1/MAT1.2

47

[1]

I CAP1.2 — Capture input for Timer 1, channel 2.
I/O SCK1 — Serial Clock for SSP. Clock output from master or input to slave.
O MAT1.2 — Match output for Timer 1, channel 2.

P0.18/CAP1.3/
MISO1/MAT1.3

53

[1]

I CAP1.3 — Capture input for Timer 1, channel 3.
I/O MISO1 — Master In Slave Out for SSP. Data input to SPI master or data

output from SSP slave.
O MAT1.3 — Match output for Timer 1, channel 3.

P0.19/MAT1.2/
MOSI1/CAP1.2

54

[1]

O MAT1.2 — Match output for Timer 1, channel 2.
I/O MOSI1 — Master Out Slave In for SSP. Data output from SSP master or data

input to SSP slave.
I CAP1.2 — Capture input for Timer 1, channel 2.

P0.20/MAT1.3/
SSEL1/EINT3

55

[2]

O MAT1.3 — Match output for Timer 1, channel 3.
I SSEL1 — Slave Select for SSP. Selects the SSP interface as a slave.
I EINT3 — External interrupt 3 input.

P0.21/PWM5/
AD1.6/CAP1.3

[4]

1

O PWM5 — Pulse Width Modulator output 5.
I AD1.6 — ADC 1, input 6. This analog input is always connected to its pin.

Available in LPC2134/36/38 only.
I CAP1.3 — Capture input for Timer 1, channel 3.

2

C1 clock input/output. Open drain output (for I2C-bus compliance)

2

C1 data input/output. Open drain output (for I2C-bus compliance).

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 10 of 39

NXP Semiconductors

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

Table 3. Pin description

…continued

Symbol Pin Type Description

P0.22/AD1.7/
CAP0.0/MAT0.0

[4]

2

I AD1.7 — ADC 1, input 7. This analog input is always connected to its pin.

Available in LPC2134/36/38 only.
I CAP0.0 — Capture input for Timer 0, channel 0.
O MAT0.0 — Match output for Timer 0, channel 0.

P0.23 58
P0.25/AD0.4/

9

AOUT
P0.26/AD0.5 10

P0.27/AD0.0/

11

CAP0.1/MAT0.1

[1]

[5]

[4]
[4]

I/O General purpose digital input/output pin.
I AD0.4 — ADC 0, input 4. This analog input is always connected to its pin.
O AOUT — DAC output. Not available in LPC2131.
I AD0.5 — ADC 0, input 5. This analog input is always connected to its pin.
I AD0.0 — ADC 0, input 0. This analog input is always connected to its pin.
I CAP0.1 — Capture input for Timer 0, channel 1.
O MAT0.1 — Match output for Timer 0, channel 1.

P0.28/AD0.1/
CAP0.2/MAT0.2

13

[4]

I AD0.1 — ADC 0, input 1. This analog input is always connected to its pin.
I CAP0.2 — Capture input for Timer 0, channel 2.
O MAT0.2 — Match output for Timer 0, channel 2.

P0.29/AD0.2/
CAP0.3/MAT0.3

14

[4]

I AD0.2 — ADC 0, input 2. This analog input is always connected to its pin.
I CAP0.3 — Capture input for Timer 0, channel 3.
O MAT0.3 — Match output for Timer 0, channel 3.

P0.30/AD0.3/
EINT3/CAP0.0

15

[4]

I AD0.3 — ADC 0, input 3. This analog input is always connected to its pin.
I EINT3 — External interrupt 3 input.
I CAP0.0 — Capture input for Timer 0, channel 0.

P0.31 17

[6]

O General purpose digital output only pin.

Important: This pin MUST NOT be externally pulled LOW when

RESET pin

is LOW or the JTAG port will be disabled.

P1.0 to P1.31 I/O Port 1: Port 1 is a 32-bit bidirectional I/O port with individual direction controls

for each bit. The operation of port 1 pins depends upon the pin function

selected via the pin connect block. Pins 0 through 15 of port 1 are not

available.

P1.16/

16

[6]

O TRACEPKT0 — Trace Packet, bit 0. Standard I/O port with internal pull-up.

TRACEPKT0
P1.17/

12

[6]

O TRACEPKT1 — Trace Packet, bit 1. Standard I/O port with internal pull-up.

TRACEPKT1
P1.18/

[6]

8

O TRACEPKT2 — Trace Packet, bit 2. Standard I/O port with internal pull-up.

TRACEPKT2
P1.19/

[6]

4

O TRACEPKT3 — Trace Packet, bit 3. Standard I/O port with internal pull-up.

TRACEPKT3
P1.20/

TRACESYNC

48

[6]

O TRACESYNC — Trace Synchronization. Standard I/O port with internal

pull-up. LOW on TRACESYNC while

RESET is LOW enables pins P1.25:16

to operate as Trace port after reset.

P1.21/

44

[6]

O PIPESTAT0 — Pipeline Status, bit 0. Standard I/O port with internal pull-up.

PIPESTAT0
P1.22/

40

[6]

O PIPESTAT1 — Pipeline Status, bit 1. Standard I/O port with internal pull-up.

PIPESTAT1
P1.23/

36

[6]

O PIPESTAT2 — Pipeline Status, bit 2. Standard I/O port with internal pull-up.

PIPESTAT2

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 11 of 39

NXP Semiconductors

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

Table 3. Pin description

…continued

Symbol Pin Type Description

P1.24/

32

[6]

O TRACECLK — Trace Clock. Standard I/O port with internal pull-up.

TRACECLK
P1.25/EXTIN0 28
P1.26/RTCK 24

[6]
[6]

I EXTIN0 — External Trigger Input. Standard I/O with internal pull-up.
I/O RTCK — Returned Test Clock output. Extra signal added to the JTAG port.

Assists debugger synchronization when processor frequency varies.

Bidirectional pin with internal pull-up. LOW on RTCK while

enables pins P1.31:26 to operate as Debug port after reset.

P1.27/TDO 64
P1.28/TDI 60
P1.29/TCK 56
P1.30/TMS 52

TRST 20

P1.31/
RESET 57

[6]
[6]
[6]
[6]
[6]
[7]

O TDO — Test Data out for JTAG interface.
I TDI — Test Data in for JTAG interface.
I TCK — Test Clock for JTAG interface.
I TMS — Test Mode Select for JTAG interface.
I TRST — Test Reset for JTAG interface.
I External reset input: A LOW on this pin resets the device, causing I/O ports

and peripherals to take on their default states, and processor execution to

begin at address 0. TTL with hysteresis, 5 V tolerant.

XTAL1 62
XTAL2 61
RTCX1 3
RTCX2 5
V

SS

[8]

[8]
[8]
[8]

I Input to the oscillator circuit and internal clock generator circuits.
O Output from the oscillator amplifier.
I Input to the RTC oscillator circuit.
O Output from the RTC oscillator circuit.

6, 18, 25, 42,50I Ground: 0 V reference.

RESET is LOW

V

SSA

V

DD

59 I Analog ground: 0 V reference. This should nominally be the same voltage

as V

, but should be isolated to minimize noise and error.

SS

23, 43, 51 I 3.3 V power supply: This is the power supply voltage for the core and I/O

ports.

V

DDA

7IAnalog 3.3 V power supply: This should be nominally the same voltage as

V

but should be isolated to minimize noise and error. This voltage is used

DD

to power the on-chip PLL.

VREF 63 I ADC reference: This should be nominally the same voltage as V

DD

but
should be isolated to minimize noise and error. Level on this pin is used as a
reference for A/D and D/A convertor(s).

VBAT 49 I RTC power supply: 3.3 V on this pin supplies the power to the RTC.

[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10ns slew rate control.
[2] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10ns slew rate control. If configured for an input

function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns.

[3] Open drain 5 V tolerant digital I/O I2C-bus 400 kHz specification compatible pad. It requires external pull-up to provide an output

functionality.

[4] 5 V tolerant pad providing digital I/O (with TTL levels and hysteresisand10 ns slewratecontrol)andanaloginputfunction.If configured

for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns. When configured as an ADC input, digital
section of the pad is disabled.

[5] 5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10ns slew rate control) and analog output function. When

configured as the DAC output, digital section of the pad is disabled.

[6] 5 V tolerant pad with built-in pull-up resistor providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.

The pull-up resistor’s value ranges from 60 kΩ to 300 kΩ.
[7] 5 V tolerant pad providing digital input (with TTL levels and hysteresis) function only.
[8] Pad provides special analog functionality.

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 12 of 39

NXP Semiconductors

6. Functional description

6.1 Architectural overview

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers. This simplicity results in a high instruction throughput and
impressive real-time interrupt response from a small and cost-effective processor core.

Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

• The standard 32-bit ARM set.

• A 16-bit Thumb set.

The Thumb set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because Thumb code
operates on the same 32-bit register set as ARM code.

Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the
performance of an equivalent ARM processor connected to a 16-bit memory system.

6.2 On-chip flash program memory

The LPC2131/32/34/36/38 incorporate a 32 kB, 64 kB, 128 kB, 256 kB and 512 kB flash
memory system respectively. This memory may be used for both code and data storage.
Programming of the flash memory may be accomplished in several ways. It may be
programmed In System via the serial port. The application program mayalso erase and/or
program the flash while the application is running, allowing a great degree of flexibility for
data storage field firmware upgrades, etc. When the LPC2131/32/34/36/38 on-chip
bootloader is used, 32/64/128/256/500 kB of flash memory is available for user code.

The LPC2131/32/34/36/38 flash memory provides a minimum of 100000 erase/write
cycles and 20 years of data-retention.

6.3 On-chip static RAM

On-chip static RAM may be used for code and/or data storage. The SRAM may be
accessed as 8-bit, 16-bit, and 32-bit. The LPC2131, LPC2132/34, and LPC2136/38
provide 8 kB, 16 kB and 32 kB of static RAM respectively.

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Product data sheet Rev. 04 — 16 October 2007 13 of 39

NXP Semiconductors

6.4 Memory map

The LPC2131/32/34/36/38 memory map incorporates several distinct regions, as shown
in Figure 6.

In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either
flash memory (the default) or on-chip static RAM. This is described in Section 6.18

“System control”.

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

4.0 GB

3.75 GB

3.5 GB

3.0 GB

2.0 GB

1.0 GB

0.0 GB

AHB PERIPHERALS

VPB PERIPHERALS

RESERVED ADDRESS SPACE

BOOT BLOCK (RE-MAPPED FROM

ON-CHIP FLASH MEMORY

RESERVED ADDRESS SPACE

TOTAL OF 32 kB ON-CHIP STATIC RAM (LPC2136/38)
TOTAL OF 16 kB ON-CHIP STATIC RAM (LPC2132/34)

TOTAL OF 8 kB ON-CHIP STATIC RAM (LPC2131)

RESERVED ADDRESS SPACE

TOTAL OF 512 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2138)

TOTAL OF 256 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2136)

TOTAL OF 128 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2134)

TOTAL OF 64 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2132)

TOTAL OF 32 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2131)

0xFFFF FFFF
0xF000 0000

0xE000 0000

0xC000 0000

0x8000 0000

0x4001 8000
0x4000 7FFF

0x4000 4000
0x4000 3FFF

0x4000 2000
0x4000 1FFF

0x4000 0000
0x0008 0000

0x0007 FFFF
0x0004 0000

0x0003 FFFF
0x0002 0000

0x0001 FFFF
0x0001 0000

0x0000 FFFF
0x0000 8000

0x0000 7FFF
0x0000 0000

002aab069

Fig 6. LPC2131/32/34/36/38 memory map

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 14 of 39

NXP Semiconductors

6.5 Interrupt controller

The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and
categorizes them as Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), and
non-vectored IRQ as defined by programmable settings. The programmable assignment
scheme means that priorities of interrupts from the various peripherals can be dynamically
assigned and adjusted.

FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC
combines the requests to produce the FIQ signal to the ARM processor. The fastest
possible FIQ latency is achieved when only one request is classified as FIQ, because then
the FIQ service routine can simply start dealing with that device. But if more than one
request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC
that identifies which FIQ source(s) is (are) requesting an interrupt.

Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned
to this category. Any of the interrupt requests can be assigned to any of the 16 vectored
IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.

Non-vectored IRQs have the lowest priority.

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

The VIC combines the requests from all the vectored and non-vectored IRQs to produce
the IRQ signal to the ARM processor. The IRQ service routine can start by reading a
register from the VIC and jumping there. If any of the vectored IRQs are requesting, the
VIC provides the address of the highest-priority requesting IRQs service routine,
otherwise it provides the address of a default routine that is shared by all the non-vectored
IRQs. The default routine can read another VIC register to see what IRQs are active.

6.5.1 Interrupt sources

Table 4 lists the interrupt sources for each peripheral function. Each peripheral device has

one interrupt line connected to the Vectored Interrupt Controller, but may have several
internal interrupt flags. Individual interrupt flags may also represent more than one
interrupt source.

Table 4. Interrupt sources

Block Flag(s) VIC channel #

WDT Watchdog Interrupt (WDINT) 0

- Reserved for software interrupts only 1
ARM Core EmbeddedICE, DbgCommRX 2
ARM Core EmbeddedICE, DbgCommTX 3
TIMER0 Match 0 to 3 (MR0, MR1, MR2, MR3)

Capture 0 to 3 (CR0, CR1, CR2, CR3)

TIMER1 Match 0 to 3 (MR0, MR1, MR2, MR3)

Capture 0 to 3 (CR0, CR1, CR2, CR3)

UART0 RX Line Status (RLS)

Transmit Holding Register empty (THRE)
RX Data Available (RDA)
Character Time-out Indicator (CTI)

4

5

6

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 15 of 39

NXP Semiconductors

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

Table 4. Interrupt sources

Block Flag(s) VIC channel #

UART1 RX Line Status (RLS)

Transmit Holding Register empty (THRE)
RX Data Available (RDA)
Character Time-out Indicator (CTI)
Modem Status Interrupt (MSI) (Available in LPC2134/36/38

only)

PWM0 Match 0 to 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6)

Capture 0 to 3 (CR0, CR1, CR2, CR3)

2

C0 SI (state change) 9

I
SPI0 SPIF, MODF 10
SSP TX FIFO at least half empty (TXRIS)

RX FIFO at least half full (RXRIS)
Receive Timeout (RTRIS)

Receive Overrun (RORRIS)
PLL PLL Lock (PLOCK) 12
RTC RTCCIF (Counter Increment), RTCALF (Alarm) 13
System Control External Interrupt 0 (EINT0) 14

External Interrupt 1 (EINT1) 15

External Interrupt 2 (EINT2) 16

External Interrupt 3 (EINT3) 17
AD0 ADC 0 18
I2C1 SI (state change) 19
BOD Brown Out Detect 20
AD1 ADC 1 (Available in LPC2134/36/38 only) 21

…continued

7

8

11

6.6 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on chip peripherals. Peripherals should be connected to the appropriate pins
prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any
enabled peripheral function that is not mapped to a related pin should be considered
undefined.

6.7 General purpose parallel I/O and Fast I/O

Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back, as well as the current state of the port pins.

6.7.1 Features

• Direction control of individual bits.

• Separate control of output set and clear.

• All I/O default to inputs after reset.

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6.7.2 Fast I/O features available in LPC213x/01 only

• Fast I/O registers are located on the ARM local bus for the fastest possible I/O timing.

• All GPIO registers are byte addressable.

• Entire port value can be written in one instruction.

• Mask registers allow single instruction to set or clear any number of bits in one port.

6.8 10-bit ADC

The LPC2131/32 contain one and the LPC2134/36/38 contain two ADCs. These
converters are single 10-bit successive approximation ADCs with eight multiplexed
channels.

6.8.1 Features

• Measurement range of 0 V to 3.3 V.

• Each converter capable of performing more than 400000 10-bit samples per second.

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition on input pin or Timer Match signal.

• Global Start command for both converters (LPC2134/36/38 only).

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

6.8.2 ADC features available in LPC213x/01 only

• Every analog input has a dedicated result register to reduce interrupt overhead.

• Every analog input can generate an interrupt once the conversion is completed.

6.9 10-bit DAC

This peripheral is available in the LPC2132/34/36/38 only. The DAC enables the
LPC2132/34/36/38 to generate variable analog output.

6.9.1 Features

• 10-bit digital to analog converter.

• Buffered output.

• Power-down mode available.

• Selectable speed versus power.

6.10 UARTs

The LPC2131/32/34/36/38 each contain two UARTs. In addition to standard transmit and
receive data lines, the LPC2134/36/38 UART1 also provides a full modem control
handshake interface.

6.10.1 Features

• 16 B Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 17 of 39

NXP Semiconductors

• Built-in baud rate generator.

• Standard modem interface signals included on UART1. (LPC2134/36/38 only)

• The LPC2131/32/34/36/38 transmission FIFO control enables implementation of

6.10.2 UART features available in LPC213x/01 only

• Fractional baud rate generator enables standard baud rates such as 115200 to be

• Auto-bauding.

• Auto-CTS/RTS flow-control fully implemented in hardware (LPC2134/36/38 only).

6.11 I2C-bus serial I/O controller

The LPC2131/32/34/36/38 each contain two I2C-bus controllers.
The I2C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line

(SCL), and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the
capability to both receive and send information (such as memory)). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus, it can be
controlled by more than one bus master connected to it.

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

software (XON/XOFF) flow control on both UARTs and hardware (CTS/RTS) flow
control on the LPC2134/36/38 UART1 only.

achieved with any crystal frequency above 2 MHz.

This I2C-bus implementation supports bit rates up to 400 kbit/s (Fast I2C).

6.11.1 Features

• Standard I

2

C compliant bus interface.

• Easy to configure as Master, Slave, or Master/Slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I

2

C-bus may be used for test and diagnostic purposes.

6.12 SPI serial I/O controller

The LPC2131/32/34/36/38 each contain one SPI controller. The SPI is a full duplex serial
interface, designed to be able to handle multiple masters and slaves connected to a given
bus. Only a single master and a single slave can communicate on the interface during a
given data transfer. During a data transfer the master always sends a byte of data to the
slave, and the slave always sends a byte of data to the master.

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 18 of 39

NXP Semiconductors

6.12.1 Features

• Compliant with Serial Peripheral Interface (SPI) specification.

• Synchronous, Serial, Full Duplex, Communication.

• Combined SPI master and slave.

• Maximum data bit rate of one eighth of the input clock rate.

6.13 SSP serial I/O controller

The LPC2131/32/34/36/38 each contain one Serial Synchronous Port controller (SSP).
The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can
interact with multiple masters and slaves on the bus. However, only a single master and a
single slave can communicate on the bus during a given data transfer. The SSP supports
full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the
slave and from the slave to the master. Often only one of these data flows carries
meaningful data.

6.13.1 Features

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

• Compatible with Motorola SPI, 4-wire TI SSI and National Semiconductor Microwire

buses.

• Synchronous Serial Communication.

• Master or slave operation.

• 8-frame FIFOs for both transmit and receive.

• Four bits to 16 bits per frame.

6.14 General purpose timers/external event counters

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an
externally supplied clock, and optionally generate interrupts or perform other actions at
specified timer values, based on four match registers. It also includes four capture inputs
to trap the timer value when an input signal transitions, optionally generating an interrupt.
Multiple pins can be selected to perform a single capture or match function, providing an
application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.

At any given time only one of peripheral’s capture inputs can be selected as an external
eventsignal source, i.e., timer’s clock. The rate of external events that can be successfully
counted is limited to PCLK/2. In this configuration, unused capture lines can be selected
as regular timer capture inputs.

6.14.1 Features

• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

• External Event Counter or timer operation.

• Four 32-bit capture channels per timer/counter that can take a snapshot of the timer

value when an input signal transitions. A capture event may also optionally generate
an interrupt.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

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Product data sheet Rev. 04 — 16 October 2007 19 of 39

NXP Semiconductors

• Four external outputs per timer/counter corresponding to match registers, with the

6.15 Watchdog timer

The purpose of the watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the watchdog will generate a system
reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined
amount of time.

6.15.1 Features

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.

following capabilities:

– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.

• Internally resets chip if not periodically reloaded.

• Debug mode.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 32-bit timer with internal pre-scaler.

• Selectable time period from (T

T

cy(PCLK)

× 4.

6.16 Real-time clock

The Real-Time Clock (RTC) is designed to provide a set of counters to measure time
when normal or idle operating mode is selected. The RTC has been designed to use little
power, making it suitable for battery powered systems where the CPU is not running
continuously (Idle mode).

6.16.1 Features

• Measures the passage of time to maintain a calendar and clock.

• Ultra-low power design to support battery powered systems.

cy(PCLK)

× 256 × 4) to (T

cy(PCLK)

× 232× 4) in multiples of

• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day

of Year.

• Can use either the RTC dedicated 32 kHz oscillator input or clock derived from the

external crystal/oscillator input at XTAL1. Programmable Reference Clock Divider
allows fine adjustment of the RTC.

• Dedicated power supply pin can be connected to a battery or the main 3.3 V.

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 20 of 39

NXP Semiconductors

6.17 Pulse width modulator

The PWM is based on the standard Timer block and inherits all of its features, although
only the PWM function is pinned out on the LPC2131/32/34/36/38. The Timer is designed
to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or
perform other actions when specified timer values occur,based on sevenmatch registers.
The PWM function is also based on match register events.

The ability to separately control rising and falling edge locations allows the PWM to be
used for more applications. For instance, multi-phase motor control typically requires three
non-overlapping PWM outputs with individual control of all three pulse widths and
positions.

Two match registers can be used to provide a single edge controlled PWM output. One
match register (MR0) controls the PWM cycle rate, by resetting the count upon match.
The other match register controls the PWM edge position. Additional single edge
controlled PWM outputs require only one match register each, since the repetition rate is
the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a
rising edge at the beginning of each PWM cycle, when an MR0 match occurs.

Three match registers can be used to provide a PWM output with both edges controlled.
Again, the MR0 match register controls the PWM cycle rate. The other match registers
control the two PWM edge positions. Additional double edge controlled PWM outputs
require only two match registers each, since the repetition rate is the same for all PWM
outputs.

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

With double edge controlled PWM outputs, specific match registers control the rising and
falling edge of the output. This allows both positive going PWM pulses (when the rising
edge occurs prior to the falling edge), and negative going PWM pulses (when the falling
edge occurs prior to the rising edge).

6.17.1 Features

• Seven match registers allow up to six single edge controlled or three double edge

controlled PWM outputs, or a mix of both types.

• The match registers also allow:

– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.

• Supports single edge controlled and/or double edge controlled PWM outputs. Single

edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the
output is a constant LOW.Double edge controlled PWM outputs can have either edge
occur at any position within a cycle. This allows for both positive going and negative
going pulses.

• Pulse period and width can be any number of timer counts. This allows complete

flexibility in the trade-off between resolution and repetition rate. All PWM outputs will
occur at the same repetition rate.

• Double edge controlled PWM outputs can be programmed to be either positive going

or negative going pulses.

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 21 of 39

NXP Semiconductors

• Match register updates are synchronized with pulse outputs to prevent generation of

• May be used as a standard timer if the PWM mode is not enabled.

• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

6.18 System control

6.18.1 Crystal oscillator

On-chip integrated oscillator operates with external crystal in range of 1 MHz to 30 MHz
and with external oscillator up to 50 MHz. The oscillator output frequency is called f
the ARM processor clock frequency is referred to as CCLK forpurposes of rate equations,
etc. f

Section 6.18.2 “PLL” for additional information.

6.18.2 PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled
Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the
multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper
frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so
there is an additional divider in the loop to keep the CCO within its frequency range while
the PLL is providing the desired output frequency. The output divider may be set to divide
by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,
it is insured that the PLL output has a 50 % duty cycle.The PLL is turned off and bypassed
following a chip reset and may be enabled by software. The program must configure and
activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The
PLL settling time is 100 µs.

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

erroneous pulses. Software must ‘release’ new match values before they can become
effective.

and

osc

and CCLK are the same value unless the PLL is running and connected. Refer to

osc

6.18.3 Reset and wake-up timer

Reset has two sources on the LPC2131/32/34/36/38: the RESET pin and watchdog reset.
The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of
chip reset by any source starts the wake-up timer (see wake-up timer description below),
causing the internal chip reset to remain asserted until the external reset is de-asserted,
the oscillator is running, a fixed number of clocks have passed, and the on-chip flash
controller has completed its initialization.

When the internal reset is removed, the processor begins executing at address 0, which is
the reset vector. At that point, all of the processor and peripheral registers have been
initialized to predetermined values.

The wake-up timer ensures that the oscillator and other analog functions required for chip
operation are fully functional before the processor is allowed to execute instructions. This
is important at power on, all types of reset, and whenever any of the aforementioned
functions are turned off for any reason. Since the oscillator and other functions are turned
off during Power-down mode, any wake-up of the processor from Power-down mode
makes use of the wake-up timer.

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 22 of 39

NXP Semiconductors

The wake-up timer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of VDD ramp (in the case of power on), the type of crystal
and its electrical characteristics (if a quartz crystal is used), as well as any other external
circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing
ambient conditions.

6.18.4 Brownout detector

The LPC2131/32/34/36/38 include 2-stage monitoring of the voltage on the VDD pins. If
this voltage falls below 2.9 V, the BOD asserts an interrupt signal to the VectoredInterrupt
Controller. This signal can be enabled for interrupt; if not, software can monitor the signal
by reading dedicated register.

The second stage of low-voltage detection asserts reset to inactivate the
LPC2131/32/34/36/38 when the voltage on the VDD pins falls below 2.6 V. This reset
prevents alteration of the flash as operation of the various elements of the chip would
otherwise become unreliable due to low voltage. The BOD circuit maintains this reset
down below 1 V, at which point the POR circuitry maintains the overall reset.

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

Both the 2.9 V and 2.6 V thresholds include some hysteresis. In normal operation, this
hysteresis allows the 2.9 V detection to reliably interrupt, or a regularly-executed event
loop to sense the condition.

Features available only in LPC213x/01 parts include ability to put the BOD in power-down
mode, turn it on or off and to control when the BOD will reset the LPC213x/01
microcontroller.This can be used to further reduce power consumption when a low power
mode (such as Power Down) is invoked.

6.18.5 Code security

This feature of the LPC2131/32/34/36/38 allow an application to control whether it can be
debugged or protected from observation.

If after reset on-chip bootloader detects a valid checksum in flash and reads 0x8765 4321
from address 0x1FC in flash, debugging will be disabled and thus the code in flash will be
protected from observation. Once debugging is disabled, it can be enabled only by
performing a full chip erase using the ISP.

6.18.6 External interrupt inputs

The LPC2131/32/34/36/38 include up to nine edge or level sensitive External Interrupt
Inputs as selectable pin functions. When the pins are combined, external events can be
processed as four independent interrupt signals. The External Interrupt Inputs can
optionally be used to wake up the processor from Power-down mode.

6.18.7 Memory Mapping Control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip
flash memory, or to the on-chip static RAM. This allows code running in different memory
spaces to have control of the interrupts.

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 23 of 39

NXP Semiconductors

6.18.8 Power Control

The LPC2131/32/34/36/38 support two reduced power modes: Idle mode and
Power-down mode.

In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs.
Peripheral functions continue operation during Idle mode and may generate interrupts to
cause the processor to resume execution. Idle mode eliminates power used by the
processor itself, memory systems and related controllers, and internal buses.

In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.
The processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Power-down mode and the logic levels of chip output pins remain
static. The Power-downmode can be terminated and normal operation resumed by either
a reset or certain specific interrupts that are able to function without clocks. Since all
dynamic operation of the chip is suspended, Power-down mode reduces chip power
consumption to nearly zero.

Selecting an external 32 kHz clock instead of the PCLK as a clock-source for the on-chip
RTC will enable the microcontroller to have the RTC active during Power-down mode.
Power-down current is increased with RTC active. However, it is significantly lower than in
Idle mode.

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

A Power Control for Peripherals feature allows individual peripherals to be turned off if
they are not needed in the application, resulting in additional power savings.

6.18.9 VPB bus

The VPB divider determines the relationship between the processor clock (CCLK) and the
clock used by peripheral devices (PCLK). The VPB divider serves two purposes. The first
is to provide peripherals with the desired PCLK via VPB bus so that they can operate at
the speed chosen for the ARM processor. In order to achieve this, the VPB bus may be
slowed down to1⁄2 to1⁄4 of the processor clock rate. Because the VPB bus must work
properly at power-up (and its timing cannot be altered if it does not work since the VPB
divider control registers reside on the VPB bus), the default condition at reset is for the
VPB bus to run at1⁄4 of the processor clock rate. The second purpose of the VPB divider
is to allow power savings when an application does not require any peripherals to run at
the full processor rate. Because the VPB divider is connected to the PLL output, the PLL
remains active (if it was running) during Idle mode.

6.19 Emulation and debugging

The LPC2131/32/34/36/38 support emulation and debugging via a JTAG serial port. A
trace port allows tracing program execution. Debugging and trace functions are
multiplexed only with GPIOs on Port 1. This means that all communication, timer and
interface peripherals residing on Port 0 are available during the development and
debugging phase as they are when the application is run in the embedded system itself.

6.19.1 EmbeddedICE

Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of
the target system requires a host computer running the debugger software and an
EmbeddedICE protocol convertor.EmbeddedICE protocol convertor converts the Remote
Debug Protocol commands to the JTAG data needed to access the ARM core.

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Product data sheet Rev. 04 — 16 October 2007 24 of 39

NXP Semiconductors

The ARM core has a Debug Communication Channel function built-in. The debug
communication channel allows a program running on the target to communicate with the
host debugger or another separate host without stopping the program flow or even
entering the debug state. The debug communication channel is accessed as a
co-processor 14 by the program running on the ARM7TDMI-S core. The debug
communication channel allows the JTAG port to be used for sending and receiving data
without affecting the normal program flow. The debug communication channel data and
control registers are mapped in to addresses in the EmbeddedICE logic.

6.19.2 Embedded trace

Since the LPC2131/32/34/36/38 have significant amounts of on-chip memory, it is not
possible to determine how the processor core is operating simply by observing the
external pins. The Embedded Trace Macrocell provides real-time trace capability for
deeply embedded processor cores. It outputs information about processor execution to
the trace port.

The ETM is connected directly to the ARM core and not to the main AMBA system bus. It
compresses the trace information and exports it through a narrow trace port. An external
trace port analyzer must capture the trace information under software debugger control.
Instruction trace (or PC trace) shows the flow of executionof the processor and provides a
list of all the instructions that were executed. Instruction trace is significantly compressed
by only broadcasting branch addresses as well as a set of status signals that indicate the
pipeline status on a cycle by cycle basis. Trace information generation can be controlled
by selecting the trigger resource. Trigger resources include address comparators,
counters and sequencers. Since trace information is compressed the software debugger
requires a static image of the code being executed.Self-modifying code can not be traced
because of this restriction.

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

6.19.3 RealMonitor

RealMonitor is a configurable software module, developed by ARM Inc., which enables
real time debug. It is a lightweight debug monitor that runs in the background while users
debug their foreground application. It communicates with the host using the DCC, which is
present in the EmbeddedICE logic. The LPC2131/32/34/36/38 contain a specific
configuration of RealMonitor software programmed into the on-chip flash memory.

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 25 of 39

NXP Semiconductors

7. Limiting values

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

[1]

Symbol Parameter Conditions Min Max Unit

V

DD

V

DDA

V

i(VBAT)

V

i(VREF)

V

IA

supply voltage (core and external rail) −0.5 +3.6 V
analog 3.3 V pad supply voltage −0.5 +4.6 V
input voltage on pin VBAT for the RTC −0.5 +4.6 V
input voltage on pin VREF −0.5 +4.6 V
analog input voltage on ADC related

−0.5 +5.1 V

pins

V

I

input voltage 5 V tolerant I/O

[2]

−0.5 +6.0 V
pins; only valid
when the V

DD

supply voltage is
present

I

DD

I

SS

T

stg

P

tot(pack)

[2]

other I/O pins

−0.5 VDD + 0.5

supply current per supply pin - 100
ground current per ground pin - 100
storage temperature
total power dissipation (per package) based on package

[5]

−40 +125 °C

- 1.5 W

[3]

V

[4]
[4]

mA
mA

heat transfer, not
device power
consumption

V

esd

electrostatic discharge voltage human body model

[6]

all pins −4000 +4000 V

[1] The following applies to the Limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventionalprecautionsbetakento avoidapplyinggreaterthantheratedmaximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless

otherwise noted.
[2] Including voltage on outputs in 3-state mode.
[3] Not to exceed 4.6 V.
[4] The peak current is limited to 25 times the corresponding maximum current.
[5] Dependent on package type.
[6] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 26 of 39

NXP Semiconductors

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

8. Static characteristics

Table 6. Static characteristics

T

=−40°C to +85°C for commercial applications, unless otherwise specified.

amb

Symbol Parameter Conditions Min Typ

V

DD

supply voltage (core and
external rail)

V

DDA

analog 3.3 V pad supply
voltage

V

i(VBAT)

V

i(VREF)

input voltage on pin VBAT 2.0
input voltage on pin VREF 3.0 3.3 3.6 V

Standard port pins,

I

IL

I

IH

I

OZ

I

latch

V

V
V
V
V
V
V
I

OH

I

OL

I

OHS

I

O
IH
IL
hys
OH
OL

LOW-level input current VI= 0 V; no pull-up - - 3 µA
HIGH-level input current VI=VDD; no-pull-down - - 3 µA
OFF-state output current VO=0V; VO=VDD; no

I/O latch-up current −(0.5VDD) < VI < (1.5VDD);

input voltage pin configured to provide a

output voltage output active 0 - V
HIGH-level input voltage 2.0 - - V
LOW-level input voltage - - 0.8 V
hysteresis voltage - 0.4 - V
HIGH-level output voltage IOH= −4 mA
LOW-level output voltage IOL= −4 mA
HIGH-level output current VOH=VDD− 0.4 V
LOW-level output current VOL= 0.4 V
HIGH-level short-circuit

current

I

OLS

LOW-level short-circuit
current

I

pd

I

pu

I

DD(act)

pull-down current VI=5V
pull-up current VI=0 V

active mode supply
current

I

DD(pd)

Power-down mode supply
current

RESET, RTCK

pull-up/down

T

< 125 °C

j

digital function

VOH=0 V

VOL=V

V
VDD= 3.3 V; T

< VI < 5 V

DD

DDA

amb

=25°C;

code

while(1){}

executed from flash, no active
peripherals

CCLK = 10 MHz - 10 - mA
CCLK = 60 MHz - 40 - mA

VDD = 3.3 V; T

= 3.3 V; T

V

DD

=25°C - 60 - µA

amb

=85°C - 200 500 µA

amb

3.0 3.3 3.6 V

2.5 3.3 3.6 V

[2]

3.3 3.6 V

--3µA

- - 100 mA

[3][4][5]

0 - 5.5 V

[6]

VDD− 0.4 - - V

[6]

- - 0.4 V

[6]

−4- - mA

[6]

4--mA

[7]

--−45 mA

[7]

- - 50 mA

[8]

10 50 150 µA

[9]

−15 −50 −85 µA

[8]

000µA

[1]

Max Unit

DD

V

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 27 of 39

NXP Semiconductors

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

Table 6. Static characteristics

T

=−40°C to +85°C for commercial applications, unless otherwise specified.

amb

…continued

Symbol Parameter Conditions Min Typ

I

BATpd

I

BATact

Power-down modebattery
supply current

[10]

active mode battery
supply current

[10]

RTC clock = 32 kHz
(from RTCX pins);
T

=25°C

amb

= 3.0 V; V

V

DD

V

DD

V

DD

V

DD

= 3.0 V; V
= 3.3 V; V
= 3.6 V; V

i(VBAT)
i(VBAT)
i(VBAT)
i(VBAT)

CCLK = 60 MHz;
PCLK = 15 MHz;

= 2.5 V - 14 - µA
= 3.0 V - 16 - µA
= 3.3 V - 18 - µA
= 3.6 V - 20 - µA

PCLK enabled to RTCK;
RTC clock = 32 kHz
(from RTCX pins);
T

=25°C

amb

I

BATact(opt)

optimized active mode
battery supply

[10][11]

current

= 3.0 V; V

V

DD

= 3.3 V; V

V

DD

= 3.6 V; V

V

DD

PCLK disabled to RTCK in the
PCONP register;
RTC clock = 32 kHz

= 3.0 V - 78 - µA

i(VBAT)

= 3.3 V - 80 - µA

i(VBAT)

= 3.6 V - 82 - µA

i(VBAT)

(from RTCX pins);
T

=25°C; V

amb

i(VBAT)

= 3.3 V

CCLK = 6 MHz - 21 - µA
CCLK = 25 MHz - 23 - µA
CCLK = 50 MHz - 27 - µA
CCLK = 60 MHz - 30 - µA

2

C-bus pins

I

V

IH

V

IL

V

hys

V

OL

I

LI

HIGH-level input voltage
LOW-level input voltage
hysteresis voltage - 0.5V
LOW-level output voltage I
input leakage current VI=V

OLS

V

I

= 3 mA

DD

=5V

[12]

0.7V

DD

[12]

- - 0.3V

[6]

- - 0.4 V

[13]

-24µA

[13]

-1022µA

--V

Oscillator pins

V

i(XTAL1)

input voltage on pin

0 - 1.8 V

XTAL1

V

o(XTAL2)

output voltage on pin

0 - 1.8 V

XTAL2

V

i(RTCX1)

input voltage on pin

0 - 1.8 V

RTCX1

V

o(RTCX2)

output voltage on pin

0 - 1.8 V

RTCX2

[1]

DD

Max Unit

V

DD

-V

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.
[2] The RTC typically fails when V
[3] Including voltage on outputs in 3-state mode.

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 28 of 39

drops below 1.6 V.

i(VBAT)

NXP Semiconductors

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

[4] VDD supply voltages must be present.
[5] 3-state outputs go into 3-state mode when VDD is grounded.
[6] Accounts for 100 mV voltage drop in all supply lines.
[7] Only allowed for a short time period.
[8] Minimum condition for VI= 4.5 V, maximum condition for VI= 5.5 V.
[9] Applies to P1.16 to P1.25.
[10] On pin VBAT.
[11] Optimized for low battery consumption.
[12] The input threshold voltage of I2C-bus pins meets the I2C-bus specification, so an input voltage below 1.5 V will be recognized as a

logic 0 while an input voltage above 3.0 V will be recognized as a logic 1.

[13] To VSS.

Table 7. ADC static characteristics

V

= 2.5 V to 3.6 V; T

DDA

Symbol Parameter Conditions Min Typ Max Unit

V

IA

C

ia

analog input voltage 0 - V
analog input

capacitance
E
E
E
E
E

D
L(adj)
O
G
T

differential linearity error V

integral non-linearity V

offset error V

gain error V

absolute error V

=−40°C to +85°C, unless otherwise specified; ADC frequency 4.5 MHz.

amb

--1pF

SSA
SSA
SSA
SSA
SSA

=0V, V
=0V, V
=0V, V
=0V, V
=0V, V

DDA
DDA
DDA
DDA
DDA

= 3.3 V
= 3.3 V
= 3.3 V
= 3.3 V
= 3.3 V

[1][2]

--±1 LSB

[3]

--±2 LSB

[4]

--±3 LSB

[5]

--±0.5 %

[6]

--±4 LSB

DDA

V

[1] The ADC is monotonic, there are no missing codes.
[2] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 7.
[3] The integral no-linearity (E

appropriate adjustment of gain and offset errors. See Figure 7.

[4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the

ideal curve. See Figure 7.

[5] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset

error, and the straight line which fits the ideal transfer curve. See Figure 7.

[6] The absolute voltage error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the

non-calibrated A/D and the ideal transfer curve. See Figure 7.

) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

L(adj)

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 29 of 39

NXP Semiconductors

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

code

out

1023

1022

1021

1020

1019

1018

offset

error

(2)

7

(1)

6

5

(5)

4

(4)

3

(3)

2

gain
error

E

E

O

G

1

0

offset error

E

O

1 LSB
(ideal)

7123456

VIA (LSB

ideal

10241018 1019 1020 1021 1022 1023

)

− V

V

DDA

1 LSB =

1024

SSA

002aac046

(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (E

L(adj)

).

(5) Center of a step of the actual transfer curve.

Fig 7. ADC characteristics

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 30 of 39

NXP Semiconductors

ADx.y

Fig 8. Suggested ADC interface - LPC2131/32/34/36/38 ADx.y pin

9. Dynamic characteristics

LPC2131/32/34/36/38

SAMPLE

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

R

20 kΩ

3 pF

V

SS

5 pF

ADx.y

vsi

V

EXT

002aad452

Table 8. Dynamic characteristics

T

=−40°C to +85°C for commercial applications, VDD over specified ranges.

amb

Symbol Parameter Conditions Min Typ

[1]

[2]

External clock

f

osc

T

cy(clk)

t

CHCX

t

CLCX

t

CLCH

t

CHCL

oscillator frequency 10 - 25 MHz
clock cycle time 40 - 100 ns
clock HIGH time T
clock LOW time T

× 0.4 - - ns

cy(clk)

× 0.4 - - ns

cy(clk)

clock rise time - - 5 ns
clock fall time - - 5 ns

Port pins (except P0.2 and P0.3)

t

r(o)

t

f(o)

2

C-bus pins (P0.2 and P0.3)

I

t

f(o)

[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.
[3] Bus capacitance Cb in pF, from 10 pF to 400 pF.

output rise time - 10 - ns
output fall time - 10 - ns

output fall time VIH to V

IL

20 + 0.1 × C

[3]

--ns

b

Max Unit

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 31 of 39

NXP Semiconductors

9.1 Timing

Fig 9. External clock timing

9.2 LPC2138 power consumption measurements

− 0.5 V

V

DD

0.45 V

VDD= 1.8 V.

0.2V

0.2V

DD

+ 0.9 V

DD

− 0.1 V

t

CHCL

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

t

t

CLCX

T

cy(clk)

CHCX

t

CLCH

002aaa907

40

IDD (mA)

30

20

10

0

0 60402010 5030

Test conditions: code executed from flash; all peripherals are enabled in PCONP register; PCLK = CCLK/4.
(1) VDD = 3.6 V at −60 °C (max)
(2) VDD = 3.6 V at 140 °C
(3) VDD = 3.6 V at 25 °C
(4) VDD = 3.3 V at 25 °C (typical)
(5) VDD = 3.3 V at 95 °C (typical)

Fig 10. I

measured at different frequencies (CCLK) and temperatures

DD(act)

002aab404

frequency (MHz)

(1)
(2)
(3)
(4)
(5)

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 32 of 39

NXP Semiconductors

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

15

IDD (mA)

10

5

0

0 60

402010 5030

Test conditions: Idle mode entered executing code from flash; all peripherals are enabled in PCONP register;

PCLK = CCLK/4.
(1) VDD = 3.6 V at 140 °C (max)
(2) VDD = 3.6 V at −60 °C
(3) VDD = 3.6 V at 25 °C
(4) VDD = 3.3 V at 25 °C (typical)
(5) VDD = 3.3 V at 95 °C (typical)

Fig 11. IDD idle measured at different frequencies (CCLK) and temperatures

002aab403

frequency (MHz)

(1)
(2)
(3)
(4)
(5)

500

(µA)

I

DD

400

300

200

100

0

−60 14010020 60−20

Test conditions: Power-down mode entered executing code from flash; all peripherals are enabled in PCONP register.
(1) VDD = 3.6 V
(2) VDD = 3.3 V (max)
(3) VDD = 3.0 V
(4) VDD = 3.3 V (typical)

Fig 12. I

measured at different temperatures

DD(pd)

002aab405

(1)
(2)
(3)
(4)

temp °(C)

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 33 of 39

NXP Semiconductors

10. Package outline

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm

c

y

X

A

48 33

49

64

pin 1 index

1

16

Z

32

E

e

H

E

E

w M

b

p

17

A

2

A

A

1

detail X

SOT314-2

(A )

3

θ

L

p

L

Z

e

DIMENSIONS (mm are the original dimensions)

A

UNIT

mm

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE
VERSION

SOT314-2 MS-026136E10

A1A2A3bpcE

max.

0.20

0.05

1.45

1.35

IEC JEDEC JEITA

1.6

b

0.25

w M

p

D

H

D

0.27

0.17

D

(1)

(1) (1)(1)

D

0.18

0.12

10.1

10.1

9.9

9.9

REFERENCES

v M

A

B

v M

B

0 2.5 5 mm

scale

eHELL

H

D

12.15

12.15

0.5

11.85

11.85

0.75

0.45

Zywv θ

p

0.12 0.11 0.2

EUROPEAN

PROJECTION

Z

D

1.45

1.05

E

1.45

7

1.05

0

ISSUE DATE

00-01-19
03-02-25

o
o

Fig 13. Package outline SOT314-2 (LQFP64)

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 34 of 39

NXP Semiconductors

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

HVQFN64: plastic thermal enhanced very thin quad flat package; no leads; 64 terminals;
body 9 x 9 x 0.85 mm

SOT804-2

terminal 1
index area

L

D

D

1

e

1

e

16

1/2 e

b

B

A

A

4

ACCB

A

c

A

1

y

detail X

C

C

1

y

E1E

v

M

w

3217

M

33

e

E

h

1

terminal 1
index area

DIMENSIONS (mm are the original dimensions)

UNIT

A

max.

mm

1

OUTLINE
VERSION

SOT804-2 - - - MO-220 - - -

64

A

A4bc eE

1

0.05

0.80

0.00

0.30

0.65

0.18

IEC JEDEC JEITA

D

h

0 5 10 mm

D

D

1

7.25

8.95

9.05

8.95

6.95

8.55

REFERENCES

49

D

E

h

9.05

8.95

e

2

1/2 e

48

X

scale

E

8.95

8.55

Le

e

1

h

1

7.25

0.5 7.5

6.95

2

0.5

7.50.2

0.3

EUROPEAN

PROJECTION

ywv

0.05 0.05

ISSUE DATE

04-03-25

y

1

0.10.1

Fig 14. Package outline SOT804-2 (HVQFN64)

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 35 of 39

NXP Semiconductors

11. Abbreviations

Table 9. Acronym list

Acronym Description

ADC Analog-to-Digital Converter
BOD BrownOut Detection
CPU Central Processing Unit
DAC Digital-to-Analog Converter
DCC Debug Communications Channel
FIFO First In, First Out
GPIO General Purpose Input/Output
JTAG Joint Test Action Group
PLL Phase-Locked Loop
POR Power-On Reset
PWM Pulse Width Modulator
RAM Random Access Memory
SPI Serial Peripheral Interface
SRAM Static Random Access Memory
SSP Synchronous Serial Port
UART Universal Asynchronous Receiver/Transmitter
VPB VLSI Peripheral Bus

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 36 of 39

NXP Semiconductors

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

12. Revision history

Table 10. Revision history

Document ID Release date Data sheet status Change notice Supersedes

LPC2131_32_34_36_38_4 20071016 Product data sheet - LPC2131_32_34_36_38_3
Modifications:

LPC2131_32_34_36_38_3 20060921 Product data sheet - LPC2131_32_34_36_38_2
LPC2131_32_34_36_38_2 20050318 Preliminary data sheet - LPC2131_2132_2138_1
LPC2131_2132_2138_1 20041118 Preliminary data sheet - -

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Figure 1: changed incorrect character font

• Figure 5: added figure note

• Table 3: description for function AD1.3, pin 38, changed LPC2138 into LPC2134/36/38

• Figure 7: added

• Figure 9: added figure note

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 37 of 39

NXP Semiconductors

13. Legal information

13.1 Data sheet status

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described inthis document may have changed since thisdocument waspublished and may differin case of multiple devices.The latestproduct status

information is available on the Internet at URL

[1][2]

Product status

13.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information includedherein and shallhave no liabilityfor the consequencesof
use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet
with thesame product typenumber(s) and title.A short data sheetis intended
for quickreference only and shouldnot be relied upon tocontain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.

13.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXPSemiconductors does not giveany representations or
warranties, expressed or implied, as tothe accuracy or completenessof such
information and shall have no liability for the consequences of use of such
information.

Right to make changes — NXP Semiconductors reserves theright to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. Thisdocument supersedes and replaces all information supplied prior
to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction ofa NXP Semiconductorsproduct can reasonablybe expectedto

[3]

http://www.nxp.com.

Definition

result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined in
the Absolute MaximumRatings System of IEC 60134)may cause permanent
damage tothe device. Limitingvalues are stress ratingsonly and operationof
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditionsof commercial sale, as published
at

http://www.nxp.com/profile/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of anylicense under any copyrights,patents
or other industrial or intellectual property rights.

13.4 Trademarks

Notice: Allreferenced brands,product names, servicenames and trademarks
are the property of their respective owners.

I2C-bus — logo is a trademark of NXP B.V.

14. Contact information

For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [e-mail]

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 38 of 39

NXP Semiconductors

15. Contents

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.1 Enhancements brought by LPC213x/01

devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.2 Key features common for LPC213x and

LPC213x/01 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3

4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9

6 Functional description . . . . . . . . . . . . . . . . . . 13

6.1 Architectural overview. . . . . . . . . . . . . . . . . . . 13

6.2 On-chip flash program memory . . . . . . . . . . . 13

6.3 On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 13

6.4 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.5 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 15

6.5.1 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 15

6.6 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 16

6.7 General purpose parallel I/O and Fast I/O . . . 16

6.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.7.2 Fast I/O features available in LPC213x/01 only 17

6.8 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.8.2 ADC features available in LPC213x/01 only. . 17

6.9 10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.10 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.10.2 UART features available in LPC213x/01 only. 18

6.11 I

2

C-bus serial I/O controller . . . . . . . . . . . . . . 18

6.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.12 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 18

6.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.13 SSP serial I/O controller . . . . . . . . . . . . . . . . . 19

6.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.14 General purpose timers/external event

counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.15 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 20

6.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.16 Real-time clock . . . . . . . . . . . . . . . . . . . . . . . . 20

6.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.17 Pulse width modulator . . . . . . . . . . . . . . . . . . 21

6.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.18 System control . . . . . . . . . . . . . . . . . . . . . . . . 22

6.18.1 Crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . 22

6.18.2 PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.18.3 Reset and wake-up timer . . . . . . . . . . . . . . . . 22

6.18.4 Brownout detector . . . . . . . . . . . . . . . . . . . . . 23

6.18.5 Code security. . . . . . . . . . . . . . . . . . . . . . . . . 23

6.18.6 External interrupt inputs. . . . . . . . . . . . . . . . . 23

6.18.7 Memory Mapping Control. . . . . . . . . . . . . . . . 23

6.18.8 Power Control. . . . . . . . . . . . . . . . . . . . . . . . . 24

6.18.9 VPB bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.19 Emulation and debugging. . . . . . . . . . . . . . . . 24

6.19.1 EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 24

6.19.2 Embedded trace. . . . . . . . . . . . . . . . . . . . . . . 25

6.19.3 RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 26

8 Static characteristics . . . . . . . . . . . . . . . . . . . 27

9 Dynamic characteristics. . . . . . . . . . . . . . . . . 31

9.1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

9.2 LPC2138 power consumption measurements 32

10 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 34

11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 36

12 Revision history . . . . . . . . . . . . . . . . . . . . . . . 37

13 Legal information . . . . . . . . . . . . . . . . . . . . . . 38

13.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 38

13.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

13.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 38

13.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 38

14 Contact information . . . . . . . . . . . . . . . . . . . . 38

15 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.

© NXP B.V. 2007. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [e-mail]

Document identifier: LPC2131_32_34_36_38_4

Date of release: 16 October 2007