NXP LPC 2138 FBD64 Datasheet

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers; 32/64/128/256/512 kB
ISP/IAP flash with 10-bit ADC and DAC

Rev. 04 — 16 October 2007 Product data sheet

1. General description

The LPC2131/32/34/36/38 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU
with real-time emulation and embedded trace support, that combine the microcontroller
with 32 kB, 64 kB, 128 kB, 256 kB and 512 kB of embedded high-speed flash memory. A
128-bit wide memory interface and a unique accelerator architecture enable 32-bit code
execution at maximum clock rate. For critical code size applications, the alternative 16-bit
Thumb mode reduces code by more than 30 % with minimal performance penalty.

Due to their tiny size and low power consumption, these microcontrollers are ideal for
applications where miniaturization is a key requirement, such as access control and
point-of-sale. With a wide range of serial communications interfaces and on-chip SRAM
options of 8 kB, 16 kB, and 32 kB, they are very well suited for communication gateways
and protocol converters, soft modems, voice recognition and low-end imaging, providing
both large buffer size and high processing power. Various 32-bit timers, single or dual
10-bit 8-channel ADC(s), 10-bit DAC, PWM channels and 47 GPIO lines with up to nine
edge or level sensitive external interrupt pins make these microcontrollers particularly
suitable for industrial control and medical systems.

2. Features

2.1 Enhancements brought by LPC213x/01 devices

2.2 Key features common for LPC213x and LPC213x/01

n Fast GPIO ports enable port pin toggling up to 3.5 times faster than the original

LPC213x. They also allow for a port pin to be read at any time regardless of its
function.

n Dedicated result registers for ADC(s) reduce interrupt overhead.
n UART0/1 include fractional baud rate generator, auto-bauding capabilities and

handshake flow-control fully implemented in hardware.

n Additional BOD control enables further reduction of power consumption.

n 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 or HVQFN package.
n 8/16/32 kB of on-chip static RAM and 32/64/128/256/512 kB of on-chip flash program

memory. 128-bit wide interface/accelerator enables high-speed 60 MHz operation.

n In-System Programming/In-ApplicationProgramming (ISP/IAP) via on-chip bootloader

software. Single flash sector or full chip erase in 400 ms and programming of 256 B in
1 ms.

n EmbeddedICE RT and Embedded Trace interfaces offer real-time debugging with the

on-chip RealMonitor software and high-speed tracing of instruction execution.

NXP Semiconductors

n One (LPC2131/32) or two (LPC2134/36/38) 8-channel 10-bit ADCs provide a total of

n Single 10-bit DAC provides variable analog output (LPC2132/34/36/38).
n Two 32-bit timers/external event counters (with four capture and four compare

n Low power Real-time clock with independent power and dedicated 32 kHz clock input.
n Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus (400 kbit/s),

n Vectored interrupt controller with configurable priorities and vector addresses.
n Up to forty-seven 5 V tolerant general purpose I/O pins in tiny LQFP64 or HVQFN

n Up to nine edge or level sensitive external interrupt pins available.
n 60 MHz maximum CPU clock available from programmable on-chip PLL with settling

n On-chip integrated oscillator operates with external crystal in range of 1 MHz to

n Power saving modes include Idle and Power-down.
n Individual enable/disable of peripheral functions as well as peripheral clock scaling

n Processor wake-up from Power-down mode via external interrupt or BOD.
n Single power supply chip with POR and BOD circuits:

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

up to 16 analog inputs, with conversion times as low as 2.44 µs per channel.

channels each), PWM unit (six outputs) and watchdog.

SPI and SSP with buffering and variable data length capabilities.

package.

time of 100 µs.

30 MHz and with external oscillator up to 50 MHz.

down for additional power optimization.

u CPU operating voltage range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O

pads.

3. Ordering information

Table 1. Ordering information

Type number Package

LPC2131FBD64 LQFP64 plastic low profile quad flat package; 64 leads;

LPC2131FBD64/01 LQFP64 plastic low profile quad flat package; 64 leads;

LPC2132FBD64 LQFP64 plastic low profile quad flat package; 64 leads;

LPC2132FBD64/01 LQFP64 plastic low profile quad flat package; 64 leads;

LPC2132FHN64 HVQFN64 plastic thermal enhanced very thin quad flat

LPC2132FHN64/01 HVQFN64 plastic thermal enhanced very thin quad flat

LPC2134FBD64 LQFP64 plastic low profile quad flat package; 64 leads;

LPC2134FBD64/01 LQFP64 plastic low profile quad flat package; 64 leads;

Name Description Version

SOT314-2

body 10 × 10 × 1.4 mm

SOT314-2

body 10 × 10 × 1.4 mm

SOT314-2

body 10 × 10 × 1.4 mm

SOT314-2

body 10 × 10 × 1.4 mm

SOT804-2
package; no leads; 64 terminals; body
9 × 9 × 0.85 mm

SOT804-2
package; no leads; 64 terminals; body
9 × 9 × 0.85 mm

SOT314-2
body 10 × 10 × 1.4 mm

SOT314-2
body 10 × 10 × 1.4 mm

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 2 of 39

NXP Semiconductors

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

Table 1. Ordering information

Type number Package

Name Description Version

LPC2136FBD64 LQFP64 plastic low profile quad flat package; 64 leads;

LPC2136FBD64/01 LQFP64 plastic low profile quad flat package; 64 leads;

LPC2138FBD64 LQFP64 plastic low profile quad flat package; 64 leads;

LPC2138FBD64/01 LQFP64 plastic low profile quad flat package; 64 leads;

LPC2138FHN64 HVQFN64 plastic thermal enhanced very thin quad flat

LPC2138FHN64/01 HVQFN64 plastic thermal enhanced very thin quad flat

…continued

body 10 × 10 × 1.4 mm

body 10 × 10 × 1.4 mm

body 10 × 10 × 1.4 mm

body 10 × 10 × 1.4 mm

package; no leads; 64 terminals; body
9 × 9 × 0.85 mm

package; no leads; 64 terminals; body
9 × 9 × 0.85 mm

3.1 Ordering options

Table 2. Ordering options

Type number Flash

memory

LPC2131FBD64 32 kB 8 kB 1 - no −40 °C to +85 °C
LPC2131FBD64/01 32 kB 8 kB 1 - yes −40 °C to +85 °C
LPC2132FBD64 64 kB 16 kB 1 1 no −40 °C to +85 °C
LPC2132FBD64/01 64 kB 16 kB 1 1 yes −40 °C to +85 °C
LPC2132FHN64 64 kB 16 kB 1 1 no −40 °C to +85 °C
LPC2132FHN64/01 64 kB 16 kB 1 1 yes −40 °C to +85 °C
LPC2134FBD64 128 kB 16 kB 2 1 no −40 °C to +85 °C
LPC2134FBD64/01 128 kB 16 kB 2 1 yes −40 °C to +85 °C
LPC2136FBD64 256 kB 32 kB 2 1 no −40 °C to +85 °C
LPC2136FBD64/01 256 kB 32 kB 2 1 yes −40 °C to +85 °C
LPC2138FBD64 512 kB 32 kB 2 1 no −40 °C to +85 °C
LPC2138FBD64/01 512 kB 32 kB 2 1 yes −40 °C to +85 °C
LPC2138FHN64 512 kB 32 kB 2 1 no −40 °C to +85 °C
LPC2138FHN64/01 512 kB 32 kB 2 1 yes −40 °C to +85 °C

RAM ADC DAC Enhanced UARTs,

ADC, Fast I/Os, and
BOD

Temperature
range

SOT314-2

SOT314-2

SOT314-2

SOT314-2

SOT804-2

SOT804-2

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 3 of 39

NXP Semiconductors

4. Block diagram

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

P0[31:0]

P1[31:16]

EINT[3:0]

8 × CAP

8 × MAT

AD0[7:0]

AD1[7:0]

AOUT

P0[31:0]

P1[31:16]

PWM[6:1]

TRST

(3)

TMS

(3)

TCK

(3)

TDI

(3)

TDO

(3)

trace

signals

XTAL1

XTAL2

RESET

LPC2131, LPC2131/01
LPC2132, LPC2132/01
LPC2134, LPC2134/01
LPC2136, LPC2136/01
LPC2138, LPC2138/01

FAST GENERAL

PURPOSE I/O

ARM7 local bus

INTERNAL

SRAM

CONTROLLER

8/16/32 kB

SRAM

TIMER 0/TIMER 1

A/D CONVERTERS

(1)

(2)

D/A CONVERTER

INTERNAL

FLASH

CONTROLLER

32/64/128/

256/512 kB

FLASH

EXTERNAL

INTERRUPTS

CAPTURE/
COMPARE

(1)

0 AND 1

GENERAL

PURPOSE I/O

PWM0

(2)

TEST/DEBUG

INTERFACE

ARM7TDMI-S

AHB BRIDGE

AHB TO APB

BRIDGE

PLL

system

EMULATION

clock

TRACE MODULE

(Advanced High-performance Bus)

APB (ARM

peripheral bus)

AMBA AHB

APB

DIVIDER

2

C SERIAL

I

INTERFACES 0 AND 1

SPI AND SSP

SERIAL INTERFACES

UART0/UART1

REAL TIME CLOCK

WATCHDOG

TIMER

SYSTEM

FUNCTIONS

VECTORED
INTERRUPT

CONTROLLER

AHB

DECODER

SCL0,1

SDA0,1

SCK0,1
MOSI0,1
MISO0,1
SSEL0,1

TXD0,1
RXD0,1

DSR1
RTS1
DCD1

RTCX1
RTCX2
VBAT

(1)

(1)

(1)

,CTS1

, DTR1

, RI1

(1)

(1)

(1)

SYSTEM

CONTROL

002aab067

(1) LPC2134/36/38 only.
(2) LPC2132/34/36/38 only.
(3) Pins shared with GPIO.

Fig 1. Block diagram

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 4 of 39

NXP Semiconductors

5. Pinning information

5.1 Pinning

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

VREF

646362616059585756555453525150

V

V

DDA

SS

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

171819202122232425262728293031

SS

V

P0.31 P1.27/TDO

P0.21/PWM5/CAP1.3 P1.20/TRACESYNC

P0.22/CAP0.0/MAT0.0 P0.17/CAP1.2/SCK1/MAT1.2

RTCX1 P0.16/EINT0/MAT0.2/CAP0.2

P1.19/TRACEPKT3 P0.15/EINT2

RTCX2 P1.21/PIPESTAT0

P1.18/TRACEPKT2 P0.14/EINT1/SDA1

P0.25/AD0.4 P1.22/PIPESTAT1
P0.26/AD0.5 P0.13/MAT1.1

P0.27/AD0.0/CAP0.1/MAT0.1 P0.12/MAT1.0

P1.17/TRACEPKT1 P0.11/CAP1.1/SCL1
P0.28/AD0.1/CAP0.2/MAT0.2 P1.23/PIPESTAT2
P0.29/AD0.2/CAP0.3/MAT0.3 P0.10/CAP1.0

P0.30/AD0.3/EINT3/CAP0.0 P0.9/RXD1/PWM6/EINT3

P1.16/TRACEPKT0 P0.8/TXD1/PWM4

SSA

P0.23

LPC2131

LPC2131/01

DD

V

P1.29/TCK

SS

V

DD

SS

49

32

48
47
46
45
44
43

V

DD

42

V

SS

41
40
39
38
37
36
35
34
33

002aab068

P1.31/TRST XTAL2

P0.0/TXD0/PWM1 XTAL1

P0.1/RXD0/PWM3/EINT0 P1.28/TDI

P1.26/RTCK RESET

P0.2/SCL0/CAP0.0 V

P1.25/EXTIN0 P0.18/CAP1.3/MISO1/MAT1.3

P1.24/TRACECLK VBAT

P0.6/MOSI0/CAP0.2 V

P0.4/SCK0/CAP0.1/AD0.6 P0.19/MAT1.2/MOSI1/CAP1.2

P0.3/SDA0/MAT0.0/EINT1 P0.20/MAT1.3/SSEL1/EINT3

P0.7/SSEL0/PWM2/EINT2 V

P0.5/MISO0/MAT0.1/AD0.7 P1.30/TMS

Fig 2. LPC2131 LQFP64 pinning

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 5 of 39

NXP Semiconductors

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

VREF

646362616059585756555453525150

V

V

DDA

SS

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

171819202122232425262728293031

SS

V

P0.31 P1.27/TDO

P0.21/PWM5/CAP1.3 P1.20/TRACESYNC

P0.22/CAP0.0/MAT0.0 P0.17/CAP1.2/SCK1/MAT1.2

RTCX1 P0.16/EINT0/MAT0.2/CAP0.2

P1.19/TRACEPKT3 P0.15/EINT2

RTCX2 P1.21/PIPESTAT0

P1.18/TRACEPKT2 P0.14/EINT1/SDA1
P0.25/AD0.4/AOUT P1.22/PIPESTAT1

P0.26/AD0.5 P0.13/MAT1.1

P0.27/AD0.0/CAP0.1/MAT0.1 P0.12/MAT1.0

P1.17/TRACEPKT1 P0.11/CAP1.1/SCL1
P0.28/AD0.1/CAP0.2/MAT0.2 P1.23/PIPESTAT2
P0.29/AD0.2/CAP0.3/MAT0.3 P0.10/CAP1.0

P0.30/AD0.3/EINT3/CAP0.0 P0.9/RXD1/PWM6/EINT3

P1.16/TRACEPKT0 P0.8/TXD1/PWM4

SSA

P0.23

LPC2132

LPC2132/01

DD

V

P1.29/TCK

SS

V

DD

SS

49

32

48
47
46
45
44
43

V

DD

42

V

SS

41
40
39
38
37
36
35
34
33

002aab406

P1.31/TRST XTAL2

P0.0/TXD0/PWM1 XTAL1

P0.1/RXD0/PWM3/EINT0 P1.28/TDI

P1.26/RTCK RESET

P0.2/SCL0/CAP0.0 V

P1.25/EXTIN0 P0.18/CAP1.3/MISO1/MAT1.3

P1.24/TRACECLK VBAT

P0.6/MOSI0/CAP0.2 V

P0.4/SCK0/CAP0.1/AD0.6 P0.19/MAT1.2/MOSI1/CAP1.2

P0.3/SDA0/MAT0.0/EINT1 P0.20/MAT1.3/SSEL1/EINT3

P0.7/SSEL0/PWM2/EINT2 V

P0.5/MISO0/MAT0.1/AD0.7 P1.30/TMS

Fig 3. LPC2132 LQFP64 pin configuration

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 6 of 39

NXP Semiconductors

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

VREF

646362616059585756555453525150

V

V

DDA

SS

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

171819202122232425262728293031

SS

V

P0.31 P1.27/TDO

P0.21/PWM5/AD1.6/CAP1.3 P1.20/TRACESYNC

P0.22/AD1.7/CAP0.0/MAT0.0 P0.17/CAP1.2/SCK1/MAT1.2

RTCX1 P0.16/EINT0/MAT0.2/CAP0.2

P1.19/TRACEPKT3 P0.15/RI1/EINT2/AD1.5

RTCX2 P1.21/PIPESTAT0

P1.18/TRACEPKT2 P0.14/DCD1/EINT1/SDA1
P0.25/AD0.4/AOUT P1.22/PIPESTAT1

P0.26/AD0.5 P0.13/DTR1/MAT1.1/AD1.4

P0.27/AD0.0/CAP0.1/MAT0.1 P0.12/DSR1/MAT1.0/AD1.3

P1.17/TRACEPKT1 P0.11/CTS1/CAP1.1/SCL1
P0.28/AD0.1/CAP0.2/MAT0.2 P1.23/PIPESTAT2
P0.29/AD0.2/CAP0.3/MAT0.3 P0.10/RTS1/CAP1.0/AD1.2

P0.30/AD0.3/EINT3/CAP0.0 P0.9/RXD1/PWM6/EINT3

P1.16/TRACEPKT0 P0.8/TXD1/PWM4/AD1.1

SSA

P0.23

P1.29/TCK

LPC2134, LPC2134/01
LPC2136, LPC2136/01
LPC2138, LPC2138/01

SS

DD

V

V

DD

SS

49

32

48
47
46
45
44
43

V

DD

42

V

SS

41
40
39
38
37
36
35
34
33

002aab407

P1.31/TRST XTAL2

P0.0/TXD0/PWM1 XTAL1

P0.1/RXD0/PWM3/EINT0 P1.28/TDI

P1.26/RTCK RESET

P0.2/SCL0/CAP0.0 V

P1.25/EXTIN0 P0.18/CAP1.3/MISO1/MAT1.3

P1.24/TRACECLK VBAT

P0.4/SCK0/CAP0.1/AD0.6 P0.19/MAT1.2/MOSI1/CAP1.2

P0.3/SDA0/MAT0.0/EINT1 P0.20/MAT1.3/SSEL1/EINT3

P0.7/SSEL0/PWM2/EINT2 V

P0.6/MOSI0/CAP0.2/AD1.0 V

P0.5/MISO0/MAT0.1/AD0.7 P1.30/TMS

Fig 4. LPC2134/36/38 LQFP64 pin configuration

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 7 of 39

NXP Semiconductors

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

terminal 1

index area

P0.21/PWM5/AD1.6/CAP1.3

P0.22/AD1.7/CAP0.0/MAT0.0

RTCX1

P1.19/TRACEPKT3

RTCX2

V

SS

V

DDA

P1.18/TRACEPKT2

P0.25/AD0.4/AOUT

P0.26/AD0.5

P0.27/AD0.0/CAP0.1/MAT0.1

P1.17/TRACEPKT1
P0.28/AD0.1/CAP0.2/MAT0.2
P0.29/AD0.2/CAP0.3/MAT0.3

P0.30/AD0.3/EINT3/CAP0.0

P1.16/TRACEPKT0

P1.27/TDO

VREF

XTAL1

646362616059585756555453525150
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40

10 39
11 38
12 37
13 36
14 35
15 34
16 33

171819202122232425262728293031

SS

V

P0.31

P0.0/TXD0/PWM1

SSA

XTAL2

P1.28/TDI

V

LPC2132/2138

P1.31/TRST

P0.2/SCL0/CAP0.0

P0.23

RESET

DD

V

P1.26/RTCK

P1.29/TCK

P0.20/MAT1.3/SSEL1/EINT3

P0.19/MAT1.2/MOSI1/CAP1.2

P0.18/CAP1.3/MISO1/MAT1.3

P1.30/TMS

VDDVSSVBAT

SS

V

P1.25/EXTIN0

49

32

P1.24/TRACECLK

P1.20/TRACESYNC
P0.17/CAP1.2/SCK1/MAT1.2
P0.16/EINT0/MAT0.2/CAP0.2
P0.15/RI1/EINT2/AD1.5
P1.21/PIPESTAT0
V

DD

V

SS

P0.14/DCD1/EINT1/SDA1
P1.22/PIPESTAT1
P0.13/DTR1/MAT1.1/AD1.4
P0.12/DSR1/MAT1.0/AD1.3
P0.11/CTS1/CAP1.1/SCL1
P1.23/PIPESTAT2
P0.10/RTS1/CAP1.0/AD1.2
P0.9/RXD1/PWM6/EINT3
P0.8/TXD1/PWM4/AD1.1

P0.1/RXD0/PWM3/EINT0

Transparent top view

P0.4/SCK0/CAP0.1/AD0.6

P0.3/SDA0/MAT0.0/EINT1

P0.7/SSEL0/PWM2/EINT2

P0.6/MOSI0/CAP0.2/AD1.0

P0.5/MISO0/MAT0.1/AD0.7

002aab943

AD1.7 to AD1.0 only available on LPC2134/36/38.

Fig 5. LPC2132/38 HVQFN64 pin configuration

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 8 of 39

NXP Semiconductors

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

5.2 Pin description

Table 3. Pin description

Symbol Pin Type Description

P0.0 to P0.31 I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit.

Total of 31 pins of the Port 0 can be used as a general purpose bidirectional
digital I/Os while P0.31 is output only pin. The operation of port 0 pins
depends upon the pin function selected via the pin connect block.

Pin P0.24 is not available.

P0.0/TXD0/
PWM1

P0.1/RXD0/
PWM3/EINT0

P0.2/SCL0/
CAP0.0

P0.3/SDA0/
MAT0.0/EINT1

P0.4/SCK0/
CAP0.1/AD0.6

P0.5/MISO0/
MAT0.1/AD0.7

P0.6/MOSI0/
CAP0.2/AD1.0

P0.7/SSEL0/
PWM2/EINT2

P0.8/TXD1/
PWM4/AD1.1

P0.9/RXD1/
PWM6/EINT3

P0.10/RTS1/
CAP1.0/AD1.2

19

21

22

26

27

29

30

31

33

34

35

[1]

[2]

[3]

[3]

[4]

[4]

[4]

[2]

[4]

[2]

[4]

O TXD0 — Transmitter output for UART0.
O PWM1 — Pulse Width Modulator output 1.
I RXD0 — Receiver input for UART0.
O PWM3 — Pulse Width Modulator output 3.
I EINT0 — External interrupt 0 input.
I/O SCL0 — I2C0 clock input/output. Open drain output (for I2C-bus compliance).
I CAP0.0 — Capture input for Timer 0, channel 0.
I/O SDA0 — I2C0 data input/output. Open drain output (for I2C-bus compliance).
O MAT0.0 — Match output for Timer 0, channel 0.
I EINT1 — External interrupt 1 input.
I/O SCK0 — Serial clock for SPI0. SPI clock output from master or input to slave.
I CAP0.1 — Capture input for Timer 0, channel 1.
I AD0.6 — ADC 0, input 6. This analog input is always connected to its pin.
I/O MISO0 — Master In Slave VDD = 3.6 V for SPI0. Data input to SPI master or

data output from SPI slave.
O MAT0.1 — Match output for Timer 0, channel 1.
I AD0.7 — ADC 0, input 7. This analog input is always connected to its pin.
I/O MOSI0 — Master Out Slave In for SPI0. Data output from SPI master or data

input to SPI slave.
I CAP0.2 — Capture input for Timer 0, channel 2.
I AD1.0 — ADC 1, input 0. This analog input is always connected to its pin.

Available in LPC2134/36/38 only.
I SSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave.
O PWM2 — Pulse Width Modulator output 2.
I EINT2 — External interrupt 2 input.
O TXD1 — Transmitter output for UART1.
O PWM4 — Pulse Width Modulator output 4.
I AD1.1 — ADC 1, input 1. This analog input is always connected to its pin.

Available in LPC2134/36/38 only.
I RXD1 — Receiver input for UART1.
O PWM6 — Pulse Width Modulator output 6.
I EINT3 — External interrupt 3 input.
O RTS1 — Request to Send output for UART1. Available in LPC2134/36/38.
I CAP1.0 — Capture input for Timer 1, channel 0.
I AD1.2 — ADC 1, input 2. This analog input is always connected to its pin.

Available in LPC2134/36/38 only.

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 9 of 39

NXP Semiconductors

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

Table 3. Pin description

…continued

Symbol Pin Type Description

P0.11/CTS1/
CAP1.1/SCL1

37

[3]

I CTS1 — Clear to Send input for UART1. Available in LPC2134/36/38.
I CAP1.1 — Capture input for Timer 1, channel 1.
I/O SCL1 — I

P0.12/DSR1/
MAT1.0/AD1.3

38

[4]

I DSR1 — Data Set Ready input for UART1. Available in LPC2134/36/38.
O MAT1.0 — Match output for Timer 1, channel 0.
I AD1.3 — ADC 1, input 3. This analog input is always connected to its pin.

Available in LPC2134/36/38 only.

P0.13/DTR1/
MAT1.1/AD1.4

39

[4]

O DTR1 — Data Terminal Ready output for UART1. Available in

LPC2134/36/38.
O MAT1.1 — Match output for Timer 1, channel 1.
I AD1.4 — ADC 1, input 4. This analog input is always connected to its pin.

Available in LPC2134/36/38 only.

P0.14/DCD1/
EINT1/SDA1

41

[3]

I DCD1 — Data Carrier Detect input for UART1. Available in LPC2134/36/38.
I EINT1 — External interrupt 1 input.
I/O SDA1 — I

P0.15/RI1/
EINT2/AD1.5

45

[4]

I RI1 — Ring Indicator input for UART1. Available in LPC2134/36/38.
I EINT2 — External interrupt 2 input.
I AD1.5 — ADC 1, input 5. This analog input is always connected to its pin.

Available in LPC2134/36/38 only.

P0.16/EINT0/
MAT0.2/CAP0.2

46

[2]

I EINT0 — External interrupt 0 input.
O MAT0.2 — Match output for Timer 0, channel 2.
I CAP0.2 — Capture input for Timer 0, channel 2.

P0.17/CAP1.2/
SCK1/MAT1.2

47

[1]

I CAP1.2 — Capture input for Timer 1, channel 2.
I/O SCK1 — Serial Clock for SSP. Clock output from master or input to slave.
O MAT1.2 — Match output for Timer 1, channel 2.

P0.18/CAP1.3/
MISO1/MAT1.3

53

[1]

I CAP1.3 — Capture input for Timer 1, channel 3.
I/O MISO1 — Master In Slave Out for SSP. Data input to SPI master or data

output from SSP slave.
O MAT1.3 — Match output for Timer 1, channel 3.

P0.19/MAT1.2/
MOSI1/CAP1.2

54

[1]

O MAT1.2 — Match output for Timer 1, channel 2.
I/O MOSI1 — Master Out Slave In for SSP. Data output from SSP master or data

input to SSP slave.
I CAP1.2 — Capture input for Timer 1, channel 2.

P0.20/MAT1.3/
SSEL1/EINT3

55

[2]

O MAT1.3 — Match output for Timer 1, channel 3.
I SSEL1 — Slave Select for SSP. Selects the SSP interface as a slave.
I EINT3 — External interrupt 3 input.

P0.21/PWM5/
AD1.6/CAP1.3

[4]

1

O PWM5 — Pulse Width Modulator output 5.
I AD1.6 — ADC 1, input 6. This analog input is always connected to its pin.

Available in LPC2134/36/38 only.
I CAP1.3 — Capture input for Timer 1, channel 3.

2

C1 clock input/output. Open drain output (for I2C-bus compliance)

2

C1 data input/output. Open drain output (for I2C-bus compliance).

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 10 of 39

NXP Semiconductors

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

Table 3. Pin description

…continued

Symbol Pin Type Description

P0.22/AD1.7/
CAP0.0/MAT0.0

[4]

2

I AD1.7 — ADC 1, input 7. This analog input is always connected to its pin.

Available in LPC2134/36/38 only.
I CAP0.0 — Capture input for Timer 0, channel 0.
O MAT0.0 — Match output for Timer 0, channel 0.

P0.23 58
P0.25/AD0.4/

9

AOUT
P0.26/AD0.5 10

P0.27/AD0.0/

11

CAP0.1/MAT0.1

[1]

[5]

[4]
[4]

I/O General purpose digital input/output pin.
I AD0.4 — ADC 0, input 4. This analog input is always connected to its pin.
O AOUT — DAC output. Not available in LPC2131.
I AD0.5 — ADC 0, input 5. This analog input is always connected to its pin.
I AD0.0 — ADC 0, input 0. This analog input is always connected to its pin.
I CAP0.1 — Capture input for Timer 0, channel 1.
O MAT0.1 — Match output for Timer 0, channel 1.

P0.28/AD0.1/
CAP0.2/MAT0.2

13

[4]

I AD0.1 — ADC 0, input 1. This analog input is always connected to its pin.
I CAP0.2 — Capture input for Timer 0, channel 2.
O MAT0.2 — Match output for Timer 0, channel 2.

P0.29/AD0.2/
CAP0.3/MAT0.3

14

[4]

I AD0.2 — ADC 0, input 2. This analog input is always connected to its pin.
I CAP0.3 — Capture input for Timer 0, channel 3.
O MAT0.3 — Match output for Timer 0, channel 3.

P0.30/AD0.3/
EINT3/CAP0.0

15

[4]

I AD0.3 — ADC 0, input 3. This analog input is always connected to its pin.
I EINT3 — External interrupt 3 input.
I CAP0.0 — Capture input for Timer 0, channel 0.

P0.31 17

[6]

O General purpose digital output only pin.

Important: This pin MUST NOT be externally pulled LOW when

RESET pin

is LOW or the JTAG port will be disabled.

P1.0 to P1.31 I/O Port 1: Port 1 is a 32-bit bidirectional I/O port with individual direction controls

for each bit. The operation of port 1 pins depends upon the pin function

selected via the pin connect block. Pins 0 through 15 of port 1 are not

available.

P1.16/

16

[6]

O TRACEPKT0 — Trace Packet, bit 0. Standard I/O port with internal pull-up.

TRACEPKT0
P1.17/

12

[6]

O TRACEPKT1 — Trace Packet, bit 1. Standard I/O port with internal pull-up.

TRACEPKT1
P1.18/

[6]

8

O TRACEPKT2 — Trace Packet, bit 2. Standard I/O port with internal pull-up.

TRACEPKT2
P1.19/

[6]

4

O TRACEPKT3 — Trace Packet, bit 3. Standard I/O port with internal pull-up.

TRACEPKT3
P1.20/

TRACESYNC

48

[6]

O TRACESYNC — Trace Synchronization. Standard I/O port with internal

pull-up. LOW on TRACESYNC while

RESET is LOW enables pins P1.25:16

to operate as Trace port after reset.

P1.21/

44

[6]

O PIPESTAT0 — Pipeline Status, bit 0. Standard I/O port with internal pull-up.

PIPESTAT0
P1.22/

40

[6]

O PIPESTAT1 — Pipeline Status, bit 1. Standard I/O port with internal pull-up.

PIPESTAT1
P1.23/

36

[6]

O PIPESTAT2 — Pipeline Status, bit 2. Standard I/O port with internal pull-up.

PIPESTAT2

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 11 of 39

NXP Semiconductors

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

Table 3. Pin description

…continued

Symbol Pin Type Description

P1.24/

32

[6]

O TRACECLK — Trace Clock. Standard I/O port with internal pull-up.

TRACECLK
P1.25/EXTIN0 28
P1.26/RTCK 24

[6]
[6]

I EXTIN0 — External Trigger Input. Standard I/O with internal pull-up.
I/O RTCK — Returned Test Clock output. Extra signal added to the JTAG port.

Assists debugger synchronization when processor frequency varies.

Bidirectional pin with internal pull-up. LOW on RTCK while

enables pins P1.31:26 to operate as Debug port after reset.

P1.27/TDO 64
P1.28/TDI 60
P1.29/TCK 56
P1.30/TMS 52

TRST 20

P1.31/
RESET 57

[6]
[6]
[6]
[6]
[6]
[7]

O TDO — Test Data out for JTAG interface.
I TDI — Test Data in for JTAG interface.
I TCK — Test Clock for JTAG interface.
I TMS — Test Mode Select for JTAG interface.
I TRST — Test Reset for JTAG interface.
I External reset input: A LOW on this pin resets the device, causing I/O ports

and peripherals to take on their default states, and processor execution to

begin at address 0. TTL with hysteresis, 5 V tolerant.

XTAL1 62
XTAL2 61
RTCX1 3
RTCX2 5
V

SS

[8]

[8]
[8]
[8]

I Input to the oscillator circuit and internal clock generator circuits.
O Output from the oscillator amplifier.
I Input to the RTC oscillator circuit.
O Output from the RTC oscillator circuit.

6, 18, 25, 42,50I Ground: 0 V reference.

RESET is LOW

V

SSA

V

DD

59 I Analog ground: 0 V reference. This should nominally be the same voltage

as V

, but should be isolated to minimize noise and error.

SS

23, 43, 51 I 3.3 V power supply: This is the power supply voltage for the core and I/O

ports.

V

DDA

7IAnalog 3.3 V power supply: This should be nominally the same voltage as

V

but should be isolated to minimize noise and error. This voltage is used

DD

to power the on-chip PLL.

VREF 63 I ADC reference: This should be nominally the same voltage as V

DD

but
should be isolated to minimize noise and error. Level on this pin is used as a
reference for A/D and D/A convertor(s).

VBAT 49 I RTC power supply: 3.3 V on this pin supplies the power to the RTC.

[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10ns slew rate control.
[2] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10ns slew rate control. If configured for an input

function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns.

[3] Open drain 5 V tolerant digital I/O I2C-bus 400 kHz specification compatible pad. It requires external pull-up to provide an output

functionality.

[4] 5 V tolerant pad providing digital I/O (with TTL levels and hysteresisand10 ns slewratecontrol)andanaloginputfunction.If configured

for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns. When configured as an ADC input, digital
section of the pad is disabled.

[5] 5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10ns slew rate control) and analog output function. When

configured as the DAC output, digital section of the pad is disabled.

[6] 5 V tolerant pad with built-in pull-up resistor providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.

The pull-up resistor’s value ranges from 60 kΩ to 300 kΩ.
[7] 5 V tolerant pad providing digital input (with TTL levels and hysteresis) function only.
[8] Pad provides special analog functionality.

LPC2131_32_34_36_38_4 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 04 — 16 October 2007 12 of 39