0220060725Updated edition of the User Manual covering both LPC213x and LPC213x/01 devices. For
detailed list of enhancements introduced by LPC213x/01 see Sectio n 1–2 “
introduced with LPC213x/01 devices” on page 3
Other changes applied to Rev 01:
Enhancements
• ECC information in Section 20–6 “Flash content protection mechanism” corrected
• The SSEL signal description corrected for CPHA = 0 and CPHA = 1 (Section 12–2.2
“SPI data transfers”)
• Bit SPIE description corrected in Section 12–4.1 “SPI Control Register (S0SPCR -
0xE002 0000)”
• Details on V
0120050624Initial version
setup added in Section 18–5 “RTC usage notes”
BAT
Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, please send an email to: sales.addresses@www.semiconductors.philips.com
User manual LPC213xRev. 02 — 25 July 2006 2 of 292
1.Introduction
UM10120
Chapter 1: Introductory information
Rev. 02 — 25 July 2006User manual LPC213x
The LPC213x and LPC213x/01 microcontrollers are based on a 16/32 bit ARM7TDMI-S
CPU with real-time emulation and embedded trace support that combines the
microcontroller with embedded high speed Flash memory r anging from 32 kB to 512 kB. A
128-bit wide memory interface and a unique accelerator architecture enable 32-bit code
execution at maximum clock rate. For critical code size applications, the alternative 16-bit
Thumb Mode reduces code by more than 30 % with minimal performance penalty.
Due to their tiny size and low power consumption, these microcontrollers are ideal for
applications where miniaturization is a key requirement, such as access control and
point-of-sale. With a wide range of serial communications interfaces and on-chip SRAM
options of 8/16/32 kB, they are very well suited for communication gateways and protocol
converters, soft modems, voice recognition and low end imaging, providing both large
buffer size and high processing power. Various 32-bit timers, single or dual 10-bit
8 channel ADC(s), 10-bit DAC, PWM channels and 47 fast GPIO lines with up to nine
edge or level sensitive external interrupt pins make these microcontrollers particularly
suitable for industrial control and medical systems.
Important: The term “LPC213x“ in the following text will be used both for devices with and
without /01 suffix. Only when needed “LPC213x/01” will be used to identify the latest ones:
LPC2131/01, LPC2132/01, LPC2134/01, LPC2136/01, and/or LPC2138/01.
2.Enhancements introduced with LPC213x/01 devices
• Fast GPIO ports enable pin toggling up to 3.5x faster than the original LPC213x. Also,
Enhanced parallel ports allow for a port pin to be read at any time regardless of the
function selected on it. For details see GPIO chapter on page 78.
• Dedicated result registers for AD converter(s) reduce interrupt overhead. For details
see ADC chapter on page 211.
• UART0/1 include Fractional Baudrate Generator, auto-bauding capabilities and
handshake control fully implemented in hardware. For more details see UART0
chapter on page 92 and UART1 chapter on page 108.
• Enhanced BOD control enables further reduction of power consumption. For det ails
see Table 4–30 “Power Control register (PCON - address 0xE01F C0C0) bit
description” on page 41
3.Features
• 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package
• 8/16/32 kB of on-chip static RAM and 32/64/128/256/512 kB of on-chip Flash program
memory. 128 bit wide interface/accelerator enables high speed 60 MHz operation.
• In-System/In-Application Programming (ISP/IAP) via on-chip boot-loader software.
Single Flash sector or full chip erase in 400 ms and 256 bytes programming in 1 ms.
The LPC213x consists of an ARM7TDMI-S CPU with emulation support, the ARM7 Lo ca l
Bus for interface to on-chip memory controllers, the AMBA Advanced High-performance
Bus (AHB) for interface to the interrupt controller, and the VLSI Peripheral Bus (APB, a
compatible superset of ARM’s AMBA Advanced Peripher al Bus) for connection to on-chip
peripheral functions. The LPC213x configures the ARM7TDMI-S processor in little-endian
byte order.
AHB peripherals are allocated a 2 megabyte range of addresses at the very top of the
4 gigabyte ARM memory space. Each AHB peripheral is allocate d a 16 kB address space
within the AHB address space. LPC213x peripheral functions (other than the interrupt
controller) are connected to the APB bus. The AHB to APB bridge interfaces the APB bus
to the AHB bus. APB peripherals are also allocated a 2 megabyte range of addresses,
beginning at the 3.5 gigabyte address point. Each APB peripheral is allocated a 16 kB
address space within the APB address space.
The connection of on-chip peripherals to device pins is controlled by a Pin Connect Block
(see chapter "Pin Connect Block" on page 72). This must be configured by softwa re to fit
specific application requirements for the use of periph er al functions and pins.
7.ARM7TDMI-S processor
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers. This simplicity results in a high instruction throughput and
impressive real-time interrupt response from a small and cost-effective processor core.
User manual LPC213xRev. 02 — 25 July 2006 5 of 292
Philips Semiconductors
Pipeline techniques are employed so that all part s of the pro cessing and memory systems
can operate continuously. T ypically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
THUMB, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
• The standard 32-bit ARM instruction set.
• A 16-bit THUMB instruction set.
The THUMB set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because THUMB code
operates on the same 32-bit register set as ARM code.
THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the
performance of an equivalent ARM processor connected to a 16-bit memory system.
UM10120
Chapter 1: Introductory information
The ARM7TDMI-S processor is described in detail in the ARM7TDMI-S Datasheet that
can be found on official ARM website.
8.On-chip Flash memory system
The LPC213x incorporates a 32, 64, 128, 256 or 512 kB Flash memory system. This
memory may be used for both code and dat a stor age. Progra mming of the Fl ash memory
may be accomplished in several ways: over the serial builtin JTAG interface, using In
System Programming (ISP) and UART0, or by means of In Application Programming
(IAP) capabilities. The application program, using the IAP functions, may also erase
and/or program the Flash while the application is running, allowing a great degree of
flexibility for data storage field firmware upgrades, etc. When the LPC213x on-chip
bootloader is used, 32/64/128/256/500 kB of Flash memory is available for user code
and/or data storage.
The LPC213x Flash memory provides minimum of 100,000 erase/write cycles and 20
years of data-retention.
9.On-chip Static RAM (SRAM)
On-chip Static RAM (SRAM) may be used for code and/or data storage. The on-chip
SRAM may be accessed as 8-bits, 16-bits, and 32-bits. The LPC213x provide 8/16/32 kB
of static RAM.
The LPC213x SRAM is designed to be accessed as a byte-addressed memory. Word and
halfword accesses to the memory ignore the alignment of the address and access the
naturally-aligned value that is addressed (so a memory access ignores address bits 0 and
1 for word accesses, and ignores bit 0 for halfword accesses). Therefore valid reads and
writes require data accessed as halfwords to originate from addresses with address line 0
being 0 (addresses ending with 0, 2, 4, 6, 8, A, C, and E in hexadecimal nottaion) and
User manual LPC213xRev. 02 — 25 July 2006 6 of 292
Philips Semiconductors
data accessed as words to originate from adresses with address lines 0 and 1 being 0
(addresses ending with 0, 4, 8, and C in hexadecimal notation). This rule applies to both
off and on-chip memory usage.
The SRAM controller incorporates a write-back buffer in order to prevent CPU stalls
during back-to-back writes. The write-back buffer always holds the last data sent by
software to the SRAM. This data is only written to the SRAM when another write is
requested by software (the data is only written to the SRAM when software does another
write). If a chip reset occurs, actual SRAM contents will not reflect the most recent write
request (i.e. after a "warm" chip reset, the SRAM does not reflect the last wr ite operation).
Any software that checks SRAM contents after reset must take this into account. Two
identical writes to a location guarantee that the data will be present after a Reset.
Alternatively, a dummy write operation before entering idle or power-down mode will
similarly guarantee that the last data written will be present in SRAM after a subsequent
Reset.
User manual LPC213xRev. 02 — 25 July 2006 8 of 292
1.Memory maps
The LPC213x incorporates several distinct memory regions, shown in the following
figures. Figure 2–2
program viewpoint following reset. The interrupt vector area supports address remapping,
which is described later in this section.
UM10120
Chapter 2: Memory maps
Rev. 02 — 25 July 2006User manual LPC213x
shows the overall map of the entire address space from the user
User manual LPC213xRev. 02 — 25 July 2006 9 of 292
Philips Semiconductors
UM10120
Chapter 2: Memory maps
4.0 GB
4.0 GB - 2 MB
3.75 GB
0xFFFF FFFF
AHB PERIPHERALS
0xFFE0 0000
0xFFDF FFFF
RESERVED
0xF000 0000
0xEFFF FFFF
RESERVED
3.5 GB + 2 MB
APB PERIPHERALS
3.5 GB
AHB section is 128 x 16 kB blocks (totaling 2 MB).
APB section is 128 x 16 kB blocks (totaling 2MB).
0xE020 0000
0xE01F FFFF
0xE000 0000
Fig 3. Peripheral memory map
Figure 2–3 through Figure 2–4 and Table 2–2 show different views of the peripheral
address space. Both the AHB and APB peripheral areas are 2 megabyte spaces which
are divided up into 128 peripherals. Each peripheral space is 16 kilobytes in size. This
allows simplifying the address decoding for each peripheral. All peripheral register
User manual LPC213xRev. 02 — 25 July 2006 10 of 292
Philips Semiconductors
addresses are word aligned (to 32-bit boundaries) regardless of their size. This eliminates
the need for byte lane mapping hardware that would be required to allow byte (8-bit) or
half-word (16-bit) accesses to occur at smaller boundaries. An implication of this is that
word and half-word registers must be accessed all at once. For example, it is not p ossible
to read or write the upper byte of a word register separately.
230xE005 C000I
240xE006 000010 bit AD1
250xE006 4000 Not used
260xE006 8000SSP
270xE006 C000DAC
28 - 1260xE007 0000 -
1270xE01F C000System control block
0xE005 8000
0xE01F 8000
2
C0
Not used
2
C1
Not used
UM10120
Chapter 2: Memory maps
2.LPC213x memory re-mapping and boot block
2.1Memory map concepts and operating modes
The basic concept on the LPC213x is that each memory area has a "natural" location in
the memory map. This is the address range for which code residing in that area is written.
The bulk of each memory space remains permanently fixed in the same location,
eliminating the need to have portions of the code designed to run in different address
ranges.
Because of the location of the interrupt vectors on the ARM7 processor (at addresses
0x0000 0000 through 0x0000 001C, as shown in Table 2–3
Boot Block and SRAM spaces need to be re-mapped in order to allow alternative uses of
interrupts in the different operating modes described in Table 2–4
interrupts is accomplished via the Memory Mapping Contro l feature (Section 4–7 “
Note: Identified as reserved in ARM documentation, this location is used
by the Boot Loader as the Valid User Program key. This is descibed in
detail in "Flash Memory System and Programming" chapter on page 237.
The Boot Loader always executes after any reset. The Boot Block
interrupt vectors are mapped to the bottom of memory to allow
handling exceptions and using interrupts during the Boot Loading
process.
Activated by Boot Loader when a valid User Program Signature is
recognized in memory and Boot Loader operation is not forced.
Interrupt vectors are not re-mapped and are found in the bottom of the
Flash memory.
Activated by a User Program as desired. Interrupt vectors are
re-mapped to the bottom of the Static RAM.
2.2Memory re-mapping
In order to allow for compatibility with future derivatives, the entire Boot Block is mapped
to the top of the on-chip memory space. In this manner, the use of larger or smaller flash
modules will not require changing the location of the Boot Block (which would require
changing the Boot Loader code itself) or changing the mapping of the Boot Block interru pt
vectors. Memory spaces other than the interrupt vectors remain in fixed locations.
Figure 2–5
The portion of memory that is re-mapped to allow interrupt processing in different modes
includes the interrupt vector area (32 bytes) and an additional 32 bytes, for a total of
64 bytes. The re-mapped code locations overlay addresses 0x0000 0000 through
0x0000 003F. A typical user program in the Flash memory can place the entire FIQ
handler at address 0x0000 001C without any need to consider memory boundaries. The
vector contained in the SRAM, external memory, and Boot Block must contain branches to
the actual interrupt handlers, or to other instructions that accomplish the branch to the
interrupt handlers.
There are three reasons this configuration was chosen:
1. To give the FIQ handler in the Flash memory the advantage of not having to take a
User manual LPC213xRev. 02 — 25 July 2006 13 of 292
shows the on-chip memory mapping in the modes defined above.
memory boundary caused by the remapping into account.
Philips Semiconductors
2. Minimize the ne ed to for the SRAM and Boot Block vectors to deal with arbitrary
boundaries in the middle of code space.
3. To provide space to store constant s for jumping beyond the range of single word
branch instructions.
Re-mapped memory areas, including the Boot Block and interrupt vectors, continue to
appear in their original location in addition to the re-mapped address.
UM10120
Chapter 2: Memory maps
Details on re-mapping and examples can be found in Section 4–7 “
User manual LPC213xRev. 02 — 25 July 2006 15 of 292
Philips Semiconductors
3.Prefetch abort and data abort exceptions
The LPC213x generates the appropriate bus cycle abort exception if an access is
attempted for an address that is in a reserved or unassigned address region. The regions
are:
• Areas of the memory map that are not implemented for a specific ARM derivative. Fo r
the LPC213x, this is:
– Address space between On-Chip Non-Volatile Memory and On-Chip SRAM,
labelled "Reserved Address Space" in Figure 2–2
device this is memory address range from 0x0000 8000 to 0x3FFF FFFF, for 64 kB
Flash device this is memory address range from 0x0001 0000 to 0x3FFF FFFF, for
128 kB Flash device this is memory address range from 0x0002 0000 to
0x3FFF FFFF, for 256 kB Flash device this is memory address range from
0x0004 0000 to 0x3FFF FFFF while for 512 kB Flash device this range is from
0x0008 0000 to 0x3FFF FFFF.
– Address space between On-Chip Static RAM and the Boot Block. Labelled
"Reserved Address Space" in Figure 2–2
address range from 0x4000 2000 to 0x7FFF CFFF, for 16 kB SRAM device this is
memory address range from 0x4000 4000 to 0x7FFF CFFF, while for 32 kB SRAM
device this range is from 0x4000 8000 to 0x7FFF CFFF.
– Address space between 0x8000 0000 and 0xDFFF FFFF, labelled "Reserved
Adress Space".
– Reserved regions of the AHB and APB spaces. See Figure 2–3
• Unassigned AHB peripheral spaces. See Figure 2–4.
• Unassigned APB peripheral spaces. See Table 2–2.
UM10120
Chapter 2: Memory maps
and Figure 2–5. For 32 kB Flash
. For 8 kB SRAM device this is memory
.
For these areas, both attempted data acce ss and in struction fetch genera te an exception.
In addition, a Prefetch Abort exception is generated for any instruction fetch that maps to
an AHB or APB peripheral address.
Within the address space of an existing APB peripheral, a data abort exception is not
generated in response to an access to an undefined address. Address decoding within
each peripheral is limited to that needed to distinguish defined registers within the
peripheral itself. For example, an access to address 0xE000 D000 (an undefined address
within the UART0 space) may result in an access to the register defined at address
0xE000 C000. Details of such address aliasing within a peripheral space are not defined
in the LPC213x documentation and are not a supported feature.
Note that the ARM core stores the Prefetch Abort flag along with the associated
instruction (which will be meaningless) in the pipeline and processes the abort only if an
attempt is made to execute the instruction fetched from the illegal address. This prevents
accidental aborts that could be caused by prefetches that occur when code is executed
very near a memory boundary.
User manual LPC213xRev. 02 — 25 July 2006 16 of 292
1.Introduction
2.Operation
UM10120
Chapter 3: Memory Acceleration Module (MAM)
Rev. 02 — 12 July 2006User manual LPC213x
The MAM block in the LPC213x maximizes the performance of the ARM processor when
it is running code in Flash memory but does so using a single Flash bank.
Simply put, the Memory Accelerator Module (MAM) attempts to have the next ARM
instruction that will be needed in its latches in time to prevent CPU fetch stalls. The
LPC213x uses one bank of Flash memory, compared to the two banks used on
predecessor devices. It includes three 128-bit buffers called the Prefetch Buffer, the
Branch Trail Buf fer and the data b uffer. When an Instruction Fetch is not satisfied by either
the Prefetch or Branch Trail Buffer, nor has a prefetch been initiated for that line, the ARM
is stalled while a fetch is initiated for the 128-bit line. If a prefetch has been initiated but not
yet completed, the ARM is stalled for a shorter time. Unless aborted by a da ta access, a
prefetch is initiated as soon as the Flash has completed the previous access. The
prefetched line is latched by the Flash module, but the MAM does not capture the line in
its prefetch buffer until the ARM core present s the address from which the prefetch has
been made. If the core presents a different address from the one from which the prefetch
has been made, the prefetched line is discarded.
The Prefetch and Branch Trail buffers each include four 32-bit ARM instructions or eight
16-bit Thumb instructions. During sequential code execution, typically the Prefetch Buf fe r
contains the current instruction and the entire Flash line that contains it.
The MAM differentiates betwee n in str uction and data accesses. Code and data acce sse s
use separate 128-bit buffers. 3 of every 4 sequential 32- bit code or data accesses "hit" in
the buffer without requiring a Flash access (7 of 8 sequ ential 16-bit accesses, 15 of eve ry
16 sequential byte accesses). The fourth (eighth, 16th) sequential data access must
access Flash, aborting any prefetch in progress. When a Flash data access is concluded,
any prefetch that had been in progress is re-initiated.
Timing of Flash read operat ions is programmable and is described later in this section.
In this manner , there is no code fetch penalty for sequential instruction execution when the
CPU clock period is greater than or equal to one fourth of the Flash access time. The
average amount of time spent doing program branches is relatively small (less than 25%)
and may be minimized in ARM (rather than Thumb) code through the use of the
conditional execution feature present in all ARM instructions. This conditional execution
may often be used to avoid small forward branches that would otherwise be necessary.
Branches and other program flow changes cause a break in the sequential flow of
instruction fetches described above. The Branch Trail Buffer captures the line to which
such a non-sequential break occurs. If the same branch is taken again, the next
instruction is taken from the Branch Trail Buffer. When a branch outside the contents of
the Prefetch and Branch T rail Buffer is taken, a st all of several clocks is needed to load the
Branch Trail buffer. Subsequently, there will typically be no further instructionfetch delays
until a new and different branch occurs.
User manual LPC213xRev. 02 — 12 July 2006 17 of 292
Philips Semiconductors
3.MAM blocks
The Memory Accelerator Module is divided into several functional blocks:
• A Flash Address Latch and an incrementor function to form prefetch addresses
• A 128-bit Prefetch Buffer and an associated Address latch and comparator
• A 128-bit Branch Trail Buffer and an associated Address latch and comparator
• A 128-bit Data Buffer and an associated Address latch and comparator
• Control logic
• Wait logic
UM10120
Chapter 3: MAM Module
Figure 3–6
paths.
In the following descriptions, the term “fetch” applies to an explicit Flash read request from
the ARM. “Pre-fetch” is used to denote a Flash read of instructions beyond the current
processor fetch address.
shows a simplified block diagram of the Memory Accelerator Module dat a
3.1Flash memory bank
There is one bank of Flash memory with the LPC213x MAM.
Flash programming operations are not controlled by the MAM, but are handled as a
separate function. A “boot block” sector contains Flash programming algorithms that may
be called as part of the application program, and a loader that may be run to allow serial
programming of the Flash memory.
MEMORY ADDRESS
FLASH MEMORY BANK
ARM LOCAL BUS
BUS
INTERFACE
BUFFERS
Fig 6. Simplified block diagram of the Memory Accelerator Module (MAM)
3.2Instruction latches and data latches
Code and Data accesses are treated separately by the Memory Accelerator Module.
There is a 128-bit Latch, a 15-bit Address
User manual LPC213xRev. 02 — 12 July 2006 18 of 292
Philips Semiconductors
Latch, and a 15-bit comparator associated with each buffer (prefetch, branch trail, and
data). Each 128-bit latch holds 4 words (4 ARM instructions, or 8 Thumb instructions).
Also associated with each buffer are 32 4:1 Multiplexers that select the requested word
from the 128-bit line.
Each Data access that is not in the Data latch causes a Flash fetch of 4 words of data,
which are captured in the Data latch. This speeds up sequential Data operations, but has
little or no effect on random accesses.
3.3Flash programming issues
Since the Flash memory does not allow accesses during programming and erase
operations, it is necessary for the MAM to force the CPU to wait if a memory access to a
Flash address is requested while the Flash module is busy. (This is accomplished by
asserting the ARM7TDMI-S local bus signal CLKEN.) Under some conditions, this delay
could result in a Watchdog time-out. The user will need to be aware of this possibility and
take steps to insure that an unwanted Watchdog reset does not cause a system failure
while programming or erasing the Flash memory.
In order to preclude the possibility of stale data being read from the Flash memory, the
LPC213x MAM holding latches are automatically invalidated at the beginnin g of any Flash
programming or erase operation. Any subsequent read from a Flash address will cause a
new fetch to be initiated after the Flash operation has completed.
UM10120
Chapter 3: MAM Module
4.MAM operating modes
Three modes of operation are defined for the MAM, trading off performance for ease of
predictability:
Mode 0: MAM off. All memory requests result in a Flash read operation (see note 2
below). There are no instruction prefetches.
Mode 1: MAM partially enabled. Sequential instruction accesses are fulfilled from the
holding latches if the data is present. Instruction prefetch is enabled. Non-sequential
instruction accesses initiate Flash read operations (see note 2 below). This means that
all branches cause memory fetches. All data operations cause a Flash read because
buffered data access timing is hard to predict and is very situation dependent.
Mode 2: MAM fully enabled. Any memory request (code or data) for a value that is
contained in one of the corresponding holding latches is fulfilled from the latch.
Instruction prefetch is enabled. Flash read operations are initiated for instruction
prefetch and code or data values not available in the corresponding holding latches.
T able 5.MAM responses to program accesses of various types
Program Memory Request TypeMAM Mode
Sequential access, data in latchesInitiate Fetch
Sequential access, data not in latchesInitiate FetchInitiate Fetch
Non-sequential access, data in latchesInitiate Fetch
Non-sequential access, data not in latches Initiate FetchInitiate Fetch
User manual LPC213xRev. 02 — 12 July 2006 19 of 292
Philips Semiconductors
[1] Instruction prefetch is enabled in modes 1 and 2.
[2] The MAM actually uses latched data if it is available, but mimics the timing of a Flash read operation. This
saves power while resulting in the same execution timing. The MAM can truly be turned off by setting the
fetch timing value in MAMTIM to one clock.
T able 6.MAM responses to data and DMA accesses of various types
Data Memory Request T ypeMAM Mode
Sequential access, data in latchesInitiate Fetch
Sequential access, data not in latchesInitiate FetchInitiate FetchInitiate Fetch
Non-sequential access, data in latchesInitiate Fetch
Non-sequential access, data not in latches Initiate FetchInitiate FetchInitiate Fetch
[1] The MAM actually uses latched data if it is available, but mimics the timing of a Flash read operation. This
saves power while resulting in the same execution timing. The MAM can truly be turned off by setting the
fetch timing value in MAMTIM to one clock.
UM10120
Chapter 3: MAM Module
012
[1]
Initiate Fetch
[1]
Initiate Fetch
[1]
[1]
Use Latched
Data
Use Latched
Data
5.MAM configuration
After reset the MAM defaults to the disabled state. Software can turn memory access
acceleration on or off at any time. This allows most of an application to be run at the
highest possible performance, while certain functions can be run at a somewhat slower
but more predictable rate if more precise timing is required.
6.Register description
All registers, regardless of size, are on word address boundaries. Details of the registers
appear in the description of each function.
T able 7.Summary of MAM registers
NameDescriptionAccess Reset
MAMCR Memory Accelerator Module Control Register.
Determines the MAM functional mode, that is, to
what extent the MAM performance enhancements
are enabled. See Table 3–8.
MAMTIM Memory Accelerator Module Timing control.
Determines the number of clocks used for Flash
memory fetches (1 to 7 processor clocks).
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Address
[1]
value
R/W0x00xE01F C000
R/W0x070xE01F C004
7.MAM Control Register (MAMCR - 0xE01F C000)
Two configuration bits select the three MAM operating modes, as shown in Table 3–8.
Following Reset, MAM functions are disabled. Changing the MAM operating mode causes
the MAM to invalidate all of the holding latches, resulting in new reads of Flash
information as required.
User manual LPC213xRev. 02 — 12 July 2006 20 of 292
Philips Semiconductors
T able 8.MAM Control Register (MAMCR - address 0xE01F C000) bit description
BitSymbolValueDescriptionReset
1:0MAM_mode
_control
7:2--Reserved, user software should not write ones to reserved
00MAM functions disabled0
01MAM functions partially enabled
10MAM functions fully en abled
11Reserved. Not to be used in the application.
bits. The value read from a reserved bit is not defined.
8.MAM Timing register (MAMTIM - 0xE01F C004)
The MAM Timing register determines how many CCLK cycles are used to access the
Flash memory. This allows tuning MAM timing to match the processor operating
frequency. Flash access times from 1 clock to 7 clocks are po ssib le . Sing le cloc k Fla sh
accesses would essentially remove the MAM from timing calculations. In this case the
MAM mode may be selected to optimize power usage.
T able 9.MAM Timing register (MAMTIM - address 0xE01F C004) bit description
BitSymbolValue DescriptionReset
2:0MAM_fetch_
cycle_timing
7:3--Reserved, user software should not write ones to reserved
0000 - Reserved.07
0011 - MAM fetch cycles are 1 processor clock (CCLK) in
duration
0102 - MAM fetch cycles are 2 CCLKs in duration
0113 - MAM fetch cycles are 3 CCLKs in duration
1004 - MAM fetch cycles are 4 CCLKs in duration
1015 - MAM fetch cycles are 5 CCLKs in duration
1106 - MAM fetch cycles are 6 CCLKs in duration
1117 - MAM fetch cycles are 7 CCLKs in duration
Warning: These bits set the duration of MAM Flash fetch operations
as listed here. Improper setting of this value may result in incorrect
operation of the device.
bits. The value read from a reserved bit is not defined.
UM10120
Chapter 3: MAM Module
value
NA
value
NA
9.MAM usage notes
When changing MAM timing, the MAM must first be turned off by writing a zero to
MAMCR. A new value may then be written to MAMTIM. Finally, the MAM may be turned
on again by writing a value (1 or 2) corresponding to the desired operating mode to
MAMCR.
For system clock slower than 20 MHz, MAMTIM can be 001. For system clock between
20 MHz and 40 MHz, Flash access time is suggested to be 2 CCLKs, while in systems
with system clock faster than 40 MHz, 3 CCLKs are proposed.
User manual LPC213xRev. 02 — 12 July 2006 21 of 292
UM10120
Chapter 4: System control block
Rev. 02 — 25 July 2006User manual LPC213x
1.Summary of system control block functions
The System Control Block includes several system features and control registers for a
number of functions that are not related to specific peripheral devices. These include:
• Crystal Oscillator
• External Interrupt Inputs
• Miscellaneous System Controls and Status
• Memory Mapping Control
• PLL
• Power Control
• Reset
• APB Divider
• Wakeup Timer
Each type of function has its own register(s) if any are required and unneeded bits are
defined as reserved in order to allow future expansion. Unrelated functions never share
the same register addresses
2.Pin description
Table 4–10 shows pins that are associated with System Control block functions.
Table 10.Pin summary
Pin namePin
XTAL1InputCrystal Oscillator Input - Input to the oscillator and internal clock
XTAL2OutputCrystal Oscillator Output - Output from the oscillator amplifier
EINT0InputExternal Interrupt Input 0 - An active low/high leve l or
EINT1InputExternal Interrupt Input 1 - See the EINT0 descri ption above.
Pin description
direction
generator circuits
falling/rising edge general purpose interrupt input. This pin may be
used to wake up the processor from Idle or Power-down modes.
Pins P0.1 and P0.16 can be selected to perform EINT0 function.
Pins P0.3 and P0.14 can be selected to perform EINT1 function.
Important: LOW level on pin P0.14 immediately after reset is
considered as an external hardware request to start the ISP
command handler. More details on ISP and Serial Boot Loader can
be found in "Flash Memory System and Programming" chapter on
page 237.
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4.Crystal oscillator
While an input signal of 50-50 duty cycle within a frequency range from 1 MHz to 50 MHz
can be used by the LPC213x if supplied to its input XTAL1 pin, this microcontroller’s
onboard oscillator circuit supports external crystals in the range of 1 MHz to 30 MHz only.
If the on-chip PLL system or the boot-loader is used, the input clock frequency is limited to
an exclusive range of 10 MHz to 25 MHz.
UM10120
Chapter 4: System control block
The oscillator output frequency is called F
referred to as CCLK for purposes of rate equations, etc. elsewhere in this document. F
and the ARM processor clock frequency is
OSC
OSC
and CCLK are the same value unless the PLL is running and connected. Refer to the
Section 4–8 “
Phase Locked Loop (PLL)” on page 33 for details and frequency limitations.
The onboard oscillator in the LPC213x can operate in one of two modes: slave mode and
oscillation mode.
In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF
(C
in Figure 4–7, drawing a), with an amplitude of at least 200 mVrms. The X2 pin in this
C
configuration can be left not connected. If slave mode is selected, the F
signal of
OSC
50-50 duty cycle can range from 1 MHz to 50 MHz.
External components and models used in oscillation mode are shown in Figure 4–7
drawings b and c, and in Table 4–12
only a crystal and the capacitances C
. Since the feedback resistance is integrated on chip,
and CX2 need to be connected externally in case
X1
of fundamental mode oscillation (the fundamental frequency is represented by L, C
R
). Capacitance CP in Figure 4–7, drawing c, represents the parallel package
S
capacitance and should not be larger than 7 pF. Parameters F
, CL, RS and CP are
C
,
and
L
supplied by the crystal manufacturer.
Choosing an oscillation mode as an on-board oscillator mode of operation limits F
OSC
clock selection to 1 MHz to 30 MHz.
LPC213xLPC213x
XTAL1XTAL2
C
C
Clock
a)b)c)
XTAL1XTAL2
C
X1
Xtal
L
< = >
C
X2
C
L
R
S
C
Fig 7. Oscillator modes and models: a) slave mode of operation, b) oscillation mode of operation, c) external
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5.External interrupt inputs
The LPC213x includes four External Interrupt Inputs as selectable pin functions. The
External Interrupt Inputs can optionally be used to wake up the processor from
Power-down mode.
5.1Register description
The external interrupt function has four registers associated with it. The EXTINT register
contains the interrupt flags, and the EXTWAKEUP register contains bits that enable
individual external interrupts to wake up the microcontroller from Power-down mode. The
EXTMODE and EXTPOLAR registers specify the level and edge sensitivity parameters.
Table 13.External interrupt registers
NameDescriptionAccess Reset
EXTINTThe External Interrupt Flag Register contains
interrupt flags for EINT0, EINT1, EINT2 and
EINT3. See Table 4–14
INTWAKEThe Interrupt Wakeup Register contains four
enable bits that control whether each external
interrupt will cause the processor to wake up
from Power-down mode. See Table 4–15
EXTPOLAR The External Interrupt Polarity Register controls
which level or edge on each pin will cause an
interrupt.
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Chapter 4: System control block
Address
[1]
value
R/W00xE01F C140
.
R/W00xE01F C144
.
R/W00xE01F C148
R/W00xE01F C14C
[1] Reset value relects the data stored in used bits only. It does not include reserved bits content.
5.2External Interrupt Flag register (EXTINT - 0xE01F C140)
When a pin is selected for its external interrupt function, the level or edge on that pin
(selected by its bits in the EXTPOLAR a nd EXTMODE registers) will set its interrupt fla g in
this register. This asserts the corresponding interrupt request to the VIC, which will cause
an interrupt if interrupts from the pin are enabled.
Writing ones to bits EINT0 through EINT3 in EXTINT register clears the corre sp onding
bits. In level-sensitive mode this action is efficacious only when the pin is in its inactive
state.
Once a bit from EINT0 to EINT3 is set and an appropriate code star ts to execute (hand ling
wakeup and/or external interrupt), this bit in EXTINT register must be cleared. Otherwise
the event that was just triggered by activity on the EINT pin will not be recognized in the
future.
Important: whenever a change of externa l interrupt operating mode (i.e. active
level/edge) is performed (including the initialization of an external interrupt), the
corresponding bit in the EXTINT register must be cleared! For details see Section
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UM10120
Chapter 4: System control block
For example, if a system wakes up from power-down using a low level on external
interrupt 0 pin, its post-wakeup code must reset the EINT0 bit in order to a llow future entry
into the power-down mode. If the EINT0 bit is left set to 1, subsequent attempt(s) to invoke
power-down mode will fail. The same goes for external interrupt handling.
More details on power-down mode will be discussed in the following chapters.
Table 14. External Interrupt Flag register (EXTINT - address 0xE01F C140) bit description
BitSymbolDescriptionReset
0EINT0In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in
1EINT1In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in
2EINT2In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in
3EINT3In level-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the pin is in
7:4-Reserved, user software should not write ones to reserved bits. The value read from a reserved
value
0
its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin,
and the selected edge occurs on the pin.
Up to two pins can be selected to perform the EINT0 function (see P0.1 and P0.16 description in
"Pin Configuration" chapter page 64.)
This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its
active state (e.g. if EINT0 is selected to be low level sensitive and a low level is present on the
corresponding pin, this bit can not be cleared; this bit can be cleared only when the signal on the
pin becomes high).
0
its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin,
and the selected edge occurs on the pin.
Up to two pins can be selected to perform the EINT1 function (see P0.3 and P0.14 description in
"Pin Configuration" chapter on page 64.)
This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its
active state (e.g. if EINT1 is selected to be low level sensitive and a low level is present on the
corresponding pin, this bit can not be cleared; this bit can be cleared only when the signal on the
pin becomes high).
0
its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin,
and the selected edge occurs on the pin.
Up to two pins can be selected to perform the EINT2 function (see P0.7 and P0.15 description in
"Pin Configuration" chapter on page 64.)
This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its
active state (e.g. if EINT2 is selected to be low level sensitive and a low level is present on the
corresponding pin, this bit can not be cleared; this bit can be cleared only when the signal on the
pin becomes high).
0
its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin,
and the selected edge occurs on the pin.
Up to three pins can be selected to perform the EINT3 function (see P0.9, P0.20 and P0.30
description in "Pin Configuration" chapter on page 64.)
This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its
active state (e.g. if EINT3 is selected to be low level sensitive and a low level is present on the
corresponding pin, this bit can not be cleared; this bit can be cleared only when the signal on the
pin becomes high).
Enable bits in the INTWAKE register allow the external interrupts to wake up the
processor if it is in Power-down mode. The related EINTn function must be mapped to the
pin in order for the wakeup process to take place. It is not necessary for the interrupt to be
enabled in the V ectored Interr upt Controller for a wake up to t ake place. T his arra ngement
allows additional capabilities, such as having an external interrupt input wake up the
processor from Power-down mode without causing an interrupt (simply resuming
operation), or allowing an interrupt to be enabled during Power-down without waking the
processor up if it is asserted (eliminating the need to disable the interrupt if the wakeup
feature is not desirable in the application).
For an external interrupt pin to be a source that would wake up the microco ntroller from
Power-down mode, it is also necessary to clear the corresponding bit in the External
Interrupt Flag register (Section 4–5.2 on page 26
The bits in this register select whether each EI NT pin is le vel- or edge- sensitive. Only pins
that are selected for the EINT function (see chapter Pin Connect Block on page 72) and
enabled via the VICIntEnable register (Section 5–4.4 “Interrupt Enable register
(VICIntEnable - 0xFFFF F010)” on page 53) can cause interrupts from the External
Interrupt function (though of course pins selected for other functions may cause i nterrupt s
from those functions).
Note: Software should only change a bit in this register when its interrupt is
disabled in the VICIntEnable register, and should write the corresponding 1 to the
EXTINT register before enabling (initializing) or re-enabling the interrupt, to clear
the EXTINT bit that could be set by changing the mode.
In level-sensitive mode, the bits in this register select whether the corresponding pin is
high- or low-active. In edge-sensitive mode, they select whether the pin is rising- or
falling-edge sensitive. Only pins that are selected for the EINT function (see "Pin Connect
Block" chapter on page 72) and enabled in the VICIntEnable register (Section 5–4.4
“Interrupt Enable register (VICIntEnable - 0xFFFF F010)” on page 53) can cause
interrupts from the External Interrupt function (though of course pins selected for other
functions may cause interrupts from those functions).
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Chapter 4: System control block
description
value
1EINT0 is edge sensitive.
1EINT1 is edge sensitive.
1EINT2 is edge sensitive.
1EINT3 is edge sensitive.
NA
bits. The value read from a reserved bit is not defined.
Note: Software should only change a bit in this register when its interrupt is
disabled in the VICIntEnable register, and should write the corresponding 1 to the
EXTINT register before enabling (initializing) or re-enabling the interrupt, to clear
the EXTINT bit that could be set by changing the polarity.
3EXTPOLAR3 0EINT3 is low-active or falling-edge sensitive (depending on
7:4 --Reserved, user software should not write ones to reserved
5.6 Multiple external interrupt pins
Software can select multiple pins for each of EINT3:0 in the Pin Select registers, which
are described in chapter Pin Connect Block on page 72. The external interrupt logic for
each of EINT3:0 receives the state of all of its associated pins from the pins’ receivers,
along with signals that indicate whether each pin is selected for the EINT function. The
external interrupt logic handles the case when m ore than one pin is so selected, dif ferently
according to the state of its Mode and Polarity bits:
UM10120
Chapter 4: System control block
description
value
0
EXTMODE3 selection).
1EINT3 is high-active or rising-edge sensitive (depending on
EXTMODE3 selection).
NA
bits. The value read from a reserved bit is not defined.
• In Low-Active Level Sensitive mode, the states of all pins selected for the same EINTx
functionality are digitally combined using a positive logic AND gate.
• In High-Active Level Sensitive mode, the states of all pins selected for the same
EINTx functionality are digitally combined using a positive logic OR gate.
• In Edge Sensitive mode, regardless of polarity, the pin with the lowest GPIO port
number is used. (Selecting multiple pins for an EINTx in edge-sensitive mode could
be considered a programming error.)
The signal derived by this logic is the EINTi signal in the following logic schematic
Figure 4–9
For example, if the EINT3 function is selected in the PINSEL0 and PINSEL1 registers for
pins P0.9, P0.20 and P0.30, and EINT3 is configured to be low level sensitive, the inputs
from all three pins will be logically ANDed. When more than one EINT pin is logically
ORed, the interrupt service routine can read the states of the pins from the GPIO port
using the IO0PIN and IO1PIN registers, to determine which pin(s) caused the interrupt.
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Chapter 4: System control block
Table 18. System Control and Status flags register (SCS - address 0xE01F C1A0) bit description
BitSymbolValue DescriptionReset
value
1GPIO1MGPIO port 1 mode selection.0
0GPIO port 1 is accessed via APB addresses in a fashion compatible with previous
LCP2000 devices.
1High speed GPIO is enabled on GPIO port 1, accessed via addresses in the on-chip
memory range. This mode includes the port masking feature described in the GPIO
chapter on page page 78.
31:2 -Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
7.Memory mapping control
The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. This allows code running in different memory spaces
to have control of the interrupts.
7.1 Memory Mapping control register (MEMMAP - 0xE01F C040)
Whenever an exception handling is necessary , the microcontroller will fetch an instruction
residing on the exception corresponding address as described in Table 2–3 “
exception vector locations” on page 13. The MEMMAP register determines the source of
data that will fill this table.
Table 19.Memory Mapping control register (MEMMAP - address 0xE01F C040) bit
description
BitSymbol ValueDescriptionReset
1:0MAP00Boot Loa der Mode. Interrupt vectors are re-mapped to Boot
Block.
01User Flash Mode. In terrupt vectors are not re-mapped and
reside in Flash.
10User RAM Mode. Interrupt vectors are re-mapped to Static
RAM.
11Reserved. Do not use this option.
Warning: Improper setting of this value may result in incorrect
operation of the device.
7:2--Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
7.2 Memory mapping control usage notes
ARM
value
00
NA
The Memory Mapping Control simply selects one out of three available sources of data
(sets of 64 bytes each) necessary fo r handling ARM exceptions (interrupts).
For example, whenever a Software Interrupt request is generated, the ARM core will
always fetch 32-bit data "residing" on 0x0000 0008 see Table 2–3 “
ARM exception vector
locations” on page 13. This means that when MEMMAP[1:0]=10 (User RAM Mode), a
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read/fetch from 0x0000 0008 will provide data stored in 0x4000 0008. In case of
MEMMAP[1:0]=00 (Boot Loader Mode), a read/fetch from 0x0000 0008 will provide data
available also at 0x7FFF E008 (Boot Block remapped from on-chip Bootloader).
8.Phase Locked Loop (PLL)
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz only. The
input frequency is multiplied up into the CCLK with the range of 10 MHz to 60 MHz using
a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32
(in practice, the multiplier value cannot be higher than 6 on th e LPC213x due to the upper
frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so
there is an additional divider in the loop to keep the CCO within its frequency range while
the PLL is providing the desired output frequency. The output divider may be set to divide
by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,
it is insured that the PLL output has a 50% duty cycle. A block diagram of the PLL is
shown in Figure 4–10
PLL activation is controlled via the PLLCON register. The PLL multiplier and divider
values are controlled by the PLLCFG register. These two registers are protected in order
to prevent accidental alteration of PLL parameters or deactivation of the PLL. Since all
chip operations, including the Watchdog Timer, are dependent on the PLL when it is
providing the chip clock, accidental changes to the PLL setup could result in unexpected
behavior of the microcontroller. The protection is accomplished by a feed sequence
similar to that of the Watchdog Timer. Details are provided in the description of the
PLLFEED register.
UM10120
Chapter 4: System control block
.
The PLL is turned off and bypassed following a chip Reset and when by en tering
Power-down mode. The PLL is enabled by software only. The program must configure
and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source.
8.1 Register description
The PLL is controlled by the registers shown in Table 4–20. More detailed descriptions
follow.
Warning: Improper setting of the PLL values may result in incorre ct operation of the
device!
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Table 20.PLL registers
NameDescriptionAccess Reset
PLLCONPLL Control Register. Holding register for
PLLCFGPLL Configuration Register . H olding reg ister for
PLLSTATPLL Status Register. Read-back register for
PLLFEEDPLL Feed Register. This register enables
updating PLL control bits. Values written to this
register do not take effec t unti l a valid PLL feed
sequence has taken place.
updating PLL configuration values. Values
written to this register do not take effect until a
valid PLL feed sequence has taken place.
PLL control and configuration information. If
PLLCON or PLLCFG have been written to, but
a PLL feed sequence has not yet occurred, they
will not reflect the current PLL state. Reading
this register provides the actual values
controlling the PLL, as well as the status of the
PLL.
loading of the PLL control and configuration
information from the PLLCON and PLLCFG
registers into the shadow registers that actually
affect PLL operation.
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Chapter 4: System control block
Address
[1]
value
R/W00xE01F C080
R/W00xE01F C084
RO00xE01F C088
WONA0xE01F C08C
[1] Reset value relects the data stored in used bits only. It does not include reserved bits content.
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PLLC
direct
0
PSEL[1:0]
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Chapter 4: System control block
CLOCK
SYNCHRONIZATION
PLLE
0
F
OSC
PLOCK
MSEL[4:0]
Fig 10. PLL block diagram
PD
bypass
PHASE-
FREQUENCY
DETECTOR
F
OUT
DIV-BY-M
MSEL<4:0>
CD
PD
CCO
PD
1
CD
F
CCO
0
/2P
0
0
CCLK
1
1
8.2 PLL Control register (PLLCON - 0xE01F C080)
The PLLCON register contains the bits that enable and connect the PLL. Enabling the
PLL allows it to attempt to lock to the current settings of the multiplier and divider values.
Connecting the PLL causes the processor and all chip functions to run from the PLL
output clock. Changes to the PLLCON register do not take effect until a correct PLL feed
sequence has been given (see Section 4–8.7 “
0xE01F C08C)” and Section 4–8.3 “PLL Configuration register (PL LCFG - 0xE01F C084)”
on page 36).
User manual LPC213xRev. 02 — 25 July 2006 35 of 292
PLL Feed register (PLLFEED -
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Table 21.PLL Control register (PLLCON - address 0xE01F C080) bit description
BitSymbolDescriptionReset
0PLLEPLL Enable. When one, and after a valid PLL feed, this bit will
1PLLCPLL Connect. When PLLC and PLLE are both set to one, and after a
7:2-Reserved, user software should not write ones to reserved bits. The
The PLL must be set up, enabled, and Lock established before it may be used as a clock
source. When switching from the oscillator clock to the PLL output or vice versa, internal
circuitry synchronizes the operation in order to ensure that glitches are not generate d.
Hardware does not insure that the PLL is locked before it is connected or automatically
disconnect the PLL if lock is lost during operation. In the event of loss of PLL lock, it is
likely that the oscillator clock has become unstable and disconnecting the PLL will not
remedy the situation.
UM10120
Chapter 4: System control block
activate the PLL and allow it to lock to the requested frequency. See
PLLSTAT register, Table 4–23
valid PLL feed, connects the PLL as the clock source for the
microcontroller. Otherwise, the oscillator clock is used directly by the
microcontroller. See PLLSTAT register, Table 4–23
The PLLCFG register contains the PLL multiplier and divider values. Changes to the
PLLCFG register do not take ef fect until a correct PLL fee d sequence has been give n (see
4:0MSELPLL Multiplier value. Supplies the value "M" in the PLL frequency
calculations.
Note: For details on selecting the right value for MSEL see Section
4–8.9 “PLL frequency calculation” on page 38.
6:5PSELPLL Divider value. Supplies the value "P" in the PLL frequency
calculations.
Note: For details on selecting the right value for PSEL see Section
4–8.9 “PLL frequency calculation” on page 38.
7-Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
8.4 PLL Status register (PLLSTAT - 0xE01F C088)
value
0
0
NA
The read-only PLLSTAT register provides the actual PLL parameters that are in effect at
the time it is read, as well as the PLL status. PLLSTAT may disagree with values found in
PLLCON and PLLCFG because changes to those registers do not take effect until a
proper PLL feed has occurred (see Section 4–8.7 “
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T able 23. PLL Status register (PLLSTAT - address 0xE01F C088) bit description
BitSymbolDescriptionReset
4:0MSELRead-back for the PLL Multiplier value. This is the value currently
6:5PSELRead-back for the PLL Divider value. This is the value currently
7-Reserved, user software should not write ones to reserved bits. The
8PLLERead-back for the PLL Enable bit. When one, the PLL is currently
9PLLCRead-back for the PLL Connect bit. When PLLC and PLLE are both
10PLOCKReflects the PLL Lock status. When zero, the PLL is not locked.
15:11-Reserved, user software should not write ones to reserved bits. The
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Chapter 4: System control block
value
0
used by the PLL.
0
used by the PLL.
NA
value read from a reserved bit is not defined.
0
activated. When zero, the PLL is turned off. This bit is automatically
cleared when Power-down mode is activated.
0
one, the PLL is connected as the clock source for the
microcontroller. When either PLLC or PLLE is zero, the PLL is
bypassed and the oscillator clock is used directly by the
microcontroller. This bit is automatically cleared when Power-down
mode is activated.
0
When one, the PLL is locked onto the requested frequency.
NA
value read from a reserved bit is not defined.
8.5 PLL Interrupt
The PLOCK bit in the PLLSTAT register is connected to the interrupt controller. This
allows for software to turn on the PLL and continue with other functions witho ut having to
wait for the PLL to achieve lock. When the interrupt occurs (PLOCK = 1), the PLL may be
connected, and the interrupt disabled.
8.6 PLL Modes
The combinations of PLLE and PLLC are shown in Table 4–24.
Table 24.PLL Control bit combinations
PLLCPLLEPLL Function
00PLL is turned off and disconnected. The system runs from the unmodified clock
input.
01The PLL is active, but not yet connected. The PLL can be connected after
PLOCK is asserted.
10Same as 00 combination. This prevents the possibility of the PLL being
connected without also being enabled.
11The PLL is active and has been connected as the system clock source.
8.7 PLL Feed register (PLLFEED - 0xE01F C08C)
A correct feed sequence must be written to the PLLFEED register in order for changes to
the PLLCON and PLLCFG registers to take effect. The feed sequence is:
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Philips Semiconductors
The two writes must be in the correct sequence, and must be consecutive APB bus
cycles. The latter requirement implies that interrupts must be disabled for the duration of
the PLL feed operation. If either of the feed values is incorrect, or one of the previously
mentioned conditions is not met, any changes to the PLLCON or PLLCFG register will not
become effective.
7:0PLLFEED The PLL feed sequence must be written to this register in order for
8.8 PLL and Power-down mode
Power-down mode automatically turns off and disconnects the PLL. Wakeup from
Power-down mode does not automatically restore the PLL settings, this must be done in
software. Typically, a routine to activate the PLL, wait for lock, and then connect the PLL
can be called at the beginning of any interrupt service routine that might be called due to
the wakeup. It is important not to attempt to restart the PLL by simply feeding it when
execution resumes after a wakeup from Power-down mode. This would enable and
connect the PLL at the same time, before PLL lock is established.
UM10120
Chapter 4: System control block
value
0x00
PLL configuration and control register changes to take effect.
8.9 PLL frequency calculation
The PLL equations use the following parameters:
Table 26.Elemens determining PLL’s frequency
ElementDescription
F
OSC
F
CCO
CCLKthe PLL output frequency (also the processor clock frequency)
MPLL Multiplier value from the MSEL bits in the PLLCFG register
PPLL Divider value from the PSEL bits in the PLLCFG register
The PLL output frequency (when the PLL is both active and connected) is given by:
CCLK = M × F
The CCO frequency can be computed as:
F
= CCLK × 2 × P or F
CCO
The PLL inputs and settings must meet the following:
the frequency from the crystal oscillator/external osicillator
the frequency of the PLL current controlled oscillator
or CCLK = F
OSC
CCO
CCO
= F
/ (2 × P)
× M × 2 × P
OSC
• F
• CCLK is in the range of 10 MHz to F
is in the range of 10 MHz to 25 MHz.
OSC
(the maximum allowed frequency for the
max
microcontroller - determined by the system microcontroller is embedded in).
User manual LPC213xRev. 02 — 25 July 2006 38 of 292
is in the range of 156 MHz to 320 MHz.
CCO
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8.10 Procedure for determining PLL settings
If a particular application uses the PLL, its configuration may be determined as follows:
1. Choose the desired processor operating frequency (CCLK). This may be based on
processor throughput requirements, need to support a specific set of UART baud
rates, etc. Bear in mind that peripheral devices may be running from a lower clock
than the processor (see Section 4–11 “
2. Choose an oscillator frequency (F
multiple of F
3. Calculate the value of M to configure the MSEL bits. M = CCLK / F
the range of 1 to 32. The value written to the MSEL bits in PLLCFG is M − 1 (see
Table 4–28
4. Find a value for P to configure the PSEL bits, such that F
frequency limits. F
of the values 1, 2, 4, or 8. The value written to the PSEL bits in PLLCFG is 00 for
P = 1; 01 for P = 2; 10 for P = 4; 11 for P = 8 (see Table 4–27
Table 27.PLL Divider values
PSEL Bits (PLLCFG bit s [6:5])Value of P
001
012
104
118
.
OSC
UM10120
Chapter 4: System control block
APB divider” on page 45).
). CCLK must be the whole (non-fractional)
OSC
.
. M must be in
OSC
is within its defined
CCO
is calculated using the equation given above. P must have one
CCO
).
Table 28.PLL Multiplier values
MSEL Bits (PLLCFG bits [4:0])Value of M
000001
000012
000103
000114
......
1111031
1111132
8.11PLL example
System design asks for F
Based on these specifications, M = CCLK / Fosc = 60 MHz / 10 MHz = 6. Consequently,
M - 1 = 5 will be written as PLLCFG[4:0].
V alue for P can be d erived from P = F
in range of 156 MHz to 320 MHz. Assuming the lowest allowed frequency for
F
= 156 MHz, P = 156 MHz / (2 x 60 MHz) = 1.3. The highest F
CCO
produces P = 2.67. The only solution for P that satisfies both of these requirements and is
listed in Table 4–27
= 10 MHz and requires CCLK = 60 MHz.
OSC
/ (CCLK x 2), using condition that F
CCO
CCO
is P = 2. Therefore, PLLCFG[6:5] = 1 will be used.
User manual LPC213xRev. 02 — 25 July 2006 39 of 292
Philips Semiconductors
9.Power control
The LPC213x supports two reduced power modes: Idle mode and Power-down mode. In
Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs.
Peripheral functions continue operation during Idle mode and may generate interrupts to
cause the processor to resume execution. Idle mode eliminates power used by the
processor itself, memory systems and related controllers, and internal buses.
In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.
The processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Power-down mode and the logic levels of chip pins remain static.
The Power-down mode can be terminated and normal operation resumed by either a
Reset or certain specific interrupts that are able to function without clocks. Since all
dynamic operation of the chip is suspended, Power-down mode reduces chip power
consumption to nearly zero.
Entry to Power-down and Idle modes must be coordinated with program execution.
Wakeup from Power-down or Idle modes via an interrupt resumes program execution in
such a way that no instructions are lost, incomplete, or repeated. Wake up from
Power-down mode is discussed further in Section 4–12 “
UM10120
Chapter 4: System control block
Wakeup timer” on page 46.
A Power Control for Peripherals feature allows individual peripherals to be turned off if
they are not needed in the application, resulting in additional power savings.
9.1 Register description
The Power Control function contains two registers, as shown in Table 4–29. More detailed
descriptions follow.
Table 29.Power control registers
NameDescriptionAccess Reset
PCONPower Control Register. This register contains
control bits that enable the two reduced power
operating modes of the microcontroller. See
Table 4–30
PCONP Power Control for Peripherals Register. This
register contains control bits that enable and
disable individual peripheral functions,
Allowing elimination of power consumption by
peripherals that are not needed.
[1]Reset value relects the data stored in used bits only. It does not include reserved bits content.
.
R/W0x000xE01F C0C0
R/W0x0008 17BE 0xE01F C0C4
value
[1]
Address
9.2 Power Control register (PCON - 0xE01F C0C0)
The PCON register contains two bits. Writing a one to the corresponding bit causes entry
to either the Power-down or Idle mode. If both bits are set, Power-down mode is entered.
User manual LPC213xRev. 02 — 25 July 2006 40 of 292
Philips Semiconductors
Table 30.Power Control register (PCON - address 0xE01F C0C0) bit description
BitSymbolValue DescriptionReset
0IDLIdle mode control.0
1PDPower-down mode control.0
2BODPDMBrown Out Power-down Mode.0
3BOGD
4BORD
7:5-Reserved, user software should not write ones to reserved bits.
Chapter 4: System control block
0Idle mode is off.
1The processor clock is stopped, while on-chip peripherals remain
active. Any enabled interrupt from a peripheral or an external
interrupt source will cause the processor to resume execution.
0Power-down mode is off.
1The oscill ator and all on-chip clocks are stopped. A wakeup
condition from an external interrupt can cause the oscillator to
restart, the PD bit to be cleared, and the processor to resume
execution.
0Brown Out Dete ction (BOD) remains operative during
Power-down mode, and its Reset can release the microcontroller
from Power-down mode
1Th e BOD circuitry will go into power down mode when PD = 1,
resulting in a further reduction in power. In this case the BOD can
not be used as a wakeup source from Power Down mode.
[2]
Brown Out Global Disable.0
0The BOD circuitry is enabled.
1The BOD is fully disabled at all times, consuming no power.
[2]
Brown Out Reset Disable.0
0The reset is enabled. The first stage of low voltage detection
(2.9 V) Brown Out interrupt is not affected.
1The second stage of low voltage detection (2.6 V) will not cause
a chip reset.
The value read from a reserved bit is not defined.
[1]
.
UM10120
value
NA
[1] Since execution is delayed until after the Wakeup Timer has allowed the main oscillator to resume stable
operation, there is no guarantee that execution will resume before V
threshold, which prevents execution. If execution does resume, there is no guarantee of how long the
microcontroller will continue execution before the lower BOD threshold terminates execution. These issues
depend on the slope of the decline of V
vicinity of the microcontroller will improve the likelihood that software will be able to do what needs to be
done when power is being lost.
[2] This feature is available in LPC213x/01 only.
. High decoupling capacitance (between VDD and ground) in the
DD
has fallen below the lower BOD
DD
9.3 Power Control for Peripherals register (PCONP - 0xE01F C0C4)
The PCONP register allows turning off selected peripheral functions for the purpose of
saving power. This is accomplished by gating off the clock source to the specified
peripheral blocks. A few peripheral functions cannot be turned off (i.e. the Watchdog timer,
GPIO, the Pin Connect block, and the System Control block). Some peripherals,
particularly those that include analog functions, may consume power that is not clock
dependent. These peripherals may contain a separate disable control that turns off
additional circuitry to reduce power. Each bit in PCONP controls one of the peripherals.
User manual LPC213xRev. 02 — 25 July 2006 41 of 292
Philips Semiconductors
The bit numbers correspond to the related peripheral number as shown in the APB
peripheral map Figure 2–4 “
Addressing" chapter.
UM10120
Chapter 4: System control block
AHB peripheral map” in the "LPC2131/2/4/6/8 Memory
If a peripheral control bit is 1, that peripheral is enabled. If a periph er al bit is 0, that
peripheral is disabled to conserve power. For example if bit 19 is 1, the I
enabled. If bit 19 is 0, the I
2
C1 interface is disabled.
2
C1 interface is
Important: valid read from a peripheral register and valid write to a peripheral
register is possible only if that peripheral is enabled in the PCONP register!
Table 31.Power Control for Peripherals register (PCONP - address 0xE01F C0C4) bit
description
BitSymbolDescriptionReset
value
0-Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
1PCTIM0Timer/Counter 0 power/clock control bit.1
2PCTIM1Timer/Counter 1 power/clock control bit.1
3PCUART0 UART0 power/clock control bit.1
4PCUART1 UART1 power/clock control bit.1
5PCPWM0 PWM0 power/clock control bit.1
6-Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
2
7PCI2C0The I
8PCSPI0The SPI0 interface power/clock control bit.1
9PCRTCThe RTC power/clock control bit.1
10PCSPI1The SSP interface power/clock control bit.1
11-Reserved, user software should not write ones to reserved bits. The
12PCAD0A/D converter 0 (ADC0) power/clock control bit.
18:13 -Reserved, user software should not write ones to reserved bits. The
19PCI2C1The I
20PCAD1A/D converter 1 (ADC1) power/clock control bit.
31:21 -Reserved, user software should not write ones to reserved bits. The
C0 interface power/clock control bit.1
value read from a reserved bit is not defined.
Note: Clear the PDN bit in the AD0CR before clearing this bit, and set
this bit before setting PDN.
value read from a reserved bit is not defined.
2
C1 interface power/clock control bit.1
Note: Clear the PDN bit in the AD1CR before clearing this bit, and set
this bit before setting PDN.
value read from a reserved bit is not defined.
NA
NA
NA
1
NA
0
NA
9.4 Power control usage notes
After every reset, the PCONP register contains the value that en ables all interfaces and
peripherals controlled by the PCONP to be enabled. Therefore, apart from proper
configuring via peripheral dedicated registers, the user’s application has no need to
access the PCONP in order to start using any of the on-board peripherals.
User manual LPC213xRev. 02 — 25 July 2006 42 of 292
Philips Semiconductors
Power saving oriented systems should have 1s in the PCONP register only in positions
that match peripherals really used in the application. All other bits, declared to be
"Reserved" or dedicated to the peripherals not used in the current application, must be
cleared to 0.
10. Reset
Reset has three sources on the LPC213x: the RESET pin, Watchdog Reset and
Brown-Out-Detector (BOD) Reset. The RESET
additional glitch filter . Assertion of chip Reset by a ny source st arts the W akeup Timer (see
description in Section 4–12 “
asserted until the external Reset is de-asserted, the oscillator is running, a fixed number
of clocks have passed, and the on-chip circuitry has completed its initialization. The
relationship between Reset, the oscillator, and the Wakeup Timer are shown in
Figure 4–11
The Reset glitch filter allows the processor to ignore exte rn al re se t puls es that are very
short, and also determines the minimum duration of RESET
order to guarantee a chip reset. Once asserted, RESET
crystal oscillator is fully running and an adequate signal is present on the X1 pin of the
microcontroller. Assuming that an external crystal is used in the crystal oscillator
subsystem, after power on, the RESET
subsequent resets when crystal oscillator is already running and stable signal is on the X1
pin, the RESET
UM10120
Chapter 4: System control block
pin is a Schmitt trigger input pin with an
Wakeup t im er ” in this chapter), causing reset to remain
.
that must be asserted in
pin can be deasserted only when
pin should be asserted for 10 ms. For all
pin needs to be asserted for 300 ns only.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the Boot Block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
External and internal Resets have some small differences. An external Reset causes the
value of certain pins to be latched to configure the part. External circuitry cannot
determine when an internal Reset occurs in order to allow setting up those special pins,
so those latches are not reloaded during an internal Reset. Pins that are examined during
an external Reset for various purposes are: P1.20/TRACESYNC, P1.26/RTCK (see
chapters "Pin Configuration" on page 64 and "Pin Connect Block" on p a ge 72). Pin P0.14
(see "Flash Memory System and Programming" chapter on page 237) is examined by
on-chip bootloader when this code is executed after every Reset.
It is possible for a chip Reset to occur during a Flash programming or erase operation.
The Flash memory will interrupt the ongoing operation and hold off the completion of
Reset to the CPU until internal Flash high voltages have settled.
This register contains one bit for each source of Reset. Writing a 1 to any of these bits
clears the corresponding read-side bit to 0. The interactions among the four sources are
described below.
0PORAssertion of the POR signal sets this bit, and clears all of the other bits in
this register. But if another Reset signal (e.g., External Reset) remains
asserted after the POR signal is negated, then its bit is set. This bit is not
affected by any of the other sources of Reset.
1EXTRAssertion of the RESET signal sets this bit. Ths bit is cleared by POR,
2WDTRThis bit is set when the Watchdog Timer times out and the WDTRESET
3BODRThis bit is set when the 3.3 V power reaches a level below 2.6 V. If the
7:4-Reserved, user software should not write ones to reserved bits. The
11. APB divider
The APB Divider determines the relationship between the processor clock (CCLK) and the
clock used by peripheral devices (PCLK). The APB Divider ser ves two purpo ses. The fir st
is to provides peripherals with desired PCLK via APB bus so that they can operate at the
speed chosen for the ARM processor. In order to achieve this, the APB bus may be
slowed down to one half or one fourth of the processor clock rate. Because the APB bus
must work properly at power up (and its timing cannot be altered if it does not work since
the APB divider control registers reside on the APB bus), the default condition at reset is
for the APB bus to run at one quarter speed. The second purpose of the APB Divider is to
allow power savings when an application does not require any per ipherals to run at the full
processor rate.
UM10120
Chapter 4: System control block
bit in the Watchdog Mode Register is 1. It is cleared by any of the other
sources of Reset.
V
voltage dips from 3.3 V to 2.5 V and backs up, the BODR bit will be
DD
set to 1. Also, if the V
level above 2.6 V, the BODR will be set to 1, too. This bit is not affected
by External Reset nor Watchdog Reset.
Note: only in case a reset occurs and the POR = 0, the BODR bit
indicates if the VDD voltage was below 2.6 V or not.
value read from a reserved bit is not defined.
voltage rises continuously from below 1 V to a
DD
value
see text
seet text
NA
The connection of the APB Divider relative to the oscillator and the processor clock is
shown in Figure 4–12
. Because the APB Divider is connected to the PLL output, the PLL
remains active (if it was running) during Idle mode.
1 1.1 Register description
Only one register is used to control the APB Divider.
Table 33.APB divider register map
NameDescriptionAccess Reset
value
APBDIVControls the rate of the APB clock in relation to
the processor clock.
[1] Reset value relects the data stored in used bits only. It does not include reserved bits content.
R/W0x000xE01F C100
Address
[1]
11.2 APBDIV register (APBDIV - 0xE01F C100)
The APB Divider register contains two bits, allowing three divide r values, as shown in
User manual LPC213xRev. 02 — 25 July 2006 45 of 292
.
Philips Semiconductors
T able 34. APB Divider register (APBDIV - address 0xE01F C100) bit description
BitSymbol ValueDescriptionReset
1:0APBDIV 00APB bus clock is one fourth of the processor clock.00
7:2--Reserved, user software should not write ones to reserved
UM10120
Chapter 4: System control block
value
01APB bus clock is the same as the processor clock.
10APB bus clock is one half of the processor clock.
11Reserved. If this value is written to the APBDIV register, it
has no effect (the previous setting is retained).
NA
bits. The value read from a reserved bit is not defined.
Fig 12. APB divider connections
12. Wakeup timer
The purpose of the wakeup timer is to ensure that the oscillator and other analog
functions required for chip operation are fully functional before the processor is allowed to
execute instructions. This is important at power on, all types of Rese t, an d when e ve r any
of the aforementioned functions are turned off for any reason. Since the oscillator and
other functions are turned off during Power-down mode, any wakeup of the processor
from Power-down mode makes use of the Wakeup Timer.
The Wakeup T i mer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of V
and its electrical characteristics (if a quartz crystal is used), as well as any other external
circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing
ambient conditions.
crystal oscillator or
external clock source
(F
)
OSC
PLL0
APB DIVIDER
ramp (in the case of power on), the type of crystal
DD
processor clock
(CCLK)
APB clock
(PCLK)
Once a clock is detected, the Wake up T imer counts 4096 clocks, then enables the on-chip
circuitry to initialize. When the onboard modules initialization is complete, the processor is
released to execute instructions if the external Reset has been deasserted. In the case
where an external clock source is used in the system (as opposed to a crystal connected
to the oscillator pins), the possibility that there could be little or no delay for oscillator
start-up must be considered. The Wakeup Timer design then ensures that any other
required chip functions will be operational prior to the beginning of program execution.
User manual LPC213xRev. 02 — 25 July 2006 46 of 292
Philips Semiconductors
Any of the various Resets can bring the microcontroller out of power-down mode, as can
the external interrupts EINT3:0, plus the RT C interrupt if the RTC is operating fr om its own
oscillator on the RTCX1-2 pins. When one of these interrupts is enabled for wakeup and
its selected event occurs, an oscillator wakeup cycle is started. The actual interrupt (if
any) occurs after the wakeup timer expires, and is handled by the Vectored Interrupt
Controller.
However, the pin multiplexing on the LPC213x (see chapters "Pin Configuration" on
page 64 and "Pin Connect Block" on page 72) was designed to allow othe r periphera ls to,
in effect, bring the device out of Power-down mode. The following pin-function pairings
allow interrupts from events relating to UART0 or 1, SPI 0 or 1, or the I
SDA / EINT1, SSEL0 / EINT2, RxD1 / EINT3, DCD1 / EINT1, RI1 / EINT2, SSEL1 /
EINT3.
To put the device in Power-down mode and allow activity on one or more of these buses
or lines to power it back up, software should reprogram the pin function to External
Interrupt, select the appropriate mode and polarity for the Interrupt, and then select
Power-down mode. Upon wakeup software should restore the pin multiplexing to the
peripheral function.
UM10120
Chapter 4: System control block
2
C: RxD0 / EINT0,
All of the bus- or line-activity indications in the list above happen to be low-active. If
software wants the device to come out of power -down mode in response to activity on
more than one pin that share the same EINTi channel, it should progr am low-level
sensitivity for that channel, because only in level mode will the channel logically OR the
signals to wake the device.
The only flaw in this scheme is that the time to restart the oscillator prevents the LPC213x
from capturing the bus or line activity that wakes it up. Idle mode is more appropriate than
power-down mode for devices that must capture and respond to external activity in a
timely manner.
To summarize: on the LPC213x, the Wakeup Timer en forces a minimum reset duration
based on the crystal oscillator, and is activated whenever there is a wakeup from
Power-down mode or any type of Reset.
13. Brown-out detection
The LPC213x includes 2-stage monitoring of the voltage on the VDD pins. If this voltage
falls below 2.9 V, the Brown-Out Detector (BOD) asserts an interrupt signal to the
Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt
Enable register (see Section 5–4.4 “Interru pt Enab le re gis te r (VICIntEnable -
0xFFFF F010)” on page 53); if not, software can monitor the signal by reading the Raw
Interrupt Status register (see Section 5–4.3 “Raw Interrupt status register (VICRawIntr -
0xFFFF F008)” on page 53).
The second stage of low-voltage detection assert s Reset to inactivate th e LPC213x when
the voltage on the V
as operation of the various elements of the chip would otherwise become unreliable due
to low voltage. The BOD circuit maintains this reset down below 1 V, at which point the
Power-On Reset circuitry maintains the overall Reset.
User manual LPC213xRev. 02 — 25 July 2006 47 of 292
pins falls below 2.6 V. This Reset prevents alteration of the Flash
DD
Philips Semiconductors
Both the 2.9 V and 2.6 V thresholds include some hysteresis. In normal operation, this
hysteresis allows the 2.9 V detection to reliably interrupt, or a regularly-executed event
loop to sense the condition.
But when Brown-Out Detection is enabled to bring the LPC213x out of Power-Down mode
(which is itself not a guaranteed operation -- see Section 4–9.2 “
(PCON - 0xE01F C0C0)”), the supply voltage may recover from a transient before the
Wakeup Timer has completed its delay. In this case, the net result of the transient BOD is
that the part wakes up and continues operation after the instructions that set Power-Down
Mode, without any interrupt occurring and with the BOD bit in the RISR being 0. Since all
other wakeup conditions have latching flags (see Section 4–5.2 “
register (EXTINT - 0xE01F C140)” and Section 18–4.3 “Interrupt Location Register (ILR 0xE002 4000)” on page 223), a wakeup of this type, without any apparent cause, can be
assumed to be a Brown-Out that has gone away.
14. Code security vs debugging
Applications in development typically need the debugging and tracing facilities in the
LPC213x. Later in the life cycle of an application, it may be more important to protect the
application code from observation by hostile or competitive eyes. The following feature of
the LPC213x allows an application to control whether it can be debugged or protected
from observation.
UM10120
Chapter 4: System control block
Power Control register
External Interrupt Flag
Details on the way Code Read Protection works can be found in the "Flash Memory
System and Programming" chapter on page 237.
User manual LPC213xRev. 02 — 25 July 2006 48 of 292
1.Features
2.Description
UM10120
Chapter 5: Vectored Interrupt Controller (VIC)
Rev. 02 — 12 July 2006User manual LPC213x
• ARM PrimeCell Vectored Interrupt Controller
• 32 interrupt request inputs
• 16 vectored IRQ interrupts
• 16 priority levels dynamically assigned to interrupt requests
• Software interrupt generation
The Vectored Interrupt Controller (VIC) takes 32 interrupt request inputs and
programmably assigns them into 3 categories, FIQ, vectored IRQ, and non-vectored IRQ.
The programmable assignment scheme means that priorities of interrupts from the
various peripherals can be dynamically assigned and adjusted.
Fast Interrupt reQuest (FIQ) requests have the high est priority. If more than one request is
assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM
processor. The fastest po ssible FIQ latency is achieved when only one request is
classified as FIQ, because then the FIQ service routine can simply start dealing with that
device. But if more than one request is assigned to the FIQ class, the FIQ service routine
can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an
interrupt.
Vectored IRQs have th e midd le pr iority, but only 16 of the 32 requests can be assigned to
this category . Any of the 32 reque sts can be as signed to any of the 16 vectored IRQ slot s,
among which slot 0 has the highest priority and slot 15 has the lowest.
Non-vectored IRQs have the lowest priority.
The VIC ORs the requests from all the vectored and non-vectored IRQs to produce the
IRQ signal to the ARM processor. The IRQ service routine can start by reading a register
from the VIC and jumping there. If any of the vectored IRQs are requesting, the VIC
provides the address of the highest-priority requesting IRQs service routine , ot he rw ise it
provides the address of a default routine that is shared by all the non-vectored IRQs. The
default routine can read another VIC register to see what IRQs are active.
All registers in the VIC are word registers. Byte and halfword reads and write are not
supported.
Additional information on the Vectored Interrupt Controller is available in the ARM
PrimeCell Vectored Interrupt Controller (PL190) documentation.
3.Register description
The VIC implements the registers shown in Table 5–35. More detailed descriptions follow.
control one of the 16 vectored IRQ slots. Slot 0 has the
highest priority and slot 15 the lowest.
VICVectCn tl 1Vector control 1 regi ster.R/W00xFFFF F204
VICVectCn tl 2Vector control 2 regi ster.R/W00xFFFF F208
VICVectCn tl 3Vector control 3 regi ster.R/W00xFFFF F20C
VICVectCn tl 4Vector control 4 regi ster.R/W00xFFFF F210
VICVectCn tl 5Vector control 5 regi ster.R/W00xFFFF F214
VICVectCn tl 6Vector control 6 regi ster.R/W00xFFFF F218
VICVectCn tl 7Vector control 7 regi ster.R/W00xFFFF F21C
VICVectCn tl 8Vector control 8 regi ster.R/W00xFFFF F220
VICVectCn tl 9Vector control 9 regi ster.R/W00xFFFF F224
VICVectCntl10Vector control 10 register.R/W00xFFFF F228
VICVectCntl11Vector control 11 register.R/W00xFFFF F22C
VICVectCntl12Vector control 12 register.R/W00xFFFF F230
VICVectCntl13Vector control 13 register.R/W00xFFFF F234
VICVectCntl14Vector control 14 register.R/W00xFFFF F238
VICVectCntl15Vector control 15 register.R/W00xFFFF F23C
R/W00xFFFF F200
Address
[1]
[1] Reset value relects the data stored in used bits only. It does not include reserved bits content.
4.VIC registers
The following section describes the VIC registers in the order in which they are used in the
VIC logic, from those closest to the interrupt request inputs to those most abstracted for
use by software. For most people, this is also the best order to read about the registers
when learning the VIC.
User manual LPC213xRev. 02 — 12 July 2006 52 of 292
0Writing a 0 leaves the corresponding bit in VICSoftInt unchanged.0
1Writing a 1 clears the corresponding bit in the Software Interrupt
register, thus releasing the forcing of this request.
Philips Semiconductors
UM10120
Chapter 5: VIC
4.3 Raw Interrupt status register (VICRawIntr - 0xFFFF F008)
This is a read only register. This register reads out the state of the 32 interrupt requests
and software interrupts, rega rdless of enabling or classification.
Table 40. Raw Interrupt status register (VICRawIntr - address 0xFFFF F008) bit allocation
When this register is read, 1s indicate interrupt requests or software interrupts
that are enabled to contribute to FIQ or IRQ.
When this register is written, ones enable interrupt requests or software
interrupts to contribute to FIQ or IRQ, zeroes have no effect. See Section 5–4.5
This is a write only register. This register allows software to clear one or more bits in the
Interrupt Enable register (see Section 5–4.4 “Interrupt Enable register (VICIntEnable -
0xFFFF F010)” on page 53), without having to first read it.
0The interrupt request with this bit number is assigned to the IRQ
category.
1The interrupt request with this bit number is assigned to the FIQ
category.
0
4.7 IRQ Status register (VICIRQStatus - 0xFFFF F000)
This is a read only register. This register reads out the state of those interrupt requests
that are enabled and classified as IRQ. It does not differentiate between vectored and
non-vectored IRQs.
Table 48. IRQ Status register (VICIRQStatus - address 0xFFFF F000) bit allocation
User manual LPC213xRev. 02 — 12 July 2006 55 of 292
Philips Semiconductors
UM10120
Chapter 5: VIC
4.8 FIQ Status register (VICFIQStatus - 0xFFFF F004)
This is a read only register. This register reads out the state of those interrupt requests
that are enabled and classified as FIQ. If more than one request is classified as FIQ, the
FIQ service routine can read this register to see which request(s) is (are) active.
Table 50. FIQ Status register (VICFIQStatus - address 0xFFFF F004 ) bit allocation
Table 51. FIQ Status register (VICFIQStatus - address 0xFFFF F004) bit de scription
BitSymbolDescriptionReset
31:0See
VICFIQStatus
bit allocation
table.
A bit read as 1 indicates a coresponding interrupt request being enabled,
classified as IRQ, and asserted
value
0
4.9 Vector Control registers 0-15 (VICvectCntl0-15 - 0xFFFF F200-23C)
These are a read/write accessible registers. Each of these registers controls one of the 16
vectored IRQ slots. Slot 0 has the highest priority and slot 15 the lowest. Note that
disabling a vectored IRQ slot in one of the VICVectCntl registers does not disable the
interrupt itself, the interrupt is simply changed to the non-vectored form.
Table 52. Vector Control registers 0-15 (VICvectCntl0-15 - 0xFFFF F200-23C) bit description
BitSymbolDescriptionReset
4:0int_request/
sw_int_assig
5IRQslot_enWhen 1, this vectored IRQ slot is enabl ed, and can produce a unique ISR
31:6-Reserved, user software should not write ones to reserved bits. The value read
The number of the interrupt request or software interrupt assigned to this
vectored IRQ slot. As a matter of good programming practice, software should
not assign the same interrupt number to more than one enabled vectored IRQ
slot. But if this does occur, the lowernumbered slot will be used when the
interrupt request or software interrupt is enabled, classified as IRQ, and
asserted.
address when its assigned interrupt request or software interrupt is enabled,
classified as IRQ, and asserted.
These are a read/write accessible registers. These registers hold the addresses of the
Interrupt Service routines (ISRs) for the 16 vectored IRQ slots.
31:0IRQ_vectorWhen one or more interrupt request or software interrupt is (are) enabled,
classified as IRQ, asserted, and assigned to an enabled vectored IRQ slot,
the value from this register for the highest-priority such slot will be provided
when the IRQ service routine reads the Vector Address register -VICVectAddr
(Section 5–4.10
31:0IRQ_vectorIf any of the interrupt requests or software interrupts that are assigned to a
0x0000 0000
vectored IRQ slot is (are) enabled, classified as IRQ, and asserted, reading
from this register returns the address in the Vector Address Register for the
highest-priority such slot (lowest-numbered) such slot. Otherwise it returns the
address in the Default Vector Address Register.
Writing to this register does not set the value for future reads from it. Rather,
this register should be written near the end of an ISR, to update the priority
hardware.
0VIC_access0VIC reg isters can be accessed in User or privileged mode.0
31:1-Reserved, user software should not write ones to reserved bits. The
value
1The VIC registers can only be accessed in privileged mode.
NA
value read from a reserved bit is not defined.
5.Interrupt sources
Table 5–57 lists the interrupt sources for each peripheral function. Each peripheral device
has one interrupt line connected to the V ectored In terrupt Controller , but may have several
internal interrupt flags. Individual interrupt flags may also represent more than one
interrupt source.
Table 57. Connection of interrupt sources to the Vectored Interrupt Controller (VIC)
BlockFlag(s)VIC Channel # and Hex
WDTWatchdog Interrupt (WDINT)00x0000 0001
-Reserved for Software Interrupts only10x0000 0002
ARM CoreEmbedded ICE, DbgCommRx20x0000 0004
ARM CoreEmbedded ICE, DbgCommTX30x0000 0008
TIMER0Match 0 - 3 (MR0, MR1, MR2, MR3)
User manual LPC213xRev. 02 — 12 July 2006 59 of 292
Philips Semiconductors
6.Spurious interrupts
Spurious interrupts are possible in the ARM7TDMI based microcontrollers such as the
LPC213x due to asynchronous interrupt handling. The asynchronous character of the
interrupt processing has its roots in the interaction of the core and the VIC. If the VIC state
is changed between the moments when the core detects an interrupt, and the core
actually processes an interrupt, problems may be generated.
Real-life applications may experience the following scenarios:
1. VIC decides there is an IRQ interrupt and sends the IRQ signal to the core.
2. Core latches the IRQ state.
3. Processing continues for a few cycles due to pipelining.
4. Core loads IRQ address from VIC.
Furthermore, It is possible that the VIC state has changed during step 3. For example,
VIC was modified so that the interrupt that triggered the sequence starting with step 1) is
no longer pending -interrupt got disabled in the executed code. In this case, the VIC will
not be able to clearly identify the interrupt that generated the interrupt request, and as a
result the VIC will return the default interrupt VicDefVectAddr (0xFFFF F034).
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Chapter 5: VIC
This potentially disastrous chain of events can be prevented in two ways:
1. Application code should be set up in a way to prevent the spurious interrupts from
occurring. Simple guarding of changes to the VIC may not be enough since, for
example, glitches on level sensitive interrupts can also cause spurious interrupts.
2. VIC default handler should be set up and tested properly.
6.1 Details and case studies on spurious interrupts
This chapter contains details that can be obtained from the official ARM website, FAQ
section.
What happens if an interrupt occurs as it is being disabled?
Applies to: ARM7TDMI
If an interrupt is received by the core during execution of an instruction that disables
interrupts, the ARM7 family will still take the interrupt. This occurs for both IRQ and FIQ
interrupts.
For example, consider the following instruction sequence:
User manual LPC213xRev. 02 — 12 July 2006 60 of 292
Philips Semiconductors
• The IRQ interrupt is taken because the core was committed to taking the interrupt
exception before the I bit was set in the CPSR.
• The CPSR (with the I bit and F bit set) is moved to the SPSR_IRQ.
This means that, on entry to the IRQ interrupt service routine, you can see the unusual
effect that an IRQ interrupt has just been taken while the I bit in the SPSR is set. In the
example above, the F bit will also be set in both the CPSR and SPSR. This means that
FIQs are disabled upon entry to the IRQ service routine, and will remain so until explicitly
re-enabled. FIQs will not be reenabled automatically by the IRQ return sequence.
Although the example shows both IRQ and FIQ interrupts be ing disabled, similar behavior
occurs when only one of the two interrupt types is being disabled. The fact that the core
processes the IRQ after completion of the MSR instruction which disables IRQs does not
normally cause a problem, since an interrupt arriving just one cycle earlier would be
expected to be taken. When the interrupt routine returns with an instruction like:
SUBS pc, lr, #4
the SPSR_IRQ is restored to the CPSR. The CPSR will now have the I bit and F bit set,
and therefore execution will continue with all interrupts disabled. However, this can cause
problems in the following cases:
UM10120
Chapter 5: VIC
Problem 1: A particular routine maybe called as an IRQ handler, or as a regular
subroutine. In the latter case, the system guarantees that IRQs would have been disabled
prior to the routine being called. The routine exploits this restriction to determine how it
was called (by examining the I bit of the SPSR), and returns using the appropriate
instruction. If the routine is entered due to an IRQ being received during execution of the
MSR instruction which disables IRQs, then the I bit in the SPSR will be set. The routine
would therefore assume that it could not have been entered via an IRQ.
Problem 2: FIQs and IRQs are both disabled by the same write to the CPSR. In this case,
if an IRQ is received during the CPSR write, FIQs will be disabled for the execution time of
the IRQ handler. This may not be acceptable in a system where FIQs must not be
disabled for more than a few cycles.
6.2 Workaround
There are 3 suggested workarounds. Which of these is most applicable will depend upon
the requirements of the particular system.
6.3 Solution 1: test for an IRQ received during a write to disable IRQs
Add code similar to the following at the start of the interrupt routine.
SUB lr, lr, #4 ; Adjust LR to point to return
STMFD sp!, {..., lr} ; Get some free regs
MRS lr, SPSR ; See if we got an interrupt while
TST lr, #I_Bit ; interrupts were disabled.
LDMNEFD sp!, {..., pc}^ ; If so, just return immediately.
; The interrupt will remain pending since we haven’t
; acknowledged it and will be reissued when interrupts
; are next enabled.
; Rest of interrupt routine
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This code will test for the situation where the IRQ was received during a write to disable
IRQs. If this is the case, the code returns immediately - resulting in the IRQ not being
acknowledged (cleared), and further IRQs being disabled.
Similar code may also be applied to the FIQ handler, in order to resolve the first issue.
This is the recommended workaround, as it overcomes both problems mentioned above.
However, in the case of p roblem two, it do es add several cycles to the maximu m length of
time FIQs will be disabled.
6.4 Solution 2: disable IRQs and FIQs using separate writes to the CPSR
This is the best workaround where the maximum time for which FIQs are disabled is
critical (it does not increase this time at all). However, it does not solve problem one, and
requires extra instructions at every point where IRQs and FIQs are disabled together.
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Chapter 5: VIC
6.5 Solution 3: re-enable FIQs at the beginning of the IRQ handler
As the required state of all bits in the c field of the CPSR are known, this can be most
efficiently be achieved by writing an immediate value to CPSR_C, for example:
MSR cpsr_c, #I_Bit:OR:irq_MODE ;IRQ should be disabled
;FIQ enabled
;ARM state, IRQ mode
This requires only the IRQ handler to be modified, and FIQs may be re-enabled more
quickly than by using workaround 1. However, this should only be used if the system can
guarantee that FIQs are never disabled while IRQs are enabled. It does not address
problem one.
7.VIC usage notes
If user code is running from an on-chip RAM and an application uses interrupts, interrupt
vectors must be re-mapped to on-chip address 0x0. This is necessary because all th e
exception vectors are located at addresse s 0x 0 an d ab o ve. Th is is easily achieved by
configuring the MEMMAP register (see Section 4–7.1 “Memory Mapping control register
(MEMMAP - 0xE01F C040)” on page 32) to User RAM mode. Application code should be
linked such that at 0x4000 0000 the Interrupt Vector Table (IVT) will reside.
Although multiple sources can be selected (VICIntSelect) to generate FIQ request, only
one interrupt service routine should be dedicated to service all available/present FIQ
request(s). Therefore, if more than one interrupt sources are classified as FIQ the FIQ
interrupt service routine must read VICFIQStatus to decide based on this content what to
do and how to process the interrupt request. However, it is recommended that only one
interrupt source should be classified as FIQ. Classifying more than one interrupt sources
as FIQ will increase the interrupt latency.
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Following the completion of the desired interrupt service routine, clearing of the interrupt
flag on the peripheral level will propagate to corresponding bits in VIC registers
(VICRawIntr, VICFIQStatus and VICIRQStatus). Also, before the next interrupt can be
serviced, it is necessary that write is performed into the VICVectAddr register before the
return from interrupt is executed. This write will clear the respective interrupt flag in the
internal interrupt priority hardware.
In order to disable the interrupt at the VIC you need to clear corresponding bit in the
VICIntEnClr register, which in turn clears the related bit in the VICIntEnable register. This
also applies to the VICSoftInt and VICSoftIntClear in which VICSoftIntClear will clear the
respective bits in VICSoftInt. For example, if VICSoftInt = 0x0000 0005 and bit 0 has to be
cleared, VICSoftIntClear = 0x0000 0001 will accomplish this. Before the new clear
operation on the same bit in VICSoftInt using writing into VICSoftIntClear is performed in
the future, VICSoftIntClear = 0x0000 0000 must be assigned. Therefore writing 1 to any
bit in Clear register will have one-time-effect in the destination register.
If the watchdog is enabled for interrupt on underflow or invalid feed sequence only then
there is no way of clearing the interrupt. The only way you could perform return from
interrupt is by disabling the interrupt at the VIC (using VICIntEnClr).
UM10120
Chapter 5: VIC
Example:
Assuming that UART0 and SPI0 are generating interrupt requests that are classified as
vectored IRQs (UART0 being on the higher level than SPI0), while UART1 and I
generating non-vectored IRQs, the following could be one possibility for VIC setup:
VICIntSelect = 0x0000 0000 ; SPI0, I2C, UART1 and UART0 are IRQ =>
; bit10, bit9, bit7 and bit6=0
VICIntEnable = 0x0000 06C0 ; SPI0, I2C, UART1 and UART0 are enabled interrupts =>
; bit10, bit9, bit 7 and bit6=1
VICDefVectAddr = 0x... ; holds address at what routine for servicing
; non-vectored IRQs (i.e. UART1 and I2C) starts
VICVectAddr0 = 0x... ; holds address where UART0 IRQ service routine starts
VICVectAddr1 = 0x... ; holds address where SPI0 IRQ service routine starts
VICVectCntl0 = 0x0000 0026 ; interrupt source with index 6 (UART0) is enabled as
; the one with priority 0 (the highest)
VICVectCntl1 = 0x0000 002A ; interrupt source with index 10 (SPI0) is enabled
; as the one with priority 1
After any of IRQ requests (SPI0, I2C, UART0 or UART1) is made, microcontroller will
redirect code execution to the address specified at location 0x0000 0018. For vectored
and non-vectored IRQ’s the following instruction could be placed at 0x0000 0018:
LDR pc, [pc,#-0xFF0]
2
C are
This instruction loads PC with the address that is present in VICVectAddr register.
In case UART0 request has been made, VICVectAddr will be identical to VICVectAddr0,
while in case SPI0 request has been made value from VICVectAddr1 will be found here. If
neither UART0 nor SPI0 have generated IRQ request but UART1 and/or I
reason, content of VICVectAddr will be identical to VICDefVectAddr.
User manual LPC213xRev. 02 — 17 July 2006 66 of 292
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UM10120
Chapter 6: Pin configuration
Table 58. Pin description
SymbolPinTypeDescription
P0.0 to P0.31I/OPort 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit.
To tal of 30 pins of the Port 0 can be used as a general purpose bi-directional
digital I/Os while P0.31 is output only pin. The operation of port 0 pins
depends upon the pin function selected via the pin connect block.
Pin P0.24 is not available.
P0.0/TXD0/
PWM1
19
[1]
I/OP0.0 — General purpose digital input/output pin.
OTXD0 — Transmitter output for UART0.
OPWM1 — Pulse Width Modulator outp ut 1.
P0.1/RxD0/
PWM3/EINT0
21
[2]
I/OP0.1 — General purpose digital input/output pin.
IRxD0 — Receiver input for UART0.
OPWM3 — Pulse Width Modulator outp ut 3.
IEINT0 — External interrupt 0 input.
P0.2/SCL0/
CAP0.0
22
[3]
I/OP0.2 — General purpose digital input/output pin.
2
I/OSCL0 — I
C0 clock input/output. Open drain output (for I2C compliance).
ICAP0.0 — Capture input for Timer 0, channel 0.
P0.3/SDA0/
MAT0.0/EINT1
26
[3]
I/OP0.3 — General purpose digital input/output pin.
2
I/OSDA0 — I
C0 data input/output. Open drain output (for I2C compliance).
OMAT0.0 — Match output for Timer 0, channel 0.
IEINT1 — External interrupt 1 input.
P0.4/SCK0/
CAP0.1/AD0.6
27
[4]
I/OP0.4 — General purpose digital input/output pin.
I/OSCK0 — Serial clock for SPI0. SPI clock output from master or input to slave.
ICAP0.1 — Capture input for Timer 0, channel 0.
IAD0.6 — A/D converter 0, input 6.
P0.5/MISO0/
MAT0.1/AD0.7
29
[4]
I/OP0.5 — General purpose digital input/output pin.
I/OMISO0 — Master In Slave Out for SPI0. Data input to SPI master or data
output from SPI slave.
OMAT0.1 — Match output for Timer 0, channel 1.
IAD0.7 — A/D converter 0, input 7.
P0.6/MOSI0/
CAP0.2/AD1.0
30
[4]
I/OP0.6 — General purpose digital input/output pin.
I/OMOSI0 — Master Out Slave In for SPI0. Dat a output fr om SP I master or dat a
input to SPI slave.
ICAP0.2 — Capture input for Timer 0, channel 2
IAD1.0 — A/D converter 1, input 0 (LPC2134/6/8 and matching /01 only).
P0.7/SSEL0/
PWM2/EINT2
31
[2]
I/OP0.7 — General purpose digital input/output pin.
ISSEL0 — Slave Select for SPI0. Selects the SPI interface as a sl ave .
OPWM2 — Pulse Width Modulator outp ut 2.
IEINT2 — External interrupt 2 input.
P0.8/TXD1/
PWM4/AD1.1
33
[4]
I/OP0.8 — General purpose digital input/output pin.
OTXD1 — Transmitter output for UART1.
OPWM4 — Pulse Width Modulator outp ut 4.
IAD1.1 — A/D converter 1, input 1 (LPC2134/6/8 and matching /01 only).
I/OP0.11 — General purpose digital input/output pin.
ICTS1 — Clear to Send input for UART1; available in LPC2134/6/8 and
matching /01 devices only
ICAP1.1 — Capture input for Timer 1, channel 1.
I/OSCL1 — I
P0.12/DSR1/
MAT1.0/AD1.3
38
[4]
I/OP0.12 — General purpose digital input/output pin
IDSR1 — Data Set Ready input for UART1. Available in LPC2134/6/8 only.
OMAT1.0 — Match output for Timer 1, channel 0.
IAD1.3 — A/D converter input 3 (LPC2134/6/8 and matching /01 only).
P0.13/DTR1/
MAT1.1/AD1.4
39
[4]
I/OP0.13 — General purpose digital input/output pin
ODTR1 — Data Terminal Ready output for UART1; available in LPC2134/6/8
and matching /01 devices only.
OMAT1.1 — Match output for Timer 1, channel 1.
IAD1.4 — A/D converter input 4 (LPC2134/6/8 and matching /01 only).
P0.14/DCD1/
EINT1/SDA1
41
[3]
I/OP0.14 — General purpose digital input/output pin.
IDCD1 — Data Carrier Detect input for UART1; available in LPC2134/6/8 and
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Chapter 6: Pin configuration
Table 58. Pin description
…continued
SymbolPinTypeDescription
P0.17/CAP1.2/
SCK1/MAT1.2
47
[1]
I/OP0.17 — General purpose digital input/output pin.
ICAP1.2 — Capture input for Timer 1, channel 2.
I/OSCK1 — Serial Clock for SSP. Clock output from master or input to slave.
OMAT1.2 — Match output for Timer 1, channel 2.
P0.18/CAP1.3/
MISO1/MAT1.3
53
[1]
I/OP0.18 — General purpose digital input/output pin.
ICAP1.3 — Capture input for Timer 1, channel 3.
I/OMISO1 — Master In Slave Out for SSP. Data input to SPI master or data
output from SSP slave.
OMAT1.3 — Match output for Timer 1, channel 3.
P0.19/MAT1.2/
MOSI1/CAP1.2
54
[1]
I/OP0.19 — General purpose digital input/output pin.
OMAT1.2 — Match output for Timer 1, channel 2.
I/OMOSI1 — Master Out Slave In for SSP. Data output from SSP master or data
input to SSP slave.
ICAP1.2 — Capture input for Timer 1, channel 2.
P0.20/MAT1.3/
SSEL1/EINT3
55
[2]
I/OP0.20 — General purpose digital input/output pin.
OMAT1.3 — Match output for Timer 1, channel 3.
ISSEL1 — Slave Select for SSP. Selects the SSP interface as a slave.
IEINT3 — External interrupt 3 input.
P0.21/PWM5/
AD1.6/CAP1.3
[4]
1
I/OP0.21 — General purpose digital input/output pin.
OPWM5 — Pulse Width Modulator output 5.
IAD1.6 — A/D converter 1, input 6 (LPC2134/6/8 and matching /01 only).
ICAP1.3 — Capture input for Timer 1, channel 3.
P0.22/AD1.7/
CAP0.0/MAT0.0
[4]
2
I/OP0.22 — General purpose digital input/output pin.
IAD1.7 — A/D converter 1, input 7 (LPC2134/6/8 and matching /01 only).
ICAP0.0 — Capture input for Timer 0, channel 0.
OMAT0.0 — Match output for Timer 0, channel 0.
P0.2358
P0.25/AD0.4/
9
Aout
[1]
[5]
I/OP0.23 — General purpose digital input/output pin.
I/OP0.25 — General purpose digital input/output pin.
IAD0.4 — A/D converter 0, input 4.
OAout — D/A converter output; available in LPC2132/4/6/8 and matching /01
devices only.
P0.26/AD0.510
[4]
I/OP0.26 — General purpose digital input/output pin.
IAD0.5 — A/D converter 0, input 5.
P0.27/AD0.0/
CAP0.1/MAT0.1
11
[4]
I/OP0.27 — General purpose digital input/output pin.
IAD0.0 — A/D converter 0, input 0.
ICAP0.1 — Capture input for Timer 0, channel 1.
OMAT0.1 — Match output for Timer 0, channel 1.
P0.28/AD0.1/
CAP0.2/MAT0.2
13
[4]
I/OP0.28 — General purpose digital input/output pin.
IAD0.1 — A/D converter 0, input 1.
ICAP0.2 — Capture input for Timer 0, channel 2.
OMAT0.2 — Match output for Timer 0, channel 2.
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Chapter 6: Pin configuration
Table 58. Pin description
…continued
SymbolPinTypeDescription
P0.29/AD0.2/
CAP0.3/MAT0.3
14
[4]
I/OP0.29 — General purpose digital input/output pin.
IAD0.2 — A/D converter 0, input 2.
ICAP0.3 — Capture input for Timer 0, Channel 3.
OMAT0.3 — Match output for Timer 0, channel 3.
P0.30/AD0.3/
EINT3/CAP0.0
15
[4]
I/OP0.30 — General purpose digital input/output pin.
IAD0.3 — A/D converter 0, input 3.
IEINT3 — External interrupt 3 input.
ICAP0.0 — Capture input for Timer 0, channel 0.
P0.3117
[6]
OP0.31 — General purpose digital output only pin
Note: This pin MUST NOT be externally pulled LOW when RESET pin is
LOW or the JTAG port will be disabled.
P1.0 to P1.31I/OPort 1: Port 1 is a 32-bit bi-directional I/O port with individual direction
controls for each bit. The operation of port 1 pins depends upon the pin
function selected via the pin connect block. Pins 0 through 15 of port 1 are not
available.
P1.16/
TRACEPKT0
P1.17/
TRACEPKT1
P1.18/
TRACEPKT2
P1.19/
TRACEPKT3
P1.20/
TRACESYNC
16
12
8
4
48
[6]
[6]
[6]
[6]
[6]
I/OP1.16 — General purpose digital input/output pin.
OTRACEPKT0 — Trace Packet, bit 0. Standard I/O port with internal pull-up.
I/OP1.17 — General purpose digital input/output pin.
OTRACEPKT1 — Trace Packet, bit 1. Standard I/O port with internal pull-up.
I/OP1.18 — General purpose digital input/output pin.
OTRACEPKT2 — Trace Packet, bit 2. Standard I/O port with internal pull-up.
I/OP1.19 — General purpose digital input/output pin.
OTRACEPKT3 — Trace Packet, bit 3. Standard I/O port with internal pull-up.
I/OP1.20 — General purpose digital input/output pin.
OTRACESYNC — Trace Synchronization. Standard I/O port with internal
pull-up.
Note: LOW on this pin while RESET
is LOW enables pins P1.25:16 to
operate as Trace port after reset
P1.21/
44
PIPESTAT0
P1.22/
40
PIPESTAT1
P1.23/
36
PIPESTAT2
P1.24/
32
TRACECLK
P1.25/EXTIN028
[6]
[6]
[6]
[6]
[6]
I/OP1.21 — General purpose digital input/output pin.
OPIPESTAT0 — Pipeline Status, bit 0. Standard I/O port with internal pul l-up.
I/OP1.22 — General purpose digital input/output pin.
OPIPESTAT1 — Pipeline Status, bit 1. Standard I/O port with internal pul l-up.
I/OP1.23 — General purpose digital input/output pin.
OPIPESTAT2 — Pipeline Status, bit 2. Standard I/O port with internal pul l-up.
I/OP1.24 — General purpose digital input/output pin.
OTRACECLK — Trace Clock. Standard I/O port with internal pull-up.
I/OP1.25 — General purpose digital input/output pin.
IEXTIN0 — External Trigger Input. Standard I/O with internal pull-up.
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Chapter 6: Pin configuration
Table 58. Pin description
…continued
SymbolPinTypeDescription
P1.26/RTCK24
[6]
I/OP1.26 — General purpose digital input/output pin.
I/ORTCK — Returned Test Clock output. Extra signal added to the JTAG port.
Assists debugger synchronization when processor frequency varies.
Bi-directional pin with internal pull-up.
Note: LOW on this pin while RESET
operate as Debug port after reset
P1.27/TDO64
[6]
I/OP1.27 — General purpose digital input/output pin.
OTDO — Test Data out for JTAG interface.
P1.28/TDI60
[6]
I/OP1.28 — General purpose digital input/output pin.
ITDI — Test Data in for JTAG interface.
P1.29/TCK56
[6]
I/OP1.29 — General purpose digital input/output pin.
ITCK — Test Clock for JTAG interface.
P1.30/TMS52
[6]
I/OP1.30 — General purpose digital input/output pin.
ITMS — Test Mode Select for JTAG interface.
P1.31/TRST
RESET
20
57
[7]
I/OP1.31 — General purpose digital input/output pin.
ITRST
— Test Reset for JTAG interface.
IExternal reset input: A LOW on this pin resets the device, causing I/O ports
[6]
and peripherals to take on their default states, and processor execution to
begin at address 0. TTL with hysteresis, 5 V tolerant.
XTAL162
XTAL261
RTCX13
RTCX25
V
SS
6, 18, 25, 42, 50IGround: 0 V reference.
[8]
[8]
[8]
[8]
IInput to the oscillator circuit and internal clock generator circuits.
OOutput from the oscillator amplifier.
IInput to the RTC oscillator circuit.
OOutput from the RTC oscillator circuit.
is LOW enables pins P1.31:26 to
V
SSA
V
DD
59IAnalog Ground: 0 V reference. This should nominally be the same voltage
, but should be isolated to minimize noise and error.
as V
SS
23, 43, 51I3.3 V Power Supply: This is the power supply voltage for the core and I/O
ports.
V
DDA
7IAnalog 3.3 V Power Supply: This should be nominally the same voltage as
VDD but should be isolated to minimize noise and error. This voltage is used
to power the ADC(s) and DAC (where available).
V
REF
63IA/D Converter Reference: This should be nominally the same voltage as
V
but should be isolated to minimize noise and error. Level on this pin is
DD
used as a reference for A/D converter and DAC (where available).
V
BAT
[1] Bidirectional pin; Plain input; 3 State Output; 10 ns Slew rate Control; TTL with Hysteresis; 5 V Tolerant.
[2] Bidirectional; Input Glitch Filter (pulses shorter than 4 ns are ignored); 3 State Ouptut; 10 ns Slew rate Control; TTL with Hysteresis.
2
C Pad; 400 kHz Specification; Open Drain; 5 V Tolerant.
[3] I
[4] Bidirectional; Input Glitch Filter (pulses shorter than 4 ns are ignored); Analog I/O; digital receiver disable; 3 State Output; 10 ns Slew
Rate Control; TTL with Hysteresis; 5 V Tolerant
[5] Bidirectional; Analog I/O; digital receiver disable; 3 State Output; 10 ns Slew Rate Control; TTL with Hysteresis; DAC enable output.
[6] Bidirectional pin; Plain input; 3 State Output; 10 ns Slew rate Control; TTL with Hysteresis; Pull-up; 5 V Tolerant.
[7] Input; TTL with Hysteresis; 5 V Tolerant (pulses shorter than 20 ns are ignored).
[8] Analog like pads having ESD structures only.
User manual LPC213xRev. 02 — 17 July 2006 71 of 292
49IRTC Power Supply: 3.3 V on this pin supplies the power to the RTC.
1.Features
2.Applications
The purpose of the Pin Connect Block is to configure the microcontroller pins to the
desired functions.
3.Description
The pin connect block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on chip peripherals.
UM10120
Chapter 7: Pin connect block
Rev. 02 — 25 July 2006User manual LPC213x
• Allows individual pin configuration.
Peripherals should be connected to the appropri ate pins prior to being activated, and prior
to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
Selection of a single function on a port pin completely excludes all other functions
otherwise available on the same pin.
The only partial exception from the above rule of exclusion is the case of inputs to the A/D
converter. Regardless of the function that is selected for the port pin that also hosts the
A/D input, this A/D input can be read at any time and var iations of the vol t age level on this
pin will be reflected in the A/D readings. However, valid analog reading(s) can be obtained
if and only if the function of an analog input is selected. Only in this case proper interface
circuit is active in between the physical pin and the A/D module. In all other cases, a par t
of digital logic necessary for the digital function to be performed will be active, and will
disrupt proper behavior of the A/D.
4.Register description
The Pin Control Module contains 2 registers as shown in Table 7–59 below.
Table 59.Pin connect block register map
NameDescriptionAccessReset value
PINSEL0Pin function select
PINSEL1Pin function select
PINSEL2Pin function select
register 0.
register 1.
register 2.
[1]
Address
Read/Write0x0000 00000xE002 C000
Read/Write0x0000 00000xE002 C004
Read/WriteSee Table 7–62
0xE002 C014
[1] Reset value relects the data stored in used bits only. It does not include reserved bits content.
User manual LPC213xRev. 02 — 25 July 2006 73 of 292
. The direction control bit in the IO0DIR register is effective only when the
01TXD (UART0)
10PWM1
11Reserved
01RxD (UART0)
10PWM3
11EINT0
2
2
C0)
C0)
[1][2]
[1][2]
or AD1.0
or AD1.1
[3]
[3]
01SCL0 (I
10Capture 0.0 (Timer 0)
11Reserved
01SDA0 (I
10Match 0.0 (Timer 0)
11EINT1
01SCK0 (SPI0)
10Capture 0.1 (Timer 0)
11AD0.6
01MISO0 (SPI0)
10Match 0.1 (Timer 0)
11AD0.7
01MOSI0 (SPI0)
10Capture 0.2 (Timer 0)
11Reserved
01SSEL0 (SPI0)
10PWM2
11EINT2
01TXD UART1
10PWM4
11Reserved
Philips Semiconductors
UM10120
Chapter 7: Pin connect block
Table 60.Pin function Select register 0 (PINSEL0 - address 0xE002 C000) bit description
BitSymbolValueFunctionReset value
19:18P0.900GPIO Port 0.90
01RxD (UART1)
10PWM6
11EINT3
21:20P0.1000GPIO Port 0.100
01Reserved
[1][2]
or RTS (UART1)
[3]
10Capture 1.0 (Timer 1)
11Reserved
[1][2]
or AD1.2
[3]
23:22P0.1100GPIO Port 0.110
01Reserved
[1][2]
or CTS (UART1)
[3]
10Capture 1.1 (Timer 1)
2
11SCL1 (I
C1)
25:24P0.1200GPIO Port 0.120
01Reserved
[1][2]
or DSR (UART1)
[3]
10Match 1.0 (Timer 1)
11Reserved
[1][2]
or AD1.3
[3]
27:26P0.1300GPIO Port 0.130
01Reserved
[1][2]
or DTR (UART1)
[3]
10Match 1.1 (Timer 1)
11Reserved
[1][2]
or AD1.4
[3]
29:28P0.1400GPIO Port 0.140
01Reserved
[1][2]
or DCD (UART1)
[3]
10EINT1
2
11SDA1 (I
C1)
31:30P0.1500GPIO Port 0.150
01Reserved
[1][2]
or RI (UART1)
[3]
10EINT2
11Reserved
[1][2]
or AD1.5
[3]
[1] Available on LPC2131 and LPC2131/01.
[2] Available on LPC2132 and LPC2132/01.
[3] Available on LPC2134/6/8, LPC2134/01, LPC2136/01, and LPC2138/01.
4.2 Pin function Select register 1 (PINSEL1 - 0xE002 C004)
The PINSEL1 register controls the functions of the pins as per the settings listed in
following tables. The direction control bit in the IO0DIR register is effective only when the
GPIO function is selected for a pin. For other functions direction is controlled
automatically.
[1] Available on LPC2131 and LPC2131/01.
[2] Available on LPC2132 and LPC2132/01.
[3] Available on LPC2134/6/8, LPC2134/01, LPC2136/01, and LPC2138/01.
4.3 Pin function Select register 2 (PINSEL2 - 0xE002 C014)
The PINSEL2 register controls the functions of the pins as per the settings listed in
Table 7–62
GPIO function is selected for a pin. For other functions direction is controlled
automatically.
Warning: use read-modify-write operation when accessing PINSEL2 register. Accidental
write of 0 to bit 2 and/or bit 3 results in loss of debug and/or trace functionality! Changing
of either bit 4 or bit 5 from 1 to 0 may cause an incorrect code execution!
User manual LPC213xRev. 02 — 25 July 2006 76 of 292
. The direction control bit in the IO1DIR register is effective only when the
Philips Semiconductors
Table 62.Pin function Select register 2 (PINSEL2 - 0xE002 C014) bit description
BitSymbolValue FunctionReset value
1:0--Reserved, user software should not write ones
2GPIO/DEBUG 0Pins P1.36-26 are used as GPIO pins.P1.26/RTCK
3GPIO/TRACE 0Pins P1.25-16 are used as GPIO pins.P1.20
31:4 --Reserved, user software should not write ones
4.4 Pin function select register values
The PINSEL registers control the functions of device pins as shown below. Pairs of bits in
these registers correspond to specific device pins.
Table 63.Pin function select register bits
PINSEL0 and PINSEL1 Va lu es FunctionValue after Reset
00Primary (default) function, typically GPIO
01First alternate function
10Second alternate function
11Reserved
UM10120
Chapter 7: Pin connect block
NA
to reserved bits. The value read from a reserved
bit is not defined.
1Pins P1.36-26 are used as a Debug port.
/
TRACESYNC
1Pins P1.25-16 are used as a Trace port.
NA
to reserved bits. The value read from a reserved
bit is not defined.
00
port
The direction control bit in the IO0DIR/IO1DIR register is effective only when the GPIO
function is selected for a pin. For other functions, direction is controlled automatically.
Each derivative typically has a different pinout and theref or e a different set of fu nct ion s
possible for each pin. Details for a specific derivative may be found in the appropriate data
sheet.
User manual LPC213xRev. 02 — 25 July 2006 77 of 292
1.Features
UM10120
Chapter 8: General Purpose Input/Output ports (GPIO)
Rev. 02 — 25 July 2006User manual LPC213x
• Every physical GPIO port is accessible via either the group of registers providing an
enhanced features and accelerated port access or the legacy group of registers
• Accelerated GPIO functions available on LPC21 3 x/0 1 incl ud e:
– GPIO registers are relocated to the ARM local bus so that the fastest possible I/O
timing can be achieved
– Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged
– All registers are byte and half-word addressable
– Entire port value can be written in one instruction
• Bit-level set and clear registers allow a single instruction set or clear of an y number of
bits in one port (LPC213x/01 only)
• Direction control of individual bits
• All I/O default to inputs after reset
• Backward compatibility with other earlier devices is maintained with legacy registers
appearing at the original addresses on the APB bus
2.Applications
• General purpose I/O
• Driving LEDs, or other indicators
• Controlling off-chip devices
• Sensing digital inputs
3.Pin description
Table 64. GPIO pin description
PinTypeDescription
P0.0-P.31
P1.16-P1.31
Input/
Output
General purpose input/output. The number of GPIOs actually available depends on the
use of alternate functions.
4.Register description
LPC213x has two 32-bit General Purpose I/O ports. Total of 30 input/output and a single
output only pin out of 32 pins are available on PORT0. POR T1 has up to 16 p ins available
for GPIO functions. PORT0 and PORT1 are controlled via two groups of 4 registers as
shown in Table 8–65
Legacy registers shown in Table 8–65
devices, using existing code. The functions an d rela tive timin g of olde r GPI O
implementations is preserved.
User manual LPC213xRev. 02 — 25 July 2006 78 of 292
Philips Semiconductors
The registers in Table 8–66 represent the enhanced GPIO features available on the
LPC213x/01 only. All of these registers are located directly on the local bus of the CPU for
the fastest possible read and write timing. An additional feature has been added that
provides byte addressability of all GPIO registers. A mask register allows treating groups
of bits in a single GPIO port separately from other bits on the same p ort.
The user must select whether a GPIO will be accessed via registers that provide
enhanced features or a legacy set of registers (see Section 4–6.1 “System Control and
Status flags register (SCS - 0xE01F C1A0)” on page 31). While both of a port’s fast and
legacy GPIO registers are controlling the same physical pins, these two port control
branches are mutually exclusive and operate independently. For example, changing a
pin’s output via a fast register will not be observable via the corresponding legacy register.
The following text will refer to the legacy GPIO as "the slow" GPIO, while GPIO equipped
with the enhanced features will be referred as "the fast" GPIO.
state of the GPIO configured port pins can
always be read from this register, regardless
of pin direction.
controls the state of output pins in
conjunction with the IOCLR register. Writing
ones produces highs at the corresponding
port pins. Writing zeroes has no effect.
register individually controls the direction of
each port pin.
register controls the state of output pins.
Writing ones produces lows at the
corresponding port pins and clears the
corresponding bits in the IOSET register.
Writing zeroes has no effect.
R/WNA0xE002 8000
R/W0x0000 0000 0xE002 8004
R/W0x0000 0000 0xE002 8008
WO0x0000 0000 0xE002 800C
value
[1]
PORT0
Address & Name
IO0PIN
IO0SET
IO0DIR
IO0CLR
UM10120
Chapter 8: GPIO
PORT1
Address & Name
0xE002 8010
IO1PIN
0xE002 8014
IO1SET
0xE002 8018
IO1DIR
0xE002 801C
IO1CLR
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
User manual LPC213xRev. 02 — 25 July 2006 79 of 292
Philips Semiconductors
UM10120
Chapter 8: GPIO
Table 66. GPIO register map (local bus accessible registers - enhanced GPIO features on LPC213x/01 only)
Generic
Name
FIODIRFast GPIO Port Direction control register.
FIOMASKFast Mask register for port. Writes, sets,
FIOPINFast Port Pin value register using FIOMASK.
FIOSETFast Port Output Set register using
FIOCLRFast Port Output Clear register using
DescriptionAccess Reset
This register individually controls the
direction of each port pin.
clears, and reads to port (done via writes to
FIOPIN, FIOSET , and FIOCLR, and reads of
FIOPIN) alter or return only the bits enabled
by zeros in this register.
The current state of digital port pins can be
read from this register, regardless of pin
direction or alternate function selection (as
long as pin is not configured as an input to
ADC). The value read is value of the
physical pins masked by ANDing the
inverted FIOMASK. Writing to this register
affects only port bits enabled by ZEROES in
FIOMASK.
FIOMASK. This register controls the state of
output pins. Writing 1s produces highs at the
corresponding port pins. Writing 0s has no
effect. Reading this register returns the
current contents of the port output register.
Only bits enabled by ZEROES in FIOMASK
can be altered.
FIOMASK. This register controls the state of
output pins. Writing 1s produces lows at the
corresponding port pins. Writing 0s has no
effect. Only bits enabled by ZEROES in
FIOMASK can be altered.
[1]
value
R/W0x0000 0000 0x3FFF C000
R/W0x0000 0000 0x3FFF C010
R/W0x0000 0000 0x3FFF C014
R/W0x0000 0000 0x3FFF C018
WO0x0000 0000 0x3FFF C01C
PORT0
Address & Name
FIO0DIR
FIO0MASK
FIO0PIN
FIO0SET
FIO0CLR
PORT1
Address & Name
0x3FFF C020
FIO1DIR
0x3FFF C030
FIO1MASK
0x3FFF C034
FIO1PIN
0x3FFF C038
FIO1SET
0x3FFF C03C
FIO1CLR
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
4.1 GPIO port Direction register (IODIR, Port 0: IO0DIR - 0xE002 8008 and
Port 1: IO1DIR - 0xE002 8018; FIODIR, Port 0: FIO0DIR - 0x3FFF C000
and Port 1:FIO1DIR - 0x3FFF C020)
This word accessible register is used to control the direction of the pins when they are
configured as GPIO port pins. Direction bit for any pin must be set according to the pin
functionality.
Legacy registers are the IO0DIR and IO1DIR, while the enhanced GPIO functions are
supported via the FIO0DIR and FIO1DIR registers.
Table 67. GPIO port 0 Direction register (IO0DIR - address 0xE002 8008) bit description
User manual LPC213xRev. 02 — 25 July 2006 80 of 292
Slow GPIO Direction control bits. Bit 0 controls P0.0 ... bit 30 controls P0.30.
0
1Controlled pin is output.
Controlled pin is input.
0x0000 0000
Philips Semiconductors
UM10120
Chapter 8: GPIO
Table 68. GPIO port 1 Direction register (IO1DIR - address 0xE002 8018) bit description
BitSymbolValue DescriptionReset value
31:0P1xDIR
Slow GPIO Direction control bits. Bit 0 in IO1DIR controls P1.0 ... Bit 30 in
0x0000 0000
IO1DIR controls P1.30.
0
Controlled pin is input.
1Controlled pin is output.
Table 69. Fast GPIO port 0 Direction register (FIO0DIR - address 0x3FFF C000) bit description
BitSymbolValue DescriptionReset value
31:0FP0xDIR
Fast GPIO Direction control bits. Bit 0 in FIO0DIR controls P0.0 ... Bit 30 in
0x0000 0000
FIO0DIR controls P0.30.
0
Controlled pin is input.
1Controlled pin is output.
Table 70. Fast GPIO port 1 Direction register (FIO1DIR - address 0x3FFF C020) bit description
BitSymbolValue DescriptionReset value
31:0FP1xDIR
Fast GPIO Direction control bits. Bit 0 in FIO1DIR controls P1.0 ... Bit 30 in
0x0000 0000
FIO1DIR controls P1.30.
0
Controlled pin is input.
1Controlled pin is output.
Aside from the 32-bit long and word only accessible FIODIR register, every fast GPIO port
can also be controlled via several byte and half-word accessible registers listed in
Table 8–71
and Table 8–72, too. Next to providing the same functions as the FIODIR
register, these additiona l registers allow easie r and faster access to the physical port pins.
Table 71. Fast GPIO port 0 Direction control byte and half-word accessible register description
Register
name
Register
length (bits)
& access
FIO0DIR08 (byte)0x3FFF C000 Fast GPIO Port 0 Direction control register 0. Bit 0 in FIO0DIR0
FIO0DIR18 (byte)0x3FFF C001 Fast GPIO Port 0 Direction control register 1. Bit 0 in FIO0DIR1
FIO0DIR28 (byte)0x3FFF C002 Fast GPIO Port 0 Direction control register 2. Bit 0 in FIO0DIR2
FIO0DIR38 (byte)0x3FFF C003 Fast GPIO Port 0 Direction control register 3. Bit 0 in FIO0DIR3
FIO0DIRL16
(half-word)
FIO0DIRU16
(half-word)
AddressDescriptionReset
register corresponds to P0.0 ... bit 7 to P0.7.
register corresponds to P0.8 ... bit 7 to P0.15.
register corresponds to P0.16 ... bit 7 to P0.23.
register corresponds to P0.24 ... bit 7 to P0.31.
0x3FFF C000 Fast GPIO Port 0 Direction control Lower half-word register. Bit 0 in
FIO0DIRL register corresponds to P0.0 ... bit 15 to P0.15.
0x3FFF C002 Fast GPIO Port 0 Direction control Upper half-word register. Bit 0 in
FIO0DIRU register corresponds to P0.16 ... bit 15 to P0.31.
User manual LPC213xRev. 02 — 25 July 2006 81 of 292
Philips Semiconductors
UM10120
Chapter 8: GPIO
Table 72. Fast GPIO port 1 Direction control byte and half-word accessible register description
Register
name
FIO1DIR08 (byte)0x3FFF C020 Fast GPIO Port 1 Direction control register 0. Bit 0 in FIO1DIR0
FIO1DIR18 (byte)0x3FFF C021 Fast GPIO Port 1 Direction control register 1. Bit 0 in FIO1DIR1
FIO1DIR28 (byte)0x3FFF C022 Fast GPIO Port 1 Direction control register 2. Bit 0 in FIO1DIR2
FIO1DIR38 (byte)0x3FFF C023 Fast GPIO Port 1 Direction control register 3. Bit 0 in FIO1DIR3
FIO1DIRL16
FIO1DIRU16
Register
length (bits)
& access
(half-word)
(half-word)
AddressDescriptionReset
register corresponds to P1.0 ... bit 7 to P1.7.
register corresponds to P1.8 ... bit 7 to P1.15.
register corresponds to P1.16 ... bit 7 to P1.23.
register corresponds to P1.24 ... bit 7 to P1.31.
0x3FFF C020 Fast GPIO Port 1 Direction control Lower half-word register. Bit 0 in
FIO1DIRL register corresponds to P1.0 ... bit 15 to P1.15.
0x3FFF C022 Fast GPIO Port 1 Direction control Upper half-word register. Bit 0 in
FIO1DIRU register corresponds to P1.16 ... bit 15 to P1.31.
4.2 Fast GPIO port Mask register (FIOMASK, Port 0: FIO0MASK 0x3FFF C010 and Port 1:FIO1MASK - 0x3FFF C030)
This register is available in the enhanced group of registers only. It is used to select port’s
pins that will and will not be affected by a write accesses to the FIOPIN, FIOSET or
FIOSLR register. Mask register also filters out port’s content when the FIOPIN register is
read.
value
0x00
0x00
0x00
0x00
0x0000
0x0000
A zero in this register’s bit enables an access to the corresponding physical pin via a read
or write access. If a bit in this register is one, corresponding pin will not be changed with
write access and if read, will not be reflected in the updated FIOPIN register. For software
examples, see Section 8–5 “GPIO usage notes” on page 89
Table 73. Fast GPIO port 0 Mask register (FIO0MASK - address 0x3FFF C010) bit description
BitSymbolValue DescriptionReset value
31:0FP0xMASK
Table 74. Fast GPIO port 1 Mask register (FIO1MASK - address 0x3FFF C030) bit description
BitSymbolValue DescriptionReset value
31:0FP1xMASK
Fast GPIO physical pin access control.
0
Pin is affected by writes to the FIOSET, FIOCLR, and FIOPIN registers.
Current state of the pin will be observable in the FIOPIN register.
1Physical pin is unaffected by writes into the FIOSET, FIOCLR and FIOPIN
registers. When the FIOPIN register is read, this bit will not be updated with
the state of the physical pin.
Fast GPIO physical pin access control.
0
Pin is affected by writes to the FIOSET, FIOCLR, and FIOPIN registers.
Current state of the pin will be observable in the FIOPIN register.
1Physical pin is unaffected by writes into the FIOSET, FIOCLR and FIOPIN
registers. When the FIOPIN register is read, this bit will not be updated with
the state of the physical pin.
User manual LPC213xRev. 02 — 25 July 2006 82 of 292
Philips Semiconductors
UM10120
Chapter 8: GPIO
Aside from the 32-bit long and word only accessible FIOMASK register, every fast GPIO
port can also be controlled via several byte and half-word accessible registers listed in
Table 8–75
and Table 8–76, too. Next to providing the same functions as the FIOMASK
register, these additiona l registers allow easie r and faster access to the physical port pins.
Table 75. Fast GPIO port 0 Mask byte and half-word accessible register description
Register
name
FIO0MASK0 8 (byte)0x3FFF C010 Fast GPIO Port 0 Mask register 0. Bit 0 in FIO0MASK0 register
FIO0MASK1 8 (byte)0x3FFF C011 Fast GPIO Port 0 Mask register 1. Bit 0 in FIO0MASK1 register
FIO0MASK2 8 (byte)0x3FFF C012 Fast GPIO Port 0 Mask register 2. Bit 0 in FIO0MASK2 register
FIO0MASK3 8 (byte)0x3FFF C013 Fast GPIO Port 0 Mask register 3. Bit 0 in FIO0MASK3 register
FIO0MASKL 16
FIO0MASKU 16
Register
length (bits)
& access
(half-word)
(half-word)
AddressDescriptionReset
corresponds to P0.0 ... bit 7 to P0.7.
corresponds to P0.8 ... bit 7 to P0.15.
corresponds to P0.16 ... bit 7 to P0.23.
corresponds to P0.24 ... bit 7 to P0.31.
0x3FFF C010 Fast GPIO Port 0 Mask Lower half-word register. Bit 0 in
FIO0MASKL register corresponds to P0.0 ... bit 15 to P0.15.
0x3FFF C012 Fast GPIO Port 0 Mask Upper half-word register. Bit 0 in
FIO0MASKU register corresponds to P0.16 ... bit 15 to P0.31.
value
0x00
0x00
0x00
0x00
0x0000
0x0000
Table 76. Fast GPIO port 1 Mask byte and half-word accessible register description
Register
name
FIO1MASK0 8 (byte)0x3FFF C010 Fast GPIO Port 1 Mask register 0. Bit 0 in FIO1MASK0 register
FIO1MASK1 8 (byte)0x3FFF C011 Fast GPIO Port 1 Mask register 1. Bit 0 in FIO1MASK1 register
FIO1MASK2 8 (byte)0x3FFF C012 Fast GPIO Port 1 Mask register 2. Bit 0 in FIO1MASK2 register
FIO1MASK3 8 (byte)0x3FFF C013 Fast GPIO Port 1 Mask register 3. Bit 0 in FIO1MASK3 register
FIO1MASKL 16
FIO1MASKU 16
Register
length (bits)
& access
(half-word)
(half-word)
AddressDescriptionReset
corresponds to P1.0 ... bit 7 to P1.7.
corresponds to P1.8 ... bit 7 to P1.15.
corresponds to P1.16 ... bit 7 to P1.23.
corresponds to P1.24 ... bit 7 to P1.31.
0x3FFF C010 Fast GPIO Port 1 Mask Lower half-word register. Bit 0 in
FIO1MASKL register corresponds to P1.0 ... bit 15 to P1.15.
0x3FFF C012 Fast GPIO Port 1 Mask Upper half-word register. Bit 0 in
FIO1MASKU register corresponds to P1.16 ... bit 15 to P1.31.
4.3 GPIO port Pin value register (IOPIN, Port 0: IO0PIN - 0xE002 8000 and
Port 1: IO1PIN - 0xE002 8010; FIOPIN, Port 0: FIO0PIN - 0x3FFF C014
and Port 1: FIO1PIN - 0x3FFF C034)
This register provides the value of port pins that are configured to perform only digital
functions. The register will give the logic value of the pin regardless of whether the pin is
configured for input or output, or as GPIO or an alternate digital function. As an example,
a particular port pin may have GPIO input, GPIO output, UART receive, and PWM output
as selectable functions. Any configuration of that pin will allow its current logic state to be
read from the IOPIN register.
User manual LPC213xRev. 02 — 25 July 2006 83 of 292
Philips Semiconductors
UM10120
Chapter 8: GPIO
If a pin has an analog function as one of its options, the pin state cannot be r ead if the
analog configuration is selected. Selecting the pin as an A/D input disconnect s the digital
features of the pin. In that case, the pin value read in the IOPIN register is not valid.
Writing to the IOPIN register stores the value in the port output register, bypassing the
need to use both the IOSET and IOCLR registers to obtain the entire written value. This
feature should be used carefully in an application since it affects the entire port.
Legacy registers are the IO0PIN and IO1PIN, while the enhanced GPIOs are supported
via the FIO0PIN and FIO1PIN registers. Access to a port pins via the FIOPIN register is
conditioned by the corresponding FIOMASK register (see Section 8–4.2 “Fast GPIO port
Mask register (FIOMASK, Port 0: FIO0MASK - 0x3FFF C010 and Port 1:FIO1MASK 0x3FFF C030)”).
Only pins masked with zeros in the Mask register (see Section 8–4.2 “Fast GPIO port
Mask register (FIOMASK, Port 0: FIO0MASK - 0x3FFF C010 and Port 1:FIO1MASK 0x3FFF C030)”) will be correlated to the current content of the Fast GPIO port pin value
register.
Table 77. GPIO port 0 Pin value register (IO0PIN - address 0xE002 8000) bit description
BitSymbolDescriptionReset value
31:0P0xVALSlow GPIO pin value bits. Bit 0 in IO0PIN corresponds to P0.0 ... Bit 31 in IO0PIN
NA
corresponds to P0.31.
Table 78. GPIO port 1 Pin value register (IO1PIN - address 0xE002 8010) bit description
BitSymbolDescriptionReset value
31:0P1xVALSlow GPIO pin value bits. Bit 0 in IO1PIN corresponds to P1.0 ... Bit 31 in IO1PIN
Table 79. Fast GPIO port 0 Pin value register (FIO0PIN - address 0x3FFF C014) bit description
BitSymbolDescriptionReset value
31:0FP0xVALFast GPIO pin value bits. Bit 0 in FIO0PIN corresponds to P0.0 ... Bit 31 in FIO0PIN
Table 80. Fast GPIO port 1 Pin value register (FIO1PIN - address 0x3FFF C034) bit description
BitSymbolDescriptionReset value
31:0FP1xVALFast GPIO pin value bits. Bit 0 in FIO1PIN corresponds to P1.0 ... Bit 31 in FIO1PIN
NA
corresponds to P1.31.
NA
corresponds to P0.31.
NA
corresponds to P1.31.
Aside from the 32-bit long and word only acce ssible FIOPIN register , every fast GPIO port
can also be controlled via several byte and half-word accessible registers listed in
Table 8–81
and Table 8–82, too. Next to providing the same functions as the FIOPIN
register, these additiona l registers allow easie r and faster access to the physical port pins.
User manual LPC213xRev. 02 — 25 July 2006 84 of 292
Philips Semiconductors
UM10120
Chapter 8: GPIO
Table 81. Fast GPIO port 0 Pin value byte and half-word accessible register description
Register
name
FIO0PIN08 (byte)0x3FFF C014 Fast GPIO Port 0 Pin value register 0. Bit 0 in FIO0PIN0 register
FIO0PIN18 (byte)0x3FFF C015 Fast GPIO Port 0 Pin value register 1. Bit 0 in FIO0PIN1 register
FIO0PIN28 (byte)0x3FFF C016 Fast GPIO Port 0 Pin value register 2. Bit 0 in FIO0PIN2 register
FIO0PIN38 (byte)0x3FFF C017 Fast GPIO Port 0 Pin value register 3. Bit 0 in FIO0PIN3 register
FIO0PINL16
FIO0PINU16
Table 82. Fast GPIO port 1 Pin value byte and half-word accessible register description
Register
name
FIO1PIN08 (byte)0x3FFF C034 Fast GPIO Port 1 Pin value register 0. Bit 0 in FIO1PIN0 register
FIO1PIN18 (byte)0x3FFF C035 Fast GPIO Port 1 Pin value register 1. Bit 0 in FIO1PIN1 register
FIO1PIN28 (byte)0x3FFF C036 Fast GPIO Port 1 Pin value register 2. Bit 0 in FIO1PIN2 register
FIO1PIN38 (byte)0x3FFF C037 Fast GPIO Port 1 Pin value register 3. Bit 0 in FIO1PIN3 register
FIO1PINL16
FIO1PINU16
Register
length (bits)
& access
(half-word)
(half-word)
Register
length (bits)
& access
(half-word)
(half-word)
AddressDescriptionReset
corresponds to P0.0 ... bit 7 to P0.7.
corresponds to P0.8 ... bit 7 to P0.15.
corresponds to P0.16 ... bit 7 to P0.23.
corresponds to P0.24 ... bit 7 to P0.31.
0x3FFF C014 Fast GPIO Port 0 Pin value Lower half-word register. Bit 0 in
FIO0PINL register corresponds to P0.0 ... bit 15 to P0.15.
0x3FFF C016 Fast GPIO Port 0 Pin value Upper half-word register. Bit 0 in
FIO0PINU register corresponds to P0.16 ... bit 15 to P0.31.
AddressDescriptionReset
corresponds to P1.0 ... bit 7 to P1.7.
corresponds to P1.8 ... bit 7 to P1.15.
corresponds to P1.16 ... bit 7 to P1.23.
corresponds to P1.24 ... bit 7 to P1.31.
0x3FFF C034 Fast GPIO Port 1 Pin value Lower half-word register. Bit 0 in
FIO1PINL register corresponds to P1.0 ... bit 15 to P1.15.
0x3FFF C036 Fast GPIO Port 1 Pin value Upper half-word register. Bit 0 in
FIO1PINU register corresponds to P1.16 ... bit 15 to P1.31.
value
0x00
0x00
0x00
0x00
0x0000
0x0000
value
0x00
0x00
0x00
0x00
0x0000
0x0000
4.4 GPIO port output Set register (IOSET, Port 0: IO0SET - 0xE002 8004
and Port 1: IO1SET - 0xE002 8014; FIOSET, Port 0: FIO0SET 0x3FFF C018 and Port 1: FIO1SET - 0x3FFF C038)
This register is used to produce a HIGH level output at the port pins configured as GPIO in
an OUTPUT mode. Writing 1 produces a HIGH level at the corresponding port pins.
Writing 0 has no effect. If any pin is configured as an input or a se condary functio n, writing
1 to the corresponding bit in the IOSET has no effect.
Reading the IOSET register returns the value of this register, as determined by previous
writes to IOSET and IOCLR (or IOPIN as noted above). This value does not reflect the
effect of any outside world influence on the I/O pins.
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UM10120
Chapter 8: GPIO
Legacy registers are the IO0SET and IO1SET, while the enhanced GPIOs are supported
via the FIO0SET and FIO1SET registers. Access to a port pins via the FIOSET register is
conditioned by the corresponding FIOMASK register (see Section 8–4.2 “Fast GPIO port
Mask register (FIOMASK, Port 0: FIO0MASK - 0x3FFF C010 and Port 1:FIO1MASK 0x3FFF C030)”).
Table 83. GPIO port 0 output Set register (IO0SET - address 0xE002 8004 bit description
BitSymbolDescriptionReset value
31:0P0xSETSlow GPIO output value Set bits. Bit 0 in IO0SET corresponds to P0.0 ... Bit 31
0x0000 0000
in IO0SET corresponds to P0.31.
Table 84. GPIO port 1 output Set register (IO1SET - address 0xE002 8014) bit description
BitSymbolDescriptionReset value
31:0P1xSETSlow GPIO output value Set bits. Bit 0 in IO1SET corresponds to P1.0 ... Bit 31
0x0000 0000
in IO1SET corresponds to P1.31.
Table 85. Fast GPIO port 0 output Set register (FIO0SET - address 0x3FFF C018) bit description
BitSymbolDescriptionReset value
31:0FP0xSETFast GPIO output value Set bits. Bit 0 in FIO0SET corresponds to P0.0 ... Bit 31
0x0000 0000
in FIO0SET corresponds to P0.31.
Table 86. Fast GPIO port 1 output Set register (FIO1SET - address 0x3FFF C038) bit description
BitSymbolDescriptionReset value
31:0FP1xSETFast GPIO output value Set bits. Bit 0 Fin IO1SET corresponds to P1.0 ... Bit
0x0000 0000
31 in FIO1SET corresponds to P1.31.
Aside from the 32-bit long and word only accessible FIOSET register, every fast GPIO
port can also be controlled via several byte and half-word accessible registers listed in
Table 8–87
and Table 8–88, too. Next to providing the same functions as the FIOSET
register, these additiona l registers allow easie r and faster access to the physical port pins.
Table 87. Fast GPIO port 0 output Set byte and half-word accessible register description
Register
name
Register
length (bits)
& access
FIO0SET08 (byte)0x3FFF C018 Fast GPIO Port 0 output Set register 0. Bit 0 in FIO0SET0 register
FIO0SET18 (byte)0x3FFF C019 Fast GPIO Port 0 output Set register 1. Bit 0 in FIO0SET1 register
FIO0SET28 (byte)0x3FFF C01A Fast GPIO Port 0 output Set register 2. Bit 0 in FIO0SET2 register
FIO0SET38 (byte)0x3FFF C01B Fast GPIO Port 0 output Set register 3. Bit 0 in FIO0SET3 register
FIO0SETL16
(half-word)
FIO0SETU16
(half-word)
AddressDescriptionReset
corresponds to P0.0 ... bit 7 to P0.7.
corresponds to P0.8 ... bit 7 to P0.15.
corresponds to P0.16 ... bit 7 to P0.23.
corresponds to P0.24 ... bit 7 to P0.31.
0x3FFF C018 Fast GPIO Port 0 output Set Lower half-word register. Bit 0 in
FIO0SETL register corresponds to P0.0 ... bit 15 to P0.15.
0x3FFF C01A Fast GPIO Port 0 output Set Upper half-word register. Bit 0 in
FIO0SETU register corresponds to P0.16 ... bit 15 to P0.31.
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Philips Semiconductors
UM10120
Chapter 8: GPIO
Table 88. Fast GPIO port 1 output Set byte and half-word accessible register description
Register
name
Register
length (bits)
AddressDescriptionReset
& access
FIO1SET08 (byte)0x3FFF C038 Fast GPIO Port 1 output Set register 0. Bit 0 in FIO1SET0 register
corresponds to P1.0 ... bit 7 to P1.7.
FIO1SET18 (byte)0x3FFF C039 Fast GPIO Port 1 output Set register 1. Bit 0 in FIO1SET1 register
corresponds to P1.8 ... bit 7 to P1.15.
FIO1SET28 (byte)0x3FFF C03A Fast GPIO Port 1 output Set register 2. Bit 0 in FIO1SET2 register
corresponds to P1.16 ... bit 7 to P1.23.
FIO1SET38 (byte)0x3FFF C03B Fast GPIO Port 1 output Set register 3. Bit 0 in FIO1SET3 register
corresponds to P1.24 ... bit 7 to P1.31.
FIO1SETL16
(half-word)
FIO1SETU16
(half-word)
0x3FFF C038 Fast GPIO Port 1 output Set Lower half-word register. Bit 0 in
FIO1SETL register corresponds to P1.0 ... bit 15 to P1.15.
0x3FFF C03A Fast GPIO Port 1 output Set Upper half-word register. Bit 0 in
FIO1SETU register corresponds to P1.16 ... bit 15 to P1.31.
4.5 GPIO port output Clear register (IOCLR, Port 0: IO0CLR 0xE002 800C and Port 1: IO1CLR - 0xE002 801C; FIOCLR, Port 0:
FIO0CLR - 0x3FFF C01C and Port 1: FIO1CLR - 0x3FFF C03C)
This register is used to produce a LOW level output at port pins configured as GPIO in an
OUTPUT mode. Writing 1 produces a LOW leve l at the cor respond ing po rt pin a nd cle ars
the corresponding bit in the IOSET register. Wr iting 0 has no effect. If any pin is configured
as an input or a secondary function, writing to IOCLR has no effect.
value
0x00
0x00
0x00
0x00
0x0000
0x0000
Legacy registers are the IO0CLR and IO1CLR, while the enhanced GPIOs ar e sup ported
via the FIO0CLR and FIO1CLR registers. Access to a port pins via the FIOCLR register is
conditioned by the corresponding FIOMASK register (see Section 8–4.2 “Fast GPIO port
Mask register (FIOMASK, Port 0: FIO0MASK - 0x3FFF C010 and Port 1:FIO1MASK 0x3FFF C030)”).
Table 89. GPIO port 0 output Clear register 0 (IO0CLR - address 0xE002 800C) bit description
BitSymbolDescriptionReset value
31:0P0xCLRSlow GPIO output value Clear bits. Bit 0 in IO0CLR corresponds to P0.0 ... Bit
Table 90. GPIO port 1 output Clear register 1 (IO1CLR - address 0xE002 801C) bit description
BitSymbolDescriptionReset value
31:0P1xCLRSlow GPIO output value Clear bits. Bit 0 in IO1CLR corresponds to P1.0 ... Bit
Table 91. Fast GPIO port 0 output Clear register 0 (FIO0CLR - address 0x3FFF C01C) bit descriptio n
BitSymbolDescriptionReset value
31:0FP0xCLRFast GPIO output value Clear bits. Bit 0 in FIO0CLR corresponds to P0.0 ... Bit
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Philips Semiconductors
UM10120
Chapter 8: GPIO
Table 92. Fast GPIO port 1 output Clear register 1 (FIO1CLR - address 0x3FFF C03C) bit descriptio n
BitSymbolDescriptionReset value
31:0FP1xCLRFast GPIO output value Clear bits. Bit 0 in FIO1CLR corresponds to P1.0 ... Bit
0x0000 0000
31 in FIO1CLR corresponds to P1.31.
Aside from the 32-bit long and word only accessible FIOCLR register, every fast GPIO
port can also be controlled via several byte and half-word accessible registers listed in
Table 8–93
and Table 8–94, too. Next to providing the same functions as the FIOCLR
register, these additiona l registers allow easie r and faster access to the physical port pins.
Table 93. Fast GPIO port 0 output Clear byte and half-word accessible register description
Register
name
Register
length (bits)
& access
FIO0CLR08 (byte)0x3FFF C01C Fast GPIO Port 0 output Clear register 0. Bit 0 in FIO0CLR0 register
FIO0CLR18 (byte)0x3FFF C01D Fast GPIO Port 0 output Clear register 1. Bit 0 in FIO0CLR1 register
FIO0CLR28 (byte)0x3FFF C01E Fast GPIO Port 0 output Clear register 2. Bit 0 in FIO0CLR2 register
FIO0CLR38 (byte)0x3FFF C01F Fast GPIO Port 0 output Clear register 3. Bit 0 in FIO0CLR3 register
FIO0CLRL16
(half-word)
FIO0CLRU 16
(half-word)
AddressDescriptionReset
corresponds to P0.0 ... bit 7 to P0.7.
corresponds to P0.8 ... bit 7 to P0.15.
corresponds to P0.16 ... bit 7 to P0.23.
corresponds to P0.24 ... bit 7 to P0.31.
0x3FFF C01C Fast GPIO Port 0 output Clear Lower half-word register. Bit 0 in
FIO0CLRL register corresponds to P0.0 ... bit 15 to P0.15.
0x3FFF C01E Fast GPIO Port 0 output Clear Upper half-word register. Bit 0 in
FIO0SETU register corresponds to P0.16 ... bit 15 to P0.31.
value
0x00
0x00
0x00
0x00
0x0000
0x0000
Table 94. Fast GPIO port 1 output Clear byte and half-word accessible register description
Register
name
Register
length (bits)
AddressDescriptionReset
& access
FIO1CLR08 (byte)0x3FFF C03C Fast GPIO Port 1 output Clear register 0. Bit 0 in FIO1CLR0 register
corresponds to P1.0 ... bit 7 to P1.7.
FIO1CLR18 (byte)0x3FFF C03D Fast GPIO Port 1 output Clear register 1. Bit 0 in FIO1CLR1 register
corresponds to P1.8 ... bit 7 to P1.15.
FIO1CLR28 (byte)0x3FFF C03E Fast GPIO Port 1 output Clear register 2. Bit 0 in FIO1CLR2 register
corresponds to P1.16 ... bit 7 to P1.23.
FIO1CLR38 (byte)0x3FFF C03F Fast GPIO Port 1 output Clear register 3. Bit 0 in FIO1CLR3 register
corresponds to P1.24 ... bit 7 to P1.31.
FIO1CLRL16
(half-word)
FIO1CLRU 16
(half-word)
0x3FFF C03C Fast GPIO Port 1 output Clear Lower half-word register. Bit 0 in
FIO1CLRL register corresponds to P1.0 ... bit 15 to P1.15.
0x3FFF C03E Fast GPIO Port 1 output Clear Upper half-word register. Bit 0 in
FIO1CLRU register corresponds to P1.16 ... bit 15 to P1.31.
User manual LPC213xRev. 02 — 25 July 2006 88 of 292
Philips Semiconductors
5.GPIO usage notes
5.1 Example 1: sequential accesses to IOSET and IOCLR affecting the
same GPIO pin/bit
State of the output configured GPIO pin is determined by writes into the pin’s port IOSET
and IOCLR registers. Last of these accesses to the IOSET/IOCLR register will determine
the final output of a pin.
pin P0.7 is configured as an output (write to IO0DIR register). After this, P0.7 output is set
to low (first write to IO0CLR register). Short high pulse follows on P0.7 (write access to
IO0SET), and the final write to IO0CLR register sets pin P0.7 back to low level.
UM10120
Chapter 8: GPIO
5.2 Example 2: an immediate output of 0s and 1s on a GPIO port
Write access to port’s IOSET followed by write to the IOCLR register results with pins
outputting 0s being slightly later then pins outputting 1s. There are systems that can
tolerate this delay of a valid output, but for some applications simultaneous output of a
binary content (mixed 0s and 1s) within a group of pins on a single GPIO port is required.
This can be accomplished by writing to the port’s IOPIN register.
Following code will preserve existing output on PORT0 pins P0.[31:16] and P0.[7:0] and
at the same time set P0.[15:8] to 0xA5, regardless of the previous value of pins P0.[15:8]:
IO0PIN = (IO0PIN && 0xFFFF00FF) || 0x0000A500
The same outcome can be obtained using the fast port access.
Solution 1: using 32-bit (word) accessible fast GPIO registers
FIO0MASK = 0xFFFF00FF;
FIO0PIN = 0x0000A500;
Solution 2: using 16-bit (half-word) accessible fast GPIO registers
FIO0MASKL = 0x00FF;
FIO0PINL = 0xA500;
Solution 3: using 8-bit (byte) accessible fast GPIO registers
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5.3 Writing to IOSET/IOCLR .vs. IOPIN
Write to the IOSET/IOCLR register allows easy change of the port’s selected output pin(s)
to high/low level at a time. Only pin/bit(s) in the IOSET/IOCLR written with 1 will be set to
high/low level, while those written as 0 will remain unaffected. However, by just writing to
either IOSET or IOCLR register it is not possible to instantaneously output arbitrary binary
data containing mixture of 0s and 1s on a GPIO port.
Write to the IOPIN register enables instantaneous output of a desired content on the
parallel GPIO. Binary data written into the IOPIN register will affect all output configured
pins of that parallel port: 0s in the IOPIN will produce low level pin outputs and 1s in IOPIN
will produce high level pin outputs. In order to change output of only a group of port’s pins,
application must logically AND readout from the IOPIN with mask containing 0s in bits
corresponding to pins that will be changed, and 1s for all others. Finally, this result has to
be logically ORred with the desired content and stored back into the IOPIN register.
Example 2 from above illustrates output of 0xA5 on PORT0 pins 15 to 8 while preserving
all other PORT0 output pins as they were before.
5.4 Output signal frequency considerations when using the legacy and
enhanced GPIO registers
UM10120
Chapter 8: GPIO
The enhanced features of the fast GPIO ports available on this microcontroller make
GPIO pins more responsive to the code that has task of controlling them. In particular,
software access to a GPIO pin is 3.5 times faster via the fast GPIO registers than it is
when the legacy set of registers is used. As a result of the access speed increase, the
maximum output frequency of the digital pin is increased 3 .5 times, too. This tremendous
increase of the output frequency is not always that visible when a plain C code is used,
and a portion of an application handling the fast port output might have to be written in an
assembly code and executed in the ARM mode.
Here is a code where the pin control section is written in assembly language for ARM. It
illustrates the difference between the fast and slow GPIO port output capabilities. Once
this code is compiled in the ARM mode, its execution from the on-chip Flash will yield the
best results when the MAM module is configured as described in Section 3–9 “MAM
usage notes” on page 21. Execution from the on-chip SRAM is independent fro m the
MAM setup.
ldrr0,=0xe01fc1a0/*register address--enable fast port*/
movr1,#0x1
strr1,[r0] /*enable fast port0*/
ldrr1,=0xffffffff
ldrr0,=0x3fffc000 /*direction of fast port0*/
strr1,[r0]
ldrr0,=0xe0028018/*direction of slow port 1*/
strr1,[r0]
ldrr0,=0x3fffc018/*FIO0SET -- fast port0 register*/
ldrr1,=0x3fffc01c/*FIO0CLR0 -- fast port0 register*/
ldrr2,=0xC0010000/*select fast port 0.16 for toggle*/
ldrr3,=0xE0028014/*IO1SET -- slow port1 register*/
ldrr4,=0xE002801C/*IO1CLR -- slow port1 register*/
ldrr5,=0x00100000/*select slow port 1.20 for toggle*/
/*Generate 2 pulses on the fast port*/
strr2,[r0]
• Register locations conform to ‘550 industry standard.
• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.
• Mechanism that enables software and hardware flow control implementation.
1.1 Enhancements introduced with LPC213x/01 devices
UM10120
Chapter 9: UART0
Powerful Fractional baud rate generator with autobauding capabilities provides standard
baud rates such as 115200 with any crystal frequency above 2 MHz.
2.Pin description
Table 95: UART0 pin description
PinTypeDescription
RXD0InputSerial Input. Serial receive data.
TXD0OutputSerial Output. Serial transmit data.
3.Register description
UART0 contains registers organized as shown in Table 9–96. The Divisor Latch Access
Bit (DLAB) is contained in U0LCR[7] and enables access to the Diviso r Latches.
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The U0RBR is the top byte of the UART0 Rx FIFO. The top byte of the Rx FIFO contains
the oldest character received and can be read via the bus interface. The LSB (bit 0)
represents the “oldest” received dat a bit. If the character received is less than 8 bits, the
unused MSBs are padded with zeroes.
The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to access the
U0RBR. The U0RBR is always Read Only.
Since PE, FE and BI bits correspond to the byte sitting on the top of the RBR FIFO (i.e.
the one that will be read in the next read from the RBR), the right approach for fetching the
valid pair of received byte and its status bits is first to read the content of the U0LSR
register, and then to read a byte from the U0RBR.
The U0THR is the top byte of the UART0 TX FIFO. The top byte is the newest character in
the TX FIFO and can be written via the bus interface. The LSB represents the first bit to
transmit.
The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to access the
U0THR. The U0THR is always Write Only.
7:0THRWriting to the UART0 Transmit Holding Register causes the data
to be stored in the UART0 transmit FIFO. The byte will be sent
when it reaches the bottom of the FIFO and the transmitter is
available.
NA
3.3 UART0 Divisor Latch Registers (U0DLL - 0xE000 C000 and U0DLM 0xE000 C004, when DLAB = 1)
The UART0 Divisor Latch is part of the UART0 Fractional Baud Rate Generator and holds
the value used to divide the clock supplied by the fractional prescaler in order to produce
the baud rate clock, which must be 16x the desired baud rate (Equation 9–1
and U0DLM registers together form a 16 bit divisor where U0DLL cont ains the lower 8 b its
of the divisor and U0DLM contains the higher 8 bits of the divisor. A 0x0000 value is
treated like a 0x0001 value as division by zero is not allowed.The Divisor Latch Access Bit
(DLAB) in U0LCR must be one in order to access the UART0 Divisor Latches.
). The U0DLL
Details on how to select the right value for U0DLL and U0DLM can be found later on in
this chapter.
This register is available in LPC213x/01 devices only.
The UART0 Fractional Divider Register (U0FDR) controls the clock pre-sca ler for the
baud rate generation and can be read and written at user’s discretion. This pre-scaler
takes the APB clock and generates an output clock per specified fractional requirements.
UM10120
Chapter 9: UART0
DLAB = 1) bit description
0x01
register, determines the baud rate of the UART0.
DLAB = 1) bit description
0x00
register, determines the baud rate of the UART0.
Important: If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value of
the DLL register must be 2 or greater.
3:0DIVADDV AL Baudrate generation pre-scaler divisor value. If this field is 0,
fractional baudrate generator will not impact the UART0
baudrate.
7:4MULV ALBaudrate pre-scaler multiplier value. This field must be greater
or equal 1 for UART0 to operate properly, regardless of
whether the fractional baudrate generator is used or not.
31:8 -Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
0
1
NA
This register controls the clock pre-scaler for the baud rate generation . Th e reset va lue of
the register keeps the fractional capabilities of UART0 disabled making sure that UART0
is fully software and hardware compatible with UARTs not equipped with this feature.
Where PCLK is the peripheral clock, U0DLM and U0DLL are the standard UART0 baud
rate divider registers, and DIVADDVAL and MULVAL are UART0 fractional baudrate
generator specific parameters.
The value of MULVAL and DIVADDVAL should comply to the following conditions:
User manual LPC213xRev. 02 — 25 July 2006 95 of 292
Philips Semiconductors
1. 0 < MULVAL ≤ 15
2. 0 ≤ DIVADDVAL ≤ 15
If the U0FDR register value does not comply to these two requests then the fractional
divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled
and the clock will not be divided.
The value of the U0FDR should not be modified while transmitting/receiving data or data
may be lost or corrupted.
Usage Note: For practical purposes, UART0 baudrate formula can be written in a way
that identifies the part of a UART baudrate generated without the fractional baudrate
generator, and the correction factor that this module adds:
Based on this representation, fractional baudrate generator contribution can also be
described as a prescaling with a factor of MULVAL / (MULVAL + DIVADDVAL).
3.5 UART0 baudrate calculation
Example 1: Using UART0baudrate formula from above, it can be determined that system
with PCLK = 20 MHz, U0DL = 130 (U0DLM = 0x00 and U0DLL = 0x82), DIVADDVAL = 0
and MULVAL = 1 will enable UART0 with UART0baudrate = 9615 bauds.
Example 2: Using UART0baudrate formula from above, it can be determined that system
with PCLK = 20 MHz, U0DL = 93 (U0DLM = 0x00 and U0DLL = 0x5D), DIVADDVAL = 2
and MULVAL = 5 will enable UART0 with UART0baudrate = 9600 bauds.
Table 102: Baudrates available when using 20 MHz peripheral clock (PCLK = 20 MHz)
MUL VAL = 0 DIVADDVAL = 0Optimal MULVAL & DIVADDVAL
U0DLM:U0DLL% error
hex
[2]
dec
[1]
[3]
U0DLM:U0DLL
[1]
dec
Fractional
pre-scaler value
MULDIV
MULDIV + DIVADDVAL
UM10120
Chapter 9: UART0
% error
[3]
[1] Values in the row represent decimal equivalent of a 16 bit long content (DLM:DLL).
[2] Values in the row represent hex equivalent of a 16 bit long content (DLM:DLL).
[3] Refers to the percent error between desired and actual baudrate.
The U0IIR provides a status code that denotes the priority and source of a pending
interrupt. The interrupts are frozen during an U0IIR access. If an interrupt occurs during
an U0IIR access, the interrupt is recorded for the next U0IIR access.
User manual LPC213xRev. 02 — 25 July 2006 98 of 292
[1]
[1]
Note that U0IIR[0] is active low. The pending interrupt can
be determined by evaluating U0IIR[3:1].
0
At least one interrupt is pending.
1No pending interrupts.
U0IER[3:1] identifies an interrupt corresponding to the
UART0 Rx FIFO. All other combinations of U0IER[3:1] not
listed above are reserved (000,100,101,111).
011
1 - Receive Line Status (RLS).
0102a - Receive Data Available (RDA).
1 102b - Character Time-out Indicator (CTI).
0013 - THRE Interrupt
bits. The value read from a reserved bit is not defined.
End of auto-baud interrupt. True if auto-baud has finished
successfully and interrupt is enabled.
Auto-baud time-out interrupt. True if auto-baud has timed
out and interrupt is enabled.
bits. The value read from a reserved bit is not defined.
1
0
NA
0
0
NA
Philips Semiconductors
[1] This feature is available in LPC213x/01 devices only.
Interrupts are handled as described in Table 9–105. Given the status of U0IIR[3:0], an
interrupt handler routine can determine the cause of the interrupt and how to clear the
active interrupt. The U0IIR must be read in order to clear the interrupt prior to exiting the
Interrupt Service Routine.
The UART0 RLS interrupt (U0IIR[3:1] = 011) is the highest priority interrupt and is set
whenever any one of four error conditions occur on the UART0 Rx input: overrun error
(OE), parity error (PE), framing error (FE) and break interru pt (BI). The UART0 Rx error
condition that set the interrupt can be observed via U0LSR[4:1]. The interrupt is cleared
upon an U0LSR read.
The UART0 RDA interrupt (U0IIR[3:1] = 010) shares the second le vel priority with the CTI
interrupt (U0IIR[3:1] = 110). The RDA is activated when the UART0 Rx FIFO reaches the
trigger level defined in U0FCR[7:6] and is reset when the UART0 Rx FIFO depth falls
below the trigger level. When the RDA interrupt goes active, the CPU can read a block of
data defined by the trigger level.
The CTI interrupt (U0IIR[3:1] = 1 10) is a second level interrupt and is set when the UART0
Rx FIFO contains at least one character and no UART0 Rx FIFO activity has occurre d in
3.5 to 4.5 character times. Any UART0 Rx FIFO activity (read or write of UART0 RSR) will
clear the interrupt. This interrupt is intended to flush the UART0 RBR after a message has
been received that is not a multiple of the trigger level size. For example, if a peripher al
wished to send a 105 character message and the trigger level was 10 ch aracters, the
CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5
CTI interrupts (depending on the service routine) resulting in the transfer of the rem aining
5 characters.
0001-NoneNone0110Hi ghestRX Line Status / Error OE
0100Second RX Data AvailableRx data available or trigger level reached in FIFO
1100Second Character Time-out
0010ThirdTHRETHRE
indication
[2]
or PE
[2]
or FE
[2]
or BI
[2]
(U0FCR0=1)
Minimum of one character in the Rx FIFO and no
character input or removed during a time period
depending on how many characters are in FIFO
and what the trigger level is set at (3.5 to 4.5
character times).
The exact time will be:
[(word length) × 7
− 2] × 8 + [(trigger level −
number of characters) × 8 + 1] RCLKs
[2]
UM10120
Chapter 9: UART0
U0LSR Read
U0RBR Read
UART0 FIFO drops
below trigger level
U0RBR Read
U0IIR Read (if source
of interrupt) or THR
[4]
write
[2]
[3]
or
[3]
[1] Values "0000", “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved.
[2] For details see Section 9–3.10 “
[3] For details see Section 9–3.1 “UART0 Receiver Buffer Register (U0RBR - 0xE000 C000, when DLAB = 0, Read Only)”
The UART0 THRE interrupt (U0IIR[3:1] = 001) is a third level interrupt and is activated
when the UART0 THR FIFO is empty provided certain initialization conditions have been
met. These initialization conditions are intended to give the UART0 THR FIFO a chance to
fill up with data to eliminate many THRE interrupts from occurring at system start-up. The
initialization conditions implement a one character delay minus the stop bit whenever
THRE=1 and there have not been at least two characters in the U0THR at one time since
the last THRE = 1 event. This delay is provided to give the CPU time to write data to
U0THR without a THRE interrupt to decode and service. A THRE interrupt is set
immediately if the UART0 THR FIFO has held two or more characters at one time and
currently , the U0THR is empty. The THRE interrupt is reset when a U0THR write occurs or
a read of the U0IIR occurs and the THRE is the highest interrupt (U0IIR[3:1] = 001).
3.8 UART0 FIFO Control Register (U0FCR - 0xE000 C008)
The U0FCR controls the operation of the UART0 Rx and TX FIFOs.
Table 106: UART0 FIFO Control Register (U0FCR - address 0xE000 C008) bit description
BitSymbolValueDescriptionReset value
0FIFO Enable 0UART0 FIFOs are disabled. Must not be used in the
application.
1Active high enable for both UART0 Rx and TX
FIFOs and U0FCR[7:1] access. This bit must be set
for proper UART0 operation. Any transition on this
bit will automatically clear the UART0 FIFOs.
1RX FIFO
Reset
2TX FIFO
Reset
5:3-0Rese rved, user software should not write ones to
7:6RX Trigger
Level
0No impact on either of UART0 FIFOs.0
1Writing a logic 1 to U0FCR[1] will clear all bytes in
UART0 Rx FIFO and reset the pointer logic. This bit
is self-clearing.
0No impact on either of UART0 FIFOs.0
1Writing a logic 1 to U0FCR[2] will clear all bytes in
UART0 TX FIFO and reset the pointer logic. This bit
is self-clearing.
reserved bits. The value read from a reserved bit is
not defined.
These two bits determine how many receiver
UART0 FIFO characters must be written before an
00
interrupt is activated.
Trigger level 0 (1 character or 0x01)
01Trigger level 1 (4 characters or 0x04)
10Trigger level 2 (8 characters or 0x08)
11Trigger level 3 (14 characters or 0x0E)
0
NA
0
3.9 UART0 Line Control Register (U0LCR - 0xE000 C00C)
The U0LCR determines the format of the data character that is to be transmitted or
received.